JP2003122628A - Digital signal processing device, program conversion device, and communication system having digital signal processing device - Google Patents

Abstract

(57) [Problem] To provide a digital signal processing circuit such as a digital signal processor without adverse effects such as a decrease in operating frequency and an increase in the number of pipeline stages, and in any of continuous access and random access forms. By controlling the supply and stop of the clock signal to the data memory, power consumption is reduced. SOLUTION: A bank group decoder 4 for specifying a bank or a bank group indicated by an address held by each of address pointer registers P0 to P3, and a bank group register 5 for holding a decoding result of the bank group decoder 4 are provided. The supply and stop of the clock signal to the bank group of the data memory 3 are controlled in accordance with the value of each bank group register 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device such as a digital signal processor and a communication system having the digital signal processing device, and more particularly to a technique for realizing a communication system with low power consumption.

[0002]

2. Description of the Related Art Generally, in a digital signal processing circuit such as a digital signal processor, it is not possible to control the supply of a clock signal to a data memory and stop the supply of the clock signal to an unused data memory. ,
Very effective in reducing power consumption. However, when controlling the supply of the clock signal based on the access signal to the data memory, there are disadvantages such as a decrease in the operating frequency and an increase in the number of pipeline stages due to the time required to control the supply of the clock signal being secured. Therefore, in the past, the clock signal was always supplied to all the data memory banks in preparation for access to any address in the memory space. Therefore, there is a problem that unnecessary power is consumed in the clock circuit of the unused data memory bank.

Therefore, in order to solve the above-mentioned conventional problems, the inventor of the present application discloses in Japanese Patent Application No. 11-169448 a case in which a predetermined continuous region in a data memory is repeatedly and continuously accessed to perform an operation. Focusing on the above, by proposing a technique for controlling the clock signal after the second access during the continuous access, the supply of the clock signal to the non-access bank is stopped to reduce the power consumption.

[0004]

However, in the above proposal, although the power supply can be reduced by stopping the supply of the clock signal to the non-access banks, the target of the stop control of the supply of the clock signal is set to the data memory. Since the continuous access is limited to the repeated access to the continuous area, the random access to the data memory does not have the effect of reducing the power consumption, and the effect of reducing the power consumption is not significant.

[0005]

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to further stop the supply of a clock signal to a non-access bank even at the time of random access to a data memory, To reduce power consumption.

In order to achieve the above object, the present invention is configured to recognize an address for accessing a data memory each time and stop supplying a clock signal to a bank other than the memory bank pointed to by the address.

That is, a digital signal processing apparatus according to a first aspect of the present invention includes a data memory having a data storage area composed of a plurality of banks, and the data memory is stored in the data memory according to an instruction code issued based on a predetermined procedure. In a digital signal processing device for processing data, an address pointer register for storing an address for accessing the data memory, a bank of the data memory indicated by an address held by the address pointer register by decoding the data of the address pointer register, or A bank group decoder for specifying a bank group and a bank group register for holding a decoding result of the bank group decoder are provided, and a clock signal for each bank of the data memory is output according to a value of the bank group register. And controlling the supply and stop.

According to a second aspect of the present invention, in the digital signal processing device according to the first aspect, a plurality of the address pointer registers are provided, and the bank group decoder is provided for each of the plurality of address pointer registers. Is characterized by.

According to a third aspect of the present invention, in the digital signal processing device according to the first aspect, a plurality of the address pointer registers are provided, and the bank group decoder is a part of the plurality of address pointer registers. Is provided corresponding to.

According to a fourth aspect of the present invention, in the digital signal processing device according to the third aspect, a plurality of the address pointer registers are provided, and the number of the bank group decoders is greater than that of the plurality of address pointer registers. Further, a pointer register selection circuit that associates a part of the plurality of address pointer registers with the bank group decoder, and a clock control pointer that specifies the part of the address pointer registers and controls the pointer register selection circuit. And a setting register.

In addition, the program conversion device of the invention described in claim 5 controls the hardware from the source program describing the signal processing procedure in the program development environment of the digital signal processing device described in claim 3. When the instruction code is generated, the signal processing procedure of the source program is analyzed in advance, and a simulation means for taking a history of the frequency of use of the address pointer register in the source program is provided, and the simulation is obtained by the simulation means. Changing a register use instruction that uses the frequently used address pointer register to an instruction that uses the address pointer register corresponding to the bank group decoder based on the history of the use frequency of the address pointer register in the source program; Characterize.

According to a sixth aspect of the present invention, there is provided a program conversion apparatus for controlling hardware in a program development environment for a digital signal processing apparatus according to the fourth aspect, from a source program describing a signal processing procedure. When the instruction code is generated, a signal processing procedure of the source program is analyzed in advance, and a simulation means for taking a history of the frequency of use of the address pointer register in the source program is provided, and the source obtained by the simulation means is provided. It is characterized in that an instruction code for specifying the frequently used address pointer registers as the partial address pointer registers is generated based on a history of the frequency of use of the address pointer registers in the program.

Furthermore, a communication system according to a seventh aspect of the present invention includes a digital signal processing device according to the first, second, third or fourth aspect, a control device, a storage device, an input device, an output device and a communication interface device. It is characterized by having.

As described above, according to the first aspect of the invention, among the plurality of banks or bank groups of the data memory,
Since the bank or bank group indicated by the address stored in the address pointer register is specified by the bank group decoder, the clock signal is supplied only to the specified bank or bank group even during random access to the data memory. The clock signal is supplied to the other banks or bank groups. Therefore, a low power consumption digital signal processing device can be realized.

Further, according to the second aspect of the invention, since the bank group decoder and the bank group register are provided for each address pointer register, the supply of the clock signal is controlled by the memory access signal after the address pointer register to be used is determined. The disadvantages such as a decrease in operating frequency and an increase in the number of pipeline stages, which occur in the conventional technique for performing the above, do not occur.

According to the third aspect of the invention, since the bank group decoder and the bank group register are provided corresponding to a part of the address pointer register, if the corresponding address pointer register is frequently used, the circuit scale will be increased. It is possible to realize a low power consumption digital signal processing device capable of supplying a clock signal only to the bank to be accessed among all the banks of the data memory without increasing the number of clocks.

Further, in the invention according to claim 4, among the plurality of address pointer registers, which of the pointer registers the bank group decoder and the bank group register are associated with is set in the clock control pointer setting register. Even if the number of decoders and bank group registers is smaller than the number of pointer registers, the degree of freedom in selecting the address pointer register that controls the supply of the clock signal increases.

In addition, in the invention of claim 5, the register use instruction using the address pointer register which is frequently used is changed to the use instruction of the address pointer register corresponding to the bank group decoder. It is possible to easily develop a program that can effectively utilize the power saving function of the described digital signal processing device.

According to the sixth aspect of the present invention, since the instruction code for specifying the frequently used address pointer register as the address pointer register associated with the bank group decoder is generated, the digital signal according to the fourth aspect. A program that can effectively utilize the low power consumption function of the processing device can be easily developed.

Further, according to the communication system of the invention described in claim 7, since the digital signal processing device according to claim 1, 2, 3 or 4 is provided, the communication system has low power consumption.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a block diagram of a part of a digital signal processor that is the digital signal processing device according to the embodiment.

In the figure, the data memory 3 is composed of four banks 0 to 3. Reference numeral 1 denotes an address pointer register, which has four address pointer registers P0 to P4, each of which has a data memory 3
The address to access is stored. An instruction decoder 6 decodes an instruction code, extracts a memory access instruction, extracts a used pointer register, and the like. Two
Is a memory access signal generation circuit, which receives a memory access instruction extraction signal, a use pointer register extraction signal, etc. from the instruction decoder 6 and outputs an access signal to each bank 0 to 3 of the data memory 3.

Reference numeral 4 denotes a bank group decoder provided for each pointer register P0 to P3, which decodes pointer data and corresponds to the corresponding pointer register P0 to P.
It is determined whether 3 indicates a bank group 01 (a pair of bank 0 and a bank 1) or a bank group 23 (a pair of a bank 2 and a bank 3). Reference numeral 5 denotes a bank group register, and similarly each pointer register P0 to P
Each 3 is composed of 2-bit registers for bank group 01 and bank group 23. Each of the bank group registers 5 outputs the corresponding bank group decoder 4, that is, the corresponding pointer registers P0 to P3.
Each time the value of is updated, it holds which bank group the pointer register points to.

Reference numeral 7 denotes a clock control signal generation circuit for bank 0 and bank 1, which is a signal indicating which pointer register P0 to P3 generated by the instruction decoder 6 is to be used, and a bank control signal generation circuit for bank group 01. Based on the value of the bank group register 5, the clock control signals for the bank groups of the two banks 0 and 1 are output. Similarly, 8 is a clock control signal generation circuit for the banks 2 and 3. Reference numeral 9 denotes a clock gate circuit provided for each of the banks 0 to 3, and the clock control signal generation circuits 7 and 8 are provided.
By receiving the clock control signal from, and gating the system clock based on this clock control signal,
When an access signal is output from the memory access signal generation circuit 2 to the data memory 3, the clock signal is supplied to the bank group to be accessed, and the supply of the clock signal to the bank group not to be accessed is controlled.

Further, 10 is an arithmetic unit for inputting the data read from the data memory 3 to perform arithmetic operation, and 11 is a data register for holding the arithmetic result of the arithmetic unit 10.

FIG. 2 shows the correspondence between memory banks and memory addresses. The operation when the instruction code string corresponding to the program source code shown in FIG. 3 is given to the digital signal processor shown in FIG. 1 as a signal processing procedure will be described.

In FIG. 3, line number 1 is an instruction for setting a hexadecimal value "0000" in the address pointer register P0. Line number 2 shows the data of the data memory address indicated by the address pointer register P0 in the register D0.
It is an instruction to transfer to. Line number 3 is an instruction to set a hexadecimal value "8000" in the address pointer register P2. Line number 4 is an instruction to transfer the data in the register D0 to the data memory address indicated by the address pointer register P2. Line number 5 is an instruction that does nothing.

FIG. 4 shows a timing chart when the instruction procedure of FIG. 3 is executed by using the present digital signal processor. In this digital signal processor, in FIG. 4, an instruction fetch is performed at a stage IF, an instruction decode is performed at a stage IDEC, an address decode of a data memory is performed at a stage ADDEC, a data memory access is performed at a stage MA, and an instruction is executed using an arithmetic unit 10 at a stage EX. The pipeline operation performed shall be performed. In the instruction of line number 1, the address pointer register P0 is set at the IDEC stage. This address pointer register P0
Value of bank group decoder 4 during stage IDEC
Then, the decoding is completed, the B01 bit of the bank group register 5 corresponding to the address pointer register P0 is set to "1", and the B23 bit is set to "0" at the head of the stage ADDEC. In the instruction of line number 2, it is determined that the instruction uses the address pointer register P0 in the stage IDEC, and the B01 bit of the bank group register 5 corresponding to the address pointer register P0 is "1" and the B23 bit is "0". Since,
The bank 01 clock control signal becomes "1" between the stage ADDEC and the stage MA of the instruction of row number 2, and the bank 23 clock control signal becomes "0". as a result,
A clock signal is supplied only to banks 0 and 1 during the stage MA of the instruction in row number 2.

Similarly, in the instruction of line number 3, the stage I
The address pointer register P2 is set by DEC.
The value of the address pointer register P2 is the stage IDEC.
Decoding is completed by the bank group decoder 4, and the address pointer register P at the beginning of the stage ADDEC.
The B23 bit of the bank group register 5 corresponding to 2 is set to "1", and the B01 bit is set to "0". In the instruction of line number 4, it is determined that the instruction uses the address pointer register P2 at the stage IDEC, and the B01 bit and the B23 bit of the bank group register 5 corresponding to the address pointer register P2 are "0" and "1". Therefore, the bank 23 clock control signal becomes "1" between the stage ADDEC and the stage MA of the instruction of the row number 4, and the bank 01 clock control signal becomes "0". Therefore, the clock signal is supplied only to the banks 2 and 3 during the stage MA of the instruction of the row number 4. As a result, the clock signal is supplied only to the necessary bank, and the power consumption can be reduced.

(Second Embodiment) Next, the second embodiment of the present invention will be described.
A digital signal processor which is the digital signal processing device of the embodiment will be described.

FIG. 5 shows a block diagram of a part of the processor. In the figure, unlike FIG. 1, the bank group decoder 4 and the bank group register 5 exist only in association with predetermined two registers P2 and P3 among the four address pointer registers P0 to P3.

Therefore, in this embodiment, the supply of the clock signal to the data memory 3 can be controlled only when the address pointer registers P2 and P3 are used, but the address pointer registers P2 and P3 are controlled.
The frequent and effective use of 3 makes it possible to reduce the power consumption by controlling the supply of the clock signal to the data memory 3 without increasing the circuit size.

(Third Embodiment) Next, a digital signal processor which is a digital signal processing apparatus according to a third embodiment of the present invention will be described.

FIG. 6 shows a block diagram of a part of the processor. In the figure, 15 is a pointer register selection circuit,
Reference numeral 16 is a clock control pointer setting register. Based on the setting value of the clock control pointer setting register 16, the pointer register selection circuit 15 inputs the address pointer registers P0 to P3 to the two bank group decoders 4, respectively. Select one of the outputs.
Reference numeral 7 denotes a clock control signal generation circuit for the bank 0 and the bank 1 of the data memory 3. The clock control signal generation circuit 7 generates a signal indicating which address pointer register P0 to P3 is used by the instruction decoder 6 and the clock control pointer setting register 16 Depending on the pointer register selection signal from the bank group register 5 and the value of the bank group register 5, each bank group (01), (2
The clock control signal is output to 3). Similarly, 8 is a clock control signal generation circuit for bank 2 and bank 3.

Therefore, in the present embodiment, it is not necessary to provide the bank group decoder 4 and the bank group register 5 for all the address pointer registers P0 to P3.
By appropriately setting the value of the clock control pointer setting register 16, the bank of the data memory 3 indicated by this address is set every time a memory access address is set for any two selected address pointer registers P0 to P3. It becomes possible to stop the supply of the clock signal to the bank groups other than the group.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.
The program conversion device of the embodiment will be described.

FIG. 7 shows a block diagram of an example of the program conversion device. Reference numeral 20 is a storage device for storing the program source code, 21 is a storage device for storing data to be externally input to the digital signal processing device shown in FIG. 5, 22
Is a simulation device (simulation means) that operates logically the same as the digital signal processing device of FIG. 5 and can take the history of the address pointer register used at each execution step of the program and the memory bank pointed to by the address pointer register. Reference numeral 23 is a memory device for storing the history of the address pointer register used by each execution step of the program obtained by the simulation device 22 and the memory bank pointed to by the address pointer register. Reference numeral 24 is a source code conversion device for converting the program source code stored in the storage device 20, based on the history of the address pointer register used for each execution step of the program stored in the storage device 23. A storage device 25 stores the program source code converted by the source code conversion device 24.

A specific example of the operation of the program conversion device will be described. FIG. 8 shows an example of a part of the source program code stored in the storage device 20. The instruction at line number 1 is
Hexadecimal value "000" is set in the address pointer register P0.
The instruction of line number 2 is an instruction of setting a hexadecimal value "0000" in the address pointer register P2. The instruction of line number 3 is from line number 4 to line number 5. The instruction of line number 4 is the address pointer register P.
This is an instruction to transfer the data of the address indicated by 0 to the register D0 and then add "1" to the address pointer register P0. The instruction in line number 5 transfers the contents of the register D0 to the data memory at the address indicated by the address pointer register P2, and then the address pointer register P2.
Is an instruction to add "1" to.

When the data memory map of the digital signal processing apparatus of FIG. 5 is the same as that of FIG. 2, the simulation apparatus 22 sets the address pointer register P0 between the row number 1 and the row number 5 to the bank 0 of the data memory 3. Is used 256 times to access the address pointer register P
2 stores in the storage device 23 a history of 256 times used to access the bank 2. Source code converter 24
Is an address pointer that uses the address pointer register P0 used between the instructions of line numbers 1 to 5 for controlling the supply of the clock signal, based on the history stored in the storage device 23 and a predetermined standard. Converted to the register P3, the program source code of FIG. 8 is converted like the program source code of FIG. Then, the converted program source code is stored in the converted source program storage device 25. Note that, in FIG. 9, each instruction of line number 0 and line number 6 is an instruction for saving and restoring the value of the address pointer register P3 by changing the address pointer register from the register P0 to the register P3.

Therefore, in this embodiment, the address pointer register P0 is used as in the digital signal processing device of FIG.
Even if the same number of bank group decoders 4 and bank group registers 5 as P3 to P3 are not provided, the digital signal processing device can be operated with low power without reducing the man-hours for program development.

(Fifth Embodiment) Next, the fifth embodiment of the present invention will be described.
The program conversion device of the embodiment will be described.

The block diagram of the program conversion device of the present embodiment is the same as FIG. However, the simulation device 22 operates logically the same as the digital signal processing device of FIG. Further, assuming that the data memory map of the digital signal processing device of FIG. 6 is the same as that of FIG. 2, a specific example in which the source code of FIG. 8 is used as the source program code stored in the storage device 20 will be described.

The simulation apparatus 22 executes the source program of FIG. 8, and the address pointer register P0 is used 256 times to access the bank 0 of the data memory 3 between the instructions of the line numbers 1 to 5 and the address pointer register P0 is used. The history that the register P2 has been used 256 times to access the bank 2 is stored in the storage device 23. The source code conversion device 24 inserts the instruction indicated by line number 0 shown in FIG. 10 based on the history stored in the storage device 23 and a predetermined standard, and stores the conversion source program code shown in FIG. It is stored in the device 25. The instruction with the line number 0 in FIG. 10 is an instruction to set the clock control pointer setting register (CKCNT) 16 in the digital signal processing apparatus in FIG. 6 so that the pointer registers subject to clock control are the registers P0 and P2.

Therefore, in this embodiment, the number of man-hours for developing a program can be reduced without providing the same number of bank group decoders 4 and bank group registers 5 as the number of address pointer registers as in the digital signal processor of FIG. Therefore, it becomes possible to operate the digital signal processing device with low power.

(Sixth Embodiment) Finally, a communication system according to a sixth embodiment of the present invention will be described.

FIG. 11 shows the communication system of this embodiment. In the figure, 30 is the digital signal processing device shown in FIG. 1, FIG. 5 or FIG. 6, 31 is a control device such as a general-purpose microcomputer for controlling the entire system, 32 is system control information and digital signal processing device 30. Is a storage device for storing input / output data, information for assisting storage of a user of the communication system, communication data, and the like.

Reference numeral 33 is an input device such as a keyboard for the user of the communication system to give an instruction to the communication system and a microphone for inputting communication contents. Reference numeral 34 is a system status for the user of the communication system. And an output device such as a display for displaying various information and a loudspeaker for outputting communication contents.

Therefore, in this embodiment, a communication system including a low power consumption digital signal processing device can be obtained.

[0050]

As described above, according to the invention described in claims 1 to 7, it is possible to stop the supply of the clock signal to the bank or bank group which is not accessed even at the time of random access to the data memory. Therefore, a low power consumption digital signal processing device and communication system can be provided.

In particular, according to the second aspect of the invention, since the bank group decoder and the bank group register are provided for each address pointer register, the supply of the clock signal is controlled by the memory access signal after the address pointer register to be used is determined. It is possible to prevent the occurrence of demerits such as a decrease in operating frequency and an increase in the number of pipeline stages, which would occur in the conventional technique for performing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital signal processing device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a specific example of a data memory map.

FIG. 3 is a diagram showing an example of a source program code.

FIG. 4 is a timing chart diagram illustrating an operation of the digital signal processing device according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing a digital signal processing device according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a digital signal processing device according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing a program conversion device according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing an example of a source program code input to a simulation device provided in the program conversion device.

9 is a diagram showing a converted source program code obtained by converting the source program code shown in FIG.

FIG. 10 is a diagram showing a conversion source program code in the program conversion device according to the fifth embodiment of the present invention.

FIG. 11 is a block diagram showing a communication system according to a sixth exemplary embodiment of the present invention.

[Description of Codes] P0 to P3 Address pointer register 2 Memory access signal generation circuit 3 Data memory 4 Bank group decoder 5 Bank group register 6 Instruction decoders 7 and 8 Clock control signal generation circuit 9 Clock gate circuit 10 Operation unit 11 Data register 15 Pointer register selection circuit 16 Clock control pointer setting register 20, 21, 23, 25, 32 Storage device 22 Simulation device (simulation means) 24 Source code conversion device 30 Digital signal processing device 31 Control device 33 Input device 34 Output device 35 Communication interface apparatus

Claims (7)

[Claims] 1. A digital signal processing device, comprising a data memory having a data storage area composed of a plurality of banks, for processing data stored in said data memory according to an instruction code issued in accordance with a predetermined procedure. An address pointer register for storing an address for accessing a data memory; a bank group decoder for decoding the data of the address pointer register to identify a bank or a bank group of the data memory indicated by the address held by the address pointer register; A bank group register which holds a decoding result of the bank group decoder, and controls supply and stop of a clock signal to each bank of the data memory according to a value of the bank group register. Signal processing device. 2. The plurality of address pointer registers are provided, and the bank group decoder is provided for each of the plurality of address pointer registers.
The described digital signal processing device. 3. The digital signal processing device according to claim 1, wherein a plurality of the address pointer registers are provided, and the bank group decoder is provided corresponding to a part of the plurality of address pointer registers. . 4. A plurality of the address pointer registers are provided, the number of the bank group decoders is smaller than that of the plurality of address pointer registers, and a part of the plurality of address pointer registers is provided in the bank group decoder. 4. The digital signal processing device according to claim 3, further comprising a pointer register selection circuit to be associated with the clock control pointer setting register for specifying the part of the address pointer registers and controlling the pointer register selection circuit. 5. In the program development environment of the digital signal processing device according to claim 3, when a command code for controlling hardware is generated from a source program describing a signal processing procedure, the signal of the source program is generated. Analyze the processing procedure in advance,
A simulation means for taking a history of the frequency of use of the address pointer register in the source program is provided, and an address pointer with a high frequency of use is based on the history of the frequency of use of the address pointer register in the source program obtained by the simulation means. A program conversion device characterized in that a register use instruction using a register is changed to an instruction using an address pointer register corresponding to the bank group decoder. 6. The program development environment of the digital signal processing device according to claim 4, wherein when a command code for controlling hardware is generated from a source program describing a signal processing procedure, the signal of the source program is generated. Analyze the processing procedure in advance,
A simulation means for taking a history of the frequency of use of the address pointer register in the source program is provided, and an address pointer with a high frequency of use is based on the history of the frequency of use of the address pointer register in the source program obtained by the simulation means. A program conversion device, which generates an instruction code that specifies a register as the part of the address pointer registers. 7. A communication system comprising the digital signal processing device according to claim 1, 2, 3 or 4, and a control device, a storage device, an input device, an output device and a communication interface device.