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JP2003110373A - Amplifier circuit - Google Patents

Amplifier circuit

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Publication number
JP2003110373A
JP2003110373A JP2001301120A JP2001301120A JP2003110373A JP 2003110373 A JP2003110373 A JP 2003110373A JP 2001301120 A JP2001301120 A JP 2001301120A JP 2001301120 A JP2001301120 A JP 2001301120A JP 2003110373 A JP2003110373 A JP 2003110373A
Authority
JP
Japan
Prior art keywords
transistor
electrode
source
gate electrode
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001301120A
Other languages
Japanese (ja)
Other versions
JP2003110373A5 (en
Inventor
Yuji Yamamoto
有二 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2001301120A priority Critical patent/JP2003110373A/en
Publication of JP2003110373A publication Critical patent/JP2003110373A/en
Publication of JP2003110373A5 publication Critical patent/JP2003110373A5/ja
Withdrawn legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide an amplifier circuit having a large input impedance. SOLUTION: A resistor R1 is connected in between transistors 1, 2, whose gate electrodes are respectively connected to a positive and a negative input terminals. Currents, having the same value, are passed to both ends of the resistor R1 by constant current sources 10, 11. The voltage at the positive and negative input terminals are the same as the voltage of both the ends of the resistor R1. The current, flowing through the resistor R1, is extracted by using current mirror transistors 4, 6 and current mirror transistors 3, 5, 7, 8. Since a current having the same value as that in the resistor R1 flows through the resistor R2, a voltage (potential difference between the positive and negative input terminals multiplied by R2/R1) is outputted to an output terminal. Since the positive and negative input terminals are connected to the gate electrodes of the transistors, the circuit has a large impedance.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は,電子回路の内で小
さい電気信号を大きく増幅する増幅回路に関する。より
詳しくは,正負の入力端子間の電圧差を,抵抗比に従う
増幅率で増幅し,出力端子とGND等の基準電位との間
の電圧差として出力する増幅回路に関する。さらに,該
増幅回路は,MOSトランジスタと抵抗のみで構成が可
能である為,集積化増幅回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit that greatly amplifies a small electric signal in an electronic circuit. More specifically, the present invention relates to an amplifier circuit that amplifies a voltage difference between positive and negative input terminals with an amplification factor according to a resistance ratio and outputs the voltage difference as a voltage difference between an output terminal and a reference potential such as GND. Furthermore, since the amplifier circuit can be configured only with MOS transistors and resistors, it relates to an integrated amplifier circuit.

【0002】[0002]

【従来の技術】まず本発明の背景を明らかにする為に従
来の増幅回路の説明を行う。図2に,従来広く用いられ
る増幅回路を示す。図2の増幅回路は,所謂,差動増幅
回路と呼ばれている。
2. Description of the Related Art First, a conventional amplifier circuit will be described to clarify the background of the present invention. FIG. 2 shows an amplifier circuit that has been widely used conventionally. The amplifier circuit of FIG. 2 is called a so-called differential amplifier circuit.

【0003】図2の回路で,R1=R3,R2=R4と
する。正入力端子と負入力端子の電圧差は,抵抗比=R
2/R1の増幅率で増幅され,出力端子と,基準電圧V
b間の電圧差として出力される。
In the circuit of FIG. 2, it is assumed that R1 = R3 and R2 = R4. The voltage difference between the positive input terminal and the negative input terminal is the resistance ratio = R
It is amplified by the amplification factor of 2 / R1, and the output terminal and the reference voltage V
It is output as the voltage difference between b.

【0004】[0004]

【発明が解決しようとする課題】図2の回路には,以下
の問題点あるいは課題がある。負入力端子とオペアンプ
14の負入力端子の間には,抵抗R1が接続されてお
り,負入力端子の入力インピーダンスは,R1となる。
正入力端子についても入力インピーダンスは,R3+R
4となる。したがって,正入力端子と負入力端子に,他
の回路の出力を接続する場合には,入力インピーダンス
を十分駆動できる能力が必要である。
The circuit shown in FIG. 2 has the following problems or problems. A resistor R1 is connected between the negative input terminal and the negative input terminal of the operational amplifier 14, and the input impedance of the negative input terminal is R1.
The input impedance of the positive input terminal is R3 + R
It becomes 4. Therefore, when connecting the outputs of other circuits to the positive input terminal and the negative input terminal, it is necessary to have the ability to drive the input impedance sufficiently.

【0005】[0005]

【課題を解決する為の手段】従来の技術の課題を解決す
るために,本発明では,図1に示す手段を講じた。即
ち,第1のトランジスタは,ドレイン電極を第3のトラ
ンジスタのドレイン電極とゲート電極と第5のトランジ
スタのゲート電極に共通に接続しゲート電極を正入力端
子に接続しソース電極を抵抗R1の一端と定電流源10
の一端に共通に接続した。第2のトランジスタは,ドレ
イン電極を第4のトランジスタのゲート電極とドレイン
電極と第6のトランジスタのゲート電極に共通に接続し
ゲート電極を負入力端子に接続しソース電極を抵抗R1
の他端と定電流源11の一端に共通に接続した。第3,
4のトランジスタは,ソース電極をGND電位に接続し
た。第5のトランジスタは,ドレイン電極を第7のトラ
ンジスタのゲート電極とドレイン電極と第8のトランジ
スタのゲート電極に共通に接続しソース電極をGND電
位に接続した。第6のトランジスタは,ドレイン電極を
第8のトランジスタのドレイン電極と演算増幅回路14
の反転入力端子と抵抗R2の一端に共通に接続しソース
電極をGND電極に接続した。第7,8のトランジスタ
は,ソース電極を電源に接続した。
In order to solve the problems of the prior art, the present invention employs the means shown in FIG. That is, in the first transistor, the drain electrode is commonly connected to the drain electrode and gate electrode of the third transistor, and the gate electrode of the fifth transistor, the gate electrode is connected to the positive input terminal, and the source electrode is connected to one end of the resistor R1. And constant current source 10
Commonly connected to one end of. In the second transistor, the drain electrode is commonly connected to the gate electrode and drain electrode of the fourth transistor, and the gate electrode of the sixth transistor, the gate electrode is connected to the negative input terminal, and the source electrode is connected to the resistor R1.
Are commonly connected to the other end of the constant current source 11. Third,
The source electrode of transistor No. 4 was connected to the GND potential. In the fifth transistor, the drain electrode was commonly connected to the gate electrode and drain electrode of the seventh transistor and the gate electrode of the eighth transistor, and the source electrode was connected to the GND potential. The drain electrode of the sixth transistor is the drain electrode of the eighth transistor and the operational amplifier circuit 14
The inverting input terminal and the one end of the resistor R2 are commonly connected, and the source electrode is connected to the GND electrode. The source electrodes of the seventh and eighth transistors were connected to the power supply.

【0006】定電流源10,11は,他端を電源に接続
した。基準電圧源Vbは,一端を前記演算増幅器の正入
力端子に他端をGND電位に接続した。抵抗R2は,他
端を出力端子と前記演算増幅器の出力に共通に接続し
た。
The other ends of the constant current sources 10 and 11 are connected to a power source. The reference voltage source Vb has one end connected to the positive input terminal of the operational amplifier and the other end connected to the GND potential. The other end of the resistor R2 is commonly connected to the output terminal and the output of the operational amplifier.

【0007】図1の回路は,正負の入力端子の電位差
が,抵抗R1の電位差とほぼ等しくなる。トランジスタ
3,4,5,6のサイズが全て等しく,トランジスタ7
と8のサイズが等しいとする。抵抗R1に流れる電流と
抵抗R2の流れる電流は等しいので,抵抗R2の両端に
は,正負の入力の電位差をR2/R1倍した電圧差が生
じる。すなわち,図1の回路は,正負の入力端子の電圧
差を増幅する。正負の入力端子は,各々トランジスタ
1,トランジスタ2のゲート電極に接続している。トラ
ンジスタ1,2は,所謂MOSトランジスタであり,ゲ
ート電極の入力インピーダンスはきわめて大きい。した
がって図1の増幅回路の入力インピーダンスはきわめて
大きく,接続しようとする前段回路の駆動能力にほとん
ど影響を与えない。
In the circuit of FIG. 1, the potential difference between the positive and negative input terminals is substantially equal to the potential difference of the resistor R1. Transistors 3, 4, 5, 6 are all the same size
And 8 are equal in size. Since the current flowing through the resistor R1 is equal to the current flowing through the resistor R2, a voltage difference that is R2 / R1 times the potential difference between the positive and negative inputs occurs at both ends of the resistor R2. That is, the circuit of FIG. 1 amplifies the voltage difference between the positive and negative input terminals. The positive and negative input terminals are connected to the gate electrodes of the transistor 1 and the transistor 2, respectively. The transistors 1 and 2 are so-called MOS transistors, and the input impedance of the gate electrode is extremely large. Therefore, the input impedance of the amplifier circuit of FIG. 1 is extremely large, and it hardly affects the driving capability of the preceding circuit to be connected.

【0008】[0008]

【発明の実施の形態】図1に,本発明による増幅回路の
具体的な回路構成を示す。図1の回路では,正負の入力
端子の電位差が,抵抗R1の電位差とほぼ等しくなる。
トランジスタ3,4,5,6のサイズが全て等しく,ト
ランジスタ7と8のサイズが等しいとする。抵抗R1に
流れる電流と抵抗R2の流れる電流は等しいので,抵抗
R2の両端には,正負の入力の電位差をR2/R1倍し
た電圧差が生じる。すなわち,図1の回路は,正負の入
力端子の電圧差を増幅回路となっている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a concrete circuit configuration of an amplifier circuit according to the present invention. In the circuit of FIG. 1, the potential difference between the positive and negative input terminals is substantially equal to the potential difference of the resistor R1.
It is assumed that the transistors 3, 4, 5 and 6 have the same size, and the transistors 7 and 8 have the same size. Since the current flowing through the resistor R1 is equal to the current flowing through the resistor R2, a voltage difference that is R2 / R1 times the potential difference between the positive and negative inputs occurs at both ends of the resistor R2. That is, the circuit of FIG. 1 is an amplifier circuit for the voltage difference between the positive and negative input terminals.

【0009】[0009]

【実施例】図1に,本発明の実施例を示す。トランジス
タ1は,ドレイン電極をトランジスタ3のドレイン電極
とゲート電極とトランジスタ5のゲート電極に共通に接
続しゲート電極を正入力端子に接続しソース電極を抵抗
R1の一端と定電流源10の一端に共通に接続した。ト
ランジスタ2は,ドレイン電極をトランジスタ4のゲー
ト電極とドレイン電極とトランジスタ6のゲート電極に
共通に接続しゲート電極を負入力端子に接続しソース電
極を抵抗R1の他端と定電流源11の一端に共通に接続
した。トランジスタ3,4は,ソース電極をGND電位
に接続した。トランジスタ5は,ドレイン電極をトラン
ジスタ7のゲート電極とドレイン電極とトランジスタ8
のゲート電極に共通に接続しソース電極をGND電位に
接続した。トランジスタ6は,ドレイン電極をトランジ
スタ8のドレイン電極と演算増幅回路14の反転入力端
子と抵抗R2の一端に共通に接続しソース電極をGND
電極に接続した。トランジスタ7,8は,ソース電極を
電源に接続した。
EXAMPLE FIG. 1 shows an example of the present invention. In the transistor 1, the drain electrode is commonly connected to the drain electrode and the gate electrode of the transistor 3 and the gate electrode of the transistor 5, the gate electrode is connected to the positive input terminal, and the source electrode is connected to one end of the resistor R1 and one end of the constant current source 10. Connected in common. In the transistor 2, the drain electrode is commonly connected to the gate electrode and the drain electrode of the transistor 4 and the gate electrode of the transistor 6, the gate electrode is connected to the negative input terminal, and the source electrode is the other end of the resistor R1 and one end of the constant current source 11. Commonly connected to. The source electrodes of the transistors 3 and 4 were connected to the GND potential. The transistor 5 has a drain electrode, a gate electrode of the transistor 7, a drain electrode, and a transistor 8
, And the source electrode was connected to the GND potential. In the transistor 6, the drain electrode is commonly connected to the drain electrode of the transistor 8, the inverting input terminal of the operational amplifier circuit 14 and one end of the resistor R2, and the source electrode is connected to GND.
It was connected to the electrode. The source electrodes of the transistors 7 and 8 were connected to the power supply.

【0010】定電流源10,11は,他端を電源に接続
した。基準電圧源Vbは,一端を前記演算増幅器の正入
力端子に他端をGND電位に接続した。抵抗R2は,他
端を出力端子と前記演算増幅器の出力に共通に接続し
た。
The other ends of the constant current sources 10 and 11 were connected to a power source. The reference voltage source Vb has one end connected to the positive input terminal of the operational amplifier and the other end connected to the GND potential. The other end of the resistor R2 is commonly connected to the output terminal and the output of the operational amplifier.

【0011】図1の回路において,定電流源10,11
には,同じ電流を流す。最初に正負の入力端子の電圧差
が0のときについて説明する。トランジスタ1,2に流
れる電流は等く,トランジスタ3,4に流れる電流も等
しい。トランジスタ1,2に流れる電流が等しい場合,
トランジスタ1,2のゲート電極とソース電極間の電圧
Vgsは等しく,抵抗R1の両端の電圧も等しいので,
抵抗R1には,電流が流れない。トランジスタ5,6は
ゲート電極が各々トランジスタ3,4のゲート電極と共
通に接続し,所謂カレントミラー回路を構成している。
したがって,トランジスタ5,6に流れる電流は,トラ
ンジスタ3,4に流れる電流にトランジスタサイズ比を
乗じたものになる。トランジスタ7,8も同様に,ゲー
ト電極が共通に接続され,所謂カレントミラー回路を構
成しているので,トランジスタ8に流れる電流は,トラ
ンジスタ7に流れる電流にトランジスタサイズ比を乗じ
たものになる。
In the circuit of FIG. 1, constant current sources 10, 11
The same current is applied to both. First, the case where the voltage difference between the positive and negative input terminals is 0 will be described. The currents flowing through the transistors 1 and 2 are equal, and the currents flowing through the transistors 3 and 4 are also equal. If the currents flowing through the transistors 1 and 2 are equal,
Since the voltage Vgs between the gate electrode and the source electrode of the transistors 1 and 2 is equal, and the voltage across the resistor R1 is also equal,
No current flows through the resistor R1. The gate electrodes of the transistors 5 and 6 are commonly connected to the gate electrodes of the transistors 3 and 4, respectively, to form a so-called current mirror circuit.
Therefore, the current flowing through the transistors 5 and 6 is the current flowing through the transistors 3 and 4 multiplied by the transistor size ratio. Similarly, since the gate electrodes of the transistors 7 and 8 are commonly connected to form a so-called current mirror circuit, the current flowing through the transistor 8 is the current flowing through the transistor 7 multiplied by the transistor size ratio.

【0012】ここで,トランジスタ3,5,トランジス
タ4,6,トランジスタ7,8のサイズを各々等しいと
する。トランジスタ3,4に流れる電流が等しい場合,
トランジスタ5,6に流れる電流は等しい。トランジス
タ7,8には,トランジスタ5に流れる電流と等しい電
流が流れる。トランジスタ8に流れる電流は,トランジ
スタ6に流れる電流と等しいので,抵抗R2には電流が
流れない。したがって,オペアンプ14の出力は,基準
電圧Vbの値に等しい。
Here, it is assumed that the sizes of the transistors 3, 5, 5, 4, 6 and 7, 8 are equal to each other. If the currents flowing through the transistors 3 and 4 are equal,
The currents flowing through the transistors 5 and 6 are equal. A current equal to the current flowing through the transistor 5 flows through the transistors 7 and 8. Since the current flowing through the transistor 8 is equal to the current flowing through the transistor 6, no current flows through the resistor R2. Therefore, the output of the operational amplifier 14 is equal to the value of the reference voltage Vb.

【0013】次に,正入力端子が,負入力端子の電圧よ
りa(Volt)高い場合について説明する。トランジ
スタ1,2のVgsをほぼ等しいとすると,トランジス
タ1のソース電極の電圧は,トランジスタ2のソース電
極の電圧よりa高くなる。従って,抵抗R1の両端の電
位差は,aとなり,抵抗R1に流れる電流は,a/R1
になる。定電流源10,11の電流値は等しいので,ト
ランジスタ2に流れる電流は,トランジスタ1に流れる
電流よりa/R1多い。トランジスタ4に流れる電流
は,トランジスタ3に流れる電流よりもa/R1多く,
トランジスタ6に流れる電流は,トランジスタ5に流れ
る電流よりa/R1多くなる。トランジスタ8に流れる
電流は,トランジスタ6に流れる電流よりa/R1少な
いので,抵抗R2には,オペアンプ14の出力端子から
オペアンプ14の反転入力端子の方向にa/R1の電流
が流れる。抵抗R2の両端の電位差は,抵抗値R2に電
流値a/R1を掛けa*R2/R1となる。
Next, the case where the positive input terminal is higher than the voltage of the negative input terminal by a (Volt) will be described. Assuming that the Vgs of the transistors 1 and 2 are substantially equal, the voltage of the source electrode of the transistor 1 becomes higher than the voltage of the source electrode of the transistor 2 by a. Therefore, the potential difference across the resistor R1 is a, and the current flowing through the resistor R1 is a / R1.
become. Since the current values of the constant current sources 10 and 11 are equal, the current flowing through the transistor 2 is larger than the current flowing through the transistor 1 by a / R1. The current flowing through the transistor 4 is a / R1 larger than the current flowing through the transistor 3,
The current flowing through the transistor 6 is a / R1 larger than the current flowing through the transistor 5. Since the current flowing through the transistor 8 is smaller than the current flowing through the transistor 6 by a / R1, a current of a / R1 flows through the resistor R2 from the output terminal of the operational amplifier 14 to the inverting input terminal of the operational amplifier 14. The potential difference across the resistor R2 becomes a * R2 / R1 by multiplying the resistance value R2 by the current value a / R1.

【0014】出力端子には,Vbを基準にすると,a*
R2/R1の電圧が発生する。即ち正負入力端子間の電
位差aをR2/R1倍した出力をうることができる。正
負入力端子に,前述したのとは逆に−a(Volt)の
電位差がある場合には,出力は,−a*R2/R1の電
圧値となる。
With respect to Vb as a reference, the output terminal has a *
A voltage of R2 / R1 is generated. That is, an output obtained by multiplying the potential difference a between the positive and negative input terminals by R2 / R1 can be obtained. When the positive and negative input terminals have a potential difference of −a (Volt), which is the opposite of the above, the output has a voltage value of −a * R2 / R1.

【0015】図1の回路で,正負の入力端子は,各々ト
ランジスタ1,2のゲート電極に接続している。ゲート
電極は,一般的に,インピーダンスが高く直流をほとん
ど通さない。従って図1の回路の前段には,駆動能力の
少ない回路を接続できる。
In the circuit of FIG. 1, positive and negative input terminals are connected to the gate electrodes of the transistors 1 and 2, respectively. The gate electrode generally has high impedance and hardly passes direct current. Therefore, a circuit having a small driving capability can be connected to the front stage of the circuit shown in FIG.

【0016】図3の回路は,図1の回路の定電流源1
0,11を,ゲート電極を一定の電圧値Vcに接続した
トランジスタ10,11で実現している。トランジスタ
10,11のソース電極は電源端子に接続し,ドレイン
電極は,各々トランジスタ1,2のソース電極に共通に
接続している。トランジスタ10,11は,ゲート電圧
が一定なので,ほぼ一定の電流が流れる。図3の回路
は,トランジスタと抵抗だけで構成しているので,集積
回路化に適する。
The circuit of FIG. 3 is the constant current source 1 of the circuit of FIG.
0 and 11 are realized by transistors 10 and 11 whose gate electrodes are connected to a constant voltage value Vc. The source electrodes of the transistors 10 and 11 are connected to the power supply terminal, and the drain electrodes are commonly connected to the source electrodes of the transistors 1 and 2, respectively. Since the gate voltage is constant in the transistors 10 and 11, a substantially constant current flows. Since the circuit of FIG. 3 is composed of only a transistor and a resistor, it is suitable for an integrated circuit.

【0017】図4の回路は,図1の回路にトランジスタ
21,22,23,24を追加したものである。トラン
ジスタ21のドレイン電極は電源に接続し,ゲート電極
は正入力端子に接続し,ソース電極はトランジスタ1の
ゲート電極とトランジスタ23のドレイン電極に共通に
接続している。トランジスタ22のドレイン電極は電源
端子に接続し,ゲート電極は負入力端子に接続しソース
電極はトランジスタ2のゲート電極とトランジスタ24
のドレイン電極に共通に接続している。トランジスタ2
3のゲート電極は,トランジスタ4のゲート電極とドレ
イン電極とトランジスタ6のゲート電極に共通に接続
し,ソース電極はGND電位に接続している。トランジ
スタ24のゲート電極はトランジスタ3のゲート電極と
ドレイン電極とトランジスタ5のゲート電極に共通に接
続し,ソース電極はGND電位に接続している。トラン
ジスタ21,22,23,24以外の部分は,図1の回
路と同一で,各回路要素は,図1の回路と同一の動作を
行う。
The circuit of FIG. 4 is obtained by adding transistors 21, 22, 23 and 24 to the circuit of FIG. The drain electrode of the transistor 21 is connected to the power supply, the gate electrode is connected to the positive input terminal, and the source electrode is commonly connected to the gate electrode of the transistor 1 and the drain electrode of the transistor 23. The drain electrode of the transistor 22 is connected to the power supply terminal, the gate electrode is connected to the negative input terminal, and the source electrode is the gate electrode of the transistor 2 and the transistor 24.
Is commonly connected to the drain electrode of. Transistor 2
The gate electrode of 3 is commonly connected to the gate electrode and drain electrode of the transistor 4 and the gate electrode of the transistor 6, and the source electrode thereof is connected to the GND potential. The gate electrode of the transistor 24 is commonly connected to the gate electrode and drain electrode of the transistor 3 and the gate electrode of the transistor 5, and the source electrode thereof is connected to the GND potential. The parts other than the transistors 21, 22, 23, and 24 are the same as the circuit of FIG. 1, and each circuit element performs the same operation as the circuit of FIG.

【0018】図4の回路において,トランジスタ24の
サイズとトランジスタ3のサイズは等しく,トランジス
タ23のサイズとトランジスタ4のサイズは等しい。ト
ランジスタ23と4,トランジスタ24と3は各々ゲー
ト電極が共通に接続しているので,トランジスタ23と
4,トランジスタ24と3に流れる電流は等しい。トラ
ンジスタ1,2,21,22の電圧電流変換係数(β)
を等しくなるようにサイズを設定する。
In the circuit of FIG. 4, the size of the transistor 24 and the size of the transistor 3 are the same, and the size of the transistor 23 and the size of the transistor 4 are the same. Since the gate electrodes of the transistors 23 and 4 and the transistors 24 and 3 are commonly connected, the currents flowing through the transistors 23, 4, and 24 and 3 are equal. Voltage-current conversion coefficient (β) of transistors 1, 2, 21, 22
Set the sizes so that they are equal.

【0019】最初に正負の入力端子の電圧差が0のとき
について説明する。トランジスタ1,2に流れる電流は
等く,トランジスタ3,4に流れる電流,トランジスタ
23,24に流れる電流,トランジスタ21,22に流
れる電流も等しい。電流が等しいので,トランジスタ2
2,21,トランジスタ1,2のゲート電極とソース電
極間の電圧Vgsは等しく,抵抗R1の両端の電圧も等
しいので,抵抗R1には,電流が流れない。トランジス
タ5,6はゲート電極が各々トランジスタ3,4のゲー
ト電極と共通に接続し,所謂カレントミラー回路を構成
している。したがって,トランジスタ5,6に流れる電
流は,トランジスタ3,4に流れる電流にトランジスタ
サイズ比を乗じたものになる。トランジスタ7,8も同
様に,ゲート電極が共通に接続され,所謂カレントミラ
ー回路を構成しているので,トランジスタ8に流れる電
流は,トランジスタ7に流れる電流にトランジスタサイ
ズ比を乗じたものになる。
First, the case where the voltage difference between the positive and negative input terminals is 0 will be described. The currents flowing through the transistors 1 and 2 are equal, and the currents flowing through the transistors 3 and 4, the currents flowing through the transistors 23 and 24, and the currents flowing through the transistors 21 and 22 are equal. Since the currents are equal, transistor 2
Since the voltage Vgs between the gate electrodes and the source electrodes of the transistors 2 and 21 and the transistors 1 and 2 is equal, and the voltage across the resistor R1 is also equal, no current flows through the resistor R1. The gate electrodes of the transistors 5 and 6 are commonly connected to the gate electrodes of the transistors 3 and 4, respectively, to form a so-called current mirror circuit. Therefore, the current flowing through the transistors 5 and 6 is the current flowing through the transistors 3 and 4 multiplied by the transistor size ratio. Similarly, since the gate electrodes of the transistors 7 and 8 are commonly connected to form a so-called current mirror circuit, the current flowing through the transistor 8 is the current flowing through the transistor 7 multiplied by the transistor size ratio.

【0020】次に,正入力端子が,負入力端子の電圧よ
りa(Volt)高い場合について説明する。図1の説
明においては,トランジスタ1,2のVgsがほぼ等し
いとしたが,実際は,トランジスタ21,22,トラン
ジスタ1,2のVgsは,流れる電流が異なるためにわ
ずかではあるが異なる。
Next, the case where the positive input terminal is higher than the voltage of the negative input terminal by a (Volt) will be described. In the description of FIG. 1, it is assumed that the Vgs of the transistors 1 and 2 are almost equal, but in reality, the Vgs of the transistors 21, 22 and 1 are slightly different because the flowing currents are different.

【0021】トランジスタの電流−電圧変換係数をβ,
トランジスタに流れる電流をId,トランジスタ1,2
に流れる電流差とトランジスタ21,22に流れる電流
差をΔId,トランジスタの閾値電圧をVthとする
と,一般的にトランジスタに流れる電流は, Id=(β/2)*(Vgs−Vth)**2 (**2は2乗を表す)(1) で表すことができる,これから,トランジスタ1,2,
トランジスタ21,22のVgsの差,ΔVgsは,片
方のトランジスタにΔId多く電流が流れているとする
と, ΔVgs=√((Id+ΔId)/(2*β))−√(Id/(2*β))(2 ) で表現できる。
The current-voltage conversion coefficient of the transistor is β,
Id is the current flowing through the transistor, and transistors 1 and 2 are
Assuming that the difference between the current flowing through the transistor and the current flowing through the transistors 21 and 22 is ΔId and the threshold voltage of the transistor is Vth, the current flowing through the transistor is generally Id = (β / 2) * (Vgs−Vth) ** 2 (** 2 represents the square) (1) can be expressed as
The difference between the Vgs of the transistors 21 and 22 and ΔVgs is ΔVgs = √ ((Id + ΔId) / (2 * β)) − √ (Id / (2 * β), assuming that a large amount of ΔId flows in one transistor. ) (2)

【0022】定電流源10,11に流れる電流は等しい
ので,トランジスタ1,2に流れる電流の差は,抵抗R
1に流れる電流となる。ここで正入力端子の電圧が負入
力端子の電圧よりa(V)高いので,トランジスタ21
のソース電極の電圧は,トランジスタ22のソース電極
の電圧よりa高く,トランジスタ1のソース電極の電圧
はトランジスタ2のソース電極の電圧からa高い。抵抗
R1は,両端がトランジスタ1,2のソース電極に接続
されているので,抵抗R1の両端の電位差は,aとな
る。抵抗R1には,a/R1の電流が流れているので,
トランジスタ2の方がΔId電流が多い。トランジスタ
2とトランジスタ1のVgsの差は式(2)で表現でき
るので,トランジスタ2のVgsの方が,トランジスタ
1のVgsより式(2)のΔVgs大きい。
Since the currents flowing through the constant current sources 10 and 11 are equal, the difference between the currents flowing through the transistors 1 and 2 is the resistance R
It becomes the electric current which flows into 1. Since the voltage at the positive input terminal is higher than the voltage at the negative input terminal by a (V), the transistor 21
Is higher than the voltage of the source electrode of the transistor 22 by a, and the voltage of the source electrode of the transistor 1 is higher by a than the voltage of the source electrode of the transistor 2. Since both ends of the resistor R1 are connected to the source electrodes of the transistors 1 and 2, the potential difference between both ends of the resistor R1 is a. Since the current of a / R1 flows through the resistor R1,
The transistor 2 has a larger ΔId current. Since the difference in Vgs between the transistor 2 and the transistor 1 can be expressed by the equation (2), the Vgs of the transistor 2 is larger than the Vgs of the transistor 1 by ΔVgs of the equation (2).

【0023】トランジスタ2に流れる電流は,トランジ
スタ4,23,21に流れる電流と等しく,トランジス
タ1に流れる電流は,トランジスタ3,24,22に流
れる電流と等しい。従ってトランジスタ21とトランジ
スタ22に流れる電流差ΔIdは,トランジスタ1,2
の電流差ΔIdと等しい。即ちトランジスタ21には,
トランジスタ22よりΔId多い電流が流れている。ト
ランジスタ21と22のVgsの差は同様に式(2)で
表すことができ,トランジスタ21の方がΔVgsだけ
Vgsが大きい。
The current flowing through the transistor 2 is equal to the current flowing through the transistors 4, 23 and 21, and the current flowing through the transistor 1 is equal to the current flowing through the transistors 3, 24 and 22. Therefore, the current difference ΔId flowing between the transistor 21 and the transistor 22 is
Is equal to the current difference ΔId. That is, in the transistor 21,
A current larger than that of the transistor 22 by ΔId is flowing. Similarly, the difference in Vgs between the transistors 21 and 22 can be expressed by the equation (2), and the transistor 21 has a larger Vgs by ΔVgs.

【0024】正負入力端子の電圧差がaの時,トランジ
スタ21,22のソース電極の電位差は,正確には,a
+ΔVgsとなる,トランジスタ1,2ゲート電極の電
位差は,当然a+ΔVgsとなり,トランジスタ1,2
のソース電極の電位差は,これからΔVgsを引いたa
となる。トランジスタ21,22,23,24が無い場
合には,抵抗R1の両端には,正確には,a+Vgsの
電圧が掛かり,ΔVgs分の誤差が生じる,図4の回路
では,トランジスタ21,22のΔVgsが,トランジ
スタ1,2のΔVgsを打ち消すので,抵抗R1の両端
の電位差と,正負入力端子の電位差が正確に等しくな
る。図4の回路は,図1の回路より誤差の少ない増幅回
路を提供できる。
When the voltage difference between the positive and negative input terminals is a, the potential difference between the source electrodes of the transistors 21 and 22 is exactly a
The potential difference between the gate electrodes of the transistors 1 and 2, which is + ΔVgs, is naturally a + ΔVgs, and
The potential difference of the source electrode of is a minus ΔVgs
Becomes In the absence of the transistors 21, 22, 23, and 24, to be precise, a voltage of a + Vgs is applied across the resistor R1 and an error of ΔVgs is generated. In the circuit of FIG. 4, the ΔVgs of the transistors 21 and 22 is increased. However, since ΔVgs of the transistors 1 and 2 is canceled, the potential difference between both ends of the resistor R1 and the potential difference between the positive and negative input terminals are exactly equal. The circuit of FIG. 4 can provide an amplifier circuit with less error than the circuit of FIG.

【0025】図4の回路の後半の回路動作について説明
する。図1の回路とまったく同一である。トランジスタ
2に流れる電流は,トランジスタ1に流れる電流よりa
/R1多い。トランジスタ4に流れる電流は,トランジ
スタ3に流れる電流よりもa/R1多く,トランジスタ
6に流れる電流は,トランジスタ5に流れる電流よりa
/R1多くなる。トランジスタ8に流れる電流は,トラ
ンジスタ6に流れる電流よりa/R1少ないので,抵抗
R2には,オペアンプ14の出力端子からオペアンプ1
4の反転入力端子の方向にa/R1の電流が流れる。抵
抗R2の両端の電位差は,抵抗値R2に電流値a/R1
を掛けa*R2/R1となる。
The circuit operation of the latter half of the circuit shown in FIG. 4 will be described. It is exactly the same as the circuit of FIG. The current flowing through the transistor 2 is a
/ R1 is large. The current flowing through the transistor 4 is a / R1 larger than the current flowing through the transistor 3, and the current flowing through the transistor 6 is a / R1 larger than the current flowing through the transistor 5.
/ R1 increases. Since the current flowing through the transistor 8 is smaller than the current flowing through the transistor 6 by a / R1, the resistor R2 is connected to the operational amplifier 1 through the output terminal of the operational amplifier 14.
The current of a / R1 flows in the direction of the inverting input terminal of No. 4. The potential difference between both ends of the resistor R2 is calculated by adding the current value a / R1 to the resistance value R2.
Multiply a * R2 / R1.

【0026】出力端子には,Vbを基準にすると,a*
R2/R1の電圧が発生する。即ち正負入力端子間の電
位差aをR2/R1倍した出力をうることができる。正
負入力端子に,前述したのとは逆に−a(Volt)の
電位差がある場合には,出力は,−a*R2/R1の電
圧値となる。
At the output terminal, when Vb is the reference, a *
A voltage of R2 / R1 is generated. That is, an output obtained by multiplying the potential difference a between the positive and negative input terminals by R2 / R1 can be obtained. When the positive and negative input terminals have a potential difference of −a (Volt), which is the opposite of the above, the output has a voltage value of −a * R2 / R1.

【0027】図5の回路は,図1の回路にトランジスタ
31,32,33,34とトランジスタ41,42,4
3,44を追加したものである。
The circuit of FIG. 5 differs from the circuit of FIG. 1 in that transistors 31, 32, 33 and 34 and transistors 41, 42 and 4 are included.
3,44 is added.

【0028】トランジスタ31のドレイン電極はGND
電位に接続しゲート電極は正入力端子に接続しソース電
極はトランジスタ1のゲート電極とトランジスタ32の
ドレイン電極に共通に接続する。トランジスタ32のゲ
ート電極はトランジスタ33のゲート電極とドレイン電
極とトランジスタ34のドレイン電極に共通に接続しソ
ース電極は電源端子に接続する。トランジスタ33のソ
ース電極は電源に接続する。トランジスタ34のゲート
電極は,トランジスタ4のドレイン電極とゲート電極に
共通に接続しソース電極はGND電位に接続する。トラ
ンジスタ41のドレイン電極はGND電位に接続しゲー
ト電極は負入力端子に接続しソース電極はトランジスタ
2のゲート電極とトランジスタ42のドレイン電極に共
通に接続する。トランジスタ42のゲート電極はトラン
ジスタ43のゲート電極とドレイン電極とトランジスタ
44のドレイン電極に共通に接続しソース電極は電源端
子に接続する。トランジスタ43のソース電極は電源に
接続する。トランジスタ44のゲート電極は,トランジ
スタ5のドレイン電極とゲート電極に共通に接続しソー
ス電極はGND電位に接続する。
The drain electrode of the transistor 31 is GND
The gate electrode is connected to the potential, the gate electrode is connected to the positive input terminal, and the source electrode is commonly connected to the gate electrode of the transistor 1 and the drain electrode of the transistor 32. The gate electrode of the transistor 32 is commonly connected to the gate electrode and drain electrode of the transistor 33 and the drain electrode of the transistor 34, and the source electrode is connected to the power supply terminal. The source electrode of the transistor 33 is connected to the power supply. The gate electrode of the transistor 34 is commonly connected to the drain electrode and the gate electrode of the transistor 4, and the source electrode is connected to the GND potential. The drain electrode of the transistor 41 is connected to the GND potential, the gate electrode is connected to the negative input terminal, and the source electrode is commonly connected to the gate electrode of the transistor 2 and the drain electrode of the transistor 42. The gate electrode of the transistor 42 is commonly connected to the gate electrode and drain electrode of the transistor 43 and the drain electrode of the transistor 44, and the source electrode is connected to the power supply terminal. The source electrode of the transistor 43 is connected to the power supply. The gate electrode of the transistor 44 is commonly connected to the drain electrode and the gate electrode of the transistor 5, and the source electrode is connected to the GND potential.

【0029】トランジスタ31,32,33,34,4
1,42,43,44以外の回路は,図1と全く同じ
で,同一要素は,同一機能を果たす。
Transistors 31, 32, 33, 34, 4
The circuits other than 1, 42, 43 and 44 are exactly the same as those in FIG. 1, and the same elements perform the same functions.

【0030】トランジスタ3と44,トランジスタ4と
34,トランジスタ33と32,トランジスタ43と4
2のサイズは等しく,トランジスタ1,2,31,41
のサイズは等しくβも等しい。トランジスタ3と44,
トランジスタ4と34,トランジスタ33と32,トラ
ンジスタ43と42はゲート電極が各々共通に接続され
ておりVgsが等しいので,流れる電流は各々等しい。
従ってトランジスタ31には,トランジスタ2と同じ電
流が流れ,トランジスタ41には,トランジスタ1と同
じ電流が流れる。
Transistors 3 and 44, Transistors 4 and 34, Transistors 33 and 32, Transistors 43 and 4
2 have the same size, and transistors 1, 2, 31, 41
Have the same size and β have the same size. Transistors 3 and 44,
The gate electrodes of the transistors 4 and 34, the transistors 33 and 32, and the transistors 43 and 42 are commonly connected to each other, and the Vgs are equal, so that the flowing currents are equal to each other.
Therefore, the same current as the transistor 2 flows through the transistor 31, and the same current as the transistor 1 flows through the transistor 41.

【0031】図5の回路は,図4の回路においてトラン
ジスタ21,22,23,24で構成された所謂ソース
フォロア回路を,トランジスタ31,32,33,34
とトランジスタ41,42,43,44で構成したもの
である。図5の回路では,ソースフォロア回路のトラン
ジスタ31,41は,トランジスタ1,2と極性が等し
いので,サイズを等しくすることにより容易にβを等し
くすることが出来る。図5の回路は,機能的には,図4
の回路と同じ動作を行う。
The circuit of FIG. 5 is a so-called source follower circuit composed of the transistors 21, 22, 23 and 24 in the circuit of FIG.
And transistors 41, 42, 43 and 44. In the circuit of FIG. 5, since the transistors 31 and 41 of the source follower circuit have the same polarity as the transistors 1 and 2, β can be easily made equal by making the sizes equal. The circuit of FIG. 5 is functionally equivalent to that of FIG.
Performs the same operation as the circuit.

【0032】抵抗R1の両端にa(V)の電位差が発生
しており,トランジスタ1のソース電極の電圧がトラン
ジスタ2のソース電極の電圧より高いとする。抵抗R1
には,a/R1の電流が流れる。一方定電流源10と1
1の電流値は同一なのでトランジスタ2の方がトランジ
スタ1より電流値がa/R1大きい。トランジスタ1,
2の電流差をΔId=a/R1とすると,トランジスタ
1,2のVgsの電位差ΔVgsは式(2)により求め
られる。従って,トランジスタ1,2のゲート電極の電
位差は,a+ΔVgsとなる。トランジスタ31に流れ
る電流は,トランジスタ2,4に流れる電流と等しく,
トランジスタ41に流れる電流はトランジスタ1,3に
流れる電流と等しいので,トランジスタ31には,トラ
ンジスタ41に比較してΔId=a/R1多い電流が流
れる。従ってトランジスタ31と41のVgsの電位差
ΔVgsは,同様に式(2)から求めることができ,ト
ランジスタ2,1のΔVgsと同じ値になる。
It is assumed that a potential difference of a (V) is generated across the resistor R1 and the voltage of the source electrode of the transistor 1 is higher than the voltage of the source electrode of the transistor 2. Resistance R1
, A current of a / R1 flows. On the other hand, constant current sources 10 and 1
Since the current value of 1 is the same, the current value of transistor 2 is larger than that of transistor 1 by a / R1. Transistor 1,
Assuming that the current difference of 2 is ΔId = a / R1, the potential difference ΔVgs of Vgs of the transistors 1 and 2 can be obtained by the equation (2). Therefore, the potential difference between the gate electrodes of the transistors 1 and 2 is a + ΔVgs. The current flowing through the transistor 31 is equal to the current flowing through the transistors 2 and 4,
Since the current flowing through the transistor 41 is equal to the current flowing through the transistors 1 and 3, the current flowing through the transistor 31 is larger by ΔId = a / R1 than the current flowing through the transistor 41. Therefore, the potential difference ΔVgs of Vgs of the transistors 31 and 41 can be similarly obtained from the equation (2) and has the same value as ΔVgs of the transistors 2 and 1.

【0033】トランジスタ31,41のソース電極は,
各々トランジスタ1,2のゲート電極と同一に接続して
いるので,電位差は,a+ΔVgsである。前述したよ
うにトランジスタ31,41のΔVgsは,トランジス
タ1,2のΔVgsと等しいので,正負入力端子間の電
圧は,aである。即ち,図5の回路は,図4の回路と同
様に,正負入力端子間の電圧が,抵抗R1の電圧と等し
くなり,トランジスタに流れる電流の差に影響されるこ
とがない。
The source electrodes of the transistors 31 and 41 are
Since they are connected to the gate electrodes of the transistors 1 and 2, respectively, the potential difference is a + ΔVgs. As described above, since ΔVgs of the transistors 31 and 41 is equal to ΔVgs of the transistors 1 and 2, the voltage between the positive and negative input terminals is a. That is, in the circuit of FIG. 5, like the circuit of FIG. 4, the voltage between the positive and negative input terminals becomes equal to the voltage of the resistor R1 and is not affected by the difference in current flowing through the transistor.

【0034】図5の回路の後半の回路動作について説明
する。図1の回路とまったく同一である。トランジスタ
2に流れる電流は,トランジスタ1に流れる電流よりa
/R1多い。トランジスタ4に流れる電流は,トランジ
スタ3に流れる電流よりもa/R1多く,トランジスタ
6に流れる電流は,トランジスタ5に流れる電流よりa
/R1多くなる。トランジスタ8に流れる電流は,トラ
ンジスタ6に流れる電流よりa/R1少ないので,抵抗
R2には,オペアンプ14の出力端子からオペアンプ1
4の反転入力端子の方向にa/R1の電流が流れる。抵
抗R2の両端の電位差は,抵抗値R2に電流値a/R1
を掛けa*R2/R1となる。
The circuit operation of the latter half of the circuit of FIG. 5 will be described. It is exactly the same as the circuit of FIG. The current flowing through the transistor 2 is a
/ R1 is large. The current flowing through the transistor 4 is a / R1 larger than the current flowing through the transistor 3, and the current flowing through the transistor 6 is a / R1 larger than the current flowing through the transistor 5.
/ R1 increases. Since the current flowing through the transistor 8 is smaller than the current flowing through the transistor 6 by a / R1, the resistor R2 is connected to the operational amplifier 1 through the output terminal of the operational amplifier 14.
The current of a / R1 flows in the direction of the inverting input terminal of No. 4. The potential difference between both ends of the resistor R2 is calculated by adding the current value a / R1 to the resistance value R2.
Multiply a * R2 / R1.

【0035】出力端子には,Vbを基準にすると,a*
R2/R1の電圧が発生する。即ち正負入力端子間の電
位差aをR2/R1倍した出力をうることができる。正
負入力端子に,前述したのとは逆に−a(Volt)の
電位差がある場合には,出力は,−a*R2/R1の電
圧値となる。
The output terminal has a *
A voltage of R2 / R1 is generated. That is, an output obtained by multiplying the potential difference a between the positive and negative input terminals by R2 / R1 can be obtained. When the positive and negative input terminals have a potential difference of −a (Volt), which is the opposite of the above, the output has a voltage value of −a * R2 / R1.

【0036】図6の回路は,図4の回路の抵抗13,オ
ペアンプ14,基準電圧Vbを容量Cで置き換えたもの
である。トランジスタ8,6のドレイン電極からは,正
負入力端子の電位差aに比例したa/R1の電流が出力
される。出力端子,即ち容量Cの両端に発生する電圧
は,電流値a/R1を時間で積分したものを容量値Cで
割ったものである。図6の回路は,図4の回路で説明し
たように,正負入力端子間の電位差が正確に抵抗R1の
両端の電位差と等しくなる。出力する電流は,トランジ
スタ1,2を流れる電流の差に影響されることがない。
The circuit of FIG. 6 is obtained by replacing the resistor 13, the operational amplifier 14, and the reference voltage Vb of the circuit of FIG. 4 with a capacitor C. From the drain electrodes of the transistors 8 and 6, a current of a / R1 proportional to the potential difference a at the positive and negative input terminals is output. The voltage generated at both ends of the output terminal, that is, the capacitance C is obtained by dividing the current value a / R1 by time and dividing it by the capacitance value C. In the circuit of FIG. 6, as described in the circuit of FIG. 4, the potential difference between the positive and negative input terminals is exactly equal to the potential difference across the resistor R1. The output current is not affected by the difference between the currents flowing through the transistors 1 and 2.

【0037】図6の回路で容量C以外の回路は,一般的
に,VI変換回路50(電圧電流変換回路)として使用
することが出来る。即ち,正負入力端子間の電位差(電
圧差)を,正確に電流に変換できる。
In the circuit of FIG. 6, circuits other than the capacitor C can be generally used as the VI conversion circuit 50 (voltage current conversion circuit). That is, the potential difference (voltage difference) between the positive and negative input terminals can be accurately converted into a current.

【0038】図7の回路は,図6中のVI変換回路50
を,フィルタの抵抗の代わりに使用したものである。正
入力端子に,入力信号を入力する。負入力端子は,出力
端子に接続する。図7のVI変換回路50は,正入力端
子と出力端子の電位差に比例した電流を出力する。電圧
と電流の変換係数はR1になる。即ち図7のVI変換回
路50は,抵抗R1と同じ機能をする。さらに,VI変
換回路50に図6の回路を用いれば,正負入力端子間の
電位差が,内部トランジスタのVgs差に影響されるこ
となく正確に電流に変換できるので,フィルタの抵抗と
して用いた場合に,抵抗値を正確に実現できる。
The circuit shown in FIG. 7 is the VI conversion circuit 50 shown in FIG.
Is used instead of the resistance of the filter. Input the input signal to the positive input terminal. The negative input terminal is connected to the output terminal. The VI conversion circuit 50 of FIG. 7 outputs a current proportional to the potential difference between the positive input terminal and the output terminal. The conversion coefficient of voltage and current becomes R1. That is, the VI conversion circuit 50 in FIG. 7 has the same function as the resistor R1. Further, if the circuit of FIG. 6 is used as the VI conversion circuit 50, the potential difference between the positive and negative input terminals can be accurately converted into a current without being affected by the Vgs difference of the internal transistor, and therefore, when used as a filter resistor. , The resistance value can be realized accurately.

【0039】[0039]

【発明の効果】以上説明したごとく,本発明によれば,
正負入力端子を,トランジスタのゲート電極に接続して
いるので,入力インピーダンスの極めて大きな増幅回路
を提供できる。さらに,ソースフォロア回路を付加する
ことにより,トランジスタに流れる電流差で生じる誤差
を,打ち消しているので,正確な増幅率を得ることが出
来る。
As described above, according to the present invention,
Since the positive and negative input terminals are connected to the gate electrode of the transistor, it is possible to provide an amplifier circuit having an extremely large input impedance. Further, by adding a source follower circuit, an error caused by a difference in current flowing through the transistor is canceled out, so that an accurate amplification factor can be obtained.

【0040】図1の回路では,正負入力端子間の電圧を
aとすると,抵抗R1の両端には,正確には,a+ΔV
gsの電圧が発生する。ΔVgsは,トランジスタ1,
2の電流差ΔIdによるVgsの差であり,式(2)で
求めることができる。図4の回路では,入力端子間の電
圧aに対して,出力電圧は,(a+ΔVgs)×R2/
R1となり誤差が生じる。
In the circuit of FIG. 1, assuming that the voltage between the positive and negative input terminals is a, to be precise, a + ΔV is present across the resistor R1.
A voltage of gs is generated. ΔVgs is the transistor 1,
It is the difference in Vgs due to the current difference ΔId of 2 and can be obtained by the equation (2). In the circuit of FIG. 4, the output voltage is (a + ΔVgs) × R2 /
It becomes R1 and an error occurs.

【0041】一方,図4の回路で,抵抗R1の両端にa
(V)の電位差が発生しており,トランジスタ1のソー
ス電極の電圧がトランジスタ2のソース電極の電圧より
高いとする。抵抗R1には,a/R1の電流が流れる。
一方定電流源10と11の電流値は同一なのでトランジ
スタ2の方がトランジスタ1より電流値がa/R1大き
い。トランジスタ1,2の電流差をΔId=a/R1と
すると,トランジスタ1,2のVgsの電位差ΔVgs
は式(2)により求められる。従って,トランジスタ
1,2のゲート電極の電位差は,a+ΔVgsとなる。
On the other hand, in the circuit of FIG.
It is assumed that the potential difference of (V) is generated and the voltage of the source electrode of the transistor 1 is higher than the voltage of the source electrode of the transistor 2. A current of a / R1 flows through the resistor R1.
On the other hand, since the constant current sources 10 and 11 have the same current value, the transistor 2 has a larger current value a / R1 than the transistor 1. Assuming that the current difference between the transistors 1 and 2 is ΔId = a / R1, the potential difference ΔVgs between the Vgs of the transistors 1 and 2 is ΔVgs.
Is calculated by the equation (2). Therefore, the potential difference between the gate electrodes of the transistors 1 and 2 is a + ΔVgs.

【0042】トランジスタ21,22のソース電極は,
各々トランジスタ1,2のゲート電極と共通に接続して
いるので,電位差は,a+ΔVgsである。トランジス
タ21,22のΔVgsは,トランジスタ1,2のΔV
gsと等しいので,正負入力端子間の電圧は,aとな
る。即ち,図4の回路では,正負入力端子間の電圧が,
抵抗R1の電圧と等しくなり,トランジスタに流れる電
流の差に影響されることがない。したがって,出力電圧
は,正確に入力端子間の電圧a*R2/R1になる。
The source electrodes of the transistors 21 and 22 are
Since they are commonly connected to the gate electrodes of the transistors 1 and 2, the potential difference is a + ΔVgs. ΔVgs of the transistors 21 and 22 is ΔVgs of the transistors 1 and 2.
Since it is equal to gs, the voltage between the positive and negative input terminals is a. That is, in the circuit of FIG. 4, the voltage between the positive and negative input terminals is
It becomes equal to the voltage of the resistor R1 and is not affected by the difference in current flowing through the transistor. Therefore, the output voltage is exactly the voltage a * R2 / R1 between the input terminals.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示す回路図。FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【図2】従来の技術による増幅回路。FIG. 2 is an amplifier circuit according to the related art.

【図3】本発明の実施例を示す回路図。FIG. 3 is a circuit diagram showing an embodiment of the present invention.

【図4】本発明の実施例を示す回路図。FIG. 4 is a circuit diagram showing an embodiment of the present invention.

【図5】本発明の実施例を示す回路図。FIG. 5 is a circuit diagram showing an embodiment of the present invention.

【図6】本発明の実施例を示す回路図。FIG. 6 is a circuit diagram showing an embodiment of the present invention.

【図7】本発明の実施例を示す回路図。FIG. 7 is a circuit diagram showing an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1,2,3,4,5,6,7,8 トランジスタ 21,22,23,24 トランジスタ 31,32,33,34 トランジスタ 41,42,43,44 トランジスタ 10,11 定電流源 14 オペアンプ 12,13,16,17 抵抗 C 容量 50 VI変換回路 1,2,3,4,5,6,7,8 transistors 21,22,23,24 transistors 31, 32, 33, 34 transistors 41, 42, 43, 44 transistors 10, 11 constant current source 14 Operational amplifier 12, 13, 16, 17 resistance C capacity 50 VI conversion circuit

フロントページの続き Fターム(参考) 5J066 AA01 AA12 CA72 CA88 FA20 HA10 HA17 HA25 HA29 KA01 KA05 KA09 MA02 MA21 ND01 ND12 ND25 PD01 TA01 5J091 AA01 CA72 CA88 FA15 HA10 HA17 HA19 HA25 HA29 KA01 KA02 KA05 KA09 KA31 KA41 MA02 MA08 MA21 TA01 5J500 AA01 AA12 AC72 AC88 AF15 AF20 AH10 AH17 AH19 AH25 AH29 AK01 AK02 AK05 AK09 AK31 AK41 AM02 AM08 AM21 AT01 DN01 DN12 DN25 DP01Continued front page    F term (reference) 5J066 AA01 AA12 CA72 CA88 FA20                       HA10 HA17 HA25 HA29 KA01                       KA05 KA09 MA02 MA21 ND01                       ND12 ND25 PD01 TA01                 5J091 AA01 CA72 CA88 FA15 HA10                       HA17 HA19 HA25 HA29 KA01                       KA02 KA05 KA09 KA31 KA41                       MA02 MA08 MA21 TA01                 5J500 AA01 AA12 AC72 AC88 AF15                       AF20 AH10 AH17 AH19 AH25                       AH29 AK01 AK02 AK05 AK09                       AK31 AK41 AM02 AM08 AM21                       AT01 DN01 DN12 DN25 DP01

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 ドレイン電極を第3のトランジスタのド
レイン電極とゲート電極と第5のトランジスタのゲート
電極に共通に接続しゲート電極を正入力端子に接続しソ
ース電極を第1の抵抗の一端と第1の定電流源の一端に
共通に接続した第1のトランジスタと,ドレイン電極を
第4のトランジスタのゲート電極とドレイン電極と第6
のトランジスタのゲート電極に共通に接続しゲート電極
を負入力端子に接続しソース電極を前記第1の抵抗の他
端と第2の定電流源の一端に共通に接続した第2のトラ
ンジスタと,ソース電極をGND電位に接続した第3の
トランジスタと,ソース電極をGND電位に接続した第
4のトランジスタと,ドレイン電極を第7のトランジス
タのゲート電極とドレイン電極と第8のトランジスタの
ゲート電極に共通に接続しソース電極をGND電位に接
続した第5のトランジスタと,ドレイン電極を第8のト
ランジスタのドレイン電極と演算増幅回路の反転入力端
子と第2の抵抗の一端に共通に接続しソース電極をGN
D電極に接続した第6のトランジスタと,ソース電極を
電源に接続した第7のトランジスタと,ソース電極を電
源に接続した第8のトランジスタと,他端を電源に接続
した前記第1の定電流源と,他端を電源に接続した前記
第2の定電流源と,一端を前記演算増幅器の正入力端子
に他端をGND電位に接続した基準電圧源と,他端を出
力端子と前記演算増幅器の出力に共通に接続した前記第
2の抵抗と,前記演算増幅回路とで構成した増幅回路。
1. A drain electrode is commonly connected to a drain electrode and a gate electrode of a third transistor, and a gate electrode of a fifth transistor, a gate electrode is connected to a positive input terminal, and a source electrode is connected to one end of a first resistor. The first transistor commonly connected to one end of the first constant current source and the drain electrode are connected to the gate electrode and drain electrode of the fourth transistor and the sixth transistor.
A second transistor commonly connected to the gate electrode of the transistor, the gate electrode connected to the negative input terminal, and the source electrode commonly connected to the other end of the first resistor and one end of the second constant current source; A third transistor whose source electrode is connected to the GND potential, a fourth transistor whose source electrode is connected to the GND potential, and a drain electrode which is the gate electrode and drain electrode of the seventh transistor and a gate electrode of the eighth transistor. A fifth transistor, which is commonly connected and whose source electrode is connected to the GND potential, and a drain electrode, which is commonly connected to the drain electrode of the eighth transistor, the inverting input terminal of the operational amplifier circuit, and one end of the second resistor, and the source electrode GN
A sixth transistor connected to the D electrode, a seventh transistor whose source electrode is connected to the power source, an eighth transistor whose source electrode is connected to the power source, and the first constant current whose other end is connected to the power source Source, the second constant current source having the other end connected to the power supply, the reference voltage source having one end connected to the positive input terminal of the operational amplifier and the other end connected to the GND potential, and the other end to the output terminal and the operation. An amplifier circuit configured by the second resistor commonly connected to the output of the amplifier and the operational amplifier circuit.
【請求項2】 ドレイン電極を電源端子に接続しゲート
電極を正入力端子に接続しソース電極を第1のトランジ
スタのゲート電極と第23のトランジスタのドレイン電
極に共通に接続した第21のトランジスタと,ドレイン
電極を電源端子に接続しゲート電極を負入力端子に接続
しソース電極を第2のトランジスタのゲート電極と第2
4のトランジスタのドレイン電極に共通に接続した第2
2のトランジスタと,ゲート電極を第3のトランジスタ
のゲート電極に共通に接続しソース電極をGND電位に
接続した第24のトランジスタと,ゲート電極を第4の
トランジスタのゲート電極に共通に接続しソース電極を
GND電位に接続した第24のトランジスタと,ドレイ
ン電極を第3のトランジスタのドレイン電極とゲート電
極と第5のトランジスタのゲート電極に共通に接続しソ
ース電極を第1の抵抗の一端と第1の定電流源の一端に
共通に接続した第1のトランジスタと,ドレイン電極を
第4のトランジスタのゲート電極とドレイン電極と第6
のトランジスタのゲート電極に共通に接続しソース電極
を前記第1の抵抗の他端と第2の定電流源の一端に共通
に接続した第2のトランジスタと,ソース電極をGND
電位に接続した第3のトランジスタと,ソース電極をG
ND電位に接続した第4のトランジスタと,ドレイン電
極を第7のトランジスタのゲート電極とドレイン電極と
第8のトランジスタのゲート電極に共通に接続しソース
電極をGND電位に接続した第5のトランジスタと,ド
レイン電極を第8のトランジスタのドレイン電極と演算
増幅回路の反転入力端子と第2の抵抗の一端に共通に接
続しソース電極をGND電極に接続した第6のトランジ
スタと,ソース電極を電源に接続した第7のトランジス
タと,ソース電極を電源に接続した第8のトランジスタ
と,他端を電源に接続した前記第1の定電流源と,他端
を電源に接続した前記第2の定電流源と,一端を前記演
算増幅器の正入力端子に他端をGND電位に接続した基
準電圧源と,他端を出力端子と前記演算増幅器の出力に
共通に接続した前記第2の抵抗と,前記演算増幅回路と
で構成した増幅回路。
2. A twenty-first transistor having a drain electrode connected to a power supply terminal, a gate electrode connected to a positive input terminal, and a source electrode commonly connected to the gate electrode of the first transistor and the drain electrode of the twenty-third transistor. , The drain electrode is connected to the power supply terminal, the gate electrode is connected to the negative input terminal, and the source electrode is connected to the gate electrode of the second transistor and the second
Second connected in common to the drain electrodes of the four transistors
The second transistor, the 24th transistor in which the gate electrode is commonly connected to the gate electrode of the third transistor and the source electrode is connected to the GND potential, and the gate electrode is commonly connected to the gate electrode of the fourth transistor in the source A twenty-fourth transistor whose electrode is connected to the GND potential, a drain electrode commonly connected to the drain electrode and the gate electrode of the third transistor, and a gate electrode of the fifth transistor, and a source electrode to one end of the first resistor and a first resistor. The first transistor commonly connected to one end of the first constant current source and the drain electrode are connected to the gate electrode and the drain electrode of the fourth transistor and the sixth transistor.
The second transistor having the source electrode commonly connected to the gate electrode of the first transistor and the source electrode commonly connected to the other end of the first resistor and one end of the second constant current source
The third transistor connected to the electric potential and the source electrode are G
A fourth transistor connected to the ND potential, and a fifth transistor having a drain electrode commonly connected to the gate electrode and drain electrode of the seventh transistor and a gate electrode of the eighth transistor, and a source electrode connected to the GND potential. , The drain electrode of the eighth transistor, the inverting input terminal of the operational amplifier circuit and one end of the second resistor are commonly connected, and the source electrode is connected to the GND electrode and the sixth transistor is connected to the power source. A connected seventh transistor, an eighth transistor having a source electrode connected to a power supply, the first constant current source having the other end connected to a power supply, and a second constant current having the other end connected to a power supply Source, a reference voltage source having one end connected to the positive input terminal of the operational amplifier and the other end to the GND potential, and the other end commonly connected to the output terminal and the output of the operational amplifier. A second resistor, the amplifier circuit constituted by said operational amplifier circuit.
【請求項3】 ドレイン電極を電源端子に接続しゲート
電極を正入力端子に接続しソース電極を第1のトランジ
スタのゲート電極と第32のトランジスタのドレイン電
極に共通に接続した第31のトランジスタと,ドレイン
電極を電源端子に接続しゲート電極を負入力端子に接続
しソース電極を第2のトランジスタのゲート電極と第4
2のトランジスタのドレイン電極に共通に接続した第4
1のトランジスタと,ゲート電極を第33のトランジス
タのドレイン電極とゲート電極と第34のトランジスタ
のドレイン電極に共通に接続しソース電極を電源端子に
接続した第32のトランジスタと,ソース電極を電源端
子に接続した第33のトランジスタと,ゲート電極を第
4のトランジスタのゲート電極に共通に接続しソース電
極をGND電位に接続した第34のトランジスタと,ゲ
ート電極を第43のトランジスタのゲート電極とドレイ
ン電極と第44のトランジスタのドレイン電極に共通に
接続しソース電極を電源端子に接続した第42のトラン
ジスタと,ソース電極を電源端子に接続した第43のト
ランジスタと,ゲート電極を第3のトランジスタのゲー
ト電極に共通に接続しソース電極をGND電位に接続し
た第44のトランジスタと,ドレイン電極を第3のトラ
ンジスタのドレイン電極とゲート電極と第5のトランジ
スタのゲート電極に共通に接続しソース電極を第1の抵
抗の一端と第1の定電流源の一端に共通に接続した第1
のトランジスタと,ドレイン電極を第4のトランジスタ
のゲート電極とドレイン電極と第6のトランジスタのゲ
ート電極に共通に接続しソース電極を前記第1の抵抗の
他端と第2の定電流源の一端に共通に接続した第2のト
ランジスタと,ソース電極をGND電位に接続した第3
のトランジスタと,ソース電極をGND電位に接続した
第4のトランジスタと,ドレイン電極を第7のトランジ
スタのゲート電極とドレイン電極と第8のトランジスタ
のゲート電極に共通に接続しソース電極をGND電位に
接続した第5のトランジスタと,ドレイン電極を第8の
トランジスタのドレイン電極と演算増幅回路の反転入力
端子と第2の抵抗の一端に共通に接続しソース電極をG
ND電極に接続した第6のトランジスタと,ソース電極
を電源に接続した第7のトランジスタと,ソース電極を
電源に接続した第8のトランジスタと,他端を電源に接
続した前記第1の定電流源と,他端を電源に接続した前
記第2の定電流源と,一端を前記演算増幅器の正入力端
子に他端をGND電位に接続した基準電圧源と,他端を
出力端子と前記演算増幅器の出力に共通に接続した前記
第2の抵抗と,前記演算増幅回路とで構成した増幅回
路。
3. A 31st transistor in which a drain electrode is connected to a power supply terminal, a gate electrode is connected to a positive input terminal, and a source electrode is commonly connected to a gate electrode of a first transistor and a drain electrode of a 32nd transistor. , The drain electrode is connected to the power supply terminal, the gate electrode is connected to the negative input terminal, and the source electrode is connected to the gate electrode of the second transistor and the fourth electrode.
4th commonly connected to the drain electrodes of the 2nd transistor
1st transistor, 32nd transistor in which the gate electrode is commonly connected to the drain electrode and gate electrode of the 33rd transistor, and the drain electrode of the 34th transistor, and the source electrode is connected to the power supply terminal, and the source electrode is the power supply terminal Connected to the 33rd transistor, the 34th transistor whose gate electrode is commonly connected to the gate electrode of the 4th transistor and whose source electrode is connected to the GND potential, and its gate electrode is the gate electrode and drain of the 43rd transistor Of the transistor and the drain electrode of the forty-fourth transistor and the source electrode connected to the power supply terminal, the forty-second transistor, the source electrode connected to the power supply terminal, the forty-third transistor, and the gate electrode of the third transistor. The 44th transistor connected commonly to the gate electrode and the source electrode to the GND potential And the drain electrode of the third transistor are commonly connected to the drain electrode and gate electrode of the third transistor and the gate electrode of the fifth transistor, and the source electrode is commonly connected to one end of the first resistor and one end of the first constant current source. First connected
Transistor and drain electrode are commonly connected to the gate electrode and drain electrode of the fourth transistor and the gate electrode of the sixth transistor, and the source electrode is the other end of the first resistor and one end of the second constant current source. The second transistor commonly connected to the third transistor and the third transistor having the source electrode connected to the GND potential.
Transistor, a fourth transistor having a source electrode connected to the GND potential, and a drain electrode commonly connected to the gate electrode and the drain electrode of the seventh transistor and the gate electrode of the eighth transistor, and the source electrode to the GND potential. The connected fifth transistor and drain electrode are commonly connected to the drain electrode of the eighth transistor, the inverting input terminal of the operational amplifier circuit, and one end of the second resistor, and the source electrode is connected to G
A sixth transistor connected to the ND electrode, a seventh transistor whose source electrode is connected to a power source, an eighth transistor whose source electrode is connected to a power source, and the first constant current whose other end is connected to a power source Source, the second constant current source having the other end connected to the power supply, the reference voltage source having one end connected to the positive input terminal of the operational amplifier and the other end connected to the GND potential, and the other end to the output terminal and the operation. An amplifier circuit configured by the second resistor commonly connected to the output of the amplifier and the operational amplifier circuit.
JP2001301120A 2001-09-28 2001-09-28 Amplifier circuit Withdrawn JP2003110373A (en)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
JP2015149519A (en) * 2014-02-04 2015-08-20 株式会社村田製作所 power amplifier module

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JPS62161204A (en) * 1986-01-10 1987-07-17 Sony Corp Amplifier
JPH0393307A (en) * 1989-09-06 1991-04-18 Fujitsu Ltd LSI amplifier
JPH04317580A (en) * 1991-04-12 1992-11-09 Olympus Optical Co Ltd Current sense amplifier
JPH0828629B2 (en) * 1987-08-31 1996-03-21 三菱電機株式会社 Differential amplifier
JPH08242130A (en) * 1994-12-29 1996-09-17 Korea Telecommun Authority Operational transconductance amplifier
JPH0964663A (en) * 1995-08-29 1997-03-07 Toshiba Corp High dynamic range gm amplifier
JP2000504900A (en) * 1996-02-07 2000-04-18 マキシム インテグレイテッド プロダクツ,インコーポレイテッド Temperature compensated logarithmic detector
JP2000151311A (en) * 1998-11-13 2000-05-30 Matsushita Electric Ind Co Ltd Gain controller
WO2000044090A1 (en) * 1999-01-19 2000-07-27 Hitachi, Ltd. Semiconductor integrated circuit
JP2001094353A (en) * 1999-09-27 2001-04-06 Texas Instr Japan Ltd Gm AMPLIFIER

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Publication number Priority date Publication date Assignee Title
JPS5848514A (en) * 1981-09-18 1983-03-22 Matsushita Electric Ind Co Ltd Differential amplifying circuit
JPS62161204A (en) * 1986-01-10 1987-07-17 Sony Corp Amplifier
JPH0828629B2 (en) * 1987-08-31 1996-03-21 三菱電機株式会社 Differential amplifier
JPH0393307A (en) * 1989-09-06 1991-04-18 Fujitsu Ltd LSI amplifier
JPH04317580A (en) * 1991-04-12 1992-11-09 Olympus Optical Co Ltd Current sense amplifier
JPH08242130A (en) * 1994-12-29 1996-09-17 Korea Telecommun Authority Operational transconductance amplifier
JPH0964663A (en) * 1995-08-29 1997-03-07 Toshiba Corp High dynamic range gm amplifier
JP2000504900A (en) * 1996-02-07 2000-04-18 マキシム インテグレイテッド プロダクツ,インコーポレイテッド Temperature compensated logarithmic detector
JP2000151311A (en) * 1998-11-13 2000-05-30 Matsushita Electric Ind Co Ltd Gain controller
WO2000044090A1 (en) * 1999-01-19 2000-07-27 Hitachi, Ltd. Semiconductor integrated circuit
JP2001094353A (en) * 1999-09-27 2001-04-06 Texas Instr Japan Ltd Gm AMPLIFIER

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015149519A (en) * 2014-02-04 2015-08-20 株式会社村田製作所 power amplifier module
US9461594B2 (en) 2014-02-04 2016-10-04 Murata Manufacturing Co., Ltd. Power amplifier module

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