CN110350876B - Preamplifiers, pre-differential amplifiers, and integrated circuits - Google Patents

Abstract

The pre-amplifier comprises an input buffer unit and a gain amplifying unit, wherein the input buffer unit comprises a main source follower and an auxiliary source follower, and the auxiliary source follower is used for eliminating a channel length modulation effect of the main source follower; the first input end of the gain amplifying unit is connected with the output of the input buffer unit, the second input end of the gain amplifying unit is connected with a bias voltage, and the gain amplifying unit outputs an amplified signal after amplifying the signal output by the input buffer unit based on the bias voltage. The auxiliary source follower can eliminate the channel length modulation effect of the main source follower, so that the linearity and gain accuracy of the preamplifier are greatly improved.

Description

Preamplifiers, pre-differential amplifiers, and integrated circuits

Technical Field

The present application belongs to the technical field of CMOS integrated devices, and in particular relates to a preamplifier, a differential preamplifier and an integrated circuit.

Background Art

The main technical indicators of the preamplifier include: gain accuracy, noise, linearity, input and output impedance, power consumption, and whether it has a level shift function. The ideal preamplifier has the characteristics of precise and constant gain, no noise, no distortion, no mismatch, infinite input impedance, and 0 output impedance, which is obviously impossible. In reality, the preamplifier, like other analog circuits, follows the "octagonal rule" of analog circuit design, and there is a serious tradeoff between these indicators. It is very difficult and often impossible to design a preamplifier with extremely low noise and extremely high linearity while ensuring that other aspects of performance do not deteriorate.

Currently commonly used preamplifier structure:

The first is based on an operational amplifier, which is connected in a closed-loop feedback structure. This structure has only one stage, which serves as both an input buffer and a gain amplifier. It has the advantages of infinite input impedance, low output impedance, precise gain, and good linearity, and is widely used in various occasions. However, the problem with this structure is that the input signal needs to provide a suitable bias voltage for the op amp to work. This bias voltage is often generated by the chip and output to the sensor through the pin, and the sensor superimposes the bias voltage on the generated signal. This increases the complexity and unreliability of the solution. Some sensors cannot even apply a bias voltage at all (for example, the voltage and current sensors in the energy meter, whose bias voltage is naturally 0V).

The second is a standard 2-stage structure. Its input buffer stage is based on a source follower structure of a single MOS tube. It has the advantages of infinite input impedance and simple circuit. However, the gain accuracy and linearity of this structure are very general, and are greatly affected by PVT (process deviation, power supply fluctuation, temperature). In addition, the bottleneck is at the input buffer stage, which is mainly limited by the channel length modulation effect.

The third type is a standard 2-stage structure. Its input buffer stage is based on a source follower structure of a single PNP tube. Since the input buffer stage uses a triode and has no channel length modulation effect, its gain accuracy and linearity are very good and do not become a bottleneck. In addition, the main problem is that the input impedance is not infinite (this is the characteristic of the BJT tube, and the base needs to flow current), resulting in poor impedance isolation. Secondly, it requires the support of the special BiCMOS process.

Summary of the invention

The purpose of the present application is to provide a preamplifier, a differential preamplifier and an integrated circuit, aiming to solve the problem that the traditional preamplifier with a single PMOS tube as an input buffer stage is limited by the channel length modulation effect and has general gain accuracy and linearity.

A first aspect of an embodiment of the present application provides a preamplifier, comprising an input buffer unit and a gain amplification unit, wherein the input buffer unit comprises a first current source connected in series in the same direction or in reverse direction between a power supply and a common potential, a first main source follower composed of a first transistor, and a first auxiliary source follower composed of at least one second transistor, wherein the gates of the first transistor and the second transistor are connected in common as an input of the preamplifier, a common point between the first current source and the first main source follower is used as an output of the input buffer unit, and the first auxiliary source follower is used to eliminate a channel length modulation effect of the first main source follower;

The first input end of the gain amplifier unit is connected to the output of the input buffer unit, the second input end of the gain amplifier unit is connected to the bias voltage, and the gain amplifier unit amplifies the signal output by the input buffer unit based on the bias voltage and outputs an amplified signal.

In one embodiment, the input buffer unit further comprises a level shift module for increasing output level shift, wherein:

The level shift module is connected between the first current source and the first main source follower, and a common point between the level shift module and the first current source serves as an output of the input buffer unit; and/or

The level shift module is connected between the first main source follower and the first auxiliary source follower.

In one embodiment, the first transistor and the second transistor are PMOS transistors, the source of the first transistor is connected to a power source through the first current source, and at least one of the second transistors is connected in series in the same direction and connected between the drain of the first transistor and a common potential; or

The first transistor and the second transistor are NMOS transistors, the source of the first transistor is connected to a common potential through the first current source, and at least one of the second transistors is connected in series in the same direction and connected between the drain of the first transistor and a power source.

In one embodiment, both the first transistor and the second transistor operate in a saturation region; a threshold voltage of the first transistor is greater than a threshold voltage of the second transistor.

In one embodiment, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor in the relationship: |Vth1|-|Vth0|≥|Vod0|+margin;

Among them, Vth1 is the threshold voltage of the first transistor, Vth0 is the threshold voltage of the second transistor, Vod0 is the over-driving voltage of the second transistor, and margin is the voltage margin.

In one embodiment, the gain amplification unit includes a first operational amplifier, a first voltage divider and a second voltage divider, the non-inverting input terminal of the first operational amplifier serves as the first input terminal of the gain amplification unit, one end of the first voltage divider is connected to the output terminal of the first operational amplifier, the other end of the first voltage divider is connected to the inverting input terminal of the first operational amplifier and one end of the second voltage divider, the other end of the second voltage divider serves as the second input terminal of the gain amplification unit, and the output terminal of the first operational amplifier serves as the output terminal of the gain amplification unit.

In one embodiment, the gain amplification unit includes a first operational amplifier, a first resistor and a second resistor, the first end of the first resistor serves as the first input end of the gain amplification unit, the second end of the first resistor is connected to the inverting input end of the operational amplifier, the non-inverting input end of the operational amplifier serves as the second input end of the gain amplification unit, the second resistor is connected between the inverting input end and the output end of the operational amplifier, and the output end of the operational amplifier serves as the output end of the gain amplification unit.

In one embodiment, it further includes a bias voltage generating unit, the bias voltage generating unit including a second current source connected in series in the same direction or in reverse direction between the power supply and the common potential, a second main source follower composed of a third transistor, a second auxiliary source follower composed of at least one fourth transistor, and a buffer driving circuit;

The gates of the third transistor and the fourth transistor are connected to a common potential, the common point between the second current source and the second main source follower is connected to the input end of the buffer drive circuit, and the output end of the buffer drive circuit serves as the output of the bias voltage generating unit to output the bias voltage.

The second aspect of an embodiment of the present application provides another pre-differential amplifier, comprising two input buffer units and a gain amplifier unit, each of the input buffer units comprising a first current source connected in series in the same direction or in reverse direction between a power supply and a common potential, a first main source follower composed of a first transistor, and a first auxiliary source follower composed of at least one second transistor, the gates of the first transistor and the second transistor are connected in common as the input of the pre-differential amplifier, the common point between the first current source and the first main source follower serves as the output of the input buffer unit, and the first auxiliary source follower is used to eliminate the channel length modulation effect of the first main source follower; the first input terminal and the second input terminal of the gain amplifier unit are respectively connected to the outputs of the two input buffer units, and the two output terminals of the gain amplifier unit serve as the two output terminals of the pre-differential amplifier.

In one embodiment, the gain amplification unit includes a first operational amplifier, a second operational amplifier, a first voltage divider element, a second voltage divider element and a third voltage divider element, the non-inverting input terminal of the first operational amplifier serves as the first input terminal of the gain amplification unit, one end of the first voltage divider element is connected to the output terminal of the first operational amplifier, the other end of the first voltage divider element is connected to the inverting input terminal of the first operational amplifier and one end of the second voltage divider element, the other end of the second voltage divider element is connected to the inverting input terminal of the second operational amplifier and one end of the third voltage divider element, the non-inverting input terminal of the second operational amplifier serves as the second input terminal of the gain amplification unit, the other end of the third voltage divider element is connected to the output terminal of the second operational amplifier, the output terminal of the first operational amplifier serves as the first output terminal of the gain amplification unit, and the output terminal of the second operational amplifier serves as the second output terminal of the gain amplification unit.

In one embodiment, the gain amplification unit includes a first operational amplifier, a first voltage divider element, a second voltage divider element, a third voltage divider element and a fourth voltage divider element, one end of the first voltage divider element serves as the first input end of the gain amplification unit, the other end of the first voltage divider element is connected to the non-inverting input end of the first operational amplifier, one end of the second voltage divider element serves as the second input end of the gain amplification unit, the other end of the second voltage divider element is connected to the inverting input end of the first operational amplifier, the third voltage divider element is connected between the non-inverting input end and the inverting output end of the first operational amplifier, the fourth voltage divider element is connected between the inverting input end and the non-inverting output end of the first operational amplifier, and the inverting output end and the non-inverting output end of the first operational amplifier serve as the first output end and the second output end of the gain amplification unit, respectively.

A third aspect of an embodiment of the present application provides an integrated circuit, comprising the preamplifier as described above.

The first input buffer stage in the above-mentioned preamplifier uses different transistors to form two source followers, one of which serves as a main source follower and the other as an auxiliary source follower. The function of the auxiliary source follower is to eliminate the channel length modulation effect of the main source follower, thereby greatly improving the linearity and gain accuracy of the preamplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

1A and 1B are schematic diagrams of two structures of a preamplifier provided in an embodiment of the present application;

FIG2 is an exemplary circuit diagram of the first embodiment of the preamplifier shown in FIG1A ;

FIG3 is an exemplary circuit diagram of an input buffer unit in the second embodiment of the preamplifier shown in FIG1A ;

FIG4 is an exemplary circuit diagram of the third embodiment of the preamplifier shown in FIG1B ;

FIG5 is an exemplary circuit diagram of an input buffer unit in the fourth embodiment of the preamplifier shown in FIG1B ;

FIG6 is an exemplary circuit diagram of the fifth embodiment of the preamplifier shown in FIG1A ;

FIG7 is an exemplary circuit diagram of an input buffer unit in the sixth embodiment of the preamplifier shown in FIG1A ;

FIG8 is a schematic diagram of a conventional source follower structure preamplifier circuit composed of a single PMOS tube and its input/output signal waveforms;

FIG9 is a circuit schematic diagram of the input buffer unit of the preamplifier shown in FIG2 and its input/output signal waveform diagram;

FIG10 is an exemplary circuit schematic diagram of a bias voltage generating unit in a preamplifier provided in an embodiment of the present application;

FIG11 is an exemplary circuit diagram of a first differential preamplifier provided in an embodiment of the present application;

FIG. 12 is an exemplary circuit diagram of a second differential preamplifier provided in an embodiment of the present application.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

Referring to FIG. 1A and FIG. 1B , the preamplifier provided in the embodiment of the present application includes an input buffer unit 10 and a gain amplifier unit 20. The input buffer unit 10 includes a first current source Iss connected in series in the same direction (see FIG. 1A ) or in series in reverse direction (see FIG. 1B ) between a power supply Vcc and a common potential Vss, a first main source follower 100 composed of a first transistor, and a first auxiliary source follower 200 composed of at least one second transistor. The gates of the first transistor and the second transistor are connected in common as the input of the preamplifier, and the common point between the first current source Iss and the first main source follower 100 is used as the output of the input buffer unit 10. The first auxiliary source follower 200 is used to eliminate the channel length modulation effect of the first main source follower 100. The first input terminal of the gain amplifier unit 20 is connected to the output of the input buffer unit 10, and the second input terminal of the gain amplifier unit 20 is connected to the bias voltage vbias. The gain amplifier unit 20 amplifies the output signal vbuffer output by the input buffer unit 10 based on the bias voltage vbias and outputs the amplified signal vout.

This solution is an improvement on the input buffer unit 10 composed of a single MOS tube. The first main source follower 100 is still a single transistor, and the first auxiliary source follower 200 is a single or multiple transistors connected in series. The first current source Iss, the first main source follower 100 and the first auxiliary source follower 200 are connected in series in a forward or reverse direction between the power supply Vcc and the common potential Vss (such as the ground), depending on whether the transistor is P-type or N-type. The input buffer unit 10 uses different transistors to form two source followers, one of which is used as a main source follower and the other as an auxiliary source follower. The function of the auxiliary source follower is to eliminate the channel length modulation effect of the main source follower, thereby greatly improving the linearity and gain accuracy of the preamplifier.

The embodiment of the input buffer unit 10 is as follows:

Embodiment 1:

Please refer to FIG. 2 . The first transistor and the second transistor in the input buffer unit 10 are PMOS transistors. Then the first current source Iss, the first main source follower 100 and the first auxiliary source follower 200 are connected in series between the power supply Vcc and the common potential Vss in sequence. The source of the first transistor is connected to the power supply Vcc through the first current source Iss. At least one second transistor is connected in series in the same direction and connected between the drain of the first transistor and the common potential Vss. Specifically, the first transistor is a PMOS transistor PM1, and the second transistor is a PMOS transistor PM0. The substrate of the PMOS transistor PM0 is connected to its source, and the drain of the PMOS transistor PM0 is grounded; the substrate of the PMOS transistor PM1 is connected to its source, and the drain of the PMOS transistor PM1 is connected to the source of the PMOS transistor PM0. The first current source Iss provides a bias current, which is placed between the power supply Vcc and the source of the PMOS transistor PM1. The bias current flows from the power supply Vcc to the PMOS transistor PM1. The input signal vin is applied to the input gates of the PMOS transistor PM0 and the PMOS transistor PM1 at the same time, and the output signal vbuffer is taken from the source of the PMOS transistor PM1.

Embodiment 2:

Please refer to Figure 3. The input buffer unit 10 of this embodiment is expanded to a series structure of multiple PMOS source followers on the basis of the first embodiment, wherein the first transistor PMOS tube PM1 constitutes a "main" source follower, and the remaining second transistors PMOS tubes PM_a0~PM_an together constitute a first auxiliary source follower 200, and the gates of the PMOS tube PM1 and the PMOS tubes PM_a0~PM_an are connected in common as the input of the preamplifier, and the output signal vbuffer is taken from the source of the PMOS tube PM1 which serves as the output of the preamplifier.

Embodiment three:

Please refer to FIG. 4 . The first transistor and the second transistor of the input buffer unit 10 are NMOS transistors. Then the first auxiliary source follower 200, the first main source follower 100 and the first current source Iss are connected in series between the power supply Vcc and the common potential Vss in sequence. The source of the first transistor is connected to the common potential Vss through the first current source Iss. At least one second transistor is connected in series in the same direction and connected between the drain of the first transistor and the power supply Vcc. Specifically, the first transistor is an NMOS transistor NM1, and the second transistor is an NMOS transistor NM0. The substrate of the NMOS transistor NM0 is connected to its source, and the drain of the NMOS transistor NM0 is connected to the power supply Vcc; the substrate of the NMOS transistor NM1 is connected to its source, and the drain of the NMOS transistor NM1 is connected to the source of the NMOS transistor NM0. The first current source Iss provides a bias current, which is placed between the common potential Vss and the source of the NMOS transistor NM1. The direction of the bias current is from the power supply Vcc to the NMOS transistor NM1 to the common potential Vss. The input signal vin is applied to the input gates of the NMOS tube NM0 and the NMOS tube NM1 at the same time, and the output signal vbuffer is taken from the source of the NMOS tube NM1. In this embodiment, a series structure consisting of two NMOS source followers is adopted, which is completely dual to the two PMOS tube structure of the first embodiment. At this time, the common mode level of the input signal vin can be very high, for example, directly taking the power supply voltage.

Embodiment 4:

Please refer to FIG5 . The input buffer unit 10 of this embodiment is expanded to a series structure of multiple NMOS source followers based on the third embodiment, wherein the first transistor NMOS tube NM1 constitutes a "main" source follower, and the remaining second transistors NMOS tubes NM_a0 to NM_an together constitute a first auxiliary source follower 200. The gates of NMOS tube NM1 and NMOS tubes NM_a0 to NM_an are connected together as the input of the preamplifier, and the output signal vbuffer is taken from the source of NMOS tube NM1 as the output of the preamplifier. The series structure of multiple NMOS source followers in this embodiment is completely dual to the series structure of multiple PMOS source followers in the second embodiment.

Embodiment five:

Please refer to FIG6 . The input buffer unit 10 of this embodiment is expanded on the basis of any one of the first to fourth embodiments to add a DC level shift module 300. In this embodiment, the level shift module 300 is connected between the first current source Iss and the first main source follower 100. The common point between the level shift module 300 and the first current source Iss is used as the output of the preamplifier. The level shift module 300 is used to increase the output level shift. Among them, the main and first auxiliary source followers 200 are not limited to PMOS tubes or NMOS tubes, and the number of MOS tubes of the first auxiliary source follower 200 is also not limited.

In the example shown in FIG6 , the DC level shift module 300 is a resistor R0, which is connected in series between the output and the PMOS tube PM1 of the first main source follower, and can solve the problem that the output level shift is insufficient when the PMOS tube PM1 is used alone. At this time, adding the level shift module 300 can further increase the DC level shift without affecting the signal quality. Sometimes, in order to allow the second-stage gain amplifier unit 20 to operate under a comfortable bias voltage vbias, this level shift module 300 is necessary. In other embodiments, the resistor R0 can be replaced by a circuit module. Regardless of the specific implementation of this circuit module, as long as its function is to increase the DC level shift without affecting the signal quality, it belongs to the protection scope of this solution.

Embodiment six:

Please refer to FIG. 7 . The input buffer unit 10 of this embodiment is a structure that is expanded on the basis of any one of the first to fourth embodiments to add a DC level shift module 400. In this embodiment, the level shift module 400 is connected between the first main source follower 100 and the first auxiliary source follower 200, and the level shift module 400 is used to increase the output level shift. Among them, the main and first auxiliary source followers 200 are not limited to PMOS tubes or NMOS tubes, and the number of MOS tubes of the first auxiliary source follower 200 is also not limited. In addition, the scheme in this embodiment can be used in combination with the scheme in the fifth embodiment.

In the example shown in FIG7 , the DC level shift module 400 is a resistor R1, which is connected in series between the PMOS transistor PM1 of the first main source follower 100 and the PMOS transistor PM0 of the first auxiliary source follower 200. It can solve the problem that the output level shift is insufficient when the PMOS transistor PM1 is used alone. At this time, adding the level shift module 400 can further increase the DC level shift without affecting the signal quality. In other embodiments, the resistor can be replaced by a circuit module. Regardless of the specific implementation of the circuit module, as long as its function is to increase the DC level shift without affecting the signal quality, it belongs to the protection scope of this solution.

It must be pointed out that, as mentioned above, although Figures 6 and 7 are illustrated using a two-stage MOS source follower series structure as an example, they are applicable to multi-stage MOS source follower series structures, and inserting a level shift module into these structures falls within the protection scope.

Please continue to refer to FIG. 2. The following will take the first transistor and the second transistor in the input buffer unit 10 as PMOS tubes, and the first auxiliary source follower 200 as a PMOS tube as an example to illustrate the relevant principles. Specifically, the core part of the preamplifier uses two PMOS tubes PM0 and PM1 and a first current source Iss. Therefore, from a structural point of view, the two PMOS tubes PM0 and PM1 both constitute source followers, but their inputs are connected in parallel and their outputs are "connected in series". PMOS tube PM1 constitutes the main source follower, and PMOS tube PM0 constitutes the auxiliary source follower; the existence of PMOS tube PM0 linearizes PMOS tube PM1, so that the linearity of PMOS tube PM1 is greatly improved, and the output signal vbuffer is generated by PMOS tube PM1. It is precisely because of this ingenious connection relationship that the linearity is greatly improved, the gain accuracy is greatly improved, and the performance of other aspects (such as output impedance, noise, power consumption, and consumption of voltage margin) is equivalent to that of an ordinary single PMOS tube source follower. This is a very rare phenomenon in the field of analog circuit design, because in the field of analog circuit design, there are many tradeoffs. Usually, when one circuit architecture performs better than another in some aspects, it is often at the expense of performance in other aspects.

In the structure of Figure 2, PMOS tube PM0 and PMOS tube PM1 need to be carefully designed and dimensioned to ensure that both MOS tubes work in the saturation region, which is the basic requirement for this structure to work effectively. It is very easy to make PMOS tube PM0 work in the saturation region, but the difficulty lies in making PMOS tube PM1 work in the saturation region, which must meet the following requirements:

|Vds1|≥(|Vgs1|-|Vth1|)+margin

Among them, Vds1, Vgs1, Vth1, and margin are the drain-source voltage, gate-source voltage, threshold voltage, and voltage margin of the PMOS tube PM1, respectively. Margin is generally about 100 to 200 mV. Assuming that the common-mode level of the input signal vin is 0, the above formula can be further written as:

vbuffer-vt≥vbuffer-|Vth1|+margin

Further:

|Vth1|≥Vt+margin

Since vt＝|Vgs0|＝|Vth0|+Vod0, vt is the common point voltage of the drain of PMOS tube PM1 and the source of PMOS tube PM0, Vgs0, Vth0, Vod0 are the gate-source voltage, threshold voltage, and overdrive voltage of PMOS tube PM0, Therefore, the above formula can be further written as:

|Vth1|-|Vth0|≥Vod0+margin≈Vod0+100mV

This means that the threshold voltage of PMOS tube PM1 must be greater than the threshold voltage of PMOS tube PM0 by Vod0+margin, that is, at least 100mV. To achieve this goal, there are at least two feasible solutions:

The first one: The process generally provides multiple threshold MOS tube options. You can choose PM1 as a high threshold MOS tube and PM0 as a low threshold MOS tube, which can easily achieve the goal.

The second method is to achieve it through fine and ingenious size design. Let the W/L (W is the width of the conductive channel, L is the length of the conductive channel) of the PMOS tube PM0 be large enough to make it work in the subthreshold region, and Vod0 will be very small (for example, 50mV). At the same time, let the L of the PMOS tube PM0 take the minimum length under the current process (for example, for the 0.35um CMOS process, take L = 0.35um), and the minimum L usually brings a smaller threshold voltage. In addition, let the W/L of the PMOS tube PM1 be as small as possible, and at the same time, let L be as large as possible under the current process (for example, for the 0.35um CMOS process, take L = 4um), so that the Vod1 of the PMOS tube PM1 is large enough, the channel length modulation effect itself is small enough, and the linearity is as good as possible. The larger L of the PMOS tube PM1 usually also brings a larger threshold voltage. In this way, by making |Vth1| as large as possible, making |Vth0| as small as possible, and making Vod0 as small as possible, the above formula is satisfied, so the effect brought by the structure of this scheme is brought into play, and the linearity is further improved.

Next, we will further analyze why the structure proposed in this scheme can greatly improve the linearity and gain accuracy. This issue needs to be examined through comparative analysis.

FIG8 is an input buffer unit 10 of a source follower structure composed of a conventional single PMOS tube, where the substrate is connected to the source. The gain from input to output is:

Where gm is the transconductance of the PMOS tube PM1, and gds is the output intrinsic admittance of the PMOS tube PM1. gm/gds is called the intrinsic gain of the MOS tube, and this value is usually around 100, that is, gds≈gm/100, which is usually negligible compared to gm, so Av is approximately equal to 1. If used in high-precision and high-linearity applications, the influence of gds cannot be ignored. The influence of gds represents the channel length modulation effect. In this structure, gds completely determines the accuracy and linearity of the gain. Note the definition of gds:

Therefore, gds is a function of vds (the drain-source voltage of the MOS tube). For the source follower in Figure 8, since vds = vbuffer-0≈vin, due to the influence of gds, the gain Av is actually still a weak function of the input signal:

This is nonlinearity, so harmonic distortion is generated. The design and simulation results on a typical CMOS process show that the second and third harmonic components of the input buffer unit 10 of the traditional single PMOS source follower structure are difficult to be lower than <-80dBc, which means that the effective number of bits (accuracy index, defined as ENOB = (SNDR-1.76)/6.02) of the measurement system based on the single PMOS source follower structure input buffer unit 10 is at most about 13 bits, which is far from enough for high-precision applications.

By analyzing Figure 8, we know that the bottleneck is gds. The patented solution we proposed almost completely eliminates the impact of gds.

As shown in Figure 9, the input signal vin passes through two source followers to generate vbuffer and vt respectively. We call the PMOS tube PM1 the first main source follower 100, and the PMOS tube PM0 the first auxiliary source follower 200. vbuffer and vt are almost exactly equal to the input signal vin, and the magnitude of the error is the harmonic component (about -80dBc, which is about one ten-thousandth of the signal itself).

In addition, note that the PMOS tube PM1,

vds＝vbuffer-vt≈vin+o(vin)-[vin+o(vin)]＝o(vin)≈0

Mathematical notation is used here, with the small o representing "much less than", for example, o(vin) represents a quantity much less than vin. Therefore, the source and drain of the PMOS tube PM1 swing synchronously with the input signal, but the difference is almost 0 (the fluctuation is about one ten-thousandth of the input signal), so the change of vds cannot be felt. Since the change of vds cannot be felt, the gds of the PMOS tube PM1 is almost equal to 0. Therefore, for the circuit structure of the present application:

The nonlinear component is greatly reduced, thus greatly reducing the harmonic distortion. The design and simulation results on the same CMOS process show that the second and third harmonic components of the input buffer unit 10 using the new source follower structure proposed in this application can be <-120dBc, which means that the measurement system based on the input buffer unit 10 of this source follower can reach a maximum effective number of bits close to 20 bits, which is sufficient for high-precision applications (usually around 16 bits is more common).

Another indicator to consider is gain accuracy, which is also crucial for high-precision measurement systems. In practice, each stage in the signal processing chain (buffer isolation, amplification, filtering, analog-to-digital conversion...) will introduce gain, and the gain of each stage will be affected by PVT (process deviation, power supply fluctuation, temperature), which is often very complex and even difficult to accurately characterize. Among the influences of PVT:

Usually the influence of power supply fluctuation V can be solved by design, such as placing it under an LDO (Low Dropout Regulator) to keep V constant.

Usually the influence of process deviation P is solved by calibration before the chip/machine leaves the factory. The so-called calibration is to record the gain value Av0 of the chip/machine before it leaves the factory and store it in the non-volatile memory of the chip. This is called calibration. In normal use, Av0 is used to calibrate the actual gain Av. In this way, the process differences between chips are eliminated;

As for the influence of temperature T, it is necessary to make the circuit gain insensitive to temperature through excellent design level and clever circuit structure.

For the traditional source follower input buffer unit 10 composed of a single PMOS tube as shown in FIG8 , its gain is:

in

Both gds(PVT) and gm(PVT) vary dramatically with temperature. From -40℃ to +85℃, the variation of gds(PVT)/gm(PVT) is often more than 2 times. As before, the typical value of gds/gm is about 1%, and the typical value of Av is about 0.99; but if the variation of gds/gm with temperature is taken into account, the variation of Av with temperature is as high as more than 1%, which brings a large measurement error, making the high-precision measurement system no longer accurate. Since gds(PVT)/gm(PVT) is not only related to T, but also to P, this means that for each chip, the temperature curve of gds(PVT)/gm(PVT) may be different, making the idea of considering temperature compensation impossible to implement (temperature compensation needs to be done for each chip, which is extremely expensive).

However, for the patent solution proposed in this application, the gains are:

in

Assuming that the value of x itself is about 1%, the change in the full temperature range is also about 1%. As before, o(x) is a quantity that is about 40dB smaller than x (about 100 times), so the value of o(x) itself is about 0.01%, and the change in the full temperature range is also about 0.01%, which is converted into a temperature coefficient of about 8ppm/℃. From the literature that can be found at present, this is the top level and meets the application of most high-precision measurement systems.

The present application uses a source follower composed of two MOS tubes, with the input ends connected in parallel and the output ends connected in series. One of the MOS tubes is used as the first main source follower 100, and the other one or more MOS tubes are used as the first auxiliary source follower 200, and the output is taken from the first main source follower 100. The function of the first auxiliary source follower 200 is to eliminate the channel length modulation effect of the first main source follower 100, thereby greatly improving the linearity and gain accuracy of the input buffer unit 10.

In order to make the MOS tubes of the main and first auxiliary source followers 200 work in the saturation region, the following design methods are adopted: one is to adopt a multi-threshold tube design method; the other is to adopt a more skillful tube size selection method. These two methods have been described in detail above.

The input buffer unit 10 and integrated circuit of the present application have excellent linearity and extremely precise gain; the input signal does not need to provide an additional bias voltage vbias (the sensor can directly take the ground as a common-mode signal); the circuit is extremely simple and fully compatible with the CMOS process, and no special devices are required; impedance isolation (input is high impedance, output is low impedance); other aspects of performance (such as noise, power consumption, and voltage margin consumption) are comparable to ordinary single MOS tube source follower structures. This is a very rare phenomenon in the field of circuit design. In the field of circuit design, there are many tradeoffs. One circuit architecture is better than another in some aspects, but it is often achieved at the expense of other aspects of performance.

The embodiment of the gain amplification unit 20 is as follows:

First embodiment:

Please refer to Figures 2 and 4. The gain amplifier unit 20 includes a first operational amplifier A0, a first voltage divider R11 and a second voltage divider R12. The non-inverting input terminal of the first operational amplifier A0 serves as the first input terminal of the gain amplifier unit 20. One end of the first voltage divider R11 is connected to the output terminal of the first operational amplifier A0. The other end of the first voltage divider R11 is connected to the inverting input terminal of the first operational amplifier A0 and one end of the second voltage divider R12. The other end of the second voltage divider R12 serves as the second input terminal of the gain amplifier unit 20. The output terminal of the first operational amplifier A0 serves as the output terminal of the gain amplifier unit 20.

In this embodiment, the gain of the entire preamplifier is:

The desired gain can be achieved by changing the ratio of the voltage divider R11 and R12. The voltage divider R11 and R12 can be a circuit composed of at least one of a resistor, a capacitor, an inductor, and a semiconductor transistor.

In this embodiment, the second gain stage adopts the closed-loop feedback form of an operational amplifier, so its linearity and gain accuracy are good. As long as the open-loop gain of the operational amplifier A1 is high enough, the linearity and gain accuracy of the gain stage can be very good.

Second embodiment:

Please refer to Figure 6, the gain amplifier unit 20 includes an operational amplifier A1, a first resistor R13 and a second resistor R14, the first end of the first resistor R13 serves as the first input end of the gain amplifier unit 20, the second end of the first resistor R13 is connected to the inverting input end of the operational amplifier A1, the non-inverting input end of the operational amplifier A1 serves as the second input end of the gain amplifier unit 20, the second resistor R14 is connected between the inverting input end and the output end of the operational amplifier A1, and the output end of the operational amplifier A1 serves as the output end of the gain amplifier unit 20.

In this embodiment, the gain stage is changed to an inverting proportional amplifier, and the gain formula of this structure is:

In addition, the present application also provides a bias voltage vbias generating unit 30 for generating the above-mentioned bias voltage vbias, which can be used to provide the bias voltage vbias for the preamplifier of each of the above-mentioned embodiments.

Please refer to Figure 10, the bias voltage vbias generating unit 30 includes a second current source Iss1 connected in series in the same direction or inverse direction between the power supply and the common potential, a second main source follower 301 composed of a third transistor PM1s and a second auxiliary source follower 302 composed of at least one fourth transistor PM0s, and a buffer driving circuit A2; the gates of the third transistor PM1s and the fourth transistor PM0s are connected to the common potential Vss, the common point between the second current source Iss1 and the second main source follower 301 is connected to the input end of the buffer driving circuit A2, and the output end of the buffer driving circuit A2 serves as the output of the bias voltage vbias generating unit 30, outputting the bias voltage vbias. It can be seen that the branch circuit structure formed by the second current source Iss1, the second main source follower 301, and the second auxiliary source follower 302 in the bias voltage vbias generating unit 30 is the same as the circuit structure of the input buffer unit 10, so the specific implementation of the bias voltage vbias generating unit 30 can directly adopt various implementations of the same input buffer unit 10 as described above, and the device size of the two units depends on actual needs. Moreover, in the same preamplifier circuit, the bias voltage vbias generating unit 30 and the input buffer unit 10 can be implemented with the same circuit structure or with different circuit structures.

In this embodiment, the branch 1 composed of the second current source Iss1, the third transistor PM1s, and the fourth transistor PM0s generates an initial bias voltage vbias_src, which is not buffered and has no driving capability. The initial bias voltage vbias_src is then passed through a unit gain buffer driving circuit A2 to generate a bias voltage vbias. The branch 1 composed of the second current source Iss1, the third transistor PM1s, and the fourth transistor PM0s has the same connection form as the branch 2 composed of the first current source Iss, the first transistor PM1, and the fourth transistor PM0, but its corresponding size is only 1/N of the branch 2 (N is a positive integer, for example, N=4). It should be noted that in this embodiment, the input terminals of the third transistor PM1s and the fourth transistor PM0s are connected to 0V, which is the same as the common mode level of the input signal vin (unless otherwise specified, this article assumes that the common mode level of the input signal vin is 0V). Therefore, without considering the mismatch, the level of the initial bias voltage vbias_src is exactly the same as the common-mode level of the output signal vbuffer, so that the second gain stage only amplifies the AC component of the output signal vbuffer, but not the DC component of the output signal vbuffer, which is very beneficial to the working state of the operational amplifier A0 of the second gain stage. In the field of circuit design, this design technique is called "self-replication" technology.

Please refer to Figures 11 and 12. The present application also discloses a pre-differential amplifier, including two input buffer units 10 and a gain amplifier unit 20. Each input buffer unit 10 includes a first current source Iss connected in series in the same direction or inverse direction between a power supply and a common potential, a first main source follower 100 composed of a first transistor PM1, and a first auxiliary source follower 200 composed of at least one second transistor PM1. The gates of the first transistor PM1 and the second transistor PM1 are connected in common as the input vip/vin of the pre-differential amplifier. The common point between the first current source Iss and the first main source follower 100 serves as the output of the input buffer unit 10. The first auxiliary source follower 200 is used to eliminate the channel length modulation effect of the first main source follower 100. The first input terminal vbf_p and the second input terminal vbf_n of the gain amplifier unit 20 are respectively connected to the outputs of the two input buffer units 10, and the two output terminals of the gain amplifier unit 20 serve as the two output terminals vop/von of the pre-differential amplifier.

The specific implementation of the two input buffer units 10 can refer to the above-mentioned embodiments 1 to 6 and their related principle descriptions, which will not be repeated here.

Please refer to Figure 11. In one embodiment, the gain amplifier unit 20 includes a first operational amplifier A3, a second operational amplifier A4, a first voltage divider element R21, a second voltage divider element R22 and a third voltage divider element R23. The non-inverting input terminal of the first operational amplifier A3 serves as the first input terminal vbf_p of the gain amplifier unit 20. One end of the first voltage divider element R21 is connected to the output terminal of the first operational amplifier A3. The other end of the first voltage divider element R21 is connected to the inverting input terminal of the first operational amplifier A3 and one end of the second voltage divider element R22. The other end of the second voltage divider element R22 is connected to the inverting input terminal of the second operational amplifier A4 and one end of the third voltage divider element R23. The non-inverting input terminal of the second operational amplifier A4 serves as the second input terminal vbf_n of the gain amplifier unit 20. The other end of the third voltage divider element R23 is connected to the output terminal of the second operational amplifier A4. The output terminal of the first operational amplifier A3 serves as the first output terminal vop of the gain amplifier unit 20. The output terminal of the second operational amplifier A4 serves as the second output terminal von of the gain amplifier unit 20.

In this embodiment, the pre-differential amplifier is a differential structure constructed on the basis of the embodiment related to FIG2. The differential circuit is symmetrical and has the ability to suppress even-order harmonics. Therefore, it has a wider range of uses. In practical applications, most amplifier circuits appear in the form of differential (or pseudo-differential). The gain amplifier unit 20 in FIG11 is not a simple copy and doubling of the first embodiment of the aforementioned gain amplifier unit 20 (i.e., the structure shown in FIG2 and FIG4), but is merged to merge the two voltage dividers R12 into a voltage divider element R22, and omit the bias voltage. Because of this, the gain formula of this structure is also different from the first embodiment of the gain amplifier unit 20, which is:

Please refer to Figure 12. In one embodiment, the gain amplifier unit 20 includes an operational amplifier A5, a first voltage divider element R31, a second voltage divider element R32, a third voltage divider element R33 and a fourth voltage divider element R34. One end of the first voltage divider element R31 serves as a first input end vbf_p of the gain amplifier unit 20, and the other end of the first voltage divider element R31 is connected to the non-inverting input end of the operational amplifier A5. One end of the second voltage divider element R32 serves as a second input end vbf_n of the gain amplifier unit 20, and the other end of the second voltage divider element R32 is connected to the inverting input end of the operational amplifier A5. The third voltage divider element R33 is connected between the non-inverting input end and the inverting output end of the operational amplifier A5. The fourth voltage divider element R34 is connected between the inverting input end and the non-inverting output end of the operational amplifier A5. The inverting output end and the non-inverting output end of the operational amplifier A5 serve as a first output end von and a second output end vop of the gain amplifier unit 20, respectively.

In this embodiment, the pre-differential amplifier is a differential structure constructed on the basis of the input buffer unit 10 in the embodiment of FIG. 2 and the gain amplifier unit 20 in the embodiment of FIG. 6, wherein the gain amplifier unit 20 is an inverting proportional amplifier of a differential structure. This is not a simple copy and doubling of the structure of the input buffer unit 10 in the embodiment of FIG. 2 and the gain amplifier unit 20 in the embodiment of FIG. 6, but is based on a single fully differential input and output operational amplifier A5, and the bias voltage is omitted.

It must be pointed out that although the two input buffer units 10 of the pre-differential amplifier are described as a two-stage PMOS series structure, in fact, all structures including but not limited to embodiments 1 to 6 can constitute a differential circuit, which all belong to the protection scope of this application. In addition, the voltage divider element can be a circuit composed of at least one of a resistor, a capacitor, an inductor, a transistor, etc.

The present application also provides an integrated circuit including the above-mentioned preamplifier 10. The present application adopts the above-mentioned input buffer structure, which greatly improves the linearity and gain accuracy. The design and simulation results on the typical CMOS process show that the second and third harmonic components of the source follower structure input buffer composed of a traditional single PMOS tube are difficult to be lower than <-80dBc, and the gain changes with temperature as high as ±1%, which is far from enough for high-precision applications. However, by adopting the input buffer structure in the present application, the second and third harmonic components can be <-120dBc, and the gain changes with temperature as low as ±0.01%, which is sufficient for most high-precision systems. Most importantly, this is achieved on a pure CMOS process, without the need for any special devices or the support of expensive BiCMOS processes.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A preamplifier comprising an input buffer unit and a gain amplifying unit, characterized in that:

The input buffer unit comprises a first current source, a first main source follower and a first auxiliary source follower, wherein the first current source is connected in parallel or in reverse series between a power supply and a common potential, the first main source follower is formed by a first transistor, the first auxiliary source follower is formed by at least one second transistor, the gates of the first transistor and the second transistor are commonly connected to serve as the input of a preamplifier, a common joint between the first current source and the first main source follower serves as the output of the input buffer unit, and the first auxiliary source follower is used for eliminating the channel length modulation effect of the first main source follower;

The first input end of the gain amplifying unit is connected with the output of the input buffer unit, the second input end of the gain amplifying unit is connected with a bias voltage, and the gain amplifying unit outputs an amplified signal after amplifying the signal output by the input buffer unit based on the bias voltage;

The input buffer unit further includes a level shift module for increasing an output level shift, wherein:

The level shifting module is connected between the first current source and the first main source follower, and a common joint between the level shifting module and the first current source is used as the output of the input buffer unit; and/or

The level shift module is connected between the first main source follower and the first auxiliary source follower;

the first transistor and the second transistor are PMOS transistors, the source electrode of the first transistor is connected with a power supply through the first current source, and at least one of the second transistors is connected between the drain electrode of the first transistor and a common potential after being connected in series in the same direction; or (b)

The first transistor and the second transistor are NMOS transistors, the source electrode of the first transistor is connected with a common potential through the first current source, and at least one second transistor is connected between the drain electrode of the first transistor and a power supply after being connected in series in the same direction.

2. The preamplifier of claim 1 wherein the first transistor and the second transistor each operate in a saturation region; the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.

3. The preamplifier of claim 2 wherein the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor by the relationship: the |Vt1| -Vt0| is not less than |Vod0|+margin;

wherein Vth1 is a threshold voltage of the first transistor, vth0 is a threshold voltage of the second transistor, vod0 is an overdrive voltage of the second transistor, and margin is a voltage margin.

4. The preamplifier according to claim 1, wherein the gain amplifying unit comprises a first operational amplifier, a first voltage divider and a second voltage divider, wherein a non-inverting input terminal of the first operational amplifier is used as a first input terminal of the gain amplifying unit, one end of the first voltage divider is connected with an output terminal of the first operational amplifier, the other end of the first voltage divider is connected with an inverting input terminal of the first operational amplifier and one end of the second voltage divider, the other end of the second voltage divider is used as a second input terminal of the gain amplifying unit, and an output terminal of the first operational amplifier is used as an output terminal of the gain amplifying unit.

5. The preamplifier according to claim 1, wherein the gain amplification unit comprises a first operational amplifier, a first resistor and a second resistor, wherein a first end of the first resistor is used as a first input end of the gain amplification unit, a second end of the first resistor is connected with an inverting input end of the operational amplifier, a non-inverting input end of the operational amplifier is used as a second input end of the gain amplification unit, and the second resistor is connected between the inverting input end and an output end of the operational amplifier, and an output end of the operational amplifier is used as an output end of the gain amplification unit.

6. The preamplifier according to claim 1, 4 or 5, further comprising a bias voltage generating unit including a second current source connected in parallel or in reverse series between a power supply and a common potential, a second main source follower constituted by a third transistor, and a second sub source follower constituted by at least one fourth transistor, and a buffer driving circuit;

The gates of the third transistor and the fourth transistor are commonly connected with a common potential, a common connection point between the second current source and the second main source follower is connected with the input end of the buffer driving circuit, and the output end of the buffer driving circuit is used as the output of the bias voltage generating unit to output the bias voltage.

7. A pre-differential amplifier, comprising two input buffer units and a gain amplifying unit, wherein each input buffer unit comprises a first current source, a first main source follower and a first auxiliary source follower, wherein the first current source is connected in parallel or in reverse series between a power supply and a common potential, the first main source follower is formed by a first transistor, the first auxiliary source follower is formed by at least one second transistor, the gates of the first transistor and the second transistor are commonly connected as the input of the pre-differential amplifier, a common joint between the first current source and the first main source follower is used as the output of the input buffer unit, and the first auxiliary source follower is used for eliminating the channel length modulation effect of the first main source follower; the first input end and the second input end of the gain amplifying unit are respectively connected with the outputs of the two input buffer units, and the two output ends of the gain amplifying unit are respectively used as the two output ends of the pre-differential amplifier;

The input buffer unit further includes a level shift module for increasing an output level shift, wherein:

The level shifting module is connected between the first current source and the first main source follower, and a common joint between the level shifting module and the first current source is used as the output of the input buffer unit; and/or

The level shifting module is connected between the first primary source follower and the first secondary source follower.

8. The pre-differential amplifier according to claim 7, wherein the gain amplifying unit comprises a first operational amplifier, a second operational amplifier, a first voltage dividing element, a second voltage dividing element and a third voltage dividing element, wherein a positive input end of the first operational amplifier is used as a first input end of the gain amplifying unit, one end of the first voltage dividing element is connected with an output end of the first operational amplifier, the other end of the first voltage dividing element is connected with an inverting input end of the first operational amplifier and one end of the second voltage dividing element, the other end of the second voltage dividing element is connected with an inverting input end of the second operational amplifier and one end of the third voltage dividing element, a positive input end of the second operational amplifier is used as a second input end of the gain amplifying unit, the other end of the third voltage dividing element is connected with an output end of the second operational amplifier, an output end of the first operational amplifier is used as a first output end of the gain amplifying unit, and an output end of the second operational amplifier is used as a second output end of the gain amplifying unit.

9. The pre-differential amplifier of claim 7, wherein the gain amplification unit comprises a first operational amplifier, a first voltage division element, a second voltage division element, a third voltage division element and a fourth voltage division element, one end of the first voltage division element is used as a first input end of the gain amplification unit, the other end of the first voltage division element is connected with a non-inverting input end of the first operational amplifier, one end of the second voltage division element is used as a second input end of the gain amplification unit, the other end of the second voltage division element is connected with an inverting input end of the first operational amplifier, the third voltage division element is connected between the non-inverting input end and the inverting output end of the first operational amplifier, and the fourth voltage division element is connected between the inverting input end and the non-inverting output end of the first operational amplifier, and the inverting output end of the first operational amplifier is respectively used as a first output end and a second output end of the gain amplification unit.

10. An integrated circuit comprising a preamplifier according to any of claims 1 to 6.