JP2003099390A - Dma circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA (direct memory access) circuit incorporating a CPU peripheral device, the circuit being configured as a high-speed, low-cost and highly functional system so as to reduce a load on a CPU by writing various instructions from the CPU without the intermediary of execution by the CPU, after finishing of DMA. SOLUTION: A DMA controller 3 in a CPU peripheral device body 1 includes an automatic write control circuit 7 and an automatic write instruction storage area 6. In the DMA circuit, an interrupt signal issued at the end of DMA transfer is input into the write control circuit 7 for writing instructions within the instruction storage area 6 into a CPU peripheral device core 2. As a result this process enables the CPU to eliminate fixed instructions to be executed after the end of DMA transfer. After all the instructions within the storage area 6 have been executed, the process is interrupted into a CPU11, and the CPU11 can write a next DMA-start instruction into the CPU peripheral device.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a DMA (Direct Mem
ory access) circuit, especially CPU (Central Process)
ing Unit) The present invention relates to improvement of a DMA circuit built in a peripheral device.

[0002]

2. Description of the Related Art Conventionally, this type of DMA circuit is disclosed, for example, in Japanese Unexamined Patent Publication No. 7-87162, "Modem Interface and Facsimile Machine", in Japanese Unexamined Patent Publication No. 7-175781, "Digital Signal Processor", in Japanese Unexamined Patent Publication No. 11-175781. −
It is disclosed in "Reception Data Processing Method" of JP-A-289357 and "DMA Device" of JP-A-2000-298640.

FIG. 6 is a block diagram showing the configuration of a conventional DMA circuit disclosed in the above-mentioned Japanese Patent Laid-Open No. 7-87162. In this prior art, the DMA circuit is
It is used to reduce the load on the CPU by not outputting the interrupt signal generated during MA execution to the CPU. The modem interface 100 includes a communication control unit 11
0, modem FIFO (first-in first-out) memory unit 111,
DMAC (DMA controller) 112, INTC11
3, a signal switching unit 114 and a MODEM (modulator / demodulator) 115 are included.

Here, the communication control unit 110 uses the INTC1
And a communication control and switching unit 1 for communication.
Recognize the signal from 14. The MODEM 115 performs modulation / demodulation of signals or image information according to various protocols.
Further, it has a data buffer and sends out a data buffer empty interrupt signal. DMAC112 is MOD
Data is transferred between the modem FIFO memory unit 111 and the data buffer in synchronization with the data buffer empty interrupt signal from the EM 115, and an end signal is sent when the DMA transfer is completed. The INTC 113 notifies the communication control unit 110 of the signal from the signal switching unit 114 according to the priority order. The signal switching unit 114 uses the MO
The data buffer empty interrupt signal from the DEM 115 is switched to the DMAC 112 or INTC 113.

Next, the operation of the DMA circuit shown in FIG. 6 will be described. When the communication control unit 110 sets the MODEM 115 in the transmission mode, the DMAC 112 sets the modem FIF.
The data stored in the O memory unit 111 is stored in the MODEM 11
5 to the data buffer. DMAC112 is DM
When the A transfer is completed, the data buffer empty interrupt signal output from the MODEM 115 is switched from the DMAC 112 to the INTC 113 by the signal switching unit 114.

[0006]

DISCLOSURE OF THE INVENTION Conventional DM as described above
In the A circuit, the access operation from the CPU to the CPU peripheral device is always input at the time of the DMA end interrupt.
There is a limit to the U load reduction. Therefore, when there are a plurality of DMA devices for one CPU, the performance of the CPU cannot be fully obtained, and therefore, it is necessary to use a CPU with higher performance, which causes a problem that the system becomes expensive. It was

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide an improved DMA circuit that enables a high-performance system to be configured at high speed and at low cost.

[0008]

A DMA circuit according to the present invention is built in a CPU peripheral device main body connected to a CPU via an address bus and a data bus, accesses an external memory, and has an external interface. A CPU peripheral device core unit that is a core of the connected CPU peripheral device and a DMA control circuit that operates according to a DMA request signal output from the CPU peripheral device core unit are provided. According to the preferred embodiment of the present invention, the memory is directly connected to the address bus and the data bus.
The CPU peripheral device body includes an arbitration circuit that arbitrates access from the CPU and the DMA control circuit to the CPU peripheral device core unit. The memory is connected to the arbitration circuit via the memory control circuit. The DMA control circuit is connected to an address bus and outputs a memory address during a DMA transfer, a DMA address control circuit that decrements each DMA cycle and outputs a transfer end signal when a predetermined value is reached, and a transfer An automatic write control circuit that is activated by an end signal and outputs a control signal to the CPU peripheral device core unit, and an automatic write instruction that is connected to the address bus and the data bus and stores the address and data in the CPU peripheral device core unit Including a storage area.

Further, the DMA circuit of the present invention is built in a CPU peripheral device main body connected to the CPU to enable access to an external memory, and controls an address to be stored in the external memory during DMA transfer. DMA address control circuit and DM for counting the number of DMA transfers
An A transfer counter, an automatic write control circuit that controls writing of an instruction to the CPU peripheral device core section instead of the CPU when the DMA ends, and a CPU of the automatic write control circuit that writes to the CPU peripheral device core section. It is equipped with an automatic write instruction storage area for storing instructions, and a DMA
When the count value of the transfer counter reaches a predetermined value, a transfer end signal is output to the automatic write control circuit, and the CPU
When there is no automatic write command to the peripheral device core section, an interrupt signal is output to the CPU.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION In order to clarify the above and other objects, features and advantages of the present invention, preferred embodiments of a DMA circuit according to the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 1 is a block diagram showing a configuration of a first embodiment of a DMA circuit according to the present invention. In FIG. 1, a CPU peripheral device body 1 is composed of a CPU peripheral device core unit 2 and a DMA control circuit 3.
Further, the DMA control circuit 3 includes a DMA address control circuit 4, a DMA transfer counter 5, and an automatic write command storage area 6
And an automatic write control circuit 7.

The CPU peripheral device core section 2 of the CPU peripheral device main body 1 is a core (core) of a CPU peripheral device such as an external serial port, and is provided by an address bus and a data bus to the CPU (see FIG. 2 which will be described later). 1
1)). CPU peripheral device
For example, it has a function of turning on / off various instructions executed after the execution of DMA. Further, the CPU peripheral device has an area for storing various instructions, and various instructions can be rewritten. On the other hand, the DMA control circuit 3 responds to the CP request signal 9 output from the CPU peripheral device core unit 2 according to the CP request signal CP.
Bus arbitration for the CPU connected to the U peripheral device body 1 is performed.

The DMA address control circuit 4 of the DMA control circuit 3 outputs an address to the external memory at the time of DMA transfer and increments the address after the DMA transfer. The DMA transfer counter 5 decrements after completion of one DMA cycle. Further, when the DMA transfer counter 5 becomes “0”, the transfer end signal 8 is output to the automatic write control circuit 7.

The automatic write control circuit 7 of the DMA control circuit 3 is activated by the transfer end signal 8 output from the DMA transfer counter 5. Then, the automatic write control circuit 7 outputs a control signal for writing an instruction to the CPU peripheral device core unit 2. Further, the instruction in the automatic write instruction storage area 6 is output to the CPU peripheral device core unit 2. The automatic write command storage area 6 is
The address, write data, and write flag in the CPU peripheral device core unit 2 are stored.

Next, FIG. 2 shows the D according to the present invention shown in FIG.
1 shows a system configuration example using the first embodiment of an MA circuit. In the system shown in FIG. 2, the CPU peripheral device 1 has a CPU 11 using an address bus and a data bus.
And an external memory (Memory) 12 are interconnected.

The operation of the DMA circuit shown in FIG. 1 will be described below with reference to the system configuration diagram of FIG. 2 and the flowchart of FIG. First, the system starts (step S1). Here, the operation starts from the state where the CPU peripheral device core unit 2 is not outputting a data request. The CPU peripheral device core unit 2 determines whether or not a DMA has occurred (step S2). If no DMA occurs (step S
2: NO), the process returns to step S2 again, and it is determined whether or not DMA has occurred. When the DMA is generated (step S2: YES), the DMA control circuit 3 makes a bus hold request to the CPU 11 (step S3). Next, it is determined whether the CPU 11 has opened the bus (step S4). When the CPU 11 releases the bus (step S4: YES), DMA data transfer is performed (step S5), and the DMA control circuit 3 releases the bus hold (step S6). Then, the DMA transfer counter 5
Is decremented and the DMA address is incremented (step S7).

Next, it is determined whether the DMA transfer counter 5 is "0" (step S8). If it is not "0" (step S8: NO), the process returns to step S2. On the other hand, when the DMA transfer counter 5 is "0" (step S8: YES), it is determined whether or not there is an instruction in the automatic write instruction storage area 6 (step S).
9). Next, it is determined whether or not there is an automatic write command in the automatic write command storage area 6 (step S9). If the automatic write command is present (step S9: YES), the automatic write is executed (step S10), and the process returns to step S9 described above. When there is no automatic write command in the automatic write command storage area 6 (step S9: NO), an interrupt is output (step S11) and all the DMA processing is finished (step S12).

Referring now to FIG. 3, the DMA according to the present invention.
A second embodiment of the circuit will be described. For convenience of explanation, the same reference numerals are used for the components corresponding to the components of the first embodiment described above. The CPU peripheral device body 1 includes a CPU peripheral device core unit 2, a DMA control circuit 3, an arbitration circuit 13, and a memory control circuit 14. This memory control circuit 14 is an external memory (Memory)
It is connected to 12.

The DMA control circuit 3 and the arbitration circuit 13 are
CPU described later via address bus and data bus
11 is connected. Further, the DMA control circuit 3 and the arbitration circuit 13 send the interrupt signal 1 to the CPU 11, respectively.
5 and CPU wait signal are output. The DMA control circuit 3 outputs the DMA wait 10 to the CPU peripheral device core unit 2. Also, CPU peripheral device core unit 2
Outputs a DMA request 9 to the DMA control circuit 3. CP
The U peripheral device core unit 2 and the arbitration circuit 13 are bidirectionally connected. Further, the arbitration circuit 13 is connected to the external memory 12 via the memory control circuit 14.

FIG. 4 shows a system configuration diagram using the DMA circuit shown in FIG. In the first embodiment of the DMA circuit according to the present invention, the connection destination of the memory 12 is a CPU.
It is the peripheral device body 1. CPU11 and CP
The U peripheral device bodies 1 are interconnected by an address bus and a data bus, respectively. Further, in the internal configuration of the CPU peripheral device main body 1, the connection from the CPU 11 to the CPU peripheral device core unit 2 is performed via the arbitration circuit 13. The arbitration circuit 13 includes a CPU 11 and a DMA.
The access from the control circuit 3 to the CPU peripheral device core unit 2 is arbitrated. Further, the CPU 11 and the CPU peripheral device core unit 2 arbitrate the access to the memory 12 from the DMA access. Therefore, the DMA generated in the CPU peripheral device main body 1 does not require a bus hold request, and thus has the effect of improving the bus usage efficiency.

The configuration and operation of the preferred embodiment of the DMA circuit according to the present invention has been described above in detail. However, such an embodiment is merely an example of the present invention and does not limit the present invention in any way. Those skilled in the art can easily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention.

[0022]

As will be understood from the above description, the DMA circuit of the present invention has the following remarkable practical effects. First of all, after the completion of DMA, it is possible to execute the instructions of various devices without depending on the instruction of the CPU. The reason is that the CPU peripheral device is provided with an area capable of storing instructions after DMA termination and a circuit capable of automatically executing the instructions.

Secondly, the system is excellent in high speed by reducing the load on the CPU. The reason is that the CPU peripheral device automatically executes the instruction after the end of DMA,
This is because there is no need for the CPU to detect an interrupt or the like and to execute a command after the end of the DMA.

Third, it is possible to provide a highly functional system at a low cost. The reason is that a high-performance system requires a higher-speed CPU because the load on the CPU is higher, but according to the present invention, in a system having a plurality of CPU peripheral devices, the load on the CPU is reduced. This is because a high speed CPU is not required.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a DMA circuit according to the present invention.

FIG. 2 is a block diagram showing a system configuration using the DMA circuit of FIG.

FIG. 3 is a block diagram showing a configuration of a second embodiment of a DMA circuit according to the present invention.

FIG. 4 is a block diagram of a system configuration using the DMA circuit shown in FIG.

5 is a flowchart showing an operation of the DMA circuit of FIG.

FIG. 6 is a block diagram showing a configuration of a conventional DMA circuit.

[Explanation of symbols]

1 CPU peripheral device body 2 CPU peripheral device core 3 DMA control circuit 4 DMA address control circuit 5 DMA transfer counter 6 Automatic write command storage area 7 Automatic write control circuit 8 Transfer end signal 9 DMA request signal 10 DMA wait signal 11 CPU 12 External memory 13 Arbitration circuit 14 Memory control circuit 15 Interrupt signal

Claims (6)

[Claims] 1. A C via an address bus and a data bus.
Built in the CPU peripheral device body connected to PU,
A DMA circuit for accessing an external memory includes a CPU peripheral device core unit which is connected to an external interface and serves as a core of a CPU peripheral device, and a DMA control circuit which operates according to a DMA request signal output from the CPU peripheral device core unit. DMA characterized by
circuit. 2. The DMA circuit according to claim 1, wherein the memory is directly connected to the address bus and the data bus. 3. The CPU peripheral device body is the CP
The DMA circuit according to claim 1, further comprising an arbitration circuit that arbitrates access from the U and the DMA control circuit to the CPU peripheral device core unit. 4. The DMA circuit according to claim 3, wherein the memory is connected to the arbitration circuit via a memory control circuit. 5. The DMA control circuit, which is connected to the address bus and outputs an address to the memory at the time of DMA transfer, decrements each DMA cycle, and sends a transfer end signal when a predetermined value is reached. A DMA transfer counter for outputting, an automatic write control circuit that is activated by the transfer end signal and outputs a control signal to the CPU peripheral device core unit, and the CPU peripheral device core connected to the address bus and the data bus. 5. The DMA circuit according to claim 1, further comprising an automatic write command storage area for storing an address and data in the unit. 6. A DMA circuit built in a CPU peripheral device main body connected to a CPU to enable access to an external memory, and a DMA address control circuit for controlling an address to be stored in the external memory during DMA transfer. ,
A DMA transfer counter for counting the number of DMA transfers,
An automatic write control circuit that controls writing of an instruction to the CPU peripheral device core unit in place of the CPU when the DMA ends, and an instruction of the CPU that the automatic write control circuit writes to the CPU peripheral device core unit. An automatic write command storage area for storing the data, and when the count value of the DMA transfer counter reaches a predetermined value, outputs a transfer end signal to the automatic write control circuit,
A DMA circuit, which outputs an interrupt signal to the CPU when there is no automatic write command to the PU peripheral device core section.