JP2003086615A - Method for sealing resin in semiconductor device - Google Patents
Method for sealing resin in semiconductor deviceInfo
- Publication number
- JP2003086615A JP2003086615A JP2001272879A JP2001272879A JP2003086615A JP 2003086615 A JP2003086615 A JP 2003086615A JP 2001272879 A JP2001272879 A JP 2001272879A JP 2001272879 A JP2001272879 A JP 2001272879A JP 2003086615 A JP2003086615 A JP 2003086615A
- Authority
- JP
- Japan
- Prior art keywords
- resin composition
- resin
- semiconductor device
- temperature
- mixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 24
- 229920005989 resin Polymers 0.000 title claims abstract description 23
- 239000011347 resin Substances 0.000 title claims abstract description 23
- 238000007789 sealing Methods 0.000 title claims abstract description 15
- 239000011342 resin composition Substances 0.000 claims abstract description 33
- 239000003054 catalyst Substances 0.000 claims abstract description 6
- 238000006243 chemical reaction Methods 0.000 claims abstract description 5
- 239000002131 composite material Substances 0.000 claims description 19
- 238000005538 encapsulation Methods 0.000 claims description 12
- 239000000203 mixture Substances 0.000 claims description 5
- 238000004132 cross linking Methods 0.000 claims description 3
- 238000003672 processing method Methods 0.000 claims 1
- 239000007790 solid phase Substances 0.000 claims 1
- 238000005520 cutting process Methods 0.000 abstract description 3
- 239000007787 solid Substances 0.000 abstract description 2
- 230000001737 promoting effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000003795 chemical substances by application Substances 0.000 description 7
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 6
- 230000009467 reduction Effects 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 150000001412 amines Chemical class 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 150000008065 acid anhydrides Chemical class 0.000 description 2
- 239000002775 capsule Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 229920003986 novolac Polymers 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 238000007259 addition reaction Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 125000000524 functional group Chemical group 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000003094 microcapsule Substances 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 239000000049 pigment Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 150000003512 tertiary amines Chemical class 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- AYEKOFBPNLCAJY-UHFFFAOYSA-O thiamine pyrophosphate Chemical compound CC1=C(CCOP(O)(=O)OP(O)(O)=O)SC=[N+]1CC1=CN=C(C)N=C1N AYEKOFBPNLCAJY-UHFFFAOYSA-O 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、一括封止法による
半導体装置の樹脂封止方法に関するものである。ここで
いう一括封止法とは、大面積基板を樹脂封止した後に切
断し半導体装置を製造する方法の総称であり、ＭＡＰ
（モールドアレイパッケージ）、ＢＧＡ（ボールグリッ
ドアレイ）、ＣＳＰ（チップスケールパッケージ）、Ｗ
ＬＰ（ウエハーレベルパッケージ）、ＮＬＰ（ノンリー
ドタイプパッケージ）等で呼ばれる半導体装置の樹脂封
止方法を示す。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin encapsulation method for semiconductor devices by a collective encapsulation method. The collective sealing method here is a general term for a method of manufacturing a semiconductor device by resin-sealing a large-area substrate and then cutting it.
(Mold array package), BGA (ball grid array), CSP (chip scale package), W
A resin sealing method for a semiconductor device called an LP (wafer level package), an NLP (non-lead type package) or the like will be shown.
【０００２】[0002]
【従来の技術】情報通信分野に於ける急速な技術進歩に
呼応して、電子機器の性能向上、小型軽量化及び低コス
ト化が強く求められ、電子機器の心臓部である半導体装
置及びその搭載基板の高集積高密度化が必須のものとな
っている。この要求は大面積基板を一括して樹脂封止す
る製法案を生み出し、電気接続部材や半導体構成単位の
違い等により様々な呼び方がされている。大きく分類す
ると、基板に半導体素子を高密度搭載する方法と、半導
体素子の集合体と基板を結合する方法の２つである。こ
れらの製法は理論的には従来の製造方法に比べて効率面
で優れる事は言うまでもない。基板や樹脂等の素部材の
使用量を少なくできる、金型の寸法を小さく且つ種類を
少なくできる等の利点が多い。2. Description of the Related Art In response to rapid technological progress in the field of information and communications, there is a strong demand for improved performance of electronic equipment, reduction in size and weight, and cost reduction, and the semiconductor device, which is the heart of electronic equipment, and its mounting. High integration and high density of substrates are essential. This requirement has created a manufacturing method for encapsulating a large-area substrate in resin at once, and is called variously depending on differences in electrical connection members and semiconductor constituent units. When roughly classified, there are two methods: a method of mounting semiconductor elements on a substrate at a high density and a method of bonding an assembly of semiconductor elements and a substrate. It goes without saying that these manufacturing methods are theoretically superior in efficiency to the conventional manufacturing methods. There are many advantages such as a reduction in the amount of base members used such as substrates and resins, a reduction in the size of the mold, and a reduction in the types.
【０００３】しかしながら、これらの一括封止技術は検
討努力にも拘わらず汎用化には至っていない。樹脂封止
時に大きな反りを生じ個別の半導体装置に切断すること
が困難である等の問題を抱えているためである。即ち、
実用性や工業性といった面での技術検討が不十分であり
未だに提案段階と呼ぶべき状態のままである。However, these collective encapsulation techniques have not been generalized in spite of research efforts. This is because there is a problem that a large amount of warpage occurs at the time of resin sealing and it is difficult to cut into individual semiconductor devices. That is,
The technical examination in terms of practicality and industriality is insufficient, and it is still in the state to be called the proposal stage.
【０００４】通常、一括封止型半導体装置は１５０℃以
上の温度で樹脂組成物を充填硬化し封止される。これが
室温に冷却される時に寸法収縮の大きな樹脂側に曲がる
ため反り問題を生じるのである。従来の封止方法でこの
問題を解決するためには樹脂の熱伸縮特性を抜本的に変
更すること、基板類と同等にする又はゴム状にする等が
必要である。しかし、いずれも大きな技術課題を有して
おり、例えば、前者は無機物としての性状が強くなるた
め加工温度が高くなり半導体素子が破壊する、後者は樹
脂強度が不足し半導体素子を保護できなくなるといった
問題を生じる。[0004] Usually, a batch-sealed semiconductor device is filled with a resin composition and cured at a temperature of 150 ° C. or higher for sealing. When this is cooled to room temperature, it bends to the side of the resin with large dimensional shrinkage, which causes a warp problem. In order to solve this problem by the conventional sealing method, it is necessary to drastically change the thermal expansion / contraction characteristics of the resin, make it equivalent to the substrates or make it rubber-like. However, both of them have a big technical problem, for example, the former has a high property as an inorganic substance, so that the processing temperature becomes high and the semiconductor element is destroyed, and the latter has insufficient resin strength and cannot protect the semiconductor element. Cause problems.
【０００５】[0005]
【発明が解決しようとする課題】本発明は、一括封止型
半導体装置を樹脂組成物にて充填硬化する場合に生じる
寸法歪みを大幅に低減する技術を提供するものである。SUMMARY OF THE INVENTION The present invention provides a technique for significantly reducing the dimensional distortion that occurs when a packaged semiconductor device is filled and cured with a resin composition.
【０００６】[0006]
【課題を解決するための手段】本発明は、複数の複合成
分で構成される樹脂組成物を使用時に混合又は及び溶融
し且つ１００℃以下の温度で充填及び硬化させることを
特徴とする樹脂封止方法である。DISCLOSURE OF THE INVENTION The present invention is characterized in that a resin composition composed of a plurality of composite components is mixed or melted at the time of use and filled and cured at a temperature of 100 ° C. or lower. It is a stopping method.
【０００７】樹脂組成物は化学反応的に安定な状態で保
管することが好ましく、複合成分毎に混練し分離する、
複合成分毎に混練し固体状で混合する、各複合成分の少
なくとも一つをカプセル化し混合する、等の方法を挙げ
ることができる。ここでいう複合成分とは、樹脂組成物
を構成する成分を複数群に分けた各群を示し２つ以上の
成分を含む混合物（配合物）である。The resin composition is preferably stored in a chemically stable state, and kneaded and separated for each composite component,
Examples of the method include kneading and mixing in a solid state for each composite component, and encapsulating and mixing at least one of the composite components. The term "composite component" as used herein refers to each group obtained by dividing the components constituting the resin composition into a plurality of groups, and is a mixture (blend) containing two or more components.
【０００８】又、１次硬化させた一括封止型半導体装置
を切断後、１００℃より高い温度で２次硬化させること
により樹脂強度、即ち保護機能を高くすることが好まし
い。この場合、樹脂組成物が１次及び２次硬化時に活性
を示す複数の触媒を含むことが好ましい。Further, it is preferable to increase the resin strength, that is, the protective function, by cutting the primary cured batch-encapsulated semiconductor device and then secondary curing at a temperature higher than 100.degree. In this case, it is preferable that the resin composition contains a plurality of catalysts that are active during the primary and secondary curing.
【０００９】樹脂組成物は硬化時及び冷却時に収縮す
る。まず、架橋反応により次に熱エネルギー減少により
体積が縮む。尚、付加反応型樹脂組成物では後者による
収縮が大きい。即ち、樹脂封止時の寸法歪みを小さくす
るためには低温（室温との温度差が小さい条件）で充填
硬化することが必要である。特に好ましくは８０℃以下
が望ましく、室温硬化型の熱硬化性樹脂組成物や光硬化
性樹脂組成物等を用いることができる。The resin composition shrinks during curing and cooling. First, due to the crosslinking reaction, the volume is reduced due to the reduction of heat energy. Incidentally, in the addition reaction type resin composition, the shrinkage due to the latter is large. That is, in order to reduce the dimensional distortion at the time of resin sealing, it is necessary to fill and cure at a low temperature (a condition where the temperature difference from room temperature is small). Particularly preferably, the temperature is 80 ° C. or lower, and a room temperature curable thermosetting resin composition, a photocurable resin composition or the like can be used.
【００１０】樹脂組成物は、樹脂、硬化剤、充填材、硬
化促進剤及び添加剤（処理剤、顔料等）で構成される。
樹脂としてはエポキシ樹脂、シリコーン樹脂、アクリル
樹脂等、硬化剤としてはノボラック類、酸無水物類、ア
ミン類、充填材としてはシリカ、アルミナ等を挙げるこ
とができる。メーカーとしては、日本化薬、信越化学工
業、東亞合成、大日本インキ化学工業、新日本理化、味
の素、電気化学工業、日本軽金属等を挙げることができ
る。The resin composition comprises a resin, a curing agent, a filler, a curing accelerator, and an additive (treatment agent, pigment, etc.).
The resin may be epoxy resin, silicone resin, acrylic resin or the like, the curing agent may be novolacs, acid anhydrides or amines, and the filler may be silica or alumina. Examples of the manufacturer include Nippon Kayaku, Shin-Etsu Chemical Co., Ltd., Toagosei, Dainippon Ink and Chemicals Co., Ltd., Shinnihon Rika, Ajinomoto, Denki Kagaku Kogyo, Nippon Light Metal and the like.
【００１１】樹脂組成物は物理的又は化学的に反応性を
抑制する方法で保管することが好ましい。例えば、２つ
の複合組成に分け別々に分離する、２つの複合組成を別
々に微粉状にし混合する、特定成分をカプセル化する等
を挙げることができる。カプセル化とは、反応性の高い
成分をマイクロカプセルに入れ隔離したり、複合成分を
別々のカプセルに入れ分離したり、反応性官能基を保護
した潜在性原料を使用する等の技術全般を示す。カプセ
ルは使用時に熱や圧力等で破壊し樹脂組成物が低温で速
硬化する。又、単純な手段であるが上記に加えて更に冷
暗所にて保管することも好ましい。The resin composition is preferably stored by a method of physically or chemically suppressing the reactivity. For example, it may be divided into two composite compositions, separated separately, two composite compositions separately pulverized and mixed, or encapsulation of specific components. Encapsulation refers to general techniques such as placing highly reactive components in microcapsules for isolation, complex components in separate capsules, and using latent raw materials with protected reactive functional groups. . The capsule is destroyed by heat or pressure during use, and the resin composition is rapidly cured at a low temperature. Further, although it is a simple means, it is preferable to store in a cool and dark place in addition to the above.
【００１２】低温で硬化させた一括封止型半導体装置は
最終的に個々の半導体装置に切断される。半導体装置に
厳しい冷熱衝撃性や樹脂強度が要求される場合は、高温
で再加熱し２次硬化することが好ましい。この場合、ま
ず一括封止型半導体装置を冷却時の反りが問題とならな
い寸法に粗切断し、次に加熱冷却後に各半導体装置に切
断しても良い。又、２次硬化する場合は、樹脂組成物に
高温で架橋反応を促進する触媒（硬化促進剤）を予め添
加しておくことが好ましい。The collectively sealed semiconductor device cured at low temperature is finally cut into individual semiconductor devices. When the semiconductor device is required to have severe thermal shock resistance and resin strength, it is preferable to reheat at high temperature to carry out secondary curing. In this case, the batch-sealed semiconductor device may first be roughly cut into a size in which warpage during cooling is not a problem, and then cut into individual semiconductor devices after heating and cooling. In the case of secondary curing, it is preferable to add a catalyst (curing accelerator) that accelerates the crosslinking reaction at a high temperature to the resin composition in advance.
【００１３】硬化促進剤としては、各種樹脂で一般的に
使用される硬化触媒を挙げることができる。例えば、エ
ポキシ樹脂ではイミダゾール系、第３級アミン系、リン
系の市販化合物（メーカーは四国化成工業、日本化薬、
北興化学工業等）を挙げることができる。特に、保管時
は不活性で低温で急速に反応する潜在性の硬化触媒が好
ましい。Examples of the curing accelerator include curing catalysts generally used in various resins. For example, for epoxy resins, imidazole-based, tertiary amine-based, and phosphorus-based commercially available compounds (manufacturers include Shikoku Kasei, Nippon Kayaku,
Hokuko Kagaku Kogyo etc.) can be mentioned. In particular, a latent curing catalyst that is inert during storage and rapidly reacts at low temperature is preferable.
【００１４】図１は、ＭＡＰと呼ばれる一括封止型半導
体装置の断面図である。半導体素子１１が基板１２に高
密度実装されており、両者は金線１３によって電気接続
されている。又、半導体素子は樹脂組成物１５によって
封止された後、個々の半導体装置に破線１６で切断され
る。最終的に個々の半導体装置は母基板に実装され電子
部品の一部となる。FIG. 1 is a sectional view of a collectively sealed semiconductor device called MAP. The semiconductor elements 11 are mounted on the substrate 12 at a high density, and both are electrically connected by the gold wire 13. Further, the semiconductor element is sealed with the resin composition 15 and then cut into individual semiconductor devices at broken lines 16. Finally, each semiconductor device is mounted on a mother board and becomes a part of an electronic component.
【００１５】図２は、ＷＬＰと呼ばれる一括封止型半導
体装置の断面図である。ウエハーレベルの半導体素子集
合体２１と基板２２が金バンプで結合されている。２７
は母基板との電気接続用ポストである。基板は樹脂組成
物２５にて封止された後、個々に半導体装置に破線２６
で切断される。尚、本例の基板は再配線回路とも呼ばれ
る。FIG. 2 is a sectional view of a collective sealing type semiconductor device called WLP. The wafer-level semiconductor device assembly 21 and the substrate 22 are bonded by gold bumps. 27
Is a post for electrical connection with the mother substrate. After the substrates are sealed with the resin composition 25, the semiconductor devices are individually broken with broken lines 26.
Is cut by. The substrate of this example is also called a rewiring circuit.
【００１６】以下、本発明を樹脂組成物の製法例、樹脂
封止の実施例及び比較例にて具体的に説明する。
樹脂組成物（１）の製法
Ａ複合成分としてエポキシ樹脂２５部（ＥＰＰＮ−５０
１、日本化薬）、球状シリカ４０部（ＦＢ−３５、電気
化学工業）、リン系硬化促進剤０．４部（ＴＰＰ、ケイ
アイ化成）及び離型剤０．４部（ヘキストＯＰ、ヘキス
ト）、Ｂ複合成分として酸無水物系硬化剤１２部（ＭＨ
−７００、新日本理化）、球状シリカ２０部（ＦＢ−３
５）、イミダゾール系硬化促進剤０．２部（２Ｅ４Ｍ
Ｚ、四国化成工業）及び離型剤０．２部（ヘキストＳ）
を別々に加熱ニーダを用いて１０分間混練し２つの複合
成分で構成される樹脂組成物を試作した。The present invention will be specifically described below with reference to a method for producing a resin composition, an example of resin encapsulation and a comparative example. 25 parts of epoxy resin (EPPN-50) as a composite component of the production method A of the resin composition (1).
1, Nippon Kayaku), 40 parts of spherical silica (FB-35, Denki Kagaku Kogyo), 0.4 parts of phosphorus-based curing accelerator (TPP, KAI KASEI) and 0.4 parts of release agent (Hoechst OP, Hoechst). , 12 parts of acid anhydride type curing agent as B composite component (MH
-700, New Japan Rika), 20 parts of spherical silica (FB-3
5), 0.2 parts of imidazole-based curing accelerator (2E4M
Z, Shikoku Chemicals) and 0.2 parts release agent (Hoechst S)
Were separately kneaded for 10 minutes using a heating kneader to produce a resin composition composed of two composite components.
【００１７】樹脂組成物（２）の製法
Ａ複合成分としてエポキシ樹脂１４部（ＹＫ−４００
０、三井化学）、球状シリカ５５部（ＴＳＳ−４、龍
森）及びアミン系硬化促進剤０．２部（ＴＡＰ、日本化
薬）、Ｂ複合成分としてノボラック系硬化剤６部（ＸＬ
−２２５、三井化学）球状シリカ２５部（ＴＳＳ−４）
及びアミン系硬化促進剤０．１部（ＤＢＵ、サンアプ
ロ）を別々に２本熱ロールを用いて５回混練し２つの複
合成分を試作した。次に、複合成分毎に微粉砕しこれら
を混合した後、ミニペレット状に加工し樹脂組成物を得
た。14 parts of epoxy resin (YK-400) as a composite component of the production method A of the resin composition (2).
0, Mitsui Chemicals), 55 parts of spherical silica (TSS-4, Tatsumori) and 0.2 parts of amine curing accelerator (TAP, Nippon Kayaku), 6 parts of novolak curing agent as B composite component (XL
-225, Mitsui Chemicals) 25 parts spherical silica (TSS-4)
And 0.1 part of amine-based curing accelerator (DBU, San-Apro) were separately kneaded 5 times by using two heating rolls to produce two composite components as a trial. Next, each composite component was finely pulverized and mixed, and then processed into a mini-pellet form to obtain a resin composition.
【００１８】[0018]
【実施例１】模擬半導体素子を搭載した大面積基板を樹
脂組成物（１）にて封止し図１のような一括封止型半導
体装置を試作した。樹脂組成物はＡ及びＢの両複合成分
を射出成形機を用いて溶融混合し封止金型に充填硬化し
た。これら封止工程の最高温度は７０℃であり硬化時間
は２分であった。この封止工程で得られた一括封止型半
導体装置は室温にて４分割に切断後、２次硬化を１７５
℃で４時間行い、最終的に個別の半導体装置に切断し
た。本例では加工作業時に問題となるような反り現象は
認められなかった。Example 1 A large area substrate on which a simulated semiconductor element was mounted was sealed with a resin composition (1) to fabricate a batch-sealed semiconductor device as shown in FIG. The resin composition was prepared by melting and mixing both composite components A and B using an injection molding machine and filling and curing in a sealing mold. The maximum temperature of these sealing steps was 70 ° C. and the curing time was 2 minutes. The batch-encapsulated semiconductor device obtained in this encapsulation process is cut into four at room temperature and then subjected to secondary curing by 175.
It was performed at 4 ° C. for 4 hours and finally cut into individual semiconductor devices. In this example, no warping phenomenon was found, which would be a problem during processing work.
【００１９】[0019]
【実施例２】金属製の受器に再配線回路を加工したウエ
ハー状半導体素子集合体を格納し次に樹脂組成物（２）
を充填し、その上に剥離紙を敷き更に金属製の重石蓋を
した後、トンネル炉（昇温３０分、５０℃・６時間、降
温１時間）で溶融硬化し図２のような一括封止型半導体
装置を試作した。この装置はほとんど反ることなく容易
に個々の半導体装置に切断できた。Example 2 A wafer-shaped semiconductor element assembly having a rewiring circuit processed was stored in a metal receiver, and then a resin composition (2) was used.
After placing a release paper on top of it and placing a metal weight cap on it, melt and harden it in a tunnel furnace (30 minutes temperature increase, 50 ° C. for 6 hours, 1 hour temperature decrease) and package as shown in Fig. 2. A static semiconductor device was prototyped. This device could be easily cut into individual semiconductor devices with almost no warpage.
【００２０】[0020]
【比較例】実施例２において、溶融硬化工程としてトン
ネル炉ではなく圧縮成型機を用いて１７５℃・２分間で
樹脂封止した。金属製容器より取り出した一括封止型半
導体装置は樹脂組成物側にお椀状に大きく婉曲しており
個々の半導体装置への切断が困難であった。[Comparative Example] In Example 2, resin-sealing was performed at 175 ° C for 2 minutes using a compression molding machine instead of a tunnel furnace as the melt-hardening step. The batch-encapsulated semiconductor device taken out from the metal container had a bowl-shaped bending on the resin composition side, and it was difficult to cut into individual semiconductor devices.
【００２１】[0021]
【発明の効果】本発明は、一括封止型半導体装置の加工
方法を提供するものである。寸法歪みのため実用化が困
難であった提案に鋭意検討を加え工業的な製造方法とし
て確立したものである。本発明の樹脂封止方法により低
コストの半導体装置を商業化することができる。The present invention provides a method of processing a collectively encapsulated semiconductor device. It was established as an industrial manufacturing method by intensively studying the proposal that was difficult to put into practical use due to dimensional distortion. By the resin sealing method of the present invention, a low-cost semiconductor device can be commercialized.
【図１】 一括封止型半導体装置の一例を示す図であ
る。FIG. 1 is a diagram showing an example of a batch-sealed semiconductor device.
【図２】 一括封止型半導体装置の別の一例を示す図で
ある。FIG. 2 is a diagram showing another example of the collectively sealed semiconductor device.
１１、２１ 半導体素子 １２、２２ 基板（電気回路小基板） １３ 金線 １５、２５ 樹脂組成物 １６、２６ 切断面を示す破線 ２７ 電気接続用ポスト 11, 21 Semiconductor element 12, 22 board (small electric circuit board) 13 gold wire 15, 25 Resin composition 16, 26 Dashed line showing cut surface 27 Posts for electrical connection
Claims (4)
構成された樹脂組成物を用いて封止する加工方法に関す
るものであり、該樹脂組成物を使用時に混合又は及び溶
融し且つ１００℃以下の温度で充填及び硬化させること
を特徴とする樹脂封止方法。1. A processing method of encapsulating a batch-encapsulated semiconductor device with a resin composition comprising a plurality of composite components, wherein the resin composition is mixed or melted at the time of use and 100 A resin sealing method comprising filling and curing at a temperature of ℃ or less.
複合成分毎に分離した状態、各複合成分を固相混合した
状態、各複合成分の少なくとも一つをカプセル化した状
態、にて保管されており使用時に混合又は及び溶融する
ことを特徴とする請求項１に記載の樹脂封止方法。2. A resin composition in a chemically stable state, a state in which each composite component is separated, a state in which each composite component is mixed in a solid phase, and a state in which at least one of each composite component is encapsulated. The resin encapsulation method according to claim 1, wherein the resin encapsulation method is stored and stored, and is mixed or melted at the time of use.
断後、１００℃より高い温度で再加熱し２次硬化するこ
とを特徴とする請求項１又は請求項２に記載の樹脂封止
方法。3. The resin encapsulation according to claim 1 or 2, wherein the filled and cured collective encapsulation type semiconductor device is cut and then reheated at a temperature higher than 100 ° C. to be secondarily cured. Method.
００℃より高い温度で架橋反応を促進する２種以上の触
媒を含む２段硬化型組成物であることを特徴とする請求
項３に記載の樹脂封止方法。4. A resin composition at a temperature lower than 100 ° C. and 1
The resin encapsulation method according to claim 3, which is a two-stage curable composition containing two or more kinds of catalysts that promote a crosslinking reaction at a temperature higher than 00 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001272879A JP2003086615A (en) | 2001-09-10 | 2001-09-10 | Method for sealing resin in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001272879A JP2003086615A (en) | 2001-09-10 | 2001-09-10 | Method for sealing resin in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003086615A true JP2003086615A (en) | 2003-03-20 |
Family
ID=19098177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001272879A Pending JP2003086615A (en) | 2001-09-10 | 2001-09-10 | Method for sealing resin in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003086615A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011054653A (en) * | 2009-08-31 | 2011-03-17 | Elpida Memory Inc | Manufacturing method of semiconductor device |
| JP2018024731A (en) * | 2016-08-08 | 2018-02-15 | 太陽インキ製造株式会社 | Semiconductor encapsulation material |
| JP2021068832A (en) * | 2019-10-25 | 2021-04-30 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
-
2001
- 2001-09-10 JP JP2001272879A patent/JP2003086615A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011054653A (en) * | 2009-08-31 | 2011-03-17 | Elpida Memory Inc | Manufacturing method of semiconductor device |
| JP2018024731A (en) * | 2016-08-08 | 2018-02-15 | 太陽インキ製造株式会社 | Semiconductor encapsulation material |
| JP2021068832A (en) * | 2019-10-25 | 2021-04-30 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
| JP7370215B2 (en) | 2019-10-25 | 2023-10-27 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
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