JP2003068862A - Spiral inductor and high-frequency semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the amount of propagation in noise via a substrate - insulating layer to a spiral inductor formed on a semiconductor substrate in a silicon process, to prevent a high-frequency circuit from being affected by noise from a logic circuit, to inhibit parasitic capacity formed between a means for reducing jump-in noise and the spiral inductor, and hence to prevent characteristic deterioration in the inductor from being generated. SOLUTION: Metal ground wiring 1 is arranged in the same insulating layer as metal wiring 2 where a spiral inductor 21 is formed around the spiral inductor 21 formed on a semiconductor by a silicon process. Additionally, connection to a metal wiring layer 5 that is the lowermost layer is made via a plurality through holes 4 to a plurality of insulting layers 8 from the metal ground wiring 1, and a shield structure for surrounding the spiral inductor 21 by the metal ground wiring 1, through hole 4, and the metal wiring 5 of the lowermost layer is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spiral inductance structure formed by using a semiconductor device manufacturing process.

[0002]

2. Description of the Related Art A spiral inductor is generally used as an inductor in a high frequency circuit of an integrated circuit. The spiral inductor is a multilayer wiring inductor in which wiring is formed in a spiral shape on a plane, and an example thereof is shown in FIGS. 6 and 7. FIG. 6 is a top view of the spiral inductor formed in the semiconductor device. Figure 7
FIG. 7 is a cross-sectional view taken along the line AA ′ of the spiral inductor shown in FIG. 6.

As shown in FIG. 6, the spiral inductor 121 includes a spiral wiring 102 formed on the uppermost insulating layer 116 of the semiconductor device 101 and an insulating layer (here, an insulating layer different from the uppermost insulating layer 116). , Linear wiring 10 formed on the uppermost second interlayer insulating layer) 117
3 and a through hole 115 for connecting the wiring 102 and the wiring 103. Further, one terminal 114 of the spiral inductor 121 is provided at an end of the spiral wiring 102, and is connected to a terminal of an external circuit (not shown) or the like. Further, the spiral inductor 12 is provided at the end of the linear wiring 103.
The other terminal 113 of 1 is provided and is connected to a terminal or the like of an external circuit (not shown).

As shown in FIG. 7, the conventional spiral inductor has a cross-sectional structure in which the uppermost insulating layer 116 is formed on the SiO ₂ film formed on the semiconductor substrate 106 via a plurality of interlayer insulating layers. The wiring 102 is formed on top. The spiral inductor 121 is formed by forming the wiring 102 on the uppermost insulating layer 116 in a spiral shape.

In FIG. 7, the plurality of insulating layers 108 is one.
An example of a 0-layer configuration is shown. Multiple insulating layers 108
Are formed for forming elements of an analog circuit section and a digital circuit section (not shown) and for multi-layer wiring.

The spiral inductor configured as described above is used as an impedance matching circuit for efficiently transmitting electric power in a high frequency circuit and as a resonance circuit for constantly maintaining the vibration of an oscillator.

Conventionally, in the process of high frequency integrated circuits, compound semiconductors such as GaAs which can form a transistor having good high frequency characteristics due to its high electron mobility are often used. Such a compound semiconductor is a semi-insulator, and in a spiral inductor formed on a semi-insulating substrate, the parasitic capacitance between the compound inductor and the substrate does not cause any particular problem. As for semiconductor devices using compound semiconductors, up to now, analog circuits such as amplifier circuits and mixers have been developed, and digital circuits such as logic units are the same as the above analog circuits. It has not been possible to mix them in a semiconductor device.
Therefore, the jump-in noise from the digital circuit to the analog circuit, which occurs when the analog circuit and the digital circuit are mixedly mounted in the same semiconductor device, is not a problem.

However, in recent years, with the progress of technology, miniaturization in the silicon process has progressed, and it has become possible to form a transistor having excellent high frequency characteristics on a silicon substrate, and a high frequency integrated circuit can be formed on the silicon substrate. Came. Since it is easy to embed a logic circuit on a silicon substrate on which a spiral inductor has been formed using a silicon process,
To the spiral inductor formed on the semiconductor substrate,
The problem of noise through the board becomes unavoidable.

The silicon substrate is a semiconductor substrate,
Since the insulating layer is provided between the spiral inductor and the substrate, the parasitic capacitance between the spiral inductor and the substrate also becomes a problem. That is, in the spiral inductor, the spiral wiring 1 formed especially in the upper wiring layer 1
Since 02 is relatively large in area, the interlayer insulating layer 1
08, between the wiring 102 and the semiconductor substrate 106,
A parasitic capacitance will be formed.

Further, since the spiral wiring 102 formed on the uppermost insulating layer 116 is relatively large in area as described above, signals (not shown) in a digital circuit portion and an analog circuit are also amplified. When an output signal or the like in the circuit propagates as jump-in noise through the interlayer insulating layer 108 and the semiconductor substrate, the high frequency circuit using this spiral inductor is likely to be adversely affected.

Therefore, Japanese Unexamined Patent Publication No. 2000-188373 discloses a technique relating to a spiral inductor in which a polysilicon layer is inserted directly below the inductor. This spiral inductor can reduce the parasitic resistance and parasitic capacitance attached to the inductor by setting the polysilicon layer to the same potential as the substrate substrate, and when the inductor is part of the resonant circuit of the oscillator circuit, Phase noise can be reduced.

[0012]

However, in the above method, the parasitic capacitance between the wiring and the polysilicon becomes large, and the characteristics of the spiral inductor are significantly deteriorated.
Further, it is considered that noise propagates from around the spiral inductor via the interlayer insulating layer.

Therefore, the present invention was created to solve the above problems, and its purpose is to propagate noise through a substrate-insulating layer to a spiral inductor formed on a semiconductor substrate in a silicon process. Reduce the amount,
That is, the noise from the logic circuit does not adversely affect the high frequency circuit. Further, in the present invention, it is to suppress the parasitic capacitance formed between the portion where the plunge noise is reduced and the spiral inductor to be small, and not to cause the characteristic deterioration of the inductor.

[0014]

The present invention has the following structure as means for solving the above problems.

(1) A shield portion is provided around a spiral wiring formed on a predetermined layer of a semiconductor device having a plurality of insulating layers by a silicon process.

In this structure, the spiral inductor has a shield portion around a spiral wiring formed by a silicon process on a predetermined layer of a semiconductor device having a plurality of insulating layers. Therefore, when a digital circuit such as a logic circuit is formed on the same substrate as the spiral inductor, noise propagation from the digital circuit is significantly reduced, and adverse effects on the high frequency circuit can be suppressed.

(2) The shield portion is on the same layer as the spiral wiring, a ground conductive surface formed around the spiral wiring, a layer on which the spiral wiring is formed, and one layer or It is characterized by comprising a conductive surface formed on a layer separated by a plurality of layers, and a ground conductive surface and a connecting portion for electrically connecting the conductive surface.

In this structure, the spiral inductor is separated from the ground conductive surface formed around the spiral wiring on the same layer as the spiral wiring, and the layer on which the spiral wiring is formed by one layer or a plurality of layers. The shield portion includes a conductive surface formed on the layer, a ground conductive surface, and a connecting portion for electrically connecting the conductive surface. Therefore, it is possible to achieve both the shield effect and the reduction of the parasitic capacitance to the spiral inductor by the shield portion.

(3) The conductive surface is formed of a substrate wiring material.

In this structure, the shield portion of the spiral inductor has a conductive surface made of a substrate wiring material. Therefore, it is easy to manufacture and does not cause a cost increase.

(4) The conductive surface is formed of polysilicon.

In this structure, the shield portion of the spiral inductor has a conductive surface made of polysilicon. Therefore, the manufacturing is easy, and the increase in cost can be suppressed.

(5) It is characterized in that the connecting portion is a plurality of through holes arranged around the spiral wiring.

In this structure, the connecting portion of the spiral inductor is composed of a plurality of through holes arranged around the spiral wiring. Therefore,
It is possible to connect the ground conductive surface and the conductive surface by a method that can be easily realized.

(6) The connecting portion is a groove-shaped concave portion arranged around the spiral inductor.

In this structure, the connecting portion of the spiral inductor is constituted by a groove-shaped recessed portion arranged around the spiral inductor. Therefore, the shield effect can be further enhanced.

(7) A spiral inductor according to any one of (1) to (6) is provided.

In this structure, the high frequency semiconductor device is
The spiral inductor according to any one of (1) to (6) is provided. Therefore, since it is possible to form an inductor that is resistant to noise, it is possible to realize a high-frequency semiconductor device in which analog circuits and digital circuits are mixedly mounted, which allows the digital processing circuit to be mixedly mounted in the amplifier circuit of the input section of the mobile phone using the GHz band. Thus, for example, it is effective in reducing the weight and size of a mobile phone.

[0029]

1 is a top view of a spiral inductor according to a first embodiment of the present invention. Also, FIG.
FIG. 2 is a cross-sectional view taken along the line AA ′ of the spiral inductor shown in FIG. 1. The spiral inductor 21 shown in FIG.
The insulating layer 8 having a 10-layer structure is provided.

Here, FIGS. 1 and 2 show only the spiral inductor according to the embodiment of the present invention, and other analog circuits and digital circuit parts constituting the semiconductor device are constructed by existing technology. , Omitted.

The structure of ten interlayer insulating layers 8 (here, SiO ₂ ) formed on the semiconductor substrate 6 (here, Si) will be described as an example. The protective layer for protecting the metal wiring 2 and the like on the uppermost insulating layer 16 is not shown. Further, the ten interlayer insulating layers 8 are formed for forming elements of an analog circuit portion and a digital circuit portion (not shown) and for multi-layer wiring.

As shown in FIG. 1, the spiral inductor 21 includes a plurality of insulating layers 8 formed on the semiconductor substrate 6.
Of the spiral metal wiring 2 formed on the uppermost insulating layer 16 and an insulating layer different from the uppermost insulating layer 16 for the lead line from the center of the spiral wiring 2 (here, from the uppermost layer). The metal wiring 3 formed on the second interlayer insulating layer) and the wiring 3 at the spiral center of the wiring 2.
And a through hole 15 for electrical connection. The wirings 2 and 3 are formed of a substrate wiring material such as aluminum wiring or copper wiring.

Further, the terminal 1 for pulling out the wiring 2 at the end of the wiring 2 and connecting it to another circuit (not shown)
4 is provided, and a terminal 13 for pulling out the wiring 3 and connecting it to another circuit (not shown) is provided at an end of the wiring 3.
Is provided.

Next, the characteristic structure of the present invention will be described. In the present invention, as shown in FIG.
As the wiring layer on the lowermost insulating layer 7 formed above, the metal surface 5 which is a conductive surface having a size larger than the outer peripheral portion of the spiral inductor 21 is formed. On the other hand, as a wiring layer (the same surface as the wiring 2) on the uppermost insulating layer 16, a ground metal surface 1 which is a ground conductive surface is formed in the peripheral portion of the spiral inductor 21. The metal surface 5 and the ground metal surface 11 are formed of a substrate wiring material such as aluminum wiring and copper wiring, and the ground metal surface 11 is grounded by wiring not shown.

Further, the metal surface 5 and the ground metal surface 11 are connected to each other through a plurality of through holes 4 which are connection portions penetrating the interlayer insulating layer 8. Here, the plurality of through holes 4 are formed in a direction perpendicular to the surface on which the spiral inductor 21 is formed.

With this structure, the spiral inductor 21 formed on the semiconductor substrate forming the semiconductor device by the silicon process via the insulating layer has the ground metal surface 11 on the uppermost insulating layer 16 and It is shielded by the shield portion composed of the metal surface 5 on the lowermost insulating layer 7 and the plurality of through holes 4 arranged around the spiral inductor 21.

As a result, although not shown, it is possible to remarkably reduce the influence of plunge noise from the analog circuit or digital circuit formed on the same semiconductor substrate through the semiconductor substrate and the plurality of insulating layers. .

Further, since the metal surface 5 can be formed at a distance from the surface on which the spiral inductor 21 is formed by forming one layer or a plurality of layers, the parasitic capacitance can be reduced. Therefore, it is possible to prevent the deterioration of the inductor characteristics due to the parasitic capacitance.

Further, the plurality of through holes 4 for connecting the metal surface 5 and the ground metal surface 11 can be formed by adjusting the number to be formed or by adjusting the intervals so that the shield effect can be improved. You can set it to.

In addition, the diameter of the through hole 4 may be increased, or instead of the through hole, grooves (recesses) are formed in the plurality of insulating layers 8 to connect the metal surface 5 and the ground metal surface 11. You may. Further, the groove may be extended over the entire surface to surround the periphery of the spiral inductor 21 excluding the terminal portion of the spiral inductor. However, the connection by the through hole is a method that can be easily realized among the general techniques for connecting the insulating layers.

In addition, in which of the plurality of insulating layers 8 the spiral inductor, the metal surface 5 and the ground metal surface 1 are formed.
Whether 1 is formed may be set in consideration of the shield effect and the parasitic capacitance. Therefore, as shown in FIG. 2, the spiral inductor 21, the metal surface 5, and the ground metal surface 11 may be formed in addition to the uppermost insulating layer 16 and the lowermost insulating layer 7.

Further, the spiral inductor 21 is formed on an arbitrary interlayer insulating layer in the plurality of insulating layers 8, and the ground metal surface 11 of the uppermost insulating layer 16 is a metal surface having a size larger than the outer peripheral portion of the spiral inductor 21. By connecting the metal surface 5 and the ground metal surface 11 with the plurality of through holes 4, the periphery of the spiral inductor 21 can be surrounded by the shield portion.

Further, the ground metal surface 11 formed on the periphery of the spiral inductor 21 on the same plane as the spiral inductor 21 is expanded to an analog circuit or a digital circuit portion (not shown) to generate from the analog circuit or the digital circuit. It is possible to reduce noise.

Next, the effect of providing the shield part will be described using an equivalent circuit of a spiral inductor. Figure 8
FIG. 8 is an equivalent circuit diagram showing noise propagation in the conventional spiral inductor shown in FIGS. 6 and 7. The equivalent circuit of the spiral inductor 21 shown in FIG. 8 is a case where 10 insulating layers are provided, and each dimension of the spiral inductor is
Track width 15 μm, track space 5 μm, track length 4000
μm. The insulating layer 8 is made of SiO ₂ and has a thickness of 1.5 μm. Further, in the equivalent circuit of the spiral inductor, the inductance value is represented by L1, the wiring resistance is represented by R1, the parasitic capacitance by the insulating layer 8 is represented by C1, the wiring resistance corresponding to the semiconductor substrate 6 is represented by R2, and the parasitic capacitance is represented by C2. In addition, R is used as a model showing the propagation of noise.
3 = 10 kΩ. The noise signal is generated from the noise source 40 and propagates from the substrate surface to the spiral inductor 21 through the interlayer insulating layer 8. The estimation of the amount of noise propagation is given by the amount of power passing from the noise source 10 to the input / output units 41 and 42 of the spiral inductor 21.

FIG. 3 is an equivalent circuit diagram showing noise propagation in the spiral inductor according to the first embodiment of the present invention. This equivalent circuit is calculated from the conventional example shown in FIG. 8 in consideration of the spiral sectional structure in the first embodiment of the present invention. The first embodiment of the present invention and the conventional example are
The wiring pattern of the spiral inductor is assumed to be the same. In the first embodiment of the present invention, as shown in the sectional view of FIG. 2, the lowermost metal surface 5 is connected to the metal ground surface 1 through the through hole 4. In this case, the inductance value L1, the wiring resistance R1, the wiring resistance R2 corresponding to the semiconductor substrate 6 and the parasitic capacitance C2, which are the values defined by the wiring pattern of the spiral inductor 21, are the same as those in the first embodiment of the present invention and the conventional example. It has the same value. Bottom metal surface 5
Thus, the parasitic capacitance of the insulating layer 8 becomes C1a (capacitance for 9 insulating layers) and C1b (capacitance for 1 insulating layer). The contact resistance when the lowermost layer metal 5 is connected to the metal ground wiring 1 through the through hole 4 is represented as R4. In this embodiment, 5Ω · layer / hole is calculated as a typical value of a through hole formed by a silicon process. Then, the total number of through holes was set to 45, and connection via the insulating film 9 layer was assumed. As a result, R4 = 5Ω / hole ×
9 layers / 45 pieces = 1.0Ω.

FIG. 4 is a graph showing a noise propagation simulation result by the spiral inductor in the first embodiment of the present invention and the conventional example. In the 2-3 GHz band, the noise propagation amount is −89 dB in the present invention. Therefore, the noise propagation amount of 48 dB can be reduced as compared with the noise propagation amount of −51 dB of the conventional example. In addition, 2-3G
In the Hz band, the characteristic improvement when the spiral inductor of the present invention is used is shown, but the frequency band is an example, and the frequency band of the present invention is not limited.

From these results, it was confirmed that the present invention using an equivalent circuit significantly reduces the influence of noise from the logic circuit and the like formed on the same substrate via the semiconductor substrate.

Next, a spiral inductor according to the second embodiment of the present invention will be described. FIG. 5 is a sectional view of the spiral inductor according to the second embodiment of the present invention. The shape of the spiral inductor according to the second embodiment of the present invention is the same as that of the spiral inductor 21 according to the second embodiment of the present invention, and thus the description thereof is omitted here.

In the spiral inductor 31 according to the second embodiment of the present invention, a conductive polysilicon surface is used instead of the metal surface 5 forming the shield portion of the spiral inductor 21. That is, the semiconductor substrate 6
Conductive polysilicon (polysilicon used for a gate or the like) is provided on (here, Si). Then, similarly to the first embodiment of the present invention, by the plurality of through holes 4 penetrating the ground metal surface 11 formed on the uppermost insulating layer 16 and the interlayer insulating layer 8 (here, SiO ₂ ), It is electrically connected.

By doing so, the spiral inductor 31 formed on the semiconductor substrate via the insulating layer by the silicon process has the ground metal surface 11 on the uppermost insulating layer 16 and the polysilicon on the semiconductor substrate 6. It is shielded by the shield portion constituted by the surface 9 and the plurality of through holes 4 arranged around the spiral inductor 31.

In this case, the interlayer insulating layer formed between the polysilicon surface 9 and the ground metal surface 2 is 10 layers, which is increased by one layer as compared with the first embodiment in which the interlayer insulating layer is 9 layers. It has the effect of lowering the parasitic capacitance.

In the embodiment of the present invention, the configuration in which the spiral inductor and the shield portion are provided on the Si substrate by using the silicon process has been described, but the present invention is not limited to this. For example, on the Si substrate. SiGe
It is also applicable to a semiconductor device formed of (silicon germanium) and is effective for a semiconductor device using an interlayer insulating layer.

As described above, according to the present invention, the ground conductive surface is formed on the same surface as the spiral wiring forming the spiral inductor, and the conductive formed on the surface of the spiral inductor through the interlayer insulating layer. And a connecting means for electrically connecting both surfaces to each other, and achieves both the shielding effect and the reduction of the parasitic capacitance to the spiral inductor by the shielding means.

Further, since it can be constructed by a known technique,
It does not increase the cost.

By forming a spiral inductor resistant to noise, it is possible to realize a high frequency semiconductor device in which an analog circuit and a digital circuit are mixedly mounted. As a result, a digital processing circuit is provided in an amplifier circuit of an input section of a mobile phone using a gigahertz band. It is effective for weight reduction and downsizing of mobile phones such as mixed loading.

[0056]

According to the present invention, the following effects can be obtained.

(1) The spiral inductor has a shield portion around a spiral wiring formed by a silicon process on a predetermined layer of a semiconductor device having a plurality of insulating layers. When a digital circuit such as a logic circuit is formed on the same substrate, noise propagation from the digital circuit is significantly reduced, and adverse effects on the high frequency circuit can be suppressed.

(2) In the spiral inductor, the ground conductive surface formed around the spiral wiring and the layer on which the spiral wiring is formed are separated by one layer or a plurality of layers on the same layer as the spiral wiring. Since the shield portion is composed of the conductive surface formed on the layer and the ground conductive surface and the connecting portion for electrically connecting the conductive surface, the shield effect and the spiral by the shield portion are provided. It is possible to achieve both reduction of parasitic capacitance to the inductor.

(3) Since the shield portion of the spiral inductor has the conductive surface formed of the substrate wiring material, it is easy to manufacture, does not cause a cost increase, and is effective in cost reduction.

(4) Since the shield part of the spiral inductor is provided with the conductive surface made of polysilicon, it is easy to manufacture and the increase in cost can be suppressed.

(5) The connection part of the spiral inductor is
Since it is composed of a plurality of through holes arranged around the spiral wiring, it is possible to connect the ground conductive surface and the conductive surface by a method that can be easily realized.

(6) The connection part of the spiral inductor is
Since the spiral inductor is formed by the groove-shaped recesses arranged around the spiral inductor, the shield effect can be further enhanced.

(7) Since the high frequency semiconductor device includes the spiral inductor according to any one of (1) to (6), it is possible to form an inductor resistant to noise. Therefore, an analog circuit or a digital circuit can be formed. A mixed high-frequency semiconductor device can be realized, and thus, a digital processing circuit can be mixedly mounted on an amplifier circuit of an input section of a mobile phone using a gigahertz band.

[Brief description of drawings]

FIG. 1 is a top view of a spiral inductor according to a first embodiment of the present invention.

FIG. 2 is an AA ′ of the spiral inductor shown in FIG.
FIG.

FIG. 3 is an equivalent circuit diagram showing noise propagation in the spiral inductor according to the first embodiment of the present invention.

FIG. 4 is a graph showing a noise propagation simulation result by the spiral inductor in the first embodiment of the present invention and the conventional example.

FIG. 5 is a sectional view of a spiral inductor according to a second embodiment of the present invention.

FIG. 6 is a top view of a spiral inductor formed in a semiconductor device.

FIG. 7 is an AA ′ of the spiral inductor shown in FIG.
FIG.

8 is an equivalent circuit diagram showing noise propagation in the conventional spiral inductor shown in FIGS. 6 and 7. FIG.

[Explanation of symbols]

1,101-semiconductor device 2-spiral wiring 4-Multiple through holes 5-metal surface 8-Multiple insulating layers 11-ground metal surface 21, 31, 121-spiral inductor

Claims (7)

[Claims] 1. A spiral inductor comprising a shield portion around a spiral wiring formed on a predetermined layer of a semiconductor device having a plurality of insulating layers by a silicon process. 2. The shield part, on the same layer as the spiral wiring, a grounding conductive surface formed around the spiral wiring, and one layer or a plurality of layers on which the spiral wiring is formed. The spiral according to claim 1, comprising a conductive surface formed on a layer separated from each other, and a ground conductive surface and a connecting portion for electrically connecting the conductive surface. Inductor. 3. The spiral inductor according to claim 2, wherein the conductive surface is formed of a substrate wiring material. 4. The spiral inductor according to claim 2, wherein the conductive surface is formed of polysilicon. 5. The spiral inductor according to claim 2, wherein the connection portion is a plurality of through holes arranged around the spiral wiring. 6. The spiral inductor according to claim 2, wherein the connecting portion is a groove-shaped concave portion arranged around the spiral inductor. 7. A high-frequency semiconductor device comprising the spiral inductor according to claim 1.