JP2003060091A - Method for manufacturing nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for efficiently manufacturing a flash memory having a surface channel type CMOS transistor in a peripheral circuit. SOLUTION: On a semiconductor substrate 3, a first gate electrode material film 8c to which impurities are not doped is formed through a first gate insulating film 7. An element isolation insulating film 4 getting to the inside of the semiconductor substrate 3 through the first gate insulating film 7 and the first gate electrode material film 8c is formed. On the first gate electrode material film 8c, a second gate electrode material film 9c to which the impurities are not doped is formed. By etching the first and second gate electrode material films 8c and 9c, a gate structure of NMOS and PMOS transistors 2a and 2b is formed. To the second gate electrode material film 9c in a memory cell region, the second gate electrode material film 9c in an NMOS region and the surface of the semiconductor substrate 3, N-type impurities are doped. To the second gate electrode material film 9c in a PMOS region and the surface of the semiconductor substrate 3, P-type impurities are doped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a method for manufacturing a nonvolatile semiconductor memory device, and more particularly to a method for forming gate electrodes of memory cell transistors and peripheral transistors and diffusion layers of peripheral transistors.

[0002]

2. Description of the Related Art Generally, a nonvolatile memory such as a flash memory has a memory cell inside a chip, a sense amplifier circuit, a row decoder circuit and various delay circuits necessary for its operation, a high voltage stabilizing circuit for writing / erasing, etc. As a peripheral control system circuit. Therefore, elements such as resistors and transistors that form these peripheral circuits are also formed inside the chip. At the time of forming such a non-volatile memory, the memory cell, the elements constituting the peripheral circuit, and the like are formed in the same process to improve the efficiency of the manufacturing process. Further, it is required to further reduce the number of manufacturing steps and further reduce the manufacturing cost to improve efficiency.

In a non-volatile memory mixed with a system LSI or in the case of considering connectivity with a system LSI, a surface channel N-type is used as a peripheral transistor which requires low power consumption or high speed operation. , P-type MOS (Metal Oxide Semiconductor) transistors are used in combination with a CMOS circuit. Also, N type M
The gate electrode of the OS transistor is formed of N-type polycrystalline silicon, and the gate electrode of the P-type MOS transistor is formed of P-type polycrystalline silicon.

21 (a), 21 (b) to 23 (a),
(B) sequentially shows an example of a conventional method of manufacturing a flash memory represented by a NOR type or a NAND type. 21B is a cross-sectional view in which the direction orthogonal to FIG. 21A is the cross-sectional direction. Similarly, FIG. 22B and FIG.
3B is a cross-sectional view in which the direction orthogonal to FIGS. 22A and 23B is the cross-sectional direction.

As shown in FIGS. 21A and 21B, on a semiconductor substrate 41 made of silicon, a gate insulating film 42,
N-type first gate electrode 43 doped with N-type impurities
a, the silicon nitride film 44 is sequentially deposited. Next, a trench that penetrates the silicon nitride film 44, the N-type first gate electrode 43a, and the first gate insulating film 42 and reaches the inside of the semiconductor substrate 41 is formed, and the trench is filled with a silicon oxide film to isolate the device. The insulating film 45 is formed.

Next, as shown in FIGS. 22A and 22B, after removing a part of the upper portion of the element isolation insulating film 45, the silicon nitride film 44 is removed. Next, a photoresist 46 is formed only in the memory cell region and the NMOS region. Next, using the photoresist 46 as a mask, a P-type impurity such as boron is injected into the N-type first gate electrode 43a, and P
The first gate electrode 43b of the mold is formed.

Next, as shown in FIGS. 23A and 23B, after removing the photoresist 46, a second gate insulating film 47 and a second gate electrode 48 are formed on the entire surface of the semiconductor device. Form. Next, the second gate insulating film 47 and the second gate electrode 48 are etched to etch the floating gate FG of the memory cell transistor 49, the control gate electrode CG,
And the gate electrode 5 of the MOS transistors 50a and 50b
1a and 51b are formed. Next, the memory cell transistor 49, N-type and P-type MOS transistors 50a and 50b
Source / drain regions 52, 53a and 53b are formed respectively.

[0008]

By the way, as described above, when forming the P-type first gate electrode 43b in the related art, the N-type first gate electrode 43a is formed, and the N-type first gate electrode 43a is formed. P-type impurities are implanted into the PMOS region of the gate electrode 43a. Therefore, the following problems occur.

That is, the N-type first gate electrode 43a
In order to make the P-type into P-type, it is necessary to implant boron with a concentration twice or more the impurity concentration of the N-type first gate electrode 43a. However, since boron has a small atomic number and is a light atom, a large amount of implanted boron penetrates the first gate insulating film 42 during the subsequent thermal diffusion, and the semiconductor substrate 41.
Diffuse to the surface of. Therefore, there is a high possibility that the device characteristics will change without the impurity concentration on the surface of the semiconductor substrate 41 being set to a predetermined value for channel control.

Usually, P (phosphorus) is used for a P-type electrode material.
Alternatively, there is a technique in which As (arsenic) is ion-implanted at a concentration twice or more that of As to make it N-type. On the other hand, the above method of implanting P-type impurities into the N-type electrode material is not often used because of the problem of outward diffusion of B (boron). However, if the gate oxide film has a high barrier property against the diffusion of B (boron), the device is not unusable.

Further, when the element isolation insulating film 45 is formed, the inner wall of the trench is usually thermally oxidized after forming the trench and before filling the trench with the silicon oxide film. At this time, the first gate electrode 43a doped with impurities has a higher oxidation rate than the semiconductor substrate 41 made of silicon. Therefore, as shown in FIG. 24, inside the trench, the thermal oxide film 54 formed on the side wall of the first gate electrode 43a projects from the thermal oxide film 55 formed on the side wall of the trench. When an oxide film is embedded in such an overhang-shaped groove, a void called a seam or a void is formed at the center of the groove. Then, when the gate electrode is processed in a later step, a part of the electrode material remains in this portion, which causes a defective case in which adjacent gates are electrically short-circuited.

The present invention has been made to solve the above problems, and an object of the present invention is to change device characteristics in a semiconductor memory device having a surface channel type CMOS transistor in a peripheral circuit. It is an object of the present invention to provide a method of manufacturing a nonvolatile semiconductor memory device that is preventable and efficient.

[0013]

In order to solve the above-mentioned problems, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a memory cell region formed on a semiconductor substrate in which a memory cell transistor is formed, In a nonvolatile semiconductor memory device having first and second peripheral regions in which first and second transistors are formed, the memory cell region and the first and second peripheral regions are provided.
A step of sequentially forming a first gate insulating film and a first gate electrode material film on the semiconductor substrate in a second peripheral region, and the first gate insulating film in the memory cell region and the first and second peripheral regions. A film, a step of penetrating the first gate electrode material film to form an element isolation insulating film reaching the inside of the semiconductor substrate, and the first gate electrode material in the memory cell region and the first and second peripheral regions. Forming a second gate electrode material film on the film, and etching the first and second gate electrode material films in the first and second peripheral regions to form gate structures of the first and second transistors And exposing a part of the surface of the semiconductor substrate, the second gate electrode material film in the memory cell region,
Implanting an impurity of the first conductivity type into the second gate electrode material film in the first peripheral region and the surface of the semiconductor substrate; and the second gate electrode material film and the semiconductor in the second peripheral region. Implanting a second conductivity type impurity into the surface of the substrate, sequentially forming a second gate insulating film and a conductive film on the second gate electrode material film in the memory cell region, and the memory cell region A step of etching the conductive film, the second gate electrode, the second gate insulating film, and the first gate electrode to form a gate structure of the memory cell transistor, and the semiconductor substrate in the memory cell region. Forming a source / drain region of the memory cell transistor by implanting impurities into the surface of the memory cell transistor.

According to another aspect of the present invention, a memory cell region formed on a semiconductor substrate in which a memory cell transistor is formed and first and second peripheral portions in which first and second transistors are formed are formed. A non-volatile semiconductor memory device having a region, a first gate insulating film on the semiconductor substrate in the memory cell region and the first and second peripheral regions,
A step of sequentially forming a gate electrode material film, and element isolation that penetrates the first gate insulating film and the gate electrode material film into the semiconductor substrate in the memory cell region and the first and second peripheral regions. Forming an insulating film; implanting an impurity of a first conductivity type into the gate electrode material film in the memory cell region and the first peripheral region; and forming the gate electrode material film in the second peripheral region. A step of injecting a second conductivity type impurity into the gate electrode material film, and a step of forming a second gate insulating film on the gate electrode material film in the memory cell region and the first and second peripheral regions;
A step of removing a part of the second gate insulating film in the second peripheral region to form an opening reaching the gate electrode material film, the second gate insulating film, and inside the opening.
Forming a conductive film on the conductive film, the conductive film and the second conductive film in the memory cell region and the first and second peripheral regions.
Etching the gate insulating film and the gate electrode material film to form the gate structure of the memory cell transistor and the first and second transistors, and exposing a part of the surface of the semiconductor substrate; and the memory cell region. And implanting impurities into the surface of the semiconductor substrate in the first and second peripheral regions to form the memory cell transistor and the source / drain regions of the first and second transistors. A method for manufacturing a characteristic nonvolatile semiconductor device can be provided.

According to another aspect of the present invention, a memory cell region formed on a semiconductor substrate in which a memory cell transistor is formed, and first and second peripheral portions in which first and second transistors are formed are formed. A non-volatile semiconductor memory device having a region, a first gate insulating film on the semiconductor substrate in the memory cell region and the first and second peripheral regions,
A step of sequentially forming a gate electrode material film, and element isolation that penetrates the first gate insulating film and the gate electrode material film into the semiconductor substrate in the memory cell region and the first and second peripheral regions. Forming an insulating film; implanting an impurity of a first conductivity type into the gate electrode material film in the memory cell region and the first peripheral region; and forming the gate electrode material film in the second peripheral region. A step of injecting a second conductivity type impurity into the gate electrode material film, and a step of forming a second gate insulating film on the gate electrode material film in the memory cell region and the first and second peripheral regions;
Removing the second gate insulating film in the second peripheral region, and on the second gate insulating film in the memory cell region,
Forming a conductive film on the gate electrode material in the first and second peripheral regions; and forming the conductive film and the second gate insulating film in the memory cell region and the first and second peripheral regions. Etching the gate electrode material film to form the gate structures of the memory cell transistor and the first and second transistors, and exposing a part of the surface of the semiconductor substrate; 1. In a second peripheral region, implanting impurities into the surface of the semiconductor substrate to form the memory cell transistor and the source / drain regions of the first and second transistors. A method for manufacturing a non-volatile semiconductor device can be provided.

Furthermore, the embodiments according to the present invention include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, when the invention is extracted by omitting some of the constituent elements shown in the embodiment, when omitting the extracted invention, the omitted part is appropriately supplemented by a well-known conventional technique. It is something that will be done.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Conventionally, the following manufacturing method has been adopted in a semiconductor memory device having a cell transistor and a peripheral circuit including a transistor and the like. That is, a gate electrode material not doped with impurities is formed, impurities are injected into the gate electrode material in a later step to make it conductive, and then a cell transistor and a peripheral transistor are formed by using this conductive gate electrode material. And other gate electrodes are formed.

Such a method has not been adopted when manufacturing a flash memory. This is because adjustment of the acceleration energy and the amount of implantation at the time of implanting impurities into the memory cell transistor portion is particularly delicate, and it is difficult to ensure the reliability of the memory cell device.

However, due to recent advances in manufacturing technology and control technology, it has become possible to apply the above method to a flash memory manufacturing method. Such a method will be briefly described with reference to FIG.

In FIG. 22, first, on the first gate insulating film 42, polycrystalline silicon or the like which is not doped with impurities is formed as the first gate electrode 43a. next,
First gate electrode 4 in NMOS region and memory cell region
By implanting an N-type impurity into 3a, the first gate electrode 43a in the memory cell region and the NMOS region simultaneously serves as an N-type conductive layer. Next, by injecting P-type impurities into the first gate electrode 43a in the PMOS region, PM
The first gate electrode 43a in the OS region is a P-type conductive layer.

According to the above method, N-type and P-type impurities are implanted into the gate electrode material not doped with impurities, so that the N-type first gate electrode 43 in the PMOS region is implanted.
It is possible to avoid the above problem that occurs when a P-type impurity is implanted into a. Therefore, it is suitable for manufacturing a flash memory having a surface channel type CMOS transistor. Further, it is possible to avoid the problem that the thermal oxide film 54 is formed due to the difference in the oxidation rate between the impurity-doped polycrystalline silicon and the silicon as shown in FIG. 24 in which the trench portion is enlarged.

However, according to the above method, since the steps of implanting N-type and P-type impurities are required, the number of manufacturing steps of the semiconductor device increases. Therefore, the efficiency of the manufacturing process cannot be improved.

An embodiment of the present invention constructed on the basis of such knowledge will be described below with reference to the drawings. In the following description, constituent elements having substantially the same functions and configurations are designated by the same reference numerals, and redundant description will be given only when necessary.

(First Embodiment) FIG. 1A is a sectional view showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention, and FIG. 1B is a sectional view of FIG. It is sectional drawing which makes a direction orthogonal to the cross-sectional direction.

As shown in FIG. 1A, a semiconductor memory device according to the present invention includes a memory cell region in which a plurality of memory cell transistors 1 forming a memory cell are formed and an N-type MOS forming a peripheral circuit. It has an NMOS region in which the transistor 2a is formed and a PMOS region in which the P-type MOS transistor 2b is formed.

In FIG. 1A, 3 is a semiconductor substrate, and a plurality of element isolation insulating films 4 which project from a part of the surface of the semiconductor substrate 3 and isolate element regions are formed. A first gate insulating film 7 is formed on the semiconductor substrate 3 between the element isolation insulating films 4.

In the memory cell region, an N-type impurity, such as an N-type impurity, is implanted on the first gate insulating film 7.
The first gate electrode 8a of the mold is formed. For example, an N-type second gate electrode 9a in which an N-type impurity is implanted is formed so as to partially extend from the N-type first gate electrode 8a to the element isolation insulating film 4. A groove 10 reaching the element isolation insulating film 4 is formed between the N-type second gate electrodes 9a substantially above the center of the element isolation insulating film 4. This groove 10
Thus, the second gate electrode 9c is separated from that of the adjacent memory cell transistor.

In the NMOS region, the first gate electrode 8a is formed on the first gate insulating film 7. Further, in the P-type MOS region, the P-type first gate electrode 8b in which the P-type impurity is implanted is formed on the first gate insulating film 7. A second gate electrode 9 is formed over the N-type and P-type first gate electrodes 8a and 8b and the element isolation insulating film 4. This second gate electrode 9 is
It is composed of an N-type second gate electrode 9a having an N-type impurity implanted in the NMOS region and a P-type second gate electrode 9b having a P-type impurity implanted in the PMOS region.

On the second gate electrode 9 and the groove 1
On the inner wall of 0, for example, an oxide film, a nitride film, an oxide film (ONO
A second gate insulating film 11 made of a film is formed. In the memory cell region, the third gate electrode 12 is formed on the second gate insulating film 11. The silicide 13 is formed on the third gate electrode 12.

As shown in FIG. 1B, a plurality of memory cell transistors 1 are formed on the semiconductor substrate 3 in the memory cell region. The memory cell transistor 1 includes the first and second gate electrodes 8a and 9a, the second gate insulating film 11, the third gate electrode 12, and the first gate electrode, which are sequentially formed on the surface of the semiconductor substrate 3. Source / drain regions 5 formed on the surface of the semiconductor substrate 3 adjacent to 8a;
It is composed of First and second gate electrodes 8a and 9a
Functions as the floating gate electrode FG of the memory cell transistor, and the third gate electrode 12 functions as the control gate electrode CG. Silicide 1 on the third gate electrode 12
3 is formed.

In the NMOS region, the N-type MOS transistor 2a is formed on the semiconductor substrate 3. The N-type MOS transistor 2a is a source formed on the surface of the semiconductor substrate 3 adjacent to the first and second gate electrodes 8a and 9a and the first gate electrode 8a which are sequentially formed on the surface of the semiconductor substrate 3. The drain region 6a. The first and second gate electrodes 8a and 9a form the gate electrode Ga of the N-type MOS transistor 2a. The silicide 13 is formed on the third gate electrode 12.

In the PMOS region, the P-type MOS transistor 2b is formed on the semiconductor substrate 3. The P-type MOS transistor 2b is a source formed on the surface of the semiconductor substrate 3 adjacent to the first and second gate electrodes 8b and 9b and the first gate electrode 8b which are sequentially formed on the surface of the semiconductor substrate 3. And the drain region 6b. The first and second gate electrodes 8b and 9b form the gate electrode Gb of the P-type MOS transistor 2b. The silicide 13 is formed on the third gate electrode 12.

The second gate insulating film 11 is formed from the top and side surfaces of the gate electrodes Ga and Gb to the surface of the semiconductor substrate 3.

2A, 2B to 11A,
(B) shows in sequence the method of manufacturing the semiconductor memory device having the above configuration. 2B is a cross-sectional view in which the direction orthogonal to FIG. 2A is the cross-sectional direction, and FIG.
It is sectional drawing which makes a direction orthogonal to (a) a sectional direction.
Hereinafter, similarly, FIGS. 4B to 11B are cross-sectional views in which the direction orthogonal to the reference numeral (a) in the drawing is the cross-sectional direction. Hereinafter, FIGS. 2 (a), 2 (b) to 13 (a),
A method of manufacturing the semiconductor memory device according to the present invention having the above-described structure will be described with reference to FIG.

As shown in FIGS. 2A and 2B, a well (not shown) is formed on the surface of the semiconductor substrate 3, and channel control is performed on the surface of the semiconductor substrate 3 in the memory cell region, the NMOS region and the PMOS region. Implant the required desired ions. Next, the first gate insulating film 7 is formed on the entire surface of the semiconductor substrate 3 by, for example, thermal oxidation. Next, a first gate electrode material film 8c made of, for example, polysilicon not doped with impurities is formed on the entire surface of the first gate insulating film 7 by using, for example, the CVD method. Next, a mask material 21 such as a silicon nitride film is formed on the entire surface of the first gate electrode material film 8c by using, for example, the CVD method.

Next, as shown in FIGS. 3 (a) and 3 (b),
A photoresist (not shown) is formed on the entire surface of the mask material 21, and the pattern of the element region is transferred to the photoresist using a photolithography process. Next, using this photoresist as a mask, the mask material 21, the first gate electrode material film 8c, the first gate insulating film 7, and the semiconductor substrate 3 are anisotropically etched by, for example, the RIE method.
To etch a part of. By doing so, a trench that penetrates the mask material 21, the first gate electrode material film 8c, and the first gate insulating film 7 and reaches the semiconductor substrate 3 is formed. Next, after forming a thermal oxide film on the inner wall of the trench, the trench is filled with the silicon oxide film by depositing, for example, a silicon oxide film on the entire surface of the semiconductor device by, for example, the CVD method. Next, the silicon oxide film is planarized by using the mask material 21 as a stopper to flatten the element isolation insulating film 4
To form. After that, the silicon oxide film may be partially etched back to reduce the height of the element isolation insulating film 4.

Next, as shown in FIGS. 4 (a) and 4 (b),
After removing the mask material 21, a second gate electrode material film 9c made of, for example, polysilicon not doped with impurities is formed on the entire surface of the semiconductor device by, for example, the CVD method.

Next, as shown in FIGS. 5 (a) and 5 (b),
A photoresist (not shown) is formed on the entire surface of the semiconductor device. Next, a photolithography process is used to form an N-type and P-type MOS transistor 2a with an opening in the memory cell region on the element isolation insulating film 4 at a substantially central portion.
The pattern having the gate pattern of 2b is transferred to the photoresist. Next, using this photoresist as a mask, the first and second gate electrode material films 8c and 9c are etched by anisotropic etching such as RIE. As a result, as shown in FIG. 5A, the trench 10 is formed on the element isolation insulating film 4 in the cell region, and the gate structures of the N-type and P-type MOS transistors 2a and 2b are formed in the peripheral region. It is formed.

Next, the photoresist is removed. It is also possible to insert a step of depositing, for example, a silicon oxide film or a silicon nitride film on the second gate electrode 9 before forming the photoresist. In this case, these silicon oxide film or silicon nitride film are removed before removing the photoresist.

Next, as shown in FIGS. 6 (a) and 6 (b),
A photoresist 22 is formed on the entire surface of the semiconductor device.
Next, using a photolithography process, a pattern having openings in only the memory cell region and the NMOS region is transferred to the photoresist 22. Next, using this photoresist 22 as a mask, for example, phosphorus (P) is used under the conditions of an accelerating voltage of several tens Kev and an implantation amount of about 10 ¹⁵ cm ^−2.
Alternatively, impurities such as arsenic (As) are implanted into the entire surface of the semiconductor device. By doing so, the second gate electrode material film 9 is formed.
By implanting impurities into c, the N-type second gate electrode 9a is formed in the memory cell region and the NMOS region, and the source / drain region 6a is formed in the NMOS region. Next, the photoresist 22 is removed.

Next, as shown in FIGS. 7 (a) and 7 (b),
A photoresist 23 is formed on the entire surface of the semiconductor device.
Next, using a photolithography process, a pattern having openings only in the PMOS region is transferred to the photoresist 23. Next, using this photoresist 23 as a mask,
For example, the accelerating voltage is more than ten Kev and the injection amount is about 10 ¹⁵ cm.
An impurity such as boron is implanted into the entire surface of the semiconductor device under the condition of ^-2 . By doing so, the impurities are implanted into the second gate electrode material film 9c, so that the PMOS
In the region, the P-type second gate electrode 9b is formed, and the source / drain region 6b is formed in the PMOS region.
Is formed.

Next, as shown in FIGS. 8 (a) and 8 (b),
After removing the photoresist 23, the semiconductor device is heat-treated to remove the photoresist in the memory cell region and the NMOS region.
Impurities in the N-type second gate electrode 9a are diffused into the first gate electrode material film 8c. At the same time, in the PMOS region, the impurities in the P-type second gate electrode 9b are diffused into the first gate electrode material film 8c. By doing so, the N-type and P-type first gate electrodes 8a and 8b are formed. Next, the second gate insulating film 11 having a thickness of, for example, 20 nm is formed on the entire surface of the semiconductor device by using, for example, the CVD method. By doing so, the second gate insulating film 11 is formed on the N-type second gate electrode 9a in the memory cell region and in the trench 10. In addition, N-type MOS
A second gate insulating film 11 is formed on the top and side surfaces of the gate electrodes Ga and Gb of the transistor 2a and the P-type MOS transistor 2b, and on the exposed surface of the semiconductor substrate 3.

Next, as shown in FIGS. 9 (a) and 9 (b),
A third gate electrode material film 12a made of, for example, impurity-doped polycrystalline silicon is formed on the entire surface of the semiconductor device by, for example, the CVD method. Next, tungsten silicide (WSix) is deposited on the third gate electrode material film 12a by, for example, the CVD method or the sputtering method to form the silicide 13.

Next, as shown in FIGS. 10A and 10B, a photoresist 25 is formed on the entire surface of the semiconductor device. Next, a pattern having an opening other than the memory cell region is transferred to the photoresist 25 by using a photolithography process. Next, using the photoresist 25 as a mask, the silicide 13 and the third gate electrode material film 12a are removed by etching using the second gate insulating film 11 as a stopper.

Next, as shown in FIGS. 11A and 11B, the photoresist 25 is removed. Next, a photoresist 26 is formed on the entire surface of the semiconductor device. Next, using a photolithography process, the photoresist 26
Then, the gate pattern of the memory cell is transferred to the memory cell region. Next, using the photoresist as a mask, the silicide 13, the third gate electrode material film 12a, the second gate insulating film 11, the N-type second film 2, and the like are formed by anisotropic etching such as RIE. First gate electrodes 9a, 8
Etch a. By doing so, the control gate electrode CG and the floating gate electrode FG of the memory cell transistor 1 are formed. After that, the photoresist is removed.

Next, as shown in FIGS. 1 (a) and 1 (b),
Gate electrodes Ga and Gb of N-type and P-type MOS transistors
An unillustrated gate sidewall such as an oxide film is formed on the sidewall of the gate. Next, a photoresist (not shown) is formed on the entire surface of the semiconductor device, and a pattern having an opening in a memory cell region is transferred to this photoresist by using a photolithography process. Next, using the photoresist as a mask, impurities are implanted to form the source / drain regions 5 of the memory cell transistor 1. After this, for example, CV
Using the D method, an insulating film (not shown) is deposited on the entire surface of the semiconductor device. Next, a contact hole (not shown) is appropriately formed in the insulating film by a photolithography process and etching. Next, this contact hole is filled with a metal such as tungsten to form a wiring (not shown). Next, a wiring made of, for example, a metal is formed on the insulating film using a well-known technique to complete an element.

According to the first embodiment described above, the first and second gate electrode material films 8c and 9 not doped with impurities.
form c. Next, the first and second gate electrode material films 8c and 9c are etched to form slits 10 for separating the memory cell transistors 1 adjacent to each other in the memory cell region, and to form NMOS, PM.
In the OS region, N-type and P-type MOS transistors 2a,
The gate structure of 2b is formed. Therefore, the lithography process and the etching process can be reduced, and the number of manufacturing processes can be reduced.

Further, the slit 10, the NMOS, and the PM
After forming the gate structure of the OS transistor, an N-type second gate electrode 9a is formed by injecting an N-type impurity into the second gate electrode material film 9c, and the second gate electrode 9a is used as a memory cell cell. It is used as the floating gate of the transistor 1 and is used as the gate electrode Ga of the NMOS transistor 2a.
Used as. Next, by implanting P-type impurities into the second gate electrode material film 9c, the P-type second gate electrode 9 is formed.
b is formed, and this second gate electrode 9b is used as the gate electrode Gb of the PMOS transistor 2b. Therefore, it is not necessary to perform the step of implanting a large amount of P-type impurities into the N-type first gate electrode 43a to partially change the conductivity type to the opposite type as shown in FIG. Therefore, it is possible to avoid the problem that P-type impurities are implanted into the semiconductor substrate 3.

Further, since the N-type and P-type impurities are respectively injected into the second gate electrode 9c which is not doped with impurities, the impurity concentration can be easily controlled. Therefore, the present invention is most suitable for forming a surface channel type CMOS transistor.

Further, when the thermal oxide film is formed on the inner wall of the trench, since the first and second gate electrode material films 8c and 9c are not doped with impurities, part of the oxide film on the inner wall of the trench is partially removed. It can be prevented from protruding.

When implanting N-type impurities into the second gate electrode material film 9c in the memory cell region and the NMOS region,
At the same time, the source / drain regions 6a of the N-type MOS transistor 2a are formed, and when the P-type impurities are implanted into the second gate electrode material film 9c in the PMOS region, the source / drain regions 6b of the P-type MOS transistor 2b are simultaneously formed. To do. Therefore, the step of implanting the source / drain regions 6a and 6b again after implanting the impurities into the second gate electrode material film 9c becomes unnecessary, and the number of manufacturing steps can be reduced.

(Second Embodiment) In the first embodiment, part of the second gate electrode 9a of each memory cell transistor 1 in the memory cell region is the element isolation insulating film 4.
Formed on. Therefore, it is necessary to form the element isolation insulating film 4 in consideration of this portion, and the width of the element isolation insulating film 4 cannot be further reduced. Therefore, it is difficult to miniaturize the semiconductor element.

The second embodiment is similar to the first embodiment in that N-type and P-type impurities are implanted into the gate electrode material film which is not doped with impurities. However, the first point is that the floating gate electrode of the memory cell transistor is formed in a self-aligned manner with the element isolation insulating film, and that the gate structures of the memory cell transistor and the NMOS and PMOS transistors are formed in the same step. Different from the embodiment.

FIG. 12A is a sectional view showing a second embodiment of the non-volatile semiconductor memory device according to the present invention, and FIG. 12B is a sectional direction in a direction orthogonal to FIG. 12A. FIG.

As shown in FIG. 12A, the semiconductor substrate 3
A plurality of element isolation insulating films 4 are formed so as to project from a part of the surface of the element isolation insulating film 4. On the substrate 1 between the element isolation insulating films 4, the first
The gate insulating film 7 is formed. Memory cell area and N
An N-type first gate electrode 8a is formed on the surface of the semiconductor substrate 3 between the element isolation insulating films 4 in the MOS region via the first gate insulating film 7. Further, a P-type first gate electrode 8b is formed on the surface of the semiconductor substrate 3 between the element isolation insulating films 4 in the PMOS region with the first gate insulating film 7 interposed therebetween. The upper ends of the first gate electrodes 8a and 8b are formed higher than the element isolation insulating film 4.

The N-type and P-type first gate electrodes 8a,
A second gate insulating film 11 is formed from above 8b to above the element isolation insulating film 4. This second gate insulating film 1
A third gate electrode 12 is formed on the first electrode 1. The third gate electrode 12 has a groove 31 reaching the element isolation insulating film 4 on the element isolation insulating film 4 at the boundary between the memory cell region and the peripheral region. The groove 31 is filled with an insulating film (not shown). A silicide 32 is formed on the third gate electrode 12.

As shown in FIG. 12B, a plurality of memory cell transistors 1 are formed on the semiconductor substrate 3 in the memory cell region. The memory cell transistor 1 is
A first gate electrode 8a, a second gate insulating film 11, and a third gate electrode 12 which are sequentially formed on the surface of the semiconductor substrate 3.
And a source / drain region 5 formed on the surface of the semiconductor substrate 3 adjacent to the first gate electrode 8a. The first gate electrode 8a functions as the floating gate electrode FG of the memory cell transistor, and the third gate electrode 1a
2 functions as a control gate electrode CG. A silicide 32 is formed on the third gate electrode 12.

In the NMOS region, the NMOS transistor 2a is formed on the semiconductor substrate 3. This N
The MOS transistor 2a includes a first gate electrode 8a, a second gate insulating film 11, and a second gate insulating film 11, which are sequentially formed on a semiconductor substrate.
The gate electrode Ga is composed of the third gate electrode 12, and the source / drain regions 6a are formed adjacent to the gate electrode Ga on the surface of the semiconductor substrate 3. The second gate insulating film 11 has an opening 33 at a substantially central portion of the gate electrode Ga, and the first gate electrode 8a and the third gate electrode 12 are electrically connected to each other through the opening 33. To be done.
A silicide 32 is formed on the third gate electrode 12.

In the PMOS region, the PMOS transistor 2b is formed on the semiconductor substrate 3. This P
The MOS transistor 2b includes a first gate electrode 8b, a second gate insulating film 11, and a second gate insulating film 11, which are sequentially formed on a semiconductor substrate.
The gate electrode Gb is formed of the third gate electrode 12, and the source / drain region 6b is formed on the surface of the semiconductor substrate 3 adjacent to the gate electrode Gb. The second gate insulating film 11 has an opening 33 at a substantially central portion of the gate electrode Gb, and the first gate electrode 8b and the third gate electrode 12 are electrically connected to each other through the opening 33. To be done.
A silicide 32 is formed on the third gate electrode 12.

FIGS. 13 (a), 13 (b) through 20 (a),
(B) shows in sequence the method of manufacturing the semiconductor memory device having the above configuration. 13B is a cross-sectional view in which the cross-sectional direction is the direction orthogonal to FIG. 13A, and FIG. 14B is a cross-sectional view in which the cross-sectional direction is the direction orthogonal to FIG. 14A. is there. Hereinafter, similarly, FIG. 15B to FIG.
It is sectional drawing which makes a direction orthogonal to the figure number (a) a sectional direction.

As shown in FIGS. 13A and 13B, a well (not shown) is formed on the surface of the semiconductor substrate 3, and channel control is performed on the surface of the semiconductor substrate 3 in the memory cell region, the NMOS region, and the PMOS region. Implant the required desired ions. Next, the first gate insulating film 7 is formed on the entire surface of the semiconductor substrate 3 by, for example, thermal oxidation. Next, a first gate electrode material film 8c is formed on the entire surface of the first gate insulating film 7 by using, for example, the CVD method. Next, a mask material 21 such as a silicon nitride film is formed on the entire surface of the first gate electrode material film 8c by using, for example, the CVD method.

Next, as shown in FIGS. 14 (a) and 14 (b), a photoresist (not shown) is formed on the entire surface of the mask material 21, and an element is formed on this photoresist by a photolithography process. Transfer the pattern of the area. Next, by using this photoresist as a mask, the mask material 21 and the first
The gate electrode material film 8c, the first gate insulating film 7, and a part of the semiconductor substrate 3 are etched. By doing this,
A trench that penetrates the mask material 21, the first gate electrode material film 8c, and the first gate insulating film 7 and reaches the semiconductor substrate 3 is formed. Next, for example, a silicon oxide film is deposited on the entire surface of the semiconductor device by, for example, the CVD method. By doing so, the trench is filled with the silicon oxide film. Next, the silicon oxide film is flattened by using the mask material 21 as a stopper to form the element isolation insulating film 4.

Next, as shown in FIGS. 15A and 15B, the height of the element isolation insulating film 4 is lowered by etching back the element isolation insulating film 4, and then the mask material 21 is removed. Remove.

Next, as shown in FIGS. 16A and 16B, a photoresist 34 is formed on the entire surface of the semiconductor device. Next, using a photolithography process, a pattern having openings in the memory cell region and the NMOS region is transferred to the photoresist 34. Next, using this photoresist 34 as a mask, for example, the acceleration voltage is several tens of K.
Impurities such as phosphorus or arsenic are implanted into the entire surface of the semiconductor device under the conditions of eV and the implantation amount of about 10 ¹⁵ cm ⁻² .
As a result, the impurities are implanted into the first gate electrode material film 8c, so that the memory cell region and the NMOS region are N-doped.
The first gate electrode material film 8d of the mold is formed.

Next, as shown in FIGS. 17A and 17B, after removing the photoresist 34, a photoresist 35 is formed on the entire surface of the semiconductor device. Next, using a photolithography process, this photoresist 35 is used.
Then, a pattern having an opening in the PMOS region is transferred. Next, using this photoresist 35 as a mask, for example, the acceleration voltage is a dozen KeV and the implantation amount is about 10 ¹⁵ cm.
An impurity such as boron is implanted into the entire surface of the semiconductor device under the condition of ^-2 . As a result, impurities are implanted into the first gate electrode material film 8c to form the P-type first gate electrode material film 8e in the PMOS region.

Next, as shown in FIGS. 18 (a) and 18 (b), after removing the photoresist 35, the entire surface of the semiconductor device is subjected to, for example, the CVD method to have a thickness of, for example, 20.
A second gate insulating film 11 having a thickness of nm is formed. By doing so, the N-type and P-type first gate electrode material films 8d,
The second gate insulating film 11 is formed from above 8e to above the element isolation insulating film 4. Next, the second gate insulating film 11
A photoresist (not shown) is formed thereon. Then, using a photolithography process, the MO is applied to the photoresist.
A pattern having an opening in each of the substantially central portions of the regions where the gate structures of the S transistors 2a and 2b are formed is transferred. Next, using this photoresist as a mask, the second gate insulating film 11 is etched by anisotropic etching such as RIE. By doing this,
An opening 33 is formed in the second gate insulating film 11 corresponding to the photoresist. In addition, this technology is Japanese Patent Application 2
000-291910. Next, the photoresist is removed.

Next, as shown in FIGS. 19A and 19B, a third gate electrode material film 12a is formed on the second gate insulating film 11. At this time, the opening 33 is filled with the third gate electrode material film 12a. Next, for example, CVD is performed on the third gate electrode material film 12a.
Method or sputtering method to deposit tungsten silicide to form the silicide 32.

Next, as shown in FIGS. 20A and 20B, a photoresist 36 is formed on the entire surface of the semiconductor device. Next, by using a photolithography process, the memory cell transistor 1 and the N
The gate patterns of the MOS and PMOS transistors 2a and 2b and the pattern having an opening at the substantially central portion on the element isolation insulating film 4 at the boundary between the memory cell region and the NMOS region are transferred. Next, using the photoresist 36 as a mask, the third gate electrode material film 12a, the second gate insulating film 11, the N-type and P-type first gate electrodes 8d,
8e is etched using anisotropic etching such as RIE. By doing so, the control gate electrode CG and the floating gate electrode FG of the memory cell transistor 1 are
And the gate electrodes Ga and Gb of the NMOS and PMOS transistors 2a and 2b are formed. At the same time, a groove 31 is formed in the center of the element isolation insulating film 4 at the boundary between the memory cell region and the NMOS region.

Next, as shown in FIGS. 12A and 12B, the photoresist 36 is removed. Next, NMO
On the side walls of the gate electrodes Ga and Gb of the S and PMOS transistors, a gate side wall (not shown) such as an oxide film is formed. Next, a photoresist (not shown) is formed on the entire surface of the semiconductor device, and a pattern having an opening in a memory cell region is transferred to this photoresist by using a photolithography process. Next, using the photoresist as a mask, impurities are implanted to form the source / drain regions 5 of the memory cell transistor 1. Next, this photoresist is removed.

Next, a photoresist (not shown) is deposited on the entire surface of the semiconductor device. Next, using a photolithography process, a pattern having openings in the NMOS region is transferred to this photoresist. Next, using the photoresist as a mask, impurities such as phosphorus and arsenic are implanted into the entire surface of the semiconductor device to form the source / drain regions 6a of the NMOS transistor 2a.

Next, a photoresist (not shown) is deposited on the entire surface of the semiconductor device. Next, using a photolithography process, a pattern having openings in the PMOS region is transferred to this photoresist. Next, using this photoresist as a mask, impurities such as boron are implanted into the entire surface of the semiconductor device to form the source / drain regions 6b of the PMOS transistor 2b.

Next, an insulating film (not shown) is deposited on the entire surface of the semiconductor device by using, for example, the CVD method. Next, a contact hole (not shown) is appropriately formed in the insulating film by a photolithography process and etching. next,
This contact hole is filled with a metal such as tungsten to form a wiring (not shown). Next, a wiring made of, for example, a metal is formed on the insulating film using a well-known technique to complete an element.

According to the second embodiment, in the semiconductor memory device having the surface channel type CMOS transistor in the peripheral circuit, the step of implanting a large amount of P-type impurities becomes unnecessary as in the first embodiment. It is possible to avoid the problem that P-type impurities are implanted into the semiconductor substrate 3. further,
At the time of thermal diffusion, it is possible to prevent a part of the oxide film on the inner wall of the trench 22 from protruding.

Further, since the floating gate electrode FG of the memory cell transistor 1 is formed in self-alignment with the element isolation insulating film 4, the floating gate electrode FG does not extend onto the element isolation insulating film 4. Therefore, the element isolation insulating film 4 can be miniaturized without considering the extension of the floating gate electrode FG. Therefore, the semiconductor element can be further downsized.
In the above embodiment, as shown in FIG.
An opening 33 is formed in the second gate insulating film 11 in the OS and PMOS regions, and the N-type and P-type first gate electrode material films 8d and 8e and the third gate electrode 12 are formed through the opening 33.
Was electrically connected. However, the present invention is not limited to this, and, for example, a step of removing all the second gate insulating film 11 in the NMOS and PMOS regions can be performed.

Although the floating gate electrode of the memory cell transistor 1 is of N type in the first and second embodiments, it may be of P type. In this case, P-type impurities may be simultaneously implanted into the gate electrode material films 8c and 9c in the memory cell region and the PMOS region.

In addition, within the scope of the idea of the present invention, those skilled in the art can come up with various modified examples and modified examples, and these modified examples and modified examples also belong to the scope of the present invention. Understood.

[0077]

As described above in detail, according to the present invention,
It is possible to provide a method for manufacturing a non-volatile semiconductor memory device in which the impurity concentration on the surface of the semiconductor substrate does not change due to the impurities being injected into the semiconductor substrate and the number of manufacturing steps can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the nonvolatile semiconductor memory device shown in FIG.

FIG. 3 is a cross-sectional view showing a step that follows FIG.

FIG. 4 is a cross-sectional view showing a step that follows FIG.

FIG. 5 is a cross-sectional view showing a step that follows FIG.

6 is a cross-sectional view showing a step that follows FIG.

FIG. 7 is a cross-sectional view showing a step that follows FIG.

FIG. 8 is a cross-sectional view showing a step that follows FIG.

FIG. 9 is a cross-sectional view showing a step that follows FIG.

FIG. 10 is a cross-sectional view showing a step that follows FIG.

11 is a cross-sectional view showing a step that follows FIG.

FIG. 12 is a second non-volatile semiconductor memory device according to the present invention.
Sectional drawing which shows the embodiment of FIG.

FIG. 13 is a cross-sectional view showing the method of manufacturing the nonvolatile semiconductor memory device shown in FIG.

FIG. 14 is a cross-sectional view showing a step that follows FIG.

FIG. 15 is a cross-sectional view showing a step that follows FIG.

16 is a cross-sectional view showing a step that follows FIG.

FIG. 17 is a cross-sectional view showing a step that follows FIG. 16.

FIG. 18 is a cross-sectional view showing a step that follows FIG.

FIG. 19 is a cross-sectional view showing a step that follows FIG.

FIG. 20 is a cross-sectional view showing a step that follows FIG.

FIG. 21 is a cross-sectional view showing the conventional method for manufacturing a nonvolatile semiconductor memory device.

22 is a cross-sectional view showing a step that follows FIG.

FIG. 23 is a cross-sectional view showing a step that follows FIG. 22.

FIG. 24 is an enlarged sectional view showing a trench portion.

[Explanation of symbols]

1 ... memory cell transistor, 2a, 2b ... NMOS, PMOS transistors, 3 ... Semiconductor substrate, 4 ... Element isolation insulating film, 5, 6a, 6b ... Source / drain regions, 7, 11 ... First and second gate insulating films, 8c, 9c ... First and second gate electrode material films, 8a, 9a ... N-type first and second gate electrodes, 9a, 9b ... P-type first and second gate electrodes, 12 ... Third gate electrode, 13 ... Silicide.

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/788 29/792 (72) Inventor Riichiro Shirata 8 Shinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa Stock company Toshiba Yokohama business In-house F-term (reference) 5F048 AA04 AA08 AB01 AC03 BA01 BB06 BB07 BB08 BB12 BB13 BE03 BG13 DA25 5F083 EP03 EP04 EP23 ER22 GA28 JA35 JA39 JA53 MA06 MA19 NA01 PR07 PR29 PR36 PR24 PR55 PR36 PR05 PR05 BB05 ZA05 512 ZA05 512 BH09 BH19 BH21

Claims (8)

[Claims] 1. A memory cell region on a semiconductor substrate, in which a memory cell transistor is formed, and first and second memory cell regions.
A non-volatile semiconductor memory device having first and second peripheral regions in which transistors are formed, a first gate insulating film, a first gate insulating film on the semiconductor substrate in the memory cell region and the first and second peripheral regions. A step of sequentially forming a gate electrode material film, and penetrating the first gate insulating film and the first gate electrode material film to reach the inside of the semiconductor substrate in the memory cell region and the first and second peripheral regions. Forming an element isolation insulating film; forming a second gate electrode material film on the first gate electrode material film in the memory cell region and the first and second peripheral regions; Etching the first and second gate electrode material films in the second peripheral region to form the gate structures of the first and second transistors and exposing a part of the surface of the semiconductor substrate. And implanting an impurity of a first conductivity type into the second gate electrode material film in the memory cell region, and the second gate electrode material film in the first peripheral region and the surface of the semiconductor substrate, Implanting an impurity of a second conductivity type into the surface of the second gate electrode material film in the second peripheral region and the semiconductor substrate; and forming a second gate on the second gate electrode material film in the memory cell region. A step of sequentially forming an insulating film and a conductive film, and etching the conductive film, the second gate electrode, the second gate insulating film, and the first gate electrode in the memory cell region to gate the memory cell transistor. Forming a structure; and in the memory cell region, implanting an impurity into a surface of the semiconductor substrate to form a source / drain region of the memory cell transistor, Method of manufacturing a nonvolatile semiconductor memory device characterized by comprising. 2. The non-volatile semiconductor according to claim 1, wherein the step of forming the first and second gate electrode material films is a step of forming a polycrystalline silicon film not doped with impurities. Storage device manufacturing method. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising a step of forming the element isolation insulating film and then partially etching the element isolation insulating film to reduce the height. Manufacturing method. 4. The second gate electrode in the memory cell region and in the first and second peripheral regions by heat treatment after implanting a second conductivity type impurity into the second gate electrode material film in the second peripheral region. The impurities of the material film are removed from the memory cell region, the first,
The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising a step of diffusing into the first gate electrode material film in a second peripheral region. 5. A memory cell region on a semiconductor substrate in which a memory cell transistor is formed, and first and second memory cell regions.
A non-volatile semiconductor memory device having first and second peripheral regions in which transistors are formed, a first gate insulating film and a gate electrode on the semiconductor substrate in the memory cell region and the first and second peripheral regions. A step of sequentially forming a material film, and an element isolation insulating film that penetrates the first gate insulating film and the gate electrode material film to reach the inside of the semiconductor substrate in the memory cell region and the first and second peripheral regions. A step of implanting an impurity of a first conductivity type into the gate electrode material film in the memory cell region and the first peripheral region; and a step of implanting a first conductive type impurity into the gate electrode material film in the second peripheral region. Two
Implanting a conductivity type impurity; forming a second gate insulating film on the gate electrode material film in the memory cell region and the first and second peripheral regions; and the first and second peripheral regions A part of the second gate insulating film is removed in the region to form an opening reaching the gate electrode material film, and a conductive film is formed on the second gate insulating film and in the opening. And the memory cell region and the first,
In the second peripheral region, the conductive film, the second gate insulating film, and the gate electrode material film are etched to form the gate structures of the memory cell transistor and the first and second transistors, and the semiconductor substrate of the semiconductor substrate is formed. Exposing a part of the surface, and implanting an impurity into the surface of the semiconductor substrate in the memory cell region and the first and second peripheral regions to form the source / source of the memory cell transistor and the first and second transistors. A method of manufacturing a non-volatile semiconductor device, comprising: forming a drain region. 6. A memory cell region formed on a semiconductor substrate in which a memory cell transistor is formed, and first and second memory cell regions.
A non-volatile semiconductor memory device having first and second peripheral regions in which transistors are formed, a first gate insulating film and a gate electrode on the semiconductor substrate in the memory cell region and the first and second peripheral regions. A step of sequentially forming a material film, and an element isolation insulating film that penetrates the first gate insulating film and the gate electrode material film to reach the inside of the semiconductor substrate in the memory cell region and the first and second peripheral regions. A step of implanting an impurity of a first conductivity type into the gate electrode material film in the memory cell region and the first peripheral region; and a step of implanting a first conductive type impurity into the gate electrode material film in the second peripheral region. Two
Implanting a conductivity type impurity; forming a second gate insulating film on the gate electrode material film in the memory cell region and the first and second peripheral regions; and the first and second peripheral regions Removing the second gate insulating film in the region, and forming a conductive film on the second gate insulating film in the memory cell region and on the gate electrode material in the first and second peripheral regions. And a step of etching the conductive film, the second gate insulating film, and the gate electrode material film in the memory cell region and the first and second peripheral regions to form the memory cell transistor and the first and second transistors. Forming a gate structure and exposing a part of the surface of the semiconductor substrate, and injecting impurities into the surface of the semiconductor substrate in the memory cell region and the first and second peripheral regions. Method of manufacturing a nonvolatile semiconductor device which is characterized by comprising the steps of forming the memory cell transistor and the first source-drain region of the second transistor and. 7. The non-volatile according to claim 5, wherein the step of forming the gate electrode material film is a step of forming a polycrystalline silicon film not doped with impurities. Manufacturing method of semiconductor memory device. 8. The method according to claim 5, further comprising the step of reducing the height by partially etching the element isolation insulating film after forming the element isolation insulating film. Non-volatile semiconductor memory device manufacturing method.