JPH08139314A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] When increasing the density of semiconductor devices such as DRAM, L
A wide contact space is secured in the MISFET having the DD structure, and low contact resistance or self-alignment is facilitated. [Structure] After patterning the gate electrode 101, thin source / drain implantation is performed to form a bit line base insulating film 107.
Is formed on the entire surface including the side portions of the gate electrode 101, Si sidewalls 106 are formed, and the gate electrode 101 and the Si are formed.
High-concentration impurity ions are implanted through the bit line base insulating film 107 using the sidewalls 106 as masks. After that, the bit line contact is connected to the Si sidewall 10
6, the gate electrode 101 by the two-step etching of the insulating film 107
Further, the bit line 109 is formed by opening the base insulating film 107 in a self-aligned manner.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an M having an LDD structure.
The present invention relates to a semiconductor device having an ISFET, and more particularly to a measure for reducing contact resistance.

[0002]

2. Description of the Related Art In recent years, the capacity of DRAMs has been increased, and sample shipments of 64Mbit DRAMs have already been shipped. Conventionally, in a DRAM type semiconductor device, MISFE is used.
The T structure adopts an LDD structure using an oxide film side wall in order to suppress the short channel effect due to the reduction of the gate length and improve the hot carrier resistance. That is, as shown in FIG. 8, the MOS transistor arranged in the peripheral circuit of the conventional DRAM is the Si substrate 5
Gate electrode 501 and the gate electrode 5 formed on
01 on-gate insulating film 502, a gate oxide film 503 provided between the gate electrode 501 and the Si substrate 500, and a silicon oxide film formed on the side of the gate electrode 501. Sidewall 506 and Si
It is provided with a low concentration source / drain region 511 formed near the end of the gate electrode 501 on the surface region of the substrate 501 and a high concentration source / drain region 512 formed outside the low concentration source / drain region 511. . And
A high-concentration source / drain region 512 is contacted through a bit line base insulating film 507 that covers the entire surface of the substrate including the gate electrode 501 and the sidewalls 506, and a contact hole formed in the bit line base insulating film 507. Bit lines 509 are provided.

Next, FIGS. 9A to 9C and FIG.
A conventional method of manufacturing a DRAM type semiconductor device will be described with reference to FIGS. Note that FIG.
10A to 10C and FIGS. 10A and 10B, the left side shows the sectional structure of the semiconductor device in the peripheral circuit Rpc, and the right side shows the structure of the memory cell portion Rmc.

First, as shown in FIG. 9A, an element isolation 504 for partitioning a surface region of a semiconductor substrate 500 is formed, and an active region partitioned by the element isolation 504 and an element isolation 5 are formed.
04 on the gate oxide film 503, the gate electrode 50
1, an insulating film 502 on the gate is formed. Then, the gate oxide film 503, the gate electrode 501, the gate insulating film 50
Using 2 as a mask, low concentration impurity ions are implanted to form low concentration source / drain regions 511 in a self-aligned manner. Impurity ion implantation is performed using an n-channel MOS transistor and a p-channel MOS transistor as necessary, and a photoresist mask is also used.

Next, as shown in FIG. 2B, an oxide film is deposited to a thickness of about 150 nm by a CVD method and anisotropic dry etching is performed to perform high-concentration source / drain implantation on the side surface of the gate electrode as shown in FIG. An oxide film (hereinafter referred to as “oxide film sidewall 406”) to be a spacer for
High concentration source / drain ion implantation is performed to form high concentration source / drain regions 506. . At this time, high concentration ions are not implanted under the oxide film sidewall 506.

Next, as shown in FIG. 2C, a bit line base insulating film 507 is deposited.

Next, as shown in FIG. 3A, a resist mask Mre is formed by a photomask process and a dry etching process.
A part of the bit line base insulating film 507 is etched by using 10, and a bit line contact hole 508 is formed in self alignment with the gate electrode 501.

Next, as shown in FIG. 3B, polycrystalline S
Bit line 5 composed of i film 509a and WSi film 509b
09 and a bit line insulating film 510 are formed.

Thereafter, although not shown, the memory cell portion R
With mc, an oxide film for capacitance insulation, a capacitance electrode, a dielectric film, a plate electrode, etc. are formed.

[0010]

However, in the above-mentioned structure, there has been a problem that the contact resistance increases with the increase in capacity and density of the DRAM, which deteriorates the device characteristics and makes contact formation difficult. . That is, when the inter-gate space becomes narrower, when the contact formation is performed in a self-aligned manner, the contact space in the direction perpendicular to the gate electrode is changed from the inter-gate space to the oxide film sidewall for LDD and the oxide film for bit line. Since the length is obtained by subtracting twice the total film thickness, it becomes extremely narrow, the contact resistance increases, and sufficient MOS transistor performance cannot be obtained. Further, in the cell portion where the space between the gates is the smallest in the DRAM, the gate length is 0.3.
When it becomes about μm, the inter-gate space becomes narrower to about 0.3 μm, and the inter-gate space in the cell section is filled with the above-mentioned oxide film, making it impossible to form a self-aligned contact.

11A to 11C show a miniaturized D
It is sectional drawing which shows the change of the structure in the manufacturing process of RAM. First, as shown in FIG. 11A, as shown in FIG.
It is assumed that the process has advanced to the state shown in. At this time, when the oxide film side wall 506 is formed, in many cases,
The space between the gate electrodes 501 of the memory cell portion Rmc is almost filled with the oxide film sidewall 506. Further, the memory cell portion R is formed by the oxide film side wall 506.
Even if the space between the gate electrodes 501 of mc is not completely filled, when the bit line base insulating film 507 is deposited,
If the space between the gates 501 becomes narrower than about 0.3 μm, the space between the gate electrodes 501 of the memory cell portion Rmc will be filled up by forming the bit line base insulating film 507.

Thereafter, as shown in FIG. 11B, when the bit line base insulating film 507 is etched through a photomask exposure process, a bit contact hole 508a is opened in the peripheral circuit portion Rpc. Even if the bit line contact 508b hole is to be opened in the memory cell portion Rmc, it is difficult to remove the buried portion and expose the surface of the Si substrate 501. That is, as shown in FIG. 11C, when etching is still continued, a part of the gate insulating film 502 is removed in the bit line contact hole 508b of the memory cell portion Rmc, and the gate electrode 501 is removed.
A part Def where the is exposed occurs.

That is, a bit line contact hole 509 is provided between the cell portion 545 and the gate 501 which are filled with the oxide film side wall 506 and the bit line base insulating film 507.
In order to open b, it is necessary to etch the step of the gate 501 and the total film thickness of the gate insulating film 502 and the bit line base insulating film 507. Gate 501
The resist opening size is made small so that it does not overlap with
Moreover, if ultra-strict alignment cannot be performed, part of the on-gate insulating film 502 is removed and the gate electrode 501 is exposed as described above. If the bit line is formed as it is, a short circuit failure between the bit line and the gate 501 occurs.

Explaining in the partial cross-sectional view shown in FIG. 8, in the portion where the bit line contact hole is formed in self-alignment with the gate electrode 501, the contact space Wco in the direction vertical to the gate electrode direction is between the gates. The length is obtained by subtracting the film thickness of twice the thickness (thickness of oxide film sidewall 506 + thickness of bit line base insulating film 507), and the opening can be made without exposing a part of the gate electrode 501. However, the contact resistance increases and sufficient performance cannot be obtained as a MOS transistor.

Further, in the formation of the capacitance electrode contact after the formation of the bit line, the interval between the gate electrodes 501 becomes twice as narrow as the thickness of the capacitance electrode base insulating film, as compared with the bit line contact hole 508b. Gate electrode 501
It becomes increasingly difficult to make contacts in a self-aligned manner. On the other hand, in order to secure a contact space, the oxide film side wall 506 and the bit line base oxide film 507 must be made very thin, which makes it difficult to suppress the short channel effect and also provides flexibility in device design and process design. Will be significantly hindered.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a desired source / drain impurity in the lateral direction of a desired LDD structure even if the element size is reduced in a semiconductor device in which a MISFET is arranged. It is intended to provide a structure of a MISFET having a distribution, a short contact effect for a bit line or a cell capacitance electrode and a low contact resistance while suppressing a short channel effect, and a manufacturing method thereof.

[0017]

In order to solve the above problems, an outline of typical inventions among the inventions disclosed by the present application will be described. That is, the insulating film sandwiched between the side surface of the gate electrode and the bit line and the insulating film sandwiched between the Si substrate active region and the bit line are effectively made to have the same structure. As a manufacturing method for realizing the structure, an oxide film and polycrystalline Si are formed on the entire surface after forming the gate electrode,
Polycrystalline Si on the side surface of the gate electrode by anisotropic dry etching
Step of forming sidewalls and then high concentration source
It is provided with a step of performing drain ion implantation, a step of removing a part of the Si sidewall and the oxide film for forming a bit line contact, and a step of forming a bit line on it.

[0018]

By the above semiconductor device and the manufacturing method thereof,
According to the invention of each claim, the following effects can be obtained.

According to the invention of claim 1 or 2, MISFET is provided.
However, even if the space between the gate electrodes becomes narrower, the contact area between the conductive member and the source / drain regions is wider than the high-concentration source / drain regions and extends to the low-concentration source / drain regions. Therefore, a wide contact area is secured. Therefore, the action of preventing the short channel effect by the low-concentration source / drain and the high-concentration source / drain is obtained, a wide contact area is secured, and the reliability is improved.

According to the third or fourth aspect of the invention, even in the portion where the gate electrode functions as a MISFET, the high-concentration source / drain region is formed by the same treatment as the portion where the conductive member covers a part of the gate electrode. Since it is formed in self-alignment with the wiring base insulating film and the highly selective sidewalls on the side of the gate electrode, it has a good positional relationship with the low concentration source / drain to prevent the short channel effect. Secured. On the other hand, since the high-selectivity sidewall has a property of being etched with a high selection ratio with respect to the side insulating film, the wiring base insulating film is not damaged during the manufacturing process, and the conductive film and the gate are not damaged. Good insulation with the electrodes is also maintained.

According to the fifth aspect of the present invention, between the gate electrodes in the MISFET formed in the peripheral circuit, the conventional insulating film between the gate electrodes is one layer less (the oxide film side wall is eliminated). Low concentration sauce
The contact space between the impurity diffusion region formed of the drain and the conductive member is widened. Therefore, a semiconductor device having a high-performance MISFET with low contact resistance can be obtained.

Further, even in the memory cell portion where the space between the gate electrodes is particularly narrow, even if the space between the gate electrodes is once filled with the film forming the highly selective sidewall, at the time of etching for opening the contact hole thereafter, The highly selective sidewall having a high selection ratio with respect to the wiring underlying insulating film is easily removed. Therefore, the space between the gate electrodes is not filled with the insulating film, and the contact can be formed in a self-aligned manner.

Further, the high-selectivity sidewall also has a flattening effect of increasing the curvature of the gate step portion, and when patterning a conductive member on the sidewall, unevenness of the resist film thickness and the underlying layer are caused in the photomask exposure step. Reduces diffuse reflection,
Facilitates resist pattern formation. Then, in the subsequent etching for patterning, the effective film thickness in the vertical direction becomes thin in the gate step portion of the film formed above, so that the etching time is shortened, and the dimensional change and the underlying film slippage in the flat portion are reduced. It also has a great effect on improving workability.

According to the sixth aspect of the present invention, since the highly selective sidewall having conductivity is in contact with the impurity diffusion region, if the conductive film is deposited from above without removing it, the both will be integrated. Function as wiring.
Then, since the impurity ions are simultaneously implanted into the high-selectivity sidewall during the impurity implantation for forming the high-concentration source / drain, it is not necessary to implant the impurity ions to reduce the contact resistance after forming the conductive film. Alternatively, the implantation amount of impurity ions is reduced.

According to the seventh or eighth aspect of the invention, in a DRAM which requires a high speed operation, a high speed MISFET is formed in the peripheral circuit.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, the first embodiment will be described. FIG. 1 is a sectional view showing a structure of a MOS transistor arranged in a peripheral circuit of a semiconductor device of the present invention.
In the figure, 100 is a Si substrate, 101 is a gate electrode, 102 is a gate insulating film, 103 is a gate oxide film,
109 is a bit line, 107 is a bit line 1 which covers the periphery of the gate electrode 101 and the insulating film 102 on the gate and the active region.
A bit line base insulating film serving as a base of 09, 111 is a low concentration source / drain region (LDD), and 112 is a high concentration source / drain region.

Here, as a characteristic of the MOS transistor shown in FIG. 1, the boundary between the high concentration source / drain region 112 and the low concentration source / drain region 111 is the bit line 1
09 is included in the contact space between the active region and 09. For example, in the region sandwiched by the two gate electrodes 101 in FIG. 1, the contact space width Wo between the bit line 109 and the active region has a high-concentration source / drain region 112.
The width W1 of the bit line 109 is larger than the width W1 of the bit line 109, and part of the bit line 109 is in contact with the low concentration source / drain region 111. In other words, a so-called LDD structure MOS having low-concentration source / drain impurity regions 111 and high-concentration impurity regions 112.
Sidewalls that are normally present in transistors,
That is, there is no oxide film sidewall that serves as an implantation mask for the high concentration source / drain impurities and defines the position of the high concentration source / drain impurity regions 112. Therefore, even if the space between the gates is narrow, the gate electrode 1
The space of the bit line contact 109 formed in a self-aligned manner with respect to 01 is secured wide, and a MOS transistor having a low contact resistance is realized. That is, the bit line contact space width Wo is obtained by subtracting twice the film thickness of the bit line base insulating film 107 from the inter-gate space.

Next, a method of manufacturing the semiconductor device of this embodiment will be described below with reference to FIGS. 2A to 2D, the left side diagram shows the state of the peripheral circuit section Rpc, and the right side diagram shows the memory cell region Rmc.
Indicates the state of.

First, as shown in FIG. 2A, an element isolation 104 for partitioning the surface region of the semiconductor substrate 100 is formed, and the active region and the element isolation 1 defined by the element isolation 104 are separated.
04, a gate oxide film 103, a gate electrode 10
1, an insulating film 102 on the gate is formed. Then, the gate oxide film 103, the gate electrode 101, the gate insulating film 10
Using 2 as a mask, low concentration impurity ions are implanted to form the low concentration source / drain regions 111 in a self-aligned manner. Impurity ion implantation is performed using an n-channel MOS transistor and a p-channel MOS transistor as necessary, and a photoresist mask is also used.

Next, as shown in FIG. 2B, a CVD oxide film (bit line base insulating film 107) is formed over the entire surface of the gate electrode 101, the insulating film above the gate 102 and the entire surface of the Si substrate 100. Then, a polycrystalline Si film (or an amorphous Si film) which is a conductive member is formed on the entire surface,
The Si sidewall 106 is formed on the side portion of the gate electrode 101 by anisotropic dry etching. At that time, in the memory cell region Rmc, depending on the spaces between the gate electrodes 101, the spaces between the gate electrodes 101 are filled with the Si sidewalls 106 as shown in part A of FIG. 2B. On the other hand, the thickness of the bit line base insulating film 107 ensures a wide contact space between the gate electrodes 101, and the impurity ion implantation for forming the high concentration source / drain 112 is performed. In order to carry out from above, it is preferable to make it as thin as possible. However, the bit line base insulating film 107 has a role of an etching stopper in a bit line etching process described later, in addition to electrical insulation, and therefore needs to have a thickness of about 20 nm. Further, the thickness of the polycrystalline Si film for forming the Si sidewall 106 is set so that the impurity ions for forming the high concentration source / drain regions 112 are implanted at desired positions. That is, the impurity ions are implanted at a position separated from the side surface of the gate electrode 101 by the total film thickness of the bit line base insulating film 107 and the Si sidewall 106. The optimum value of the total film thickness varies depending on the gate length of the transistor, heat treatment in the subsequent process, driving voltage, etc.
It is about 8 μm.

After forming the Si sidewall 106, an n-channel and p-channel MOS are subjected to a photomask exposure process.
High-concentration impurity ions are implanted into each of the transistors to form high-concentration source / drain regions 112.
At that time, ion implantation is performed through the bit line base insulating film 107 using the resist, the gate electrode 101, and the Si sidewall 106 as a mask. However, among the n-channel MOS transistors, the MOS in the memory cell region Rmc
The transistor may avoid this implantation with a resist mask.

Next, as shown in FIG. 2C, the Si sidewall 106 and a part of the bit line base insulating film 107 are continuously formed by using the resist mask Mre1 formed by the photomask exposure process. Etching is performed to expose a part of the active region and form a bit line contact hole 108.
In this process, when the Si sidewall 106 is etched, it is necessary to etch the polycrystalline Si film of about the level difference (total film thickness) between the gate electrode 101 and the gate insulating film 102. Since the etching selectivity between the polycrystalline Si film (or amorphous Si film) and the silicon oxide film forming the bit line base insulating film 107 is high, the bit line base insulating film 107 below the Si side wall 106 is hardly etched. It won't disappear. Further, since the bit line base insulating film 107 is thinner than the gate insulating film 102, the contact hole can be opened in a self-aligned manner without exposing the gate electrode 101 when the bit line base insulating film 107 is etched. . Particularly, when the bit line contact hole 108 of the peripheral circuit portion Rpc is formed at the same time as the memory cell region Rmc as in the present embodiment, the bit line base insulating film 107 is exposed from the initial etching of the Si sidewall 106. However, even with the current dry etching technology, polycrystalline Si
The maximum selection ratio with respect to the silicon oxide film at the time of etching the film is close to 100.
6 There is no fear that the Si substrate 100 will be etched because the bit line base insulating film 107 is lost during etching.

Although the case where the resist mask Mre1 is simultaneously formed in the memory cell region Rmc and the peripheral circuit portion Rpc to open the bit line contact hole 108 has been described here, the photomask exposure process and the etching process are performed in the memory cell region Rmc. It is also conceivable that the peripheral circuit unit Rpc and the peripheral circuit unit Rpc are divided into two times. In this case, the number of steps is increased, but the Si sidewall 10 is etched when the peripheral circuit portion Rpc is etched.
The etching of 6 becomes unnecessary.

Next, as shown in FIG. 2D, the bit line 109 that contacts the active region through the bit line contact hole 108 is formed. Here, as an example, WS
Bit lines of i-polycide are to be formed. After opening the bit line contact hole 108, first, a polycrystalline Si film 109a is deposited to a thickness of about 20 nm to 150 nm as a WSi base. After that, for example, arsenic ions are implanted into the polycrystalline Si film 109a to reduce the resistance, and then the WSi film 109b is deposited to a thickness of about 50 nm to 200 nm. Then, in order to enable the cell capacitance electrode contact hole formed in the next step to be formed in self-alignment with the bit line, the WSi film 109b is formed.
A CVD oxide film (hereinafter referred to as a bit line insulating film 110) is formed on top. After that, a bit line insulating film 110 and a WSi film 10 are formed by a photomask process and a dry etching process.
9b, polycrystalline Si film 109a, Si sidewall 10
6 is etched, and the bit line 109 is patterned. In some cases, the CVD oxide film is further continuously etched to expose a part of the active region.

Next, as shown in FIG. 3A, after the bit line 109 is formed, for example, a CVD oxide film is formed as a capacitor electrode base insulating film 114 for cell capacitor electrode insulation, and a photomask exposure process and a dry process are performed. Resist Mre by etching process
The capacitor electrode base insulating film 114 is etched by using 2 as a mask to expose a part of the active region to form a capacitor electrode contact hole 116.

After that, as shown in FIG. 3B, the capacitor electrode 117 is formed of, for example, a phosphorus-containing polycrystalline Si film or a dielectric film 118.
Is formed of, for example, an ONO film, and the plate electrode 119 is formed of, for example, a phosphorus-containing polycrystalline Si film. After that, an insulating film, a conductive film, a photo process, and an etching process are performed several times to form upper wirings, thereby completing a device (DRAM type semiconductor device).

The role of the Si sidewall 106 will be supplemented here. The Si sidewall 106 not only acts as a spacer at the time of implantation, but also has an effect of increasing the curvature of the gate step portion, which facilitates the resist pattern formation by the photomask exposure process of the bit line 109 and the subsequent bit line etching process. There is also an effect to do.
That is, the Si sidewall 106 has a function of automatically flattening without increasing the number of steps.

If unnecessary portions of the Si sidewalls 106 other than below the bit lines 109 remain in the subsequent steps, inconvenience may occur during the formation of contact holes. However, the WSi film 109b of the bit lines 109, the polycrystalline film. Si film 109
Since it is automatically removed at the time of etching a, it is not necessary to provide a removing step. Although arsenic is shown here as an example for low resistance implantation into the polycrystalline Si film 109a, phosphorus may be used.

In the above embodiment, the polycrystalline Si film 109 is used.
Although the WSi film 109b was formed as it was after the formation of a and after the arsenic implantation, the polycrystalline Si film may be etched back if it is desired to expand the process margin by further flattening even if the number of processes is increased. That is, after the high concentration source / drain implantation, the polycrystalline Si is slightly thicker and the film thickness is 20
After depositing about 0 nm to 500 nm, polycrystal Si is etched back to leave about 10 nm to 150 nm at the thinnest part (flat part), and then low resistance implantation is performed. WSi film 1
Of course, a method of depositing 09b is also possible.

Further, in the above embodiment, the WSi polycide structure is used as the bit line 109, but the polycide using the refractory metal silicide other than TiSi polycide or the refractory metal silicide may be used.

Although the bit line base insulating film 107 is formed by depositing the CVD oxide film once in the above embodiment, a combination of thermal oxidation and CVD oxide film deposition may be used. In addition, after forming a thin oxide film first, the Si sidewall 106 is formed, and the high concentration source / drain region 1 is formed.
There is also a method of completely removing the Si sidewall 106 after implanting the impurity ions for forming 12 and depositing an oxide film again to form a bit line contact and a bit line. By dividing the formation of the oxide film into two times with the implantation interposed, the oxide film formed the second time has high insulation and etching resistance because it is not damaged by the implantation. Of course, even in this case, it is natural to set the film thickness so that the inter-gate electrode spacer is not filled with the oxide film twice. In order to form a thicker oxide film for the second time, after removing the Si sidewall 106, the first thin oxide film may be etched by HF treatment before the second oxide film is formed.

After forming the bit line base insulating film 107, an injection spacer may be formed by using, for example, a SiN film or an organic film instead of the polycrystalline Si film. In this case, it is necessary to use a material having a large etching selection ratio with respect to the underlying oxide film so that the underlying oxide film is not scraped off when the spacer is etched.

Next, the high-concentration source / drain region 112 and the low-concentration source /
The boundary position with the drain region 111 (hereinafter referred to as “high-concentration source / drain region boundary position”) will be described.
The high-concentration boundary position moves due to impurity diffusion due to thermal processes such as heat treatment and oxidation after implantation, as compared with immediately after implantation.
The position will be described with reference to FIG.

FIG. 4 shows an MO formed by the above embodiment.
Among the S transistors, the bit line 109 is the gate electrode 10
1 is a cross-sectional view of a MOS transistor crossing over the upper part of FIG. 1, and the same members as those shown in FIGS. 1 and 2 have the same reference numerals. However, Si sidewall 1
Although 06 is removed when the device is completed, it is indicated by a broken line for easy understanding. Where line A
1, A2 are horizontal high-concentration source / drain region boundary positions after the device is completed, straight lines B1 and B2 are horizontal high-concentration source / drain region boundary positions defined by the bit line base insulating film, and straight lines C1 and C2 are In the process shown in FIG. 2B of the embodiment, the lateral high-concentration source / drain region boundary positions immediately after the impurity ion implantation, the straight lines D1 and D2 are high-concentration after the bit line underlying insulating film is formed and before the Si sidewall 106 is formed. The high-concentration source / drain region boundary position immediately after the implantation is shown when the implantation is performed.

In this embodiment, since the impurity ions for forming the high-concentration source / drain regions are injected after the Si sidewall 106 is formed, the high-concentration boundary immediately after the injection is located at the positions of straight lines C1 and C2. is there. In the heat treatment until the device is completed, it diffuses in both the vertical and horizontal directions. However, if the final vertical high-concentration source / drain region boundary depth is d, the horizontal high-concentration source The boundary of the drain region is located inside by a distance (0.8d) of about 80% of the depth d, that is, at the position indicated by the straight lines A1 and A2. On the other hand, if it is assumed that the high-concentration implantation is performed immediately after the formation of the bit line base insulating film 107, the boundary position immediately after the implantation will be the positions indicated by the straight lines D1 and D2, and the length from the straight lines D1 and D2 after the device is completed. The positions are the straight lines B1 and B2 that are located 0.8d inside. If high-concentration implantation is performed immediately after patterning the gate electrode 101, the high-concentration source / drain region boundary position after completion of the device should be located further inside the positions of the straight lines B1 and B2.

Regarding the sectional structure of FIG. 4, a characteristic part of the present invention other than the source / drain boundary position will be described. First, the Si sidewall 106 is the bit line 109.
Since it is in direct contact with, it is regarded as a part of the bit line 109.
A portion of the bit line base insulating film 107 sandwiched between the gate electrode 101 and the bit line 109 (thickness x), and the bit line 109 and the substrate active region (source / drain region) of the bit line base insulating film 107. Since the portion sandwiched between (e.g., etc.) (referred to as the film thickness y) is formed at the same time, the film thickness is also approximately x = y.

FIG. 4 is a sectional view of a transistor in which the bit line 109 crosses over the gate electrode 101.
Actually, there are many MOS transistors apart from the bit line on one LSI chip. In that case, in FIG.
From which the Si sidewall 106 and the bit line 101 are omitted. However, the horizontal boundary position of the high-concentration source / drain region 112 is defined by the total film thickness of the bit line base insulating film 107 and the Si sidewall 106 because the bit line 109 crosses the gate electrode 101. It is similar to the MOS transistor in the portion where it is present.
The film thickness of the bit line base insulating film 107 and the film thickness of the Si sidewall 106 are not the transistor part but the element isolation 1
04, the gate electrode 101 and the bit line 109
The same applies to the intersection of and.

(Second Embodiment) Next, a second embodiment will be described. FIG. 5 shows a cross-sectional structure of a MOS transistor arranged in the peripheral circuit portion of the semiconductor device according to the second embodiment. The structure of the MOS transistor shown in FIG.
Although the structure is almost the same as that of the MOS transistor shown in FIG. 1 of the embodiment, in this embodiment, the Si sidewall 106 formed during the manufacturing process remains in the bit line contact portion and is integrated with the bit line 109. Has been converted.

In the manufacturing process, in the first embodiment, the bit line contact portion is formed after the Si sidewall is formed and the high concentration source / drain regions are ion-implanted, while in the second embodiment. Immediately after the formation of the bit line base insulating film and before the formation of the Si sidewall.

Hereinafter, FIGS. 6A to 6D and FIG.
A method of manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS.

First, as shown in FIG. 6A, an element isolation 104 for partitioning the surface region of the semiconductor substrate 100 is formed, and an active region partitioned by the element isolation 104 and the element isolation 1 are formed.
04, a gate oxide film 103, a gate electrode 10
1, an insulating film 102 on the gate is formed. Then, the gate oxide film 103, the gate electrode 101, the gate insulating film 10
Using 2 as a mask, low concentration impurity ions are implanted to form the low concentration source / drain regions 111 in a self-aligned manner. Impurity ion implantation is performed using an n-channel MOS transistor and a p-channel MOS transistor as necessary, and a photoresist mask is also used.

Next, as shown in FIG. 6B, a CVD oxide film (bit line base insulating film 107) is formed over the entire surface of the gate electrode 101, the insulating film above the gate 102 and the entire surface of the Si substrate 100. To do. The process up to this step is the same as in the first embodiment.

Next, as shown in FIG. 6C, a resist mask Mre3 is formed by a photomask exposure process and a dry etching process, and the bit line base insulating film 107 is etched using the resist mask Mre3 to form a substrate. A part of the active region is exposed and the bit line contact hole 108 is opened.

Next, as shown in FIG. 6D, after a non-single crystal Si film is deposited, anisotropic dry etching is performed to form Si sidewalls made of non-single crystal Si on the side surfaces of the gate electrode 101. Form 106. After that, through a photomask exposure process, high-concentration ion implantation is performed on the source and drain of the n-channel MOS transistor and the p-channel MOS transistor, respectively, and the high-concentration source / drain region 11
Form 2

The subsequent steps are as shown in FIG. 2 of the first embodiment.
This is the same as the step shown in FIG. 7D, and as shown in FIG. 7A, the bit line insulating film 110, the WSi film 109b, the polycrystalline Si film 1 are formed by a photomask step and a dry etching step.
09a and the Si sidewall 106 are etched, and the bit line 109 is patterned. Then, after forming the bit line 109, a CVD oxide film, for example, is formed as a capacitor electrode base insulating film 114 for cell capacitor electrode insulation, and a resist Mre is formed by a photomask exposure process and a dry etching process.
The capacitor electrode base insulating film 114 is etched by using 4 as a mask to expose a part of the active region, and a capacitor electrode contact hole 116 is formed.

Further, as shown in FIG. 7B, a capacitance electrode 117, a capacitance insulating film 118, and a plate electrode 119 are formed.

As in the second embodiment, the bit line contact hole 109 is first opened and then the Si sidewall 106 is formed.
As a result, arsenic is simultaneously implanted into the Si sidewall 106, which is in contact with the bottom surface of the bit line contact 109, during the ion implantation for forming the high-concentration source / drain of the n-channel MOS transistor.
Therefore, it is not necessary to implant arsenic ions to reduce the contact resistance after forming the polycrystalline Si film 110, or at least the ion implantation amount can be reduced.

Here, the Si sidewall 10 is used.
6 uses a non-doped film, but if non-single-crystal Si doped with arsenic is used as a constituent material of the Si sidewall 106, there is an advantage that arsenic implantation for reducing the contact resistance becomes almost unnecessary. is there.

[0060]

As described above, according to claims 1, 2, 3
According to the invention of 4 or 4, MISFE having an LDD structure
In a semiconductor device including T, the degree of integration and reliability can be improved while maintaining the function of preventing the short channel effect.

According to the invention of claim 5, 6, 7 or 8,
DRA mounted with MISFET having LDD structure
In the manufacturing process of a semiconductor device such as M, it is possible to easily secure a contact between the active region and the conductive member between the narrow gate electrodes, so that it is possible to provide a semiconductor device having a high degree of integration and reliability. it can.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a DRAM according to a first embodiment.

FIG. 2 is a cross-sectional view showing a structural change in a manufacturing process up to formation of a bit line of the DRAM according to the first embodiment.

FIG. 3 is a cross-sectional view showing a structural change in the manufacturing process after forming the bit line of the DRAM according to the first embodiment.

FIG. 4 is a cross-sectional view for explaining the positional relationship between the high-concentration source / drain regions and the insulating film on the side wall of the gate of the DRAM according to the first example.

FIG. 5 is a sectional view showing a structure of a semiconductor device according to a second embodiment.

FIG. 6 is a cross-sectional view showing a structural change in a manufacturing process up to formation of a bit line of a DRAM according to a second embodiment.

FIG. 7 is a cross-sectional view showing a structural change in a manufacturing process after forming a bit line of a DRAM according to a second embodiment.

FIG. 8 is a cross-sectional view showing the structure of a conventional DRAM.

FIG. 9 is a cross-sectional view showing a structural change in a process up to formation of a bit line base insulating film in a process of manufacturing a DRAM having a conventional LDD structure.

FIG. 10 is a cross-sectional view showing a structural change in the process after the formation of the bit line base insulating film in the process of manufacturing the DRAM having the conventional LDD structure.

FIG. 11 is a cross-sectional view showing a structural change in a manufacturing process when a conventional DRAM having an LDD structure is miniaturized.

[Explanation of symbols]

 100 Si substrate 101 Gate electrode 102 Gate insulating film 103 Gate oxide film 104 Element isolation 106 Si sidewall 107 Bit line base insulating film 108 Bit line contact 109 Bit line 110 Bit line upper insulating film 111 Low concentration source / drain region 112 High concentration Source / drain region Rmc Memory cell part Rpc Peripheral circuit part

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/8234 27/088 27/108 21/8242 H01L 21/265 Y 27/08 102 D 7735- 4M 27/10 681 B 29/78 301 M

Claims (8)

[Claims] 1. A semiconductor device having a MISFET mounted on a semiconductor substrate, wherein the MISFET is substantially outside a region of the gate electrode formed on the semiconductor substrate and a region directly below the gate electrode of the semiconductor substrate. Two impurity diffusion regions formed on one side of the low-concentration source / drain region and the high-concentration source / drain region, a wiring base insulating film formed on the semiconductor substrate including the sides of the gate electrode, and the gate A conductive member that contacts the impurity diffusion region in a self-aligning manner with respect to the electrode and the wiring underlying insulating film, and at least one of the boundary positions of the high-concentration source / drain regions and the low-concentration source / drain regions One is on the side of the conductive member rather than the boundary position between the wiring base insulating film on the side of the gate electrode and the conductive member, and the conductive member has a low density. A semiconductor device characterized by being in contact with part of the source / drain region. 2. The semiconductor device according to claim 1, wherein the MISFET is arranged in a peripheral circuit portion of a DRAM, and the conductive member is a bit line. 3. The semiconductor device according to claim 1, wherein in the portion where the conductive member covers at least a part of the gate electrode, the wiring underlayer insulation is lateral to the gate electrode and above the semiconductor substrate. A highly selective sidewall made of a material having etching characteristics with a high selection ratio with respect to the wiring underlying insulating film, the film thickness of the highly selective sidewall and the side insulating film being provided. The sum of the film thickness defines a lateral boundary between at least a part of the low-concentration source / drain regions and the high-concentration source / drain regions, and the high-selectivity sidewall is at least a part of the conductive member. A semiconductor device characterized by being in contact with each other. 4. The semiconductor device according to claim 3, wherein the highly selective sidewall is made of any one material of polycrystalline Si and amorphous Si. Semiconductor device. 5. A method of manufacturing a semiconductor device having a MISFET having an LDD structure, the method comprising: forming a gate electrode of the MISFET and an insulating film on the gate on a semiconductor substrate; and insulating the gate electrode and the insulating film on the gate. A step of implanting low-concentration impurity ions into the active region of the semiconductor substrate using the film as a mask to form low-concentration source / drain regions, and a thin wiring base insulating film over the entire surface of the semiconductor substrate including the sides of the gate electrode. And a step of forming, on the surface of the wiring base insulating film on the side of the gate electrode, a highly selective sidewall made of a material having an etching target characteristic with a high selection ratio with respect to the wiring base insulating film. , Through the wiring base insulating film, using at least the gate electrode and the highly selective sidewall as a mask, a high-concentration impurity layer is formed in the substrate active region. Ion implantation to form high-concentration source / drain, and etching a part of the high-selectivity sidewall and a part of the wiring underlying insulating film to perform self-alignment with the gate electrode. A method of manufacturing a semiconductor device, comprising: a step of forming a contact hole in the wiring; and a step of filling the contact hole and forming a conductive film that covers at least a part of the wiring base insulating film. . 6. A method of manufacturing a semiconductor device having a MISFET having an LDD structure, the method comprising: forming a gate electrode of the MISFET and an insulating film on the gate on a semiconductor substrate; and the gate electrode and the gate. A step of implanting low-concentration impurity ions into the active region of the semiconductor substrate using the insulating film as a mask to form low-concentration source / drain regions, and a thin wiring base insulation on the entire surface of the semiconductor substrate including the side of the gate electrode. A step of forming a film, a step of etching a part of the wiring base insulating film to expose a part of the substrate active region to form a contact hole, and a step of filling the contact hole and at least the wiring base insulating film. A film made of a conductive material having a high etching selectivity with respect to the wiring underlying insulating film is deposited so as to cover a part of the wiring underlying insulating film, and the anisotropic dry film is deposited. Forming a highly selective side wall on the surface of the wiring underlying insulating film on the side of the gate electrode, and using a mask of at least the gate electrode and the highly selective side wall as a mask to form a high concentration A step of implanting impurity ions to form high-concentration source / drain, and a step of filling the contact hole from above the highly selective sidewall and forming a conductive film so as to cover the wiring underlying insulating film. A method of manufacturing a semiconductor device, comprising: 7. The method of manufacturing a semiconductor device according to claim 5, wherein the MISFET is arranged in a peripheral circuit portion of a DRAM, and the conductive film is patterned to form a bit line. A method of manufacturing a semiconductor device, further comprising: 8. The method of manufacturing a semiconductor device according to claim 7, wherein in the memory cell portion of the DRAM, a step of forming an electrode base insulating film after forming the bit line, a part of the electrode base insulating film and the wiring. A step of etching a part of the base insulating film to form a capacitance electrode contact hole in a self-aligned manner with the gate electrode and the bit line; And a step of depositing an electrode film to cover and patterning the electrode film to form a capacitor electrode.