JP2003007052A - Semiconductor storage device and memory system using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory and a memory system in which data bus efficiency is improved. SOLUTION: An address corresponding to a first memory region and an address corresponding to a second memory region are inputted to an address buffer 2 and data read from first and second memory area are outputted alternately to a data input/output section 30. In a data bus of a double data rate, a cluster of data in read operation of one time is made half of conventional one, and data bus efficiency is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a memory system, and more particularly to a semiconductor memory device connected to a data bus for transferring data at a double data rate and a memory system including the same.

[0002]

2. Description of the Related Art With the improvement of clock operating speed of microprocessors, in recent years, in order to further increase the speed of a synchronous dynamic random access memory (SDRAM) which transmits and receives data in synchronization with a clock, a rising edge and a falling edge of the clock A double data rate SDRAM (DDR SDRAM) has been developed which transfers data at the edge at a double rate of a clock.

FIG. 10 is a block diagram showing a schematic configuration of a conventional semiconductor memory device 501.

Referring to FIG. 10, semiconductor memory device 501
Synchronizes memory array banks 514 # 0 to 514 # 1 each having a plurality of memory cells arranged in a matrix, and externally applied address signals A0-An and bank address signal BA with clock signal CLKI. An address buffer 502 for fetching, outputting an internal row address, an internal column address and an internal bank address, and a clock signal CLK and a clock enable signal C from the outside.
A clock buffer 504 that receives KE and outputs clock signals CLKI and CLKQ used inside the semiconductor device.
And control signals / CS, / RAS, /
Control signal input buffer 506 that receives CAS, / WE and mask signal DQMU / L in synchronization with clock signal CLKI.

Semiconductor memory device 501 further receives an internal address signal from address buffer 502, and
From the control signal input buffer 506, the control signal int. RAS, int. CAS, in
t. The control circuit includes a control circuit that receives WE and outputs a control signal to each block in synchronization with the clock signal CLKI, and a mode register that holds the operation mode recognized by the control circuit. In FIG. 10, the control circuit and the mode register are shown as one block 508.

The control circuit controls the internal bank address signal int. BA0, int. A bank address decoder (not shown) for decoding BA1 and a control signal int. R
AS, int. CAS, int. It also includes a command decoder (not shown) that receives and decodes WE.

Semiconductor memory device 501 further includes row decoders provided corresponding to memory array banks 514 # 0 to 514 # 1, respectively, for decoding row address signal X supplied from address buffer 502, and these row decoders. According to the output signal of the decoder, the memory array bank 51
A word driver for driving the addressed row (word line) inside 4 # 0 to 514 # 1 to a selected state. In FIG. 10, the row decoder and the word driver are collectively shown as blocks 510 # 0 to 510 # 1.

Semiconductor memory device 501 further includes internal column address signal Y supplied from address buffer 502.
Column decoder 512 for decoding a column and generating a column selection signal
# 0-512 # 1 and memory array banks 514 # 0
Sense amplifiers 516 # 0-51 for detecting and amplifying the data of the memory cells connected to the selected row of 514 # 1
6 # 1 and.

Semiconductor memory device 501 further includes a write driver for amplifying write data and transmitting the amplified write data to the selected memory cell, and a preamplifier for amplifying data read from the selected memory cell.

Preamplifiers and write drivers are provided corresponding to the memory array banks 514 # 0 to 514 # 1. In FIG. 10, the preamplifier and the write driver are included in one block, and blocks 518 # 0 to 518 are included.
Shown as 18 # 1.

Semiconductor memory device 501 further includes a data input / output circuit 530 for inputting / outputting data between the outside and the memory array. Data input / output circuit 530 includes an input buffer 522 that receives write data from the outside to generate internal write data, and an output buffer 520 that further buffers the data from the preamplifier and outputs the data to the outside.

Semiconductor memory device 501 further includes a Vref generating circuit 524 for generating reference potential Vref.
The reference potential Vref is input to the input buffer 522 and serves as a threshold value reference when data is taken in.

The input buffer 522 receives the data DQ0 to DQ7 externally applied to the terminals as an external data fetch signal D.
Take it in according to QS. This external data acquisition signal D
QS is a signal that is output in synchronization with data by another semiconductor device or the like that outputs data to the semiconductor memory device 501, and is a signal that serves as a reference for the data capture time. The semiconductor memory device 501 receives an external data take-in signal DQS which is transmitted in parallel with data from the outside and is given to a terminal, and uses it as a data signal take-in reference.

The output buffer 520 is a semiconductor memory device 5.
When 01 outputs data to the outside, the data DQ0 to DQ7 are output in synchronization with the clock signal CLKQ, and the external data take-in signal DQS is given to the outside as a reference for taking in this data signal by another semiconductor device. Output.

[0015]

Although the data rate of the semiconductor memory device has been remarkably improved, the speed of the internal elements of the semiconductor memory device is not the same. Therefore, in the semiconductor memory device, a technique called prefetch is used to realize high-speed data transfer.

The prefetch is a process of reading a plurality of data in parallel from a plurality of memory elements by one activation of the memory array, thereby increasing the substantial bandwidth. Conventionally, in prefetching, the address of data that can be processed in one operation is only the associated address.

The mass of data (granularity) read from the memory array in parallel in one operation is then serially output at high speed to the external data bus, but these masses of data are output to the same device. I can only send.
This chunk of data becomes larger as the transfer rate of the data bus increases. However, the device that uses the transfer destination data does not always need a large chunk of data.

FIG. 11 is a block diagram showing a schematic configuration of a conventional memory system 550.

Referring to FIG. 11, memory system 550.
Is a semiconductor memory device 501 and a chipset 55 including a memory control circuit for controlling the operation of the semiconductor memory device 501.
2 and the semiconductor memory device 50 via the chip set 552.
1 and a CPU 554 for exchanging data with each other, and a video display circuit 556.

Chip set 552 and semiconductor memory device 50
It is connected to 1 by a bus 558. The chipset 552 and the CPU 554 are connected by the bus 560. Video display circuit 556 and chipset 552
Are connected to each other by a bus 562.

When a personal computer is taken as an example of the system, the bus 562 has an AGP (accelerated grd).
aphics port). AGP is an interface for video display circuits. AGP is a conventional P
It is a dedicated bus that is independent of the CI bus. By connecting the video display circuit and the main memory, a large amount of image data such as three-dimensional graphics can be transferred. By placing data such as textures on the main memory, high-quality 3D graphics can be displayed even if the video memory on the video board is small.

In a system using such a conventional semiconductor memory device 501, the semiconductor memory device 501 is replaced by a CPU.
A block of data to be serially read at high speed is transmitted to 554, and after the transfer is completed, a block of data is transmitted from semiconductor memory device 501 to video display circuit 556. Was there. That is, the semiconductor memory device 501 includes the CPU 554 and the video display circuit 55.
I was sending data for every 6 chunks alternately.

If the granularity becomes large, the data used at the transfer destination may become a part of the transferred block. In such a case, the use efficiency of the data bus is lowered, and the actual data transfer rate reaches the ceiling.

An object of the present invention is to provide a semiconductor memory device and a memory system capable of reducing the amount of data smaller than before and improving the usage efficiency of the data bus.

[0025]

According to another aspect of the present invention, there is provided a semiconductor memory device, wherein data is transferred between a first memory area corresponding to a first address given from the outside and a first memory area. A first data bus to be performed, a second memory area corresponding to a second address given from the outside, a second data bus to transfer data between the second memory area, and an internal clock signal. Accordingly, the first and second data buses are alternately switched and selected, and the selected first and second data buses are selected.
And a data switching circuit for performing data communication between any one of the data buses and the external data bus.

According to a second aspect of the semiconductor memory device, in addition to the configuration of the semiconductor memory device according to the first aspect, an address for taking in externally applied first and second addresses in accordance with an internal clock signal. The input circuit, the first address bus for transmitting the first address, and the first address from the first address bus are received, the first address is decoded, and a part of the first memory area is selected. A first address decoding circuit for transmitting a second address and a second address for transmitting a second address.
Receives the second address from the second address bus and the second address bus, decodes the second address,
And a second address decoding circuit for selecting a part of the second memory area.

According to a third aspect of the present invention, in addition to the configuration of the semiconductor memory device according to the second aspect, each of the first and second memory areas has a plurality of memories arranged in a matrix. A first address decode circuit including a cell, the first address decode circuit selecting a row corresponding to the first address;
The second address decoding circuit includes a row decoding circuit that selects a row corresponding to the second address and a column decoding circuit that selects a column corresponding to the second address. And a column decode circuit for selection.

According to a fourth aspect of the present invention, in addition to the configuration of the semiconductor memory device according to the first aspect, in the data switching circuit, the internal clock signal changes from the first logical value to the second logical value. The data on the first data bus is output in response to the transitioning first polarity edge, and the first clock signal is output in response to the second polarity edge in which the internal clock signal transitions from the second logic value to the first logic value. A data transfer unit for outputting data on the data bus, and an output buffer circuit receiving an output from the data transfer unit.

According to a fifth aspect of the semiconductor memory device of the present invention, in addition to the configuration of the semiconductor memory device according to the fourth aspect, the data transfer unit is connected between the output node and the first data bus, It has a first field effect transistor receiving a clock signal at its gate, and a second field effect transistor connected between the output node and the second data bus and receiving at its gate an inverted signal of the internal clock signal.

According to a sixth aspect of the semiconductor memory device, in addition to the configuration of the semiconductor memory device according to the first aspect, the data switching circuit changes the internal clock signal from the first logical value to the second logical value. The externally applied data is output to the first data bus in response to the transitioning first polarity edge, and the internal clock signal changes to the second polarity edge from the second logic value to the first logic value. A data input circuit for outputting data externally applied to the second data bus in response thereto is included.

According to a seventh aspect of the present invention, in addition to the configuration of the semiconductor memory device according to the sixth aspect, the data input circuit has an input node for receiving externally applied data, an input node, and a first node. Connected to the first data field bus and to the gate for receiving the internal clock signal, and between the input node and the second data bus for receiving the inverted clock signal of the internal clock signal. A second field effect transistor.

A memory system according to an eighth aspect is a memory system having an external data bus for transmitting data at a data rate twice the clock frequency, the semiconductor system including a semiconductor memory device, wherein the semiconductor memory device is the first memory device. First memory area corresponding to the first address, the first internal data bus for transferring data between the first memory area, the second memory area corresponding to the second address, and the second memory area corresponding to the second address. The second internal data bus for transferring data to and from the memory area and the first and second internal data buses are alternately switched and selected according to the internal clock signal, and the selected first and second internal data buses are selected. A data switching circuit for performing data communication between either one of the data buses and the external data bus is included, and data transmitted in odd number and data transmitted in even number in the external data bus. First respectively separates the motor, the second
A memory control circuit for outputting the separated data of the
And a first circuit and a second circuit which receive and operate respectively.

According to a ninth aspect of the present invention, in addition to the configuration of the memory system according to the eighth aspect, the external data bus transmits a data strobe signal that provides a timing reference for taking in the data together with the data. The control circuit separates the data transmitted on the external data bus into first and second separated data according to the data strobe signal.

According to a tenth aspect of the present invention, in addition to the configuration of the memory system according to the eighth aspect, the semiconductor memory device further includes a control unit for generating an internal clock signal according to an external clock signal. The memory control circuit
The data transmitted on the external data bus is separated into first and second separated data according to the external clock signal.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same reference numerals in the drawings indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is a schematic block diagram showing a structure of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 1, semiconductor memory device 1 includes memory arrays 14 # 0-14 # 1 each having a plurality of memory cells arranged in rows and columns, and externally applied address signals A0-An. And the bank address signal BA in synchronization with the internal clock signal to fetch the internal row address,
An address buffer 2 which outputs an internal column address and an internal bank address, a clock buffer 4 which receives a clock signal CLK and a clock enable signal CKE from the outside and outputs an internal clock signal used inside the semiconductor device, and a control provided from the outside. Signal / CS, / R
Control signal input buffer 6 for taking in AS, / CAS, / WE and mask signal DQM in synchronization with the internal clock signal
Including and

The semiconductor memory device 1 further receives the internal address signal from the address buffer 2 and receives from the control signal input buffer 6 a control signal int. RAS, int. CAS, int. The control circuit includes a control circuit that receives WE and outputs a control signal to each block in synchronization with the clock signal CLKI, and a mode register that holds the operation mode recognized by the control circuit. In FIG. 1, the control circuit and the mode register are shown as one block 8.

The control circuit controls the internal bank address signal int. BA0, int. A bank address decoder (not shown) for decoding BA1 and a control signal int. R
AS, int. CAS, int. It also includes a command decoder (not shown) that receives and decodes WE.

The semiconductor memory device 1 is further provided corresponding to each of the memory arrays 14 # 0 to 14 # 1 and decodes a row address signal X supplied from the address buffer 2, and row decoders for these row decoders. And a word driver for driving an addressed row (word line) inside memory arrays 14 # 0 to 14 # 1 to a selected state in accordance with the output signal of FIG. In FIG. 1, the row decoder and the word driver are combined into blocks 10 # 0 to 10 #.
Shown as 1.

Semiconductor memory device 1 further includes column decoders 12 # 0-12 that decode internal column address signal Y supplied from address buffer 2 to generate a column selection signal.
# 1 and sense amplifiers 16 # 0 to 16 # 1 for detecting and amplifying the data of the memory cells connected to the selected row of the memory arrays 14 # 0 to 14 # 1.

Semiconductor memory device 1 further includes a write driver for amplifying write data and transmitting it to the selected memory cell, and a preamplifier for amplifying data read from the selected memory cell.

Preamplifiers and write drivers are provided corresponding to the memory arrays 14 # 0-14 # 1. In FIG. 1, the preamplifier and the write driver are shown as blocks 18 # 0 to 18 # 1 as one block.

Semiconductor memory device 1 further includes a data input / output circuit 30 for inputting / outputting data between the outside and the memory array. The data input / output circuit 30 receives an external write data and generates an internal write data.
2 and an output buffer 20 for further buffering the data from the preamplifier and outputting it to the outside.

The semiconductor memory device 1 further includes a reference potential V
A Vref generation circuit 24 for generating ref is included. The reference potential Vref is input to the input buffer 22 and serves as a threshold reference when data is taken in.

The input buffer 22 receives the data DQ0 to DQ7 externally applied to the terminals from the external data fetch signal DQ.
Take in according to S. This external data acquisition signal DQ
S is a signal that another semiconductor device or the like that outputs data to the semiconductor memory device 1 outputs in synchronization with the data, and is a signal that serves as a reference for the data acquisition time. The semiconductor memory device 1 receives an external data take-in signal DQS which is transmitted in parallel with data from the outside and is applied to a terminal, and uses it as a reference for taking in a data signal.

Output buffer 20 receives clock signal CLK when semiconductor memory device 1 outputs data to the outside.
The data DQ0 to DQ7 are output in synchronization with Q, and an external data capture signal DQS is output to the outside as a reference for capturing this data signal by another semiconductor device.

FIG. 2 is a circuit diagram showing the configurations of output buffer 20 and multiplexer 21 in FIG.

Referring to FIG. 2, multiplexer 21 includes multiplexers 21 # 0 to 21 # 7 corresponding to terminals to which data DQ0 to DQ7 are output, respectively, and multiplexer 21 corresponds to a terminal to output data strobe signal DQS. Further includes multiplexer 21 # 8.

Multiplexer 21 # 0 is connected between data bus IBA # 0 connected to memory array 14 # 0, which is the first memory area in FIG. 1, and node N1, and receives clock signal ICLK at its gate. N channel M
OS transistor 46 and claim clock signal ICL
An N-channel which is connected between an inverter 42 which receives K and inverts it, and a node N1 which is connected between a data bus IBB # 0 connected to a memory array 14 # 1 which is a second memory area and a node N1. And a MOS transistor 44.

Multiplexers 21 # 1 to 21 # 7 have a structure similar to that of multiplexer 21 # 0 and description thereof will not be repeated. Since the data bus of the corresponding bit is connected to the data bus, for example, the multiplexer 2
If 1 # 7, N-channel MOS transistor 46 is connected to data bus IBA # 7, and MOS transistor 44 is connected to data bus IBB # 7.

The multiplexer 21 # 8 provided corresponding to the data strobe signal DQS is also the multiplexer 2
It has the same structure as 1 # 0, and the description thereof will not be repeated. Regarding the strobe signal, since H data and L data are alternately output, a power supply node is connected instead of data bus IBB # 0 in the configuration of multiplexer 21 # 0, and a ground node is used instead of data bus IBA # 0. Are connected.

The output buffer 20 includes a multiplexer 21.
Output buffers 20 # 0-2 provided between # 0-21 # 7 and terminals for outputting data DQ0-DQ7, respectively.
0 # 7, and further includes an output buffer 20 # 8 provided between multiplexer 21 # 8 and a terminal outputting strobe signal DQS.

Output buffer 20 # 0 includes an inverter 48 having an input connected to node N1 and an output connected to node N2, and an inverter 50 having an input connected to node N2 and an output interconnected to node N1. Is connected to the node N2 and the other input is connected to the output enable signal OE.
NAND circuit 54 for receiving the output and the output enable signal OE
An inverter 52 that receives and inverts it; a NOR circuit 56 that has one input connected to the node N2 and the other input that receives the output of the inverter 52; and a NAND circuit 54 connected between the power supply node and the node N3 and having a gate P channel MOS transistor 58 receiving an output, and N channel MOS transistor 60 connected between node N3 and the ground node and receiving the output of NOR circuit 56 at the gate are included.

A terminal for outputting the data DQ0 is connected to the node N3. Output buffers 20 # 1-20 #
8 has a structure similar to that of output buffer 20 # 0, and description thereof will not be repeated. Output buffer 20 # 8 is supplied with output enable signal OES instead of output enable signal OE.

FIG. 3 shows the address buffer 2 in FIG.
3 is a circuit diagram showing the configuration of FIG. Referring to FIG. 3, address buffer 2 includes address input circuit 2 # 0 provided corresponding to address bit A0 and address bits A1 to A1.
Address input circuit 2 provided corresponding to each An
# 1 to 2 # n are included.

Address input circuit 2 # 0 includes an inverter 72 which receives and inverts clock signal ICLK, and node N.
4 and an address bus ABA # 0 for transmitting an address to the first memory area, and an N channel MOS transistor 74 receiving a clock signal ICLK at its gate, and a node N4 and a second memory area. An N channel MOS transistor 74 connected to an address bus ABB # 0 for transmitting an address signal and having a gate receiving an output of inverter 72 is included.

Address input circuits 2 # 1 to 2 # n have the same structure as address input circuit 2 # 0, and description thereof will not be repeated.

FIG. 4 is a circuit diagram showing the configuration of input buffer 22 in FIG. Referring to FIG. 4, input buffer 22 includes data input circuits 22 # 0 to 22 # 7 provided corresponding to data bits DQ0 to DQ7, respectively.

Data input circuit 22 # 0 includes an inverter 82 which receives and inverts strobe signal DQS, an input node N5 connected to a terminal, and a data bus IDBA # 0 which transfers the input data to the first memory area. N-channel MO connected between and receiving strobe signal DQS at its gate
S-transistor 84 and an N-channel MOS transistor 86 connected between node N5 and data bus IDBB # 0 transmitting input data to the second memory region and receiving the output of inverter 82 at the gate are included.

Data input circuits 22 # 1 to 22 # 7 have the same structure as data input circuit 22 # 0, and description thereof will not be repeated.

FIG. 5 is a diagram conceptually illustrating a read operation of semiconductor memory device 1 shown in FIG.

Referring to FIG. 5, semiconductor memory device 1 having received the read command reads data from memory arrays 14 # 0 and 14 # 1 which are two different data areas and transmits the data to the multiplexer. The data are alternately arranged according to the rising edge and the falling edge of the clock. The combined data string is output from the output circuit 20a to the outside in synchronization with the internal clock. The data strobe signal is output from the output circuit 2 in synchronization with the output data.
It is output from 0b. It is possible to recognize from which area the data originated by the data strobe signal.

FIG. 6 is an operation waveform diagram showing the operation described with reference to FIG. Referring to FIG. 6, at time t1 to t2, address ADR0 which is the address of the first memory area.
Is given as an address signal. Address AD which is the address of the second memory area at time t2 to t3
R1 is given externally. Further, in parallel with the address, a read command is externally given at times t1 to t3.

From time t4 to t12, data is output according to the read command. 8 output in series
The data DATA0, which is the data from the first memory area, is output to the odd-numbered one of the data.
The data DATA1 output from the second memory area is output at an even number.

A data strobe signal is also output together with the output of data. From time t4 to t5, the data strobe signal DQS is at H level. Therefore, it is understood that the data output by this is the data output from the first memory area.

Subsequently, the data strobe signal DQS is at L level from time t5 to time t6. Therefore, it can be recognized that the data at this time is output from the second memory area.

As described above, since the size of the mass of data transmission is half that of the conventional one, the transmission efficiency of the bus is substantially improved.

FIG. 7 is a diagram for conceptually explaining the operation of semiconductor memory device 1 at the time of writing data.

Referring to FIG. 7, the semiconductor memory device 1 receiving the write command receives the data DQ input to the input circuit 22a by using the rising edge and the falling edge of the data strobe signal DQS. Divide into 2 memory areas. That is, the memory area corresponding to the rise of the data strobe signal corresponds to memory array 14 # 0 which is the first memory area. The memory area corresponding to the fall of the data strobe signal is the second memory area and corresponds to memory array 14 # 1.

The distributed data independently propagates through the internal data bus lines toward the respective memory areas, the data is sent to the respective memory areas, and the data is written in the respective memory areas.

As described above, in the semiconductor memory device of the first embodiment, the first memory area indicating the first memory area is used.
Data and the second address indicating the second memory area are alternately read and written, the amount of data to be transmitted is halved, and the transmission efficiency of the bus is substantially improved. It becomes possible.

[Second Embodiment] FIG. 8 is a block diagram showing a structure of a memory system 150 according to a second embodiment.

Referring to FIG. 8, memory system 150
Is a semiconductor memory device 1 described in the first embodiment, a chip set 152 including a memory control circuit for controlling data transfer of the semiconductor memory device 1, and a chip set 1.
C for exchanging data with the semiconductor memory device 1 via 52
It includes a PU 154 and a video display circuit 156. The chip set 152 and the semiconductor memory device 1 are connected by a bus 158. The chip set 152 and the CPU 154 are connected by a bus 160. The video display circuit 156 and the chip set 152 are connected by a bus 162.

FIG. 9 shows the memory system 15 shown in FIG.
FIG. 7 is an operation waveform diagram for explaining a 0 read operation.

Referring to FIG. 9, an address ADR0 indicating a data address to be transmitted to CPU 154 is applied to semiconductor memory device 1 at times t1 to t2, and subsequently output to video display circuit 156 at times t2 to t3. An address ADR1 indicating a data address is given to the semiconductor memory device 1.

The chip set 152 also outputs a read command at times t1 to t3 in parallel with the output of the address.

In response to this, the semiconductor memory device 1 operates at time t.
From 4 to t12, data DATA0 and DATA1 from the first memory area and the second memory area, respectively.
Are read and output alternately. In parallel with this, the semiconductor memory device 1 also outputs a data strobe signal DQS to the chip set 152 to indicate from which memory area the data is coming from.

In response to this, the chip set 152 distributes and outputs the first data of the data DATA0 to the bus 160 in response to the rise of the strobe signal DQS.

Then, at time t5, the strobe signal D
The chip set 152 outputs the second data to the bus 162 in response to the fall of QS. After that, the chip set 152 alternately distributes the data according to the strobe signal and alternately outputs the data to the bus 160 and the bus 162.

Memory system 150 is bus 16 in the case of a personal computer system or the like.
2 to AGP (1 of interface for video display circuit
It is possible to improve the efficiency of the data bus substantially.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0083]

In the semiconductor memory device according to the first to third aspects, since the amount of data to be transmitted at one time is made substantially small, the use efficiency of the external bus can be improved.

According to another aspect of the semiconductor memory device of the present invention,
In addition to the effect of the semiconductor memory device according to the first aspect, it is possible to improve the practical use efficiency of the external bus when outputting data.

According to the sixth aspect of the semiconductor memory device of the present invention,
In addition to the effect of the semiconductor memory device according to the first aspect, it is possible to improve the practical use efficiency of the external bus when inputting data.

The memory system according to claims 8 to 10 can improve the practical use efficiency of the double data rate data bus.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

2 is a circuit diagram showing a configuration of an output buffer 20 and a multiplexer 21 in FIG.

3 is a circuit diagram showing a configuration of an address buffer 2 in FIG.

4 is a circuit diagram showing a configuration of an input buffer 22 in FIG.

5 is a diagram conceptually illustrating a read operation of semiconductor memory device 1 shown in FIG. 1. FIG.

FIG. 6 is an operation waveform diagram showing the operation described in FIG.

FIG. 7 is a diagram conceptually illustrating an operation of semiconductor memory device 1 at the time of writing data.

FIG. 8 is a block diagram showing a configuration of a memory system 150 according to the second embodiment.

9 is an operation waveform diagram for explaining a read operation of memory system 150 shown in FIG.

FIG. 10 is a block diagram showing a schematic configuration of a conventional semiconductor memory device 501.

FIG. 11 is a block diagram showing a schematic configuration of a conventional memory system 550.

[Explanation of symbols]

1 semiconductor memory device, 2 address buffers, 2 # 0
2 # n address input circuit, 4 clock buffer, 6
Control signal input buffer, 8, 10, 18 blocks,
12 column decoder, 14 memory array, 16 sense amplifier, 20 output buffer, 20a, 20b output circuit, 21 multiplexer, 22 # 0 to 22 # 7 data input circuit, 22 input buffer, 22a input circuit,
24 generation circuit, 30 data input / output circuit, 42, 4
8, 50, 52, 72, 82 Inverter, 44, 4
6, 58, 60, 74, 84, 86 transistors, 5
4 NAND circuits, 56 NOR circuits, 150 memory systems, 152 chipsets, 156 video display circuits, 158, 160, 162 buses.

Continued front page    F-term (reference) 5B060 CA12                 5M024 AA50 AA90 BB03 BB04 BB07                       BB17 BB30 BB33 BB34 DD03                       DD09 DD32 DD42 DD45 DD59                       DD73 DD80 DD83 HH01 JJ03                       JJ20 JJ32 KK24 LL01 PP01                       PP02 PP03 PP07

Claims (10)

[Claims] 1. A first memory area corresponding to a first address provided from the outside, and a first memory area for transferring data between the first memory area and the first memory area.
Second data area between the second data area, the second memory area corresponding to the second address given from the outside, and the second memory area.
Data bus and the first and second data buses are alternately switched and selected according to an internal clock signal, and one of the selected first and second data buses is connected to the external data bus. And a data switching circuit for performing data communication in the semiconductor memory device. 2. An address input circuit for taking in the first and second addresses given from the outside according to the internal clock signal, a first address bus for transmitting the first address, and the first address bus. A first address decoding circuit for receiving the first address from the address bus, decoding the first address, and selecting a part of the first memory area; and transmitting the second address. A second address bus and a second address decoding circuit that receives the second address from the second address bus, decodes the second address, and selects a part of the second memory area The semiconductor memory device according to claim 1, further comprising: 3. Each of the first and second memory regions includes a plurality of memory cells arranged in a matrix, and the first address decoding circuit includes the row corresponding to the first address. A row decode circuit for selecting the row, and a column decode circuit for selecting the column corresponding to the first address, wherein the second address decode circuit includes a row decode circuit for selecting the row corresponding to the second address. The semiconductor memory device according to claim 2, further comprising a circuit and a column decode circuit that selects the column corresponding to the second address. 4. The data switching circuit outputs data on the first data bus in response to an edge of a first polarity at which the internal clock signal transits from a first logical value to a second logical value. A data transfer unit for outputting data on the first data bus in response to an edge of the second polarity at which the internal clock signal transits from the second logical value to the first logical value; The semiconductor memory device according to claim 1, further comprising an output buffer circuit that receives an output of the unit. 5. The data transfer unit is connected between an output node and the first data bus,
A first field effect transistor having a gate receiving the internal clock signal, and a second field effect transistor connected between the output node and the second data bus and having a gate receiving an inverted signal of the internal clock signal. The semiconductor memory device according to claim 4, further comprising: 6. The data switching circuit outputs data given from the outside in response to an edge of a first polarity at which the internal clock signal transits from a first logical value to a second logical value. The internal clock signal is output to the bus, and externally applied data is output to the second data bus in response to an edge of the second polarity at which the internal clock signal transits from the second logical value to the first logical value. The semiconductor memory device according to claim 1, further comprising a data input circuit. 7. The data input circuit is connected between an input node for receiving externally applied data and the first data bus, and has a first electric field for receiving the internal clock signal at its gate. 7. The semiconductor memory according to claim 6, further comprising: an effect transistor, and a second field effect transistor connected between the input node and the second data bus and having a gate receiving an inverted signal of the internal clock signal. apparatus. 8. A memory system having an external data bus for transmitting data at a data rate twice as high as a clock frequency, comprising a semiconductor memory device, wherein the semiconductor memory device has a first address corresponding to a first address. Data transfer between the first memory area and the first memory area
Second internal data bus, a second memory area corresponding to a second address, and a second memory area for transferring data between the second memory area and the second memory area.
Internal data bus and the first and second internal data buses are alternately switched according to an internal clock signal to select one of the selected first and second internal data buses and the external data. A data switching circuit that performs data communication with the bus, and separates the odd-numbered transmitted data and the even-numbered transmitted data in the external data bus into first and second separated data, respectively. The memory system further comprising: a memory control circuit that outputs the first and second separated data; and first and second circuits that operate by receiving the first and second separated data, respectively. 9. The external data bus transmits a data strobe signal that provides a timing reference for taking in the data together with the data, and the memory control circuit transmits the data transmitted on the external data bus to the data strobe. 9. The memory system according to claim 8, wherein the first and second separated data are separated according to a signal. 10. The semiconductor memory device further includes a control unit that generates the internal clock signal in response to an external clock signal, and the memory control circuit outputs data transmitted on the external data bus to the external clock signal. According to the signal, the first,
The memory system according to claim 8, wherein the memory system is separated into second separated data.