JP2003005708A - Display device and driving method of the device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a display device using a time gradation system when a multiple gradation display is not required. SOLUTION: In a second display mode in which the number of gradation levels is reduced compared with a first display mode of multiple gradations, writing of digital video signals of low-order bits to a memory is not conducted by a memory controller of a signal control circuit of the display device. Moreover, reading of the digital video signals of low-order bits from the memory is eliminated. Furthermore, the amount of information of digital video signals to be inputted into a source signal line driving circuit is reduced. Along with the above operations, a display controller reduces the frequencies of start and clock pulses to be inputted into driving circuits and sets the writing intervals of the subframe intervals, in which displaying is conducted, and the display intervals longer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying an image by inputting a digital video signal. In particular, the present invention relates to a display device having a light emitting element. Further, the invention relates to an electronic device using the display device.

[0002]

2. Description of the Related Art A display device for displaying an image by arranging light emitting elements for each pixel and controlling light emission of these light emitting elements will be described below.

In this specification, the light emitting element is described as an element (OLED element) having a structure in which an organic compound layer which emits light when an electric field is generated is sandwiched between an anode and a cathode. Not limited. An element that emits light by applying an electric field between the anode and the cathode can be freely used.

The light emitting device utilizes light emission (fluorescence) when transitioning from singlet excitons to the ground state,
Luminescence during transition from triplet excitons to the ground state (phosphorescence)
The description will be given assuming that both of them utilize.

Examples of the organic compound layer include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer and an electron injection layer. The light-emitting element is basically shown as a structure in which the anode / light-emitting layer / cathode are stacked in this order, but in addition to this, a structure in which the anode / hole injection layer / light-emitting layer / electron injection layer / cathode are stacked in this order, There is a structure in which an anode / hole injection layer / hole transport layer / light emitting layer / electron transport layer / electron injection layer / cathode are stacked in this order.

The organic compound layer is not limited to the one having a layered structure in which the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, the electron injection layer, etc. are clearly distinguished. That is, the organic compound layer may have a structure having a layer in which materials constituting the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, the electron injection layer and the like are mixed.

Inorganic substances may be mixed.

The organic compound layer of the OLED element may be any of low molecular weight material, high molecular weight material and medium molecular weight material.

In the present specification, the medium-molecular material means that the number of molecules is 20 or less or the length of chained molecules is 10 or less.
It is not more than μm and has no sublimation property.

The display device comprises a display and peripheral circuits for inputting signals to the display.

The structure of the display will be described.

The display is composed of a source signal line drive circuit, a gate signal line drive circuit, and a pixel section. The pixel portion has a structure in which pixels are arranged in a matrix.

A thin film transistor (hereinafter referred to as a TFT) is arranged in each pixel of the pixel portion. here,
A method of arranging two TFTs for each pixel and controlling the light emission of the light emitting element of each pixel will be described.

FIG. 7 shows the structure of the pixel portion of the display device.

In the pixel section 700, source signal lines S1 to S are provided.
x, gate signal lines G1 to Gy, and power supply lines V1 to Vx are arranged, and pixels of x (x is a natural number) column y (y is a natural number) rows are arranged. Each pixel 800 includes a switching TFT 801, a driving TFT 802, and a storage capacitor 80.
3 and a light emitting element 804.

FIG. 8 is an enlarged view of one pixel in the pixel section shown in FIG.

The pixel includes one of the source signal lines S1 to Sx and one of the gate signal lines G1 to Gy.
One of the power supply lines V1 to Vx, a switching TFT 801, a driving TFT 802, and a storage capacitor 8
03 and a light emitting element 804.

The gate electrode of the switching TFT 801 is connected to the gate signal line G, and the switching TFT
One of the source region and the drain region of 801 is connected to the source signal line S, and the other is connected to the gate electrode of the driving TFT 802 or one electrode of the storage capacitor 803. One of the source region and the drain region of the driving TFT 802 is connected to the power supply line V, and the other is connected to the anode or the cathode of the light emitting element 804. Of the two electrodes of the storage capacitor 803, the driving TF
The side not connected to T802 and the switching TFT 801 is connected to the power supply line V.

In this specification, the driving TFT 80 is used.
The second source region or drain region is the light emitting element 80.
4 is connected to the anode, the anode of the light emitting element 804 is called a pixel electrode and the cathode is called a counter electrode. On the other hand, the source region or the drain region of the driving TFT 802 is
When connected to the cathode of the light emitting element 804, the cathode of the light emitting element 804 is called a pixel electrode and the anode is called a counter electrode.

The potential applied to the power supply line V is called the power supply potential, and the potential applied to the counter electrode is called the counter potential.

Switching TFT 801 and driving T
The FT802 is a p-channel TFT or an n-channel T
Although it may be an FT, when the pixel electrode of the light emitting element 804 is an anode, the driving TFT 802 is preferably a p-channel TFT, and the switching TFT 801 is preferably an n-channel TFT. On the other hand, when the pixel electrode is the cathode,
The driving TFT 802 is preferably an n-channel TFT, and the switching TFT 801 is a p-channel TF.
T is desirable.

The storage capacitor 803 does not necessarily have to be provided.

For example, when the n-channel TFT used as the driving TFT 802 has an LDD region provided so as to overlap the gate electrode through the gate insulating film, the gate is generally provided in this overlapping region. Although a parasitic capacitance called a capacitance is formed, this parasitic capacitance can be positively used as a storage capacitance for holding the voltage applied to the gate electrode of the driving TFT 802.

The operation of displaying an image in the pixel having the above structure will be described below.

When a signal is input to the gate signal line G, the potential of the gate electrode of the switching TFT 801 changes,
The gate voltage changes. A signal is input from the source signal line S to the gate electrode of the driving TFT 802 through the source / drain of the switching TFT 801 which has become conductive. In addition, the signal is held in the storage capacitor 803. The gate voltage of the driving TFT 802 is changed by the signal input to the gate electrode of the driving TFT 802, and the source and drain are brought into conduction. The potential of the power supply line V is applied to the pixel electrode of the light emitting element 804 through the driving TFT 802. Thus, the light emitting element 804 emits light.

A method of expressing gradation in a pixel having such a configuration will be described.

The method of expressing gradation can be broadly divided into an analog method and a digital method. Compared with the analog method, the digital method has advantages such as suitable for multi-gradation.

Here, attention is paid to a digital gradation expression method.

As a digital gradation expression method, there is a time gradation method.

The driving method of the time gray scale method will be described in detail below.

This driving method is a method of expressing gradation by controlling the period during which each pixel of the display device emits light.

When the period for displaying one image is one frame period, one frame period is divided into a plurality of subframe periods.

Light is turned on or off for each sub-frame period, that is, the light emitting element of each pixel is turned on or off, and the period during which the light emitting element emits light is controlled per frame period to control each pixel. The gradation is expressed.

This time gradation driving method will be described in detail with reference to the timing chart of FIG.

Note that FIG. 5A shows an example in which gradation is expressed using a 4-bit digital video signal.

For the configuration of the pixel and the pixel portion, refer to those shown in FIGS. 7 and 8.

Here, the opposite potential is between the potential of the power supply lines V1 to Vx (power potential) or the potential of the power supply lines V1 to Vx by an external power source (not shown). , The light emitting element 804 can be switched to have a potential difference such that the light emitting element 804 emits light.

One frame period F is divided into a plurality of subframe periods SF1 to SF4.

In the first sub-frame period SF1,
First, the gate signal line G1 is selected, and the gate signal line G1 is selected.
Switching TFT 80 in which the gate electrode is connected to 1
1 in each of the pixels having the source signal lines S1 to S1.
A digital video signal is input from Sx. By the input digital video signal, the driving TFT 8 of each pixel is
02 is turned on or off.

In this specification, the state in which the TFT is turned on means that the source and drain are in a conductive state due to the gate voltage thereof. Further, the state in which the TFT is off means that the source and the drain are in a non-conductive state due to the gate voltage thereof.

At this time, the opposing potential of the light emitting element 804 is
Since the potentials (power source potentials) of the power supply lines V1 to Vx are set to be substantially equal to each other, the light emitting element 804 does not emit light even in a pixel in which the driving TFT 802 is turned on.

Here, FIG. 5B shows the driving T of each pixel.
6 is a timing chart showing the operation of inputting a digital video signal to the FT 802.

In FIG. 5B, the period during which the signal corresponding to each source signal line is sampled by the source signal line drive circuit (not shown) is shown by S1 to Sx. The sampled signal is simultaneously output to all the source signal lines during the blanking period in the figure. The signal thus output is
In the pixel where the gate selection line is selected, the driving TFT 8
No. 02 gate electrode.

The above operation is repeated for all the gate signal lines G1 to Gy, and the writing period Ta1 ends.

The writing period of the first sub-frame period SF1 is called Ta1. Generally the jth (j is a natural number)
The writing period of the sub-frame period SFj will be referred to as Taj.

When the writing period Ta1 ends, the counter potential changes so as to have a potential difference with the power supply potential to the extent that the light emitting element 804 emits light. Thus, the display period Ts
1 starts.

The display period of the first sub-frame period SF1 is called Ts1. Generally, the display period of the j-th (j is a natural number) sub-frame period SFj is called Tsj.

In the display period Ts1, the light emitting element 804 of each pixel is in a light emitting or non-light emitting state according to the input signal.

As shown in FIG. 5A, the above operation is repeated for all subframe periods SF1 to SF4, and 1
The frame period F1 ends.

Here, sub-frame periods SF1 to SF4
By appropriately setting the lengths of the display periods Ts1 to Ts4, the gradation is expressed by the total of the display periods of the sub-frame periods in which the light emitting element 804 emits light per one frame period F.
That is, the gradation is expressed by the sum of the lighting times in one frame period.

Generally, a method of inputting an n-bit digital video signal and expressing 2 ⁿ gradations will be described.

At this time, for example, one frame period is divided into n subframe periods SF1 to SFn, and the ratio of the lengths of the display periods Ts1 to Tsn of each subframe period SF1 to SFn is Ts1: Ts2 :. ..: Tsn-1: T
^{sn = 2 0: 2- 1:} ···: 2- n + 2: set to be 2- ^{n + 1.} Note that the writing periods Ta1 to Tan have the same length.

In the light emitting element 804 during one frame period, the sum of the display periods Ts in which the light emitting state is selected is calculated to determine the gradation of the pixel in that frame period. For example, when n = 8, assuming that the luminance when the pixel emits light in the entire display period is 100%, Ts8
When Ts7 and Ts7 emit light, a luminance of 1% can be expressed, and when Ts6, Ts4, and Ts1 are selected, a luminance of 60% can be expressed.

A circuit for inputting a signal for performing the above-described time gray scale driving method to the source signal line driver circuit and the gate signal line driver circuit of the display will be described with reference to FIG.

In this specification, a signal input to the display device is called a digital video signal. It should be noted that here, a display device for displaying an image by inputting an n-bit digital video signal will be described as an example.

The display device has a source signal line drive circuit 110.
7, the gate signal line driving circuit 1108, and the pixel portion 110
9, a display 1100, a signal control circuit 1101, and a display controller 110.
2 and.

A digital video signal is read into the signal control circuit 1101, and the signal control circuit 1101 outputs a digital video signal (VD) to the display 1100.

In the present specification, the signal control circuit edits the digital video signal, and the display 11
A signal converted into a signal input to 00 is called a digital video signal.

The signals for driving the source signal line drive circuit 1107 and the gate signal line drive circuit 1108 of the display 1100 are the display controller 110.
Is entered by 2.

The configurations of the signal control circuit 1101 and the display controller 1102 will be described.

The source signal line drive circuit 1107 of the display 1100 is composed of shift registers 1110, LA.
It is composed of T (A) 1111 and LAT (B) 1112. In addition, although not shown, a level shifter, a buffer, or the like may be provided.

The signal control circuit 1101 includes the CPU 110.
4, a memory A 1105, a memory B 1116, and a memory controller 1103.

The digital video signal input to the signal control circuit 1101 is sent to the memory A11 via the CPU 1104.
It is input to 05.

That is, in the digital video signal, the digital signal of each bit for each pixel is the memory A11.
05 is input and stored.

Here, the memory A 1105 has a capacity capable of storing n-bit digital signals for all pixels of the pixel portion 1109 of the display 1100.

When a digital signal for one frame period is stored in the memory A 1105, the memory controller 110
The digital signal of each bit is sequentially read by 3, and is input to the source signal line drive circuit as the digital video signal VD.

When the reading of the signal stored in the memory A1105 is started, this time, the CPU 1 is stored in the memory B1106.
A digital video signal corresponding to the next frame period is input via 104 and starts to be stored. Memory B110
Similarly to the memory A1105, it is assumed that 6 has a capacity capable of storing n-bit digital signals for all pixels of the display device.

As described above, the signal control circuit 1101 is capable of storing the n-bit digital signal for each one frame period and the memory A1105 and the memory B.
1106, and this memory A1105 and memory B11
Alternately and 06 are used to sample the digital video signal.

Although the signal control circuit 1101 which stores the signal by alternately using the two memories A1105 and B1106 has been shown here, in general, it has a memory capable of storing a plurality of frames of information, These memories can be used alternately.

Memory A1105 of signal control circuit 1101
The configuration of the memory controller 1103 that controls input of a digital video signal and reading of a signal from each memory in the memory B 1106 will be described with reference to FIG. 11.

In FIG. 11, the memory controller 11
03 is a memory read / write control (hereinafter, memory R
/ W) circuit 1202, reference oscillation circuit 1203, variable frequency divider circuit 1204, x counter 1205a, y counter 1205b, x decoder 1206a and y decoder 1
It is composed of 206b.

Hereinafter, both the memories A and B included in the above-mentioned signal control circuit will be collectively referred to as a memory. Further, the memory is composed of a plurality of storage elements, and those storage elements are selected by the address (x, y).

The signal from the CPU 1104 is input to the reference oscillation circuit 1203. The signal from the reference oscillation circuit 1203 is input to the variable frequency dividing circuit 1204 and converted into a signal having an appropriate frequency. The signal from the variable frequency dividing circuit 1204 is the x counter 1205a and the x decoder 1206a.
Select the x-address of the memory via. Similarly, the signal from the variable frequency dividing circuit 1204 is the y counter 1205b.
And y decoder 1206b to select a memory y address. Thus, the memory address (x, y) is selected. A signal from the CPU 1104 is input to the memory R / W circuit 1202, and a memory R / W signal for selecting an operation of writing a signal in the memory or an operation of reading a signal from the memory is output.

Thus, memory x address and memory y
The address selects the address of the memory when writing or reading the digital signal, and the memory R / W signal performs the writing or reading operation of the digital signal in the storage element selected by the address.

Next, the structure of the display controller 1102 in FIG. 10 will be described below.

The display controller 1102 outputs signals such as start pulses (S_SP, G_SP) and clock pulses (S_CLK, G_CLK) to the source signal line drive circuit 1107 and the gate signal line drive circuit 1108.

The structure of the display controller 1102 will be described with reference to FIG.

The display controller 1102 includes a reference clock generation circuit 1301 and a horizontal clock generation circuit 1.
303, a vertical clock generation circuit 1304, and a light emitting element power supply control circuit 1305.

The clock signal 31 input from the CPU 1104 is input to the reference clock generation circuit 1301.
Generate a reference clock. This reference clock is used as a horizontal clock generation circuit 1303 and a vertical clock generation circuit 13.
It is input to 04. In addition, the horizontal clock generation circuit 130
A horizontal period signal 32 that determines a horizontal period is input to the CPU 3 from the CPU 1104, and outputs a clock pulse S_CLK and a start pulse S_SP for the source signal line drive circuit. Similarly, the vertical clock generation circuit 1304 has a C
A vertical cycle signal 33 that determines the vertical cycle is input from PU, and a clock pulse G_CL for the gate signal line drive circuit is input.
K and start pulse G_SP are output.

Referring back to FIG.

Source signal line drive circuit start pulse S_S output from the display controller 1102.
P and the clock pulse S_CLK are displayed on the display 11
00 source signal line driving circuit 1107 is input to the shift register 1110. Further, a gate signal line driver circuit start pulse G_SP and a clock pulse G_CLK
Is a gate signal line drive circuit 11 of the display 1100.
08 is input.

Here, the display controller 110
2, the light-emitting-element power supply control circuit 1305 keeps the potential of the counter electrode of the light-emitting element of each pixel of the display at the same potential as the power supply potential during the writing period and keeps the same level as the power supply potential during the display period. In the meantime, it is controlled to change so as to have a potential difference such that the light emitting element emits light.

In this way, the display device displays the image.

Here, the display device is desired to consume as little power as possible. When incorporated and used in a portable information device or the like, it is particularly desired to reduce power consumption.

Therefore, there is proposed a method of reducing the power consumption of the display device by reducing the number of gradations (the number of gradations to be expressed) when displaying an image when multi-gradation display is not required.

This method will be described below in detail with reference to the timing chart of FIG.

Here, a 4-bit signal is input and 2
Focus on a display device that expresses ^four gradations. By the switching signal, the gradation is expressed by using only the upper 1-bit signal (digital signal). Thus, a method of reducing the power consumption of the display device will be described as an example.

At this time, the case where a 4-bit digital video signal is input to express 2 ⁴ gradations is called the first display mode, and the case where 2 gradations are expressed using only the upper 1-bit signal Will be referred to as a second display mode.

Generally, in the case where the input digital video signal is an n-bit signal, the case where the gradation is expressed by using the n-bit signal is called the first display mode. , M (m is a natural number smaller than n)
A case where the gradation is expressed using only the bit signal will be referred to as a second display mode.

In the n-bit digital video signal, the first bit is the most significant bit and the nth bit is the least significant bit.

In the second display mode, the gradation is expressed without using the signal corresponding to the lower bit of the digital video signal in the first display mode.

One frame period is divided into four subframe periods SF1 to SF4. The sub-frame periods SF1 to SF4 sequentially represent sub-frame periods corresponding to the lower-order bits from the sub-frame period for the higher bits, and appear in this order to form one frame period.

In the first display mode, the input 4
Since the gradation is expressed using all bit digital video signals, the signal input from the signal control circuit to the source signal line drive circuit expresses gradation using the 4-bit digital video signal as described above. It is the same as Also,
The source signal line drive circuit clock pulse S_CLK and the start pulse S_SP, and the gate signal line drive circuit clock pulse G_CLK and the start pulse G_SP output from the display controller also express gradation using a 4-bit digital video signal. It is represented by the same signal as the case.

A method of driving the display device in the second display mode will be described below.

FIG. 9 is a timing chart showing the driving method of the display device in the second display mode.

In the first sub-frame period SF1,
A signal is input to each pixel. When the signal is input to all the pixels, the counter potential changes so as to have a potential difference with the power supply potential to the extent that the light emitting element emits light. Thus
The light emitting element of each pixel is in a light emitting state or a non-light emitting state.

The operation in the first sub-frame period is the same as the operation in the first display mode.

Next, also in the second sub-frame period, digital video signals are similarly written in all the pixels in the writing period, but in the subsequent display period, the potential of the counter electrode is between the power source potential and Does not change so as to have a potential difference such that the light emitting element emits light. That is, in the display period of the second sub-frame period, the light emitting elements of all the pixels do not uniformly emit light regardless of the signal input to the pixels. This period is referred to as non-display.

The same operation as the operation in the second subframe period is repeated for the third subframe period and the fourth subframe period, and one frame period ends.

Of the one frame period, the period during which the pixel displays is only the first sub-frame period. Thus, in the second display mode, the number of times the light emitting element of the pixel emits light can be reduced and power consumption of the display device can be reduced.

[0101]

In the conventional display device,
When the display mode is switched to the second display mode in which the gradation is expressed without using the information of the lower bit, each pixel of the display device does not display during the period other than the sub-frame period corresponding to the upper bit. However, in each drive circuit (source signal line drive circuit and gate signal line drive circuit), the operation of writing the digital video signal into each pixel is performed. At this time, a start pulse, a clock pulse, or the like is input to each drive circuit of the display device and continues to operate.

Therefore, in the second display mode, even when gradation display is performed with a small amount of information, each drive circuit is equivalent to the sampling operation in the drive in the first display mode and the digital video signal The sampling operation will be repeated. Therefore, there is a problem that power is consumed for sampling and power consumption cannot be reduced.

Further, in the non-display sub-frame period other than the actual display sub-frame period, the pixels are in a non-display state in which they do not uniformly emit light, so that the effective per frame period is effective. There is a problem that the ratio of display period is small.

Therefore, in the case of performing driving with a reduced number of gradations to be expressed, a display device which consumes less power and has a large proportion of an effective display period per frame period, and a driving method thereof are provided. Is an issue.

[0105]

In the second display mode with respect to the first display mode, the memory controller of the signal control circuit of the display device writes the lower bit signal of the digital video signal to the memory. To lose.
Further, reading of the lower-order bit digital signal from the memory is eliminated. In this way, each drive circuit supplies a digital video signal (second digital video signal) having a reduced amount of information with respect to the digital video signal (first digital video signal) in the first display mode to the source signal line drive circuit. To enter. In response to this operation, the display controller slightly changes the frequencies of the start pulse and the clock pulse input to each drive circuit (source signal line drive circuit and gate signal destination drive circuit). by this,
The writing period and the display period of the sub-frame period related to the display are set to be long.

With the above structure, it is possible to provide a display device which consumes less power and has a large proportion of effective display periods per frame period, and a driving method thereof.

The constitution of the present invention will be described below.

According to the present invention, one frame period is divided into a plurality of subframe periods, and the subframe period is
In a display device which is turned on or off and expresses gradation by the sum of the lighting time in one frame period,
The first display mode in which the one frame period is divided into n (n is a natural number) subframe periods, and the one frame period is m (m is a natural number smaller than n) subframe periods A display device is provided, which has a second display mode that is divided.

According to the present invention, it has a display and a display controller for supplying a clock signal,
The number of gradations to be expressed in a display device in which one frame period is divided into a plurality of subframe periods, the subframe period is turned on or off, and the gradation is expressed by the sum of lighting times in the one frame period. Accordingly, a display device is provided, wherein the display controller supplies clock signals of different frequencies to the display.

According to the present invention, a memory for storing a digital video signal for one frame period is provided, the one frame period is divided into a plurality of subframe periods, and the subframe period is turned on or off, and In a display device that expresses gradations by the total of lighting times in one frame period, the display device is characterized in that the digital video signals stored in the memory are read at different frequencies according to the number of gradations to be expressed. Will be provided.

According to the present invention, it has a display and a display controller for supplying a clock signal,
A memory for storing a digital video signal for one frame period is provided, and one frame period is divided into a plurality of subframe periods, and the subframe period is turned on or off and the lighting time of the one frame period is changed. In a display device that expresses gray scales with a total sum, the display controller supplies clock signals of different frequencies to the display according to the number of gray scales to be expressed, and also the digital video signals stored in the memory. A display device is provided which is characterized by reading at different frequencies.

According to the present invention, it has a display and a display controller for supplying a clock signal,
In a display device in which one frame period is divided into a plurality of subframe periods, the subframe period is turned on or off, and a gray scale is expressed by a total of lighting times in the one frame period, the one frame period is , N (n
Is a natural number) sub-frame periods and the first frame mode is divided into m (where m is a natural number smaller than n) sub-frame periods.
The display device is characterized in that in the first display mode and the second display mode, the display controller supplies clock signals of different frequencies to the display. To be done.

According to the present invention, a memory for storing a digital video signal for one frame period is provided, the one frame period is divided into a plurality of subframe periods, and the subframe period is turned on or off, and In a display device that expresses gradation by the total of lighting times in one frame period, the one frame period is divided into n (n is a natural number) sub-frame periods, and the one frame A second display mode in which a period is divided into m (m is a natural number smaller than n) sub-frame periods, and the memory is used in the first display mode and the second display mode. A display device is provided, characterized in that the digital video signal stored in the memory is read at different frequencies.

According to the present invention, it has a display and a display controller for supplying a clock signal,
A memory for storing a digital video signal for one frame period is provided, and one frame period is divided into a plurality of subframe periods, and the subframe period is turned on or off and the lighting time of the one frame period is changed. In a display device that expresses gray scales with a total sum, the first display mode in which the one frame period is divided into n (n is a natural number) subframe periods and the one frame period is m (m
Has a second display mode divided into subframe periods of a natural number smaller than n), and in the first display mode and the second display mode, the display controller causes the display to A display device is provided, which supplies clock signals of different frequencies and reads out the digital video signals stored in the memory at different frequencies.

The display device may be characterized in that the brightness at the time of lighting in the sub-frame period is different according to the number of gradations to be expressed.

In the first display mode and the second display mode, the luminance during lighting in the sub-frame period is
The display device may be different.

According to the present invention, a display and a memory are provided, the display has a plurality of pixels, each of the plurality of pixels has a light emitting element, and a digital video signal is written in the memory. From the memory,
A writing period in which a digital video signal is output to the display, one frame period is divided into a plurality of subframe periods, and the digital video signal is input to the plurality of pixels in each of the plurality of subframe periods,
A display period in which the light emitting element is in a light emitting state or a non-light emitting state according to the digital video signal input to the plurality of pixels in the writing period, and the first bit to the n (n) th bit of the digital video signal. Is a natural number), and a first display mode in which a gradation is expressed using a signal of a bit, and the first to m-th bits (m is n) of the digital video signal.
A display device for displaying an image by switching between a second display mode in which gradation is expressed by using a signal of a smaller natural number) bit and a first bit of the digital video signal in the first display mode. To the n-th bit signal are stored in the memory, and in the second display mode, the 1-th to m-th bit signals of the digital video signal are stored in the memory to display the second display. In the mode, the writing period and the display period of the sub-frame period corresponding to the t-th (t is a natural number equal to or smaller than m) bit are the sub-frames corresponding to the t-th bit in the first display mode. A display device is provided, which is longer than each of the writing period and the display period of a frame period.

According to the present invention, a display and a memory are provided, the display has a plurality of pixels, the plurality of pixels has a plurality of light emitting elements, and a digital video signal is written in the memory. , From the memory,
A writing period in which a digital video signal is output to the display, one frame period is divided into a plurality of subframe periods, and the digital video signal is input to the plurality of pixels in each of the plurality of subframe periods,
A display period in which the light emitting element is in a light emitting state or a non-light emitting state according to the digital video signal input to the plurality of pixels in the writing period, and the first bit to the n (n) th bit of the digital video signal. Is a natural number), and a first display mode in which a gradation is expressed using a signal of a bit, and the first to m-th bits (m is n) of the digital video signal.
The image is displayed by switching between the second display mode in which the gradation is expressed using a signal of a smaller natural number) bit.
In the first display mode, the plurality of subframe periods are n in number, and the ratio of the lengths of the display periods Ts1 to Tsn included in each of the n subframe periods is:
2 ⁰ : 2 ⁻¹ : 2 ^{− (n−2)} : 2 ^{− (n−1)} , and in the second display mode, the plurality of subframe periods are m
The ratio of the lengths of the display periods Ts1 to Tsm, which are present in each of the m sub-frame periods, is 2 ⁰ : 2 ⁻¹ :
2 ^{− (m−2)} : 2 ^{− (m−1)} in the display device, a first display mode in which the first to nth bits of the digital video signal are stored in the memory, A second display mode in which the signal of the first bit to the m-th bit of the digital video signal is stored in the memory is switched, and in the second display mode, the t-th (t is,
The writing period and the display period of the sub-frame period corresponding to the m or less natural number bits are respectively the writing period and the display period of the sub-frame period corresponding to the t-th bit in the first display mode. A display device is provided which is characterized by being longer.

In the display period corresponding to the t-th bit in the second display mode, the emission brightness of the light-emitting element whose emission state is selected becomes the t-th bit in the first display mode. The display device may be characterized in that the potential of the counter electrode of the light emitting element is changed so that the light emitting state becomes lower than the emission brightness of the selected light emitting element in the corresponding display period.

According to the present invention, there is provided a signal control circuit, a display controller, and a display, the display having a source signal line drive circuit, a gate signal line drive circuit, and a plurality of pixels. Each pixel has a light emitting element, and the signal control circuit is a CPU
And a memory and a memory controller, wherein the display controller inputs a clock pulse for a source signal line drive circuit and a start pulse for a source signal line drive circuit to the source signal line drive circuit, and the gate signal line. A gate pulse for the gate signal line drive circuit and a start pulse for the gate signal line drive circuit are input to the drive circuit, a digital video signal is written to the memory, and a digital video signal is output from the memory to the display. The frame period is divided into a plurality of subframe periods, and in each of the plurality of subframe periods,
A writing period in which the digital video signal is input to the plurality of pixels, and a display period in which the light emitting element is in a light emitting or non-light emitting state depending on the digital video signal input to the plurality of pixels in the writing period. A first display mode for expressing gradation using a signal of the first to n-th (n is a natural number) bits of the digital video signal; and a first to m-th bit of the digital video signal. In a display device for displaying an image by switching between a second display mode in which gradations are expressed using a signal of (m is a natural number smaller than n) bits, in the first display mode, the memory controller is , In the memory,
The digital video signal of the 1st bit to the nth bit is written from the CPU, and the digital video signal written to the memory is output to the source signal line drive circuit as the digital video signal, Two
In the display mode, the memory controller writes the digital video signal of the 1st bit to the mth bit from the CPU to the memory, and writes the digital video signal written to the memory to the digital video signal. A video signal is output to the source signal line drive circuit, and the display controller compares the clock pulse for the source signal line drive circuit with the source in the second display mode as compared with the first display mode. There is provided a display device characterized in that the frequency of each of the signal line drive circuit start pulse, the gate signal line drive circuit clock pulse, and the gate signal line drive circuit start pulse is lowered.

The display controller has a variable frequency dividing circuit, a gradation control signal is input to the variable frequency dividing circuit, and in the second display mode, as compared with the first display mode, A display characterized by lowering the frequencies of the source signal line drive circuit clock pulse, the source signal line drive circuit start pulse, the gate signal line drive circuit clock pulse, and the gate signal line drive circuit start pulse. It may be a device.

The display controller has a light emitting element power supply control circuit, and changes the potential of the counter electrode of the light emitting element according to a gradation control signal input to the light emitting element power supply control circuit, In the display period corresponding to the t-th (t is a natural number equal to or smaller than m) bit of the display mode, the emission brightness of the light-emitting element whose emission state is selected is the t-th position of the first display mode. In the display period corresponding to the bit of, the light emission state is lower than the light emission luminance of the selected light emitting element,
A display device may be characterized in that the potential of the counter electrode of the light emitting element is changed.

A video camera, a DVD reproducing device, a television receiver, a head mounted display, a personal digital assistant, or a personal computer characterized by using the display device may be used.

[0124]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described.

FIG. 1 is a timing chart showing the driving method of the display device of the present invention.

In FIG. 1, attention is paid to a display device to which a 4-bit digital video signal is input. In the first display mode, a 4-bit digital video signal is input to the display to display an image. On the other hand, in the second display mode, the gradation is expressed by the 1-bit digital video signal using only the high-order 1-bit digital video signal of the 4-bit digital video signal.
In this embodiment, an example of the above case will be described, but the display device of the present invention is not limited to this case.

In general, attention is paid to a display device which inputs an n-bit (n is a natural number) digital video signal. In the first display mode, an n-bit digital video signal can be used to express 2 ⁿ gray scales by ⁿ sub-frame periods SF1 to SFn. On the other hand, due to the switching operation, in the second display mode, an m (m is a natural number smaller than n) bit digital video signal is used to generate 2
Represents ^m gradation. It can be applied to such a case.

Note that, more generally, attention is paid to a display device which inputs an n-bit (n is a natural number) digital video signal. In the first display mode, an n-bit digital video signal is input, and w (w is a natural number) gray scale can be expressed using r (r is a natural number) subframe periods. On the other hand, due to the switching operation, in the second display mode, a digital video signal of m (m is a natural number smaller than n) bits is used, and u is generated by s (s is a natural number smaller than r) subframe periods. (U is a natural number smaller than w) The gradation is expressed. It can be applied to such a case.

FIG. 1A shows a timing chart in the first display mode in which a 4-bit signal is input to express 2 ⁴ gray levels.

In each of the sub-frame periods SF1 to SF4 forming one frame period, the light emitting or non-light emitting state of each pixel is selected. Here, the counter potential is set to be substantially the same as the power supply potential during the writing period, and changes so as to have a potential difference with the power supply potential such that the light emitting element emits light during the display period.

Since this operation is the same as the conventional example, detailed description will be omitted.

FIG. 1B shows a timing chart in the case of the second display mode in which the gradation is expressed using only the signal of the upper 1 bit.

Compared with the case of the first display mode shown in FIG. 1A, the writing period and the display period are set to be longer, and one frame period substantially corresponds to the first sub-frame period.

The structure of the display device for performing the above driving operation will be described below.

A block diagram of a display device which performs the above operation is shown in FIGS.

The display device includes a signal line control circuit 101, a display controller 102, and a display 100.
It is composed of and.

The display controller 102 supplies the display 100 with the start pulse SP and the clock pulse CLK.

The signal control circuit 101 includes a CPU 104,
It is composed of a memory A 105, a memory B 106, and a memory controller 103.

FIG. 4 shows an example of a display device in which a 4-bit digital video signal is input and a gradation is expressed by using the 4-bit digital video signal in the first display mode. The memory A105 is configured by memories 105_1 to 105_4 that store the signals of the first bit to the fourth bit of the digital video signal, respectively. Similarly, the memory B106 is also composed of memories 106_1 to 106_4 for storing the signals of the first bit to the fourth bit of the digital video signal, respectively. Each of the memories corresponding to these digital signals of each bit has a number of storage elements capable of storing a signal of 1 bit for the number of pixels forming one screen.

Generally, in a display device capable of expressing gradation using an n-bit digital video signal, the memory A is a memory 105_1 which stores information of the 1st bit to the nth bit, respectively. .About.105_n. Similarly, the memory B also stores the information of the first bit to the n-th bit, respectively.
1 to 106_n. The memory corresponding to each of these bits outputs a signal for 1 bit to 1
It has a capacity capable of storing the number of pixels forming the screen.

The structure of the memory controller 103 in FIG. 4 is shown in FIG.

In FIG. 2, the memory controller 103
Is a gradation limiting circuit 201, a memory R / W circuit 202, a reference oscillating circuit 203, a variable frequency dividing circuit 204, an x counter 2.
05a, y counter 295b, x decoder 206a, y
It is composed of a decoder 206b.

Both the memories A and B described above are collectively referred to as a memory. Also, the memory is
It is composed of a plurality of storage elements. Those storage elements shall be selected by the address of (x, y).

A signal from the CPU 104 is input to the memory R / W circuit 202 via the gradation limiting circuit 201. The gradation limiting circuit 201 inputs a signal to the memory R / W circuit 202 according to either the first display mode or the second display mode. Memory R / W circuit 202
Selects whether to write each digital video signal corresponding to each bit in the memory according to the signal of the gradation limiting circuit 201. Similarly, the operation of reading the digital signal written in the memory is selected.

The signal from the CPU 104 is input to the reference oscillation circuit 203. The signal from the reference oscillating circuit 203 is input to the variable frequency dividing circuit 204 and converted into a signal having an appropriate frequency. Here, a signal from the gradation limiting circuit 201 is input to the variable frequency dividing circuit 204 according to either the first display mode or the second display mode. With this signal, the signal from the variable frequency dividing circuit 204 is transmitted to the x counter 205a and the x decoder 206a.
Select the x-address of the memory via. Similarly, the signal from the variable frequency dividing circuit 204 is input to the y counter 205b and the y decoder 206b to select the memory y address.

The memory controller 10 having such a configuration
By using 3, the information amount of the signal written to the memory and the information (digital video signal) read from the memory among the digital video signals input to the signal control circuit when high gradation display is not required Can be suppressed. Further, the frequency of reading the signal from the memory can be changed.

The above is the description of the memory controller 103.

The structure of the display controller 102 shown in FIG. 4 will be described below.

FIG. 3 is a diagram showing the configuration of the display controller of the present invention.

The display controller 102 includes a reference clock generating circuit 301, a variable frequency dividing circuit 302, a horizontal clock generating circuit 303, a vertical clock generating circuit 304,
The light-emitting element power source 305 is used.

The clock signal 31 input from the CPU 104 is input to the reference clock generation circuit 301 and generates a reference clock. This reference clock is input to the horizontal clock generating circuit 303 and the vertical clock generating circuit 304 via the variable frequency dividing circuit 302. The gradation control signal 34 is input to the variable frequency dividing circuit 302.
This signal changes the frequency of the reference clock.

The degree to which the frequency of the reference clock is changed in the variable frequency dividing circuit 302 can be appropriately determined by the practitioner. This is because the sub-frame period in the first display mode, which corresponds to the bits involved in the gradation expression in the second display mode, varies depending on the ratio occupied in one frame period.

That is, in the second display mode, the sub-frame period in one frame period is reduced as compared with the first display mode. In the present invention, the frequency of the reference clock is changed in the variable frequency dividing circuit 302 in order to set the effective display period in one frame period to be long even in the second display mode. The rate of changing the frequency can be changed according to the rate of reduction of the number of bits.

The horizontal clock circuit 303 has a CP
The horizontal period signal 32 that determines the horizontal period is input from U104, and the clock pulse S_ for the source signal line drive circuit is input.
CLK and the start pulse S_SP are output. Similarly, the vertical clock generation circuit 304 includes a CPU
The vertical cycle signal 33 that determines the vertical cycle is input from 104, and the clock pulse G_CL for the gate signal line drive circuit is input.
K and the start pulse G_SP are output.

The above is the display controller 102.
Is the explanation.

Thus, in the display device of the present invention, in the second display mode, the memory controller of the signal control circuit eliminates the reading of the lower bit signal from the memory. In addition, the frequency of reading the signal from the memory is reduced. Corresponding to this operation, the display controller reduces the frequencies of the sampling pulse SP and the clock pulse CLK input to each drive circuit (source signal line drive circuit and gate signal destination drive circuit) to display an image in a subframe period. The writing period and the display period are set to be long.

For example, in the first display mode, one frame period is divided into four subframe periods. Then, the display period Ts1: T of each sub-frame period
s2: Ts3: Ts4 ratio of 2 ^0: 2 ^-1: 2 ^-2: as 2 ^-3, using 4-bit digital video signals, consider a display device for expressing a gray level of 2 ^4. For simplicity, the lengths of the display periods Ts1 to Ts4 in each subframe period are
It is set to 8, 4, 2, 1. Further, the length of the writing periods Ta1 to Ta4 in each subframe period is set to 1. Also, consider a case where a gradation is expressed using a signal of the upper 1 bit in the second display mode.

At this time, in the second display mode, the ratio of the sub-frame period in the first display mode corresponding to the bits involved in the gradation expression to one frame period is 9/19.

That is, the subframe period involved in the gradation expression in the second display mode is the subframe period (denoted as SF1) corresponding to the upper 1 bit. Here, in the first display mode, the ratio of SF1 in one frame period is 9/19.

When the structure of the present invention is not used, for example, when the driving method as shown in FIG. 9 of the conventional example is used, 10 / of 1 frame period is set in the second display mode.
19 is a period in which the display is not involved.

On the other hand, according to the present invention, in the second display mode, the frequency of the clock signal or the like input to each drive circuit of the display is changed in the second display mode, so that the writing period in the first display mode is 19/9. A writing period having a double length is set, and similarly, a display period is also set to be 19/9 times as long as the display period Ts1 of the sub-frame period SF1 corresponding to the first bit in the first display mode. Thus, one frame period can be occupied by the subframe period SF1. In this way, in the second display mode, it is possible to reduce the period that is not involved in the display in one frame period.

In general, a first display mode in which a gradation is expressed by using a signal of the 1st bit to the nth (n is a natural number) bit, and 1st bit to the mth (m is smaller than n) Attention is given to a display device having a second display mode in which a grayscale is expressed using a signal of (natural number) bits.

In the second display mode, the sub-frame period in the first display mode, which corresponds to the bits involved in gradation expression, occupies 1 / q (q is a number larger than 1) per frame period. ) Consider the case.

That is, in the first display mode, the first
The ratio of the sub-frame period corresponding to the bit from the m-th bit to one frame period is 1 / q (q
Is a number greater than 1).

In the sub-frame period corresponding to the t-th bit (t is a natural number of m or less) in the second display mode, each drive circuit (source signal line drive circuit and gate signal line drive circuit) of the display is operated. The frequency of each input signal (clock pulse, start pulse, etc.) is changed by a factor of 1 / q, and the frequency is q times the writing period of the sub-frame period corresponding to the t-th bit in the first display mode. Set the writing period. Similarly, the display period is set to be q times as long as the display period of the sub-frame period corresponding to the t-th (t is a natural number of m or less) bit in the first display mode. The image can be displayed sufficiently.

Thus, even in the second display mode,
The display period of the light emitting element per one frame period can be long.

Therefore, in the second display mode, the luminance of the light emitting element whose light emitting state is selected in the display period of the sub-frame period corresponding to the first bit is set to the first bit in the first display mode. In the display period of the corresponding sub-frame period, the light emitting state can be made smaller than the luminance of the selected light emitting element. Therefore, in the second display mode, the voltage applied between the anode and the cathode of the light emitting element can be set small in the display period.

A method of changing the voltage applied between the anode and the cathode of the light emitting element according to the display mode will be described.

In FIG. 3, the light-emitting element power supply control circuit 3
Reference numeral 05 indicates that the electric potential of the counter electrode of the light emitting element (counter electric potential) is maintained at substantially the same potential as the power source potential during the writing period, and the light emitting element emits light between the power source potential and the display period during the display period. It is controlled so as to have a potential difference.
Here, the gradation control signal 34 is also input to the light emitting element power supply control circuit 305. As a result, in the pixel in which the light emitting state is selected, the potential of the counter electrode of the light emitting element is changed so that the voltage applied between both electrodes of the light emitting element becomes smaller as the light emitting element emits light for a longer period.

Generally, in the second display mode, the t-th (t is
In the sub-frame period corresponding to the (m natural number) bit, the display period is set to q (q
Consider a case where the length is set to a value larger than 1) times. The luminance of the light emitting element whose emission state is selected in the sub-frame period corresponding to the t-th bit in the second display mode is selected as the emission state in the sub-frame period corresponding to the t-th bit in the first display mode. The brightness can be 1 / q times the luminance of the light emitting element.

In the second display mode, since the magnitude of the voltage applied between both electrodes of the light emitting element can be reduced, the stress of the light emitting element due to the applied voltage can be reduced.

Although the display device for switching between the first display mode and the second display mode has been shown, in addition to the first display mode and the second display mode, the floor to be expressed in more detail. It can be applied when a mode in which the number of keys is changed is set and a plurality of display modes are switched to perform display.

Here, the configuration of the pixel portion included in the display of the display device of the present invention is as shown in FIG.
The pixel having the configuration shown in can be used. In addition, pixels of other known configurations can be freely used.

For example, the following two types of pixels can be applied. One is a pixel in which the luminance of the light emitting element is determined by determining the voltage applied between the anode and the cathode of the light emitting element. The pixel having the configuration shown in FIG. 8 corresponds to a pixel of this system. The second is a pixel of a system in which the luminance of the light emitting element is determined by determining the current flowing through the light emitting element.

Further, as the source signal line driver circuit and the gate signal line driver circuit included in the display of the display device of the invention, circuits having a known structure can be freely used.

The present invention also provides an OLE as a light emitting device.
The invention is applicable not only to a display device using a D element, but also to other self-luminous display devices such as FDP and PDP.

[0177]

EXAMPLES Examples of the present invention will be described below.

(Embodiment 1) In this embodiment, a configuration example of a source signal line driver circuit of a display device of the present invention will be described.

FIG. 15 shows a configuration example of the source signal line drive circuit.

The source signal line drive circuit includes a shift register, a scanning direction switching circuit, LAT (A) and LAT.
(B). In FIG. 15, the LAT corresponding to one of the outputs from the shift register
Although only a part 2612 of (A) and a part 2618 of LAT (B) are shown, LAT (A) and LAT (B) having the same configuration correspond to all outputs from the shift register.

The shift register 2601 includes clocked inverters 2602 and 2603, an inverter 2604, N.
It is configured by AND2607. A source signal line driver circuit start pulse S_SP is input to the shift register 2601, and the source signal line driver circuit clock pulse S_CLK and an inverted clock pulse S_CLKB for the source signal line driver circuit, which is a signal whose polarity is inverted.
Clocked inverters 2602 and 2603
Changes to the conductive state or the non-conductive state,
Sampling pulses are output to LAT (A) in order from ND2607.

The scanning direction switching circuit is composed of a switch 2605 and a switch 2606, and has a function of switching the operating direction of the shift register to the left or right as viewed in the drawing. In FIG. 15, when the left / right switching signal L / R corresponds to the signal of Lo, the shift register sequentially outputs sampling pulses from left to right in the drawing.
On the other hand, when the left / right switching signal L / R corresponds to the Hi signal, sampling pulses are output in order from right to left in the drawing.

The LAT (A) 2613 of each stage is composed of clocked inverters 2614 and 2615 and inverters 2616 and 2617.

Here, the LAT (A) of each stage is
LA that captures the video signal input to one source signal line
Let T (A) be indicated.

Here, the digital video signal output from the signal control circuit described in the embodiment is VD,
It is input after being divided into p (p is a natural number). That is, the signals corresponding to the outputs to the p source signal lines are input in parallel. Sampling pulses are buffers 2608-26
11 through p stages of LAT (A) 2612
When the clocked inverters 2614 and 2615 are simultaneously input, the p-divided input signals are simultaneously sampled in the LAT (A) 2612 of the p stages.

Here, the source signal line drive circuit 2600 that outputs a signal current to x source signal lines has been described as an example, so that x / p sampling pulses are sequentially output from the shift register per horizontal period. Is output. LAT of p stages according to each sampling pulse
The (A) 2613 simultaneously samples digital video signals corresponding to the output to the p source signal lines.

In the present specification, a method of dividing the digital video signal input to the source signal line drive circuit into p-phase parallel signals and simultaneously capturing p digital video signals by one sampling pulse is used in this specification. , P division drive.

By performing the above division drive, it is possible to give a margin to the sampling of the shift register of the source signal line drive circuit. Thus, the reliability of the display device can be improved.

When all the signals for one horizontal period are input to the LAT (A) 2613 of each stage, the latch pulse LP
Further, the inverted latch pulse LPB whose polarity is inverted is input, and the signals input to the LAT (A) 2613 of each stage are simultaneously output to the LAT (B) 2619 of each stage.

Note that the LAT (B) of each stage is a LAT (B) circuit to which the signal from the LAT (A) of each stage is input.

Each stage 2619 of LAT (B) is composed of clocked inverters 2620 and 2621 and inverters 2622 and 2623. LAT
The signal output from each stage 2613 in (A) is L
At the same time as being held in AT (B), each source signal line S1
To Sx.

Although not shown here, a level shifter, a buffer, etc. may be provided as appropriate.

Shifter register and LAT (A), LAT
The start pulse S_SP, the clock pulse S_CLK, and the like input to (B) are input from the display controller described in the embodiment of the invention.

In the present invention, the operation of inputting a digital video signal having a small number of bits to the LAT (A) of the source signal line drive circuit is performed by the signal control circuit, and at the same time, input to the shift register of the source signal line drive circuit. The display controller performs the operation of reducing the frequency of the clock pulse S_CLK and the start pulse S_SP to be generated.

As described above, in the second display mode, it is possible to reduce the operation of the source signal line drive circuit sampling the digital video signal and suppress the power consumption of the display device.

Note that the display device of the present invention is not limited to the structure of the source signal line driver circuit of this embodiment, and a source signal line driver circuit of a known structure can be freely used.

(Embodiment 2) In this embodiment, a configuration example of a gate signal line drive circuit of a display device of the present invention will be described.

The gate signal line drive circuit is composed of a shift register, a scanning direction switching circuit, and the like.
Although not shown here, a level shifter, a buffer, or the like may be provided as appropriate.

The start pulse G--
SP, the clock pulse G_CLK, etc. are input and the gate signal line selection signal is output.

The structure of the gate signal line driver circuit will be described with reference to FIG.

The shift register 3601 includes clocked inverters 3602 and 3603, inverters 3604, N.
It is configured by AND3607. A start pulse G_SP is input to the shift register 3601.
The clocked inverters 3602 and 3603 are changed to a conductive state and a non-conductive state by the clock pulse G_CLK and an inverted clock pulse G_CLKB which is a signal whose polarity is inverted, so that sampling pulses are sequentially output from the NAND 3607.

The scanning direction switching circuit is composed of the switch 3605 and the switch 3606, and has a function of switching the operation direction of the shift register to the left or right as viewed in the drawing. In FIG. 16, the scanning direction switching signal U /
When D corresponds to the signal of Lo, the shift register sequentially outputs sampling pulses from left to right in the drawing. On the other hand, when the scanning direction switching signal U / D corresponds to the Hi signal, sampling pulses are output in order from right to left in the drawing.

The sampling pulse output from the shift register is input to the NOR 3608 and operated as the enable signal ENB. This calculation is performed in order to prevent a situation where adjacent gate signal lines are simultaneously selected due to rounding of the sampling pulse. NOR3608
The signal output from the above is output to the gate signal lines G1 to Gy via the buffers 3609 and 3610.

Although not shown here, a level shifter, a buffer, etc. may be provided as appropriate.

The start pulse G_SP, the clock pulse G_CLK and the like input to the shifter register are input from the display controller described in the embodiment.

In the present invention, in the second display mode,
The display controller performs an operation of reducing the frequency of the clock pulse G_CLK, the start pulse G_SP, and the like which are input to the shift register of the gate signal line driver circuit.

Thus, in the second lower display mode,
The sampling operation of the gate signal line driver circuit can be reduced and power consumption of the display device can be suppressed.

The display device of the present invention is not limited to the structure of the gate signal line drive circuit of this embodiment, and a gate signal line drive circuit of a known structure can be freely used.

This embodiment can be implemented by being freely combined with Embodiment 1.

(Embodiment 3) In this embodiment, a method for sealing a display device of the present invention will be described with reference to FIG.

13A is a top view of the display device, FIG. 13B is a cross-sectional view taken along the line AA 'in FIG. 13A, and FIG. 13C is FIG. 13A. It is a sectional view taken along line BB ′ of FIG.

Pixel portion 400 provided on substrate 4001
2, source signal line driver circuit 4003, first and second
A sealant 4009 is provided so as to surround the gate signal line driver circuits 4004a and 4004b. In addition, the pixel portion 4002 and the source signal line driver circuit 4003
And the first and second gate signal line driver circuits 4004a,
A sealing material 4008 is provided on the surface 4004b. Therefore, the pixel portion 4002, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 40
04a and 4004b are the substrate 4001 and the sealing material 40.
09 and the sealing material 4008, the filler 421
It is sealed at 0.

Further, the pixel portion 4 provided on the substrate 4001
002, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 4004a and 4004b each include a plurality of TFTs. In FIG. 13B, a driving TFT included in the source signal line driver circuit 4003 which is typically formed over the base film 4010 (note that an n-channel TFT and a p-channel TFT are illustrated here).
4201 and the driving TFT 4 included in the pixel portion 4002
202 is illustrated.

In this embodiment, a p-channel TFT or an n-channel TFT manufactured by a known method is used as the driving TFT 4201, and a p-channel TFT manufactured by a known method is used as the driving TFT 4202. To be Further, the pixel portion 4002 is provided with a storage capacitor (not shown) connected to the gate of the driving TFT 4202.

The driving TFT 4201 and the driving TFT 42
02, an interlayer insulating film (planarizing film) 4301 is formed, and a pixel electrode (anode) 4203 electrically connected to the drain of the driving TFT 4202 is formed thereon. A transparent conductive film having a high work function is used as the pixel electrode 4203. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide or indium oxide can be used. Moreover, you may use what added gallium to the said transparent conductive film.

An insulating film 4302 is formed on the pixel electrode 4203, and the insulating film 4302 forms the pixel electrode 420.
3, an opening is formed on the upper part. In this opening, an organic compound layer 4204 is formed on the pixel electrode 4203. A known organic material or inorganic material can be used for the organic compound layer 4204. Further, the organic material includes a low molecular weight (monomer type) material and a high molecular weight (polymer type) material, and either of them may be used.

As a method for forming the organic compound layer 4204, a known vapor deposition technique or coating technique may be used. The structure of the organic compound layer is a hole injection layer, a hole transport layer, a light emitting layer,
The electron transport layer or the electron injection layer may be freely combined to form a laminated structure or a single layer structure.

A cathode 4205 made of a conductive film having a light-shielding property (typically, a conductive film containing aluminum, copper, or silver as a main component or a laminated film of these and another conductive film) is formed over the organic compound layer 4204. Is formed. Also, the cathode 4
It is desirable to remove water and oxygen existing at the interface between 205 and the organic compound layer 4204 as much as possible. Therefore, the organic compound layer 4204 is formed in a nitrogen or rare gas atmosphere,
It is necessary to devise a method of forming the cathode 4205 without exposing it to oxygen and moisture. In the present embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film forming apparatus. And the cathode 42
05 is given a predetermined voltage.

As described above, the pixel electrode (anode) 42
03, the organic compound layer 4204, and the cathode 4205, a light emitting element 4303 is formed. And the light emitting element 430
A protective film 4209 is formed on the insulating film 4302 so as to cover the insulating film 4302. The protective film 4209 is formed on the light emitting element 4303.
It is effective in preventing oxygen and water from entering the body.

Reference numeral 4005a is a leading wiring connected to the power supply line, and is electrically connected to the source region of the driving TFT 4202. The lead wiring 4005a passes between the sealing material 4009 and the substrate 4001, and the FPC 4006 has F through the anisotropic conductive film 4300.
It is electrically connected to the PC wiring 4301.

As the sealing material 4008, a glass material, a metal material (typically a stainless material), a ceramic material, and a plastic material (including a plastic film) can be used. As a plastic material, FRP
(Fiberglass-Reinforced Pl
astics) plate, PVF (polyvinyl fluoride)
A film, mylar film, polyester film or acrylic resin film can be used. Alternatively, a sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can be used.

However, the cover material must be transparent when the emission direction of light from the light emitting element is toward the cover material side. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

Further, as the filler 4103, an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone can be used. Resin, PVB (polyvinyl butyral) or E
VA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.

In order to expose the filler 4210 to a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen, the substrate 400 of the sealing material 4008 is used.
A concave portion 4007 is provided on the surface on the first side, and a hygroscopic substance or a substance 4207 capable of adsorbing oxygen is arranged. The hygroscopic substance or the substance 4207 capable of adsorbing oxygen is held by the recessed cover material 4208 in the recess 4007 so that the hygroscopic substance or the substance 4207 capable of adsorbing oxygen does not scatter. Note that the recess cover material 4208 has a fine mesh shape and has a structure in which air and moisture can pass through and a hygroscopic substance or a substance that can adsorb oxygen 4207 cannot pass through. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the light-emitting element 4303 can be suppressed.

As shown in FIG. 13C, the pixel electrode 42
At the same time that 03 is formed, a conductive film 4203a is formed so as to be in contact with the lead wiring 4005a.

The anisotropic conductive film 4300 has a conductive filler 4300a. Substrate 4001 and F
By thermocompression bonding with PC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4301 on the FPC 4006 are electrically connected by the conductive filler 4300a.

This embodiment can be implemented by freely combining with Embodiments 1 and 2.

(Embodiment 4) In this embodiment, electronic equipment using the display device of the present invention will be described with reference to FIG.

FIG. 14A shows a schematic diagram of a portable information terminal using the display device of the present invention. The mobile information terminal is the main body 2
701a, operation switch 2701b, power switch 27
01c, an antenna 2701d, a display portion 2701e, and an external input port 2701f. The display device having the structure described in Embodiment Mode and Embodiments 1 to 3 can be used for the display portion 2701e.

FIG. 14B shows a schematic diagram of the personal computer of the present invention. The personal computer includes a main body 2702a, a housing 2702b, a display unit 2702c, operation switches 2702d, a power switch 2702e, and an external input port 2702f. The display device having the structure shown in Embodiment Mode and Embodiments 1 to 3 can be used for the display portion 2702c.

FIG. 14C shows a schematic diagram of the image reproducing apparatus of the present invention. The image reproducing device includes a main body 2703a and a housing 2.
703b, a recording medium 2703c, a display unit 2703d, a voice output unit 2703e, and an operation switch 2703f. The display device having the structure shown in Embodiment Mode and Embodiments 1 to 3 can be used for the display portion 2703d.

FIG. 14D shows a schematic diagram of the television of the present invention. The television includes a main body 2704a, a housing 2704b, a display portion 2704c, and operation switches 2704d. The display device having the structure described in Embodiment Mode and Embodiments 1 to 3 can be used for the display portion 2704c.

FIG. 14 (E) shows a schematic view of the head mounted display of the present invention. The head mounted display includes a main body 2705a, a monitor unit 2705b, a head fixing band 2705c, a display unit 2705d, an optical system 270.
5e. Embodiment and Example 1
-The display unit having the configuration shown in the third embodiment has the display unit 2705.
can be used for d.

FIG. 14F shows a schematic diagram of the video camera of the present invention. The video camera includes a main body 2706a and a housing 2.
706b, connection unit 2706c, image receiving unit 2006d, eyepiece unit 2706e, battery 2706f, voice input unit 27
06g, and the display unit 2706h. The display device having the structure described in Embodiment Modes and Embodiments 1 to 3 can be used for the display portion 2706h.

The present invention is not limited to the above-mentioned applied electronic equipment and can be applied to various electronic equipment.

[0236]

According to the present invention, with the above structure, the power consumption of the display device can be suppressed. Moreover, in the second display mode, even when the number of sub-frames used for expressing gradation is reduced, it is possible to lengthen the display period per one frame period, which enables clear image display. It is possible to provide a display device and a driving method thereof.

Further, since the display period of the light emitting element per one frame period can be made long, when expressing the same brightness per one frame, the voltage applied between the anode and the cathode of the light emitting element is set small. be able to. Thus, a highly reliable display device can be provided.

The present invention can be applied not only to a display device using an OLED element as a light emitting element, but also to other self-luminous display devices such as FDP and PDP.

[Brief description of drawings]

FIG. 1 is a diagram showing a timing chart showing a driving method of a display device of the present invention.

FIG. 2 is a diagram showing a configuration of a memory controller of a display device of the present invention.

FIG. 3 is a diagram showing a configuration of a display controller of the display device of the present invention.

FIG. 4 is a block diagram showing a configuration of a display device of the present invention.

FIG. 5 is a diagram showing a timing chart showing a driving method of a time gray scale method.

FIG. 6 is a block diagram showing a configuration of a display device of the present invention.

FIG. 7 illustrates a structure of a pixel portion of a display device.

FIG. 8 illustrates a pixel structure of a display device.

FIG. 9 is a diagram showing a timing chart showing a driving method of a conventional display device.

FIG. 10 is a block diagram showing a configuration of a conventional display device.

FIG. 11 is a diagram showing a configuration of a memory controller of a conventional display device.

FIG. 12 is a diagram showing a configuration of a display controller of a conventional display device.

FIG. 13 is a diagram showing a method of sealing a light emitting element of a display device of the present invention.

FIG. 14 illustrates an electronic device of the invention.

FIG. 15 illustrates a structure of a source signal line driver circuit of a display device of the present invention.

FIG. 16 is a diagram showing a configuration of a gate signal line driver circuit of a display device of the present invention.

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) G09G 3/20 G09G 3/20 641P H05B 33/14 H05B 33/14 A

Claims (12)

[Claims] 1. A means for dividing one frame period into a plurality of sub-frame periods, and a digital signal is input to a corresponding pixel in each of the plurality of sub-frame periods so as to change a light emitting state or a non-light emitting state of the pixel. A display device having a selecting unit, wherein the unit selects the first display mode or the second display mode, and in the first display mode, in the pixel, n ( n is a natural number) means for inputting the digital signal of a bit as a first digital video signal; and, in the second display mode, the pixel of the n-bit digital signal during the one frame period. , First
Means for inputting the m-th (m is a natural number smaller than n) digital signal as the second digital video signal, the second bit in the second display mode, The length of the sub-frame period corresponding to the digital signal of the first bit of the digital video signal, ..., The digital signal of the m-th bit is respectively set to the first digital value in the first display mode. , A means for multiplying the length of the sub-frame period corresponding to the digital signal of the m-th bit of the video signal by q (q is a number greater than 1) times. A display device characterized by the above. 2. The pixel unit according to claim 1, further comprising a pixel unit in which the pixels are arranged in a matrix, and the digital signal is supplied to the pixel unit in the second display mode with respect to the first display mode. A display device having means for setting a drive frequency of a drive circuit input to each corresponding pixel to 1 / q. 3. The display device according to claim 1, further comprising a pixel portion in which the pixels are arranged in a matrix, and a memory, wherein the memory is the one in the first display mode. The n-bit digital signal input to each pixel of the pixel unit is stored, and in the second display mode, the first-order bit among the n-th bit digital signals for the number of pixels of the pixel unit is stored. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,, "" ,,,,,,. A display device having means for setting a frequency to 1 / q. 4. The luminance according to claim 1, wherein in the second display mode with respect to the first display mode, the luminance of the pixel whose light emitting state is selected is lowered. A display device having means. 5. The light emitting element according to claim 1, wherein the pixel has a light emitting element, and the luminance of the light emitting element whose light emitting state is selected in the second display mode is: A display device comprising means for changing an electric potential of an electrode of the light emitting element so that a light emitting state in the first display mode becomes lower than a luminance of the selected light emitting element. 6. The electronic device according to claim 1, wherein the display device is used. 7. One frame period is divided into a plurality of subframe periods, and in each of the plurality of subframe periods, a light emitting state or a non-light emitting state of the pixel is selected by inputting a digital signal to a corresponding pixel. A driving method of a display device, wherein a first display mode or a second display mode is selected, and in the first display mode, in the pixel, n (n is a natural number) bits in the one frame period. Of the n-bit digital video signal in the pixel during the one frame period in the second display mode.
The digital signal of the first bit, ..., The digital signal of the m-th bit (m is a natural number smaller than n) are input as a second digital video signal, and the second digital image signal in the second display mode is input. The length of the sub-frame period corresponding to the digital signal of the first bit of the digital video signal, ..., The digital signal of the mth bit is respectively the first digital in the first display mode. The length of a sub-frame period corresponding to the digital signal of the 1st bit of the video signal, ..., The digital signal of the mth bit is q (q is a number greater than 1) times as long as Method for driving display device. 8. The pixel unit according to claim 7, further comprising a pixel unit in which the pixels are arranged in a matrix, and the digital signal is supplied to the pixel unit in the second display mode with respect to the first display mode. A driving method of a display device, wherein a driving frequency of a driving circuit input to each corresponding pixel is 1 / q. 9. The pixel unit according to claim 7, further comprising a pixel portion in which the pixels are arranged in a matrix, and a memory, wherein the memory has the number of pixels of the pixel portion in the first display mode. Minutes of the n-th bit digital signal are stored, and in the second display mode, of the n-th bit digital signals for the number of pixels of the pixel section, the first-order bit digital signal, ... .. Read the digital signal of the m-th bit, and in the second display mode with respect to the first display mode, the frequency of reading the digital signal from the memory is 1 / q And method for driving a display device. 10. The brightness according to claim 7, wherein in the second display mode, the luminance of the pixel whose light emitting state is selected is low with respect to the first display mode. And a method for driving a display device. 11. The light emitting element according to claim 7, wherein the pixel has a light emitting element, and the luminance of the light emitting element whose light emitting state is selected in the second display mode is the light emitting element. A driving method of a display device, wherein the potential of the electrode of the light emitting element is changed so that the light emitting state in the first display mode is lower than the luminance of the selected light emitting element. 12. An electronic device according to claim 7, wherein the driving method of the display device is used.