JP2002543630A - Smart power circuit capable of changing mask configuration, its application, and GS-NMOS device - Google Patents

Abstract

  (57) [Summary] The present invention relates to a novel approach to smart power semi-custom design, based on the required function, using only a metal mask on the surface and the basic cells in a matrix that is conveniently designed to be easily programmed. It can process high voltage signals like interface with microprocessor, using one kind of cell combination as all required topologies for rectification, driving, protection, amplification, sensing and control, Rapidly build prototypes to perform error detection and process monitoring.

Description

DETAILED DESCRIPTION OF THE INVENTION

SUMMARY OF THE INVENTION The present invention provides a smart power circuit suitable for implementing the general functions required of a power control block, utilizing an array based on only one type of NMOS cell. It is about an important improvement when designing into a matrix. With this technology, a low-cost semi-custom design and a new IC configuration strategy that can be easily industrialized without any additional processing process, toward the digital integration of smart power circuits using standard CMOS technology. Becomes possible. This method can also be applied to the technology for rapidly producing sophisticated smart power circuit prototypes.

BACKGROUND OF THE INVENTION Advances in smart power circuits have been associated with the development of new technological processes, requiring digital and analog libraries. It should be noted that the potential of the new technological process depends on the exact characterization and availability of the power device, so a sophisticated and costly technical process is needed. With such sophisticated technologies, various types of semiconductors have been produced. To illustrate, to a small extent, N-MOS, P-MOS, HV-NMOS (
High-Voltage NMOS: High-voltage NMOS, HV-PMOS (Hi
gh-Voltage PMOS: high-voltage PMOS, field-effect transistor (N
PN, PNP, HV-PNP, HV-NPN), bipolar junction transistor (
BJT, Zener diode, rectifier diode), IGBT, and MOS thyristor.

[0003] Research is actively under way around the world to find solutions that are compatible with CMOS technology. However, with any approach, it is not possible to achieve the functions required for the power control block in a smart power IC using devices that are completely compatible with standard CMOS, using only one type of cell. I can't.

[0004] Applicants have chosen another approach, which has been developed for low speed (high speed and highly integrated)
5 volts) custom digital IC with a single polysilicon layer, N
Type well, high-side and low-side (l) using low cost and sub-micron standard CMOS technology with double metallization.
ow-side) switch placement and whether it is possible to manufacture a smart power IC using a modified structure to obtain an NMOS based side-optimized switching cell at very low cost. evaluated.

[0005] The following list contains all references known to the applicant on this subject. Applicants believe that these references are representative and, in a sense, are considered to be the background of the invention.

[Reference] United States Patent No. 5,386,136 January 1995 Richard Williams et al. (R
Richard Williams et al. ). "Lightly doped drain MOSFET with improved breakdown characteristics ("
Lightly-Doped Drain MOSFET With Impr
oved Breakdown Characteristics ")"

[Other Documents] Balun and M.C. Ducleruk, "High-Voltage Devices and Circuits in Standard CMOS Technology", Kruwer Academic Publishers, Dordrecht,
The Netherlands, 1999 (H. Ballan and M. Declercq "H
high Voltage Devices and Circuits in
Standard CMOS Technologies ”, Kiwer A
Cademic Publishers, Dordrecht, The Net
herlands, 1999).

B. J. Bariga "Overview of Smart Power Technology", IEEE on Electronic Devices
E Report, Vol. 38, No. 7, pp. 1568-1575, July 1991 (B
. J. Baliga "An Overview of Smart Power
Technology ", IEEE Trans. On Electroni.
c Devices, Vol. 38, n. 7, pp. 1568-1575, Ju
1991).

W. Prebuild "Technology, design and application related to integrated smart power circuits"
, 22nd European Solid State Circuit Conference, ESSC IRC'96, Neuchatel, Switzerland, September 17-19, 1996 (W. Pribyl, "Integ").
rated Smart Power Circuits Technology
y, Design and Application ”, in Proceed
ings of the 22nd European Solid-Stat
e Circuits Conference, Esscirc'96, Neu
chatel, Switcherland, 17-19 September 1
996).

A. B. Murati, F. Bertotto, G. A. Vignola (eds.) "Smart Power IC-Technology and Applications", Springer, Berlin, 1996 (A.
B. Murati, F .; Berottoti and G. A. Vignola (
Eds. ), "Smart Power ICs-Technologies
and Applications ", Springer, Berlin, 19
96).

“Smart Power Circuit Markets and Applications”, Electronic Trend Publications, 1996 (“Smart Power Markets and
Applications, "Electronic Trend Public
cations, 1996). A. G. FIG. M. Dorney, O. H. Schade, B.S. Goldsmith, L.A. A. Goodman: Enhanced CM for application to analog-digital power ICs
OS ", IEEE Report on Electronic Devices, ED-33, 1985-1
991, 1986 (AGM Dolny, OH Schade,
B. Goldsmith, and L.M. A. Goodman, "Enhance
d CMOS for analog-digital power ICa
applications, "IEEE Trans. Electron Dev."
ices, vol. ED-33, pp. 1985-1991, 1986).

B. Z. Palpier, C.I. A. T. Salama, R. A. Haddaway, "Modeling and Characterization of High-Voltage Device Structures Compatible with CMOS", IEEE Report on Electronic Devices, ED-34, pp. 2335-2343, 19
1987 (BZ Parpia, C.A.T. Salama and R.A.
Hadaway, "Modelling and characterisat
ion of CMOS-compatible high-voltage
device structures ", IEEE Trans. Electr.
on Devices, vol. ED-34, pp. 2335-2343,19
87. ).

C. T. Efland, T.W. Keller, S.M. Keller, J.A. Rodriguez, "Optimized LDMOS-FET for Compensated 40 Volt Power Using Existing Manufacturing Steps in Submicron CMOS Technology," IEDM Technology Digest, pp. 399-402, 1994 (CT Eland, T. Keller, S. .Kelle
r and J. Rodriguez, "Optimized complete"
entry 40V power LDMOS-FETs using e
xisting fabrication steps in submicror
on CMOS technology ", in IEDM Tech. Dig
. Pp. 1994).

S. Finco, F.C. H. Behrens, M .; I. Castrosimus, "Smart Power ICs for DC-DC Power Regulation", 27th Annual Meeting of the IEEE Society of Industrial Applications, IAS '92, pp. 1204-1121, Houston, Texas, USA, October 1992 (S Finco, FH Behrens,
M. I. Castro Simas, “A Smart Power IC f
or DC-DC Power Regulation ”, in Process
dings IEEE Industrial Applications S
ociety 27th Annual Meeting, IAS'92, pp
. 1204-1121, Houston, Teas, U.S.A. S. A. , Octob
er 1992).

M. I. Castrosimus, J.M. Costa. Freire, S.M. Finco, F.C. H. Behrens, "Modeling and Characterization of NMOS Transistors for LDD and LDSD", The 28th Annual Meeting of the IEEE Society of Industrial Application, IAS'93, 11
83-1189, Toronto, Ontario, Canada, October 1993 (
M. I. Castro Simas, J. et al. Costa Freire, S.M. Fi
nco, F.C. H. Behrens, "Modeling and Charac
teration of LDD and LDSD NMOS Tran
sistors "in Proceedings IEEE Industry
al Applications Society 28th Annual
Meeting, IAS '93, pp. 1183-1189, Toronto,
Ontario, Canada, October 1993).

[Description and Application of the Invention] Hereinafter, description will be made with reference to the drawings. The drawings are essential for explaining the present invention and are intended to facilitate understanding of the present invention. However, the present invention is not limited to the drawings. To evaluate the feasibility of quickly making smart power circuit prototypes, a single layer of polysilicon, intended for the production of high speed, highly integrated, low voltage (5 volt) custom digital circuits, Choose N-well, low cost, sub-micron standard CMOS technology with double metallization,
A smart power IC using a structure modified to obtain a high-side and low-side switch structure and an optimized switching cell on the side based on NMOS (that is, (GSLDD / GSLDSD-NMOS)) is extremely low. Power devices, ie GSLDSD, LDSD, or any other suitable combination of floating transistors, plus integrated or non-integrated passive elements in the same monolithic circuit Can be repeatedly formed to form an array, which can be incorporated into a matrix arrangement. The array can also be used, depending on the required function.
It can be easily programmed with a conventional metal mask.

In addition, circuits suitable for implementing the functions necessary to drive and protect these devices, and the functions necessary to detect and control according to a particular topology for controlling or amplifying power. Is a kind of NM thanks to its technological development
New blocks can be created using only OS cells. By the way, this NMOS cell is mainly GSLDSD or LDSD which is a floating transistor, or LDMOS which is another high-pass transistor. Standard CMOS technology was used to see if this method was feasible. Power device and drive circuit block for efficient drive, such as NMOS
Level shifter, reference voltage source, NMOS rectifier, NMOS-based charge pump, NMOS-based bootstrap, NMOS current source implemented using a matrix based on a programmable NMOS structure did. Only the surface metal mask was used to make the required interconnections.

These optimized NMOS devices, already in mature CMOS technology, have been incorporated into special structures in a matrix arrangement, resulting in a low cost and reliable solution. Furthermore, electronic design automation (EDA)
) Because tools are already available, error-free circuits can be realized in a short design cycle using automatic placement and routing, system and circuit simulators, and standard cell libraries.

The method is therefore very suitable for the design of semi-custom smart power circuits, thus making it possible to quickly produce a smart power circuit prototype using standard CMOS technology without any additional processing steps. It can be seen that the method is also very suitable for. In addition, this concept can be applied to dedicated technology for obtaining a ready-made solution for manufacturing custom ICs with low continuous production costs and short production cycles.

Scope of the Invention The present invention relates to a new strategy for performing semi-custom design of a smart power circuit. In short, the invention implements all the topologies needed for rectification, driving, protection, amplification, detection, and control, can handle high-voltage signals, interfaces with microprocessors, detects defects and processes. Combining only one type of cell as a basic array in a matrix arrangement that is easy to design because it can be easily programmed using only the surface metal mask, depending on the required function, such as enabling the monitoring of On making prototypes faster.

In this manner, a circuit based on the NMOS structure is obtained. In designing this circuit, the circuit is obtained by realizing appropriate interconnections that can be configured using the metal film on the surface in and between the basic cell arrays. In this way, the uniqueness of rapid prototype production of a smart power circuit using not only the CMOS technology but also the technology dedicated to the integrated power circuit is created.

If a prototype of a smart power circuit can be quickly manufactured, it can be immediately applied to low power and intermediate power applications. It has applications in the automotive, robotics, mobile communications and medical device industries, where high reliability and compactness are required.

[Object and Object of the Invention] The present invention relates to a smart monolithic power system (monolithic Sm).
art Power systems), using only the NMOS structure,
The present invention relates to the design and realization of circuits for switching, driving, controlling, amplifying, detecting, and protecting. (A) Providing a programmable matrix-arranged cell library based on an NMOS structure. It uses a convenient means of metal film interconnection,
This is to realize functions required for power conversion and amplification.

(B) Provide a circuit topology capable of realizing necessary functions such as handling a high voltage and controlling, driving, detecting, and protecting a device while using only an NMOS structure. (C) Optimizing LDSD and LDD NMOS transistors using standard CMOS technology, ie, using optimized NMOS devices (GSLDD and GSLDSD) to increase the breakdown voltage to 50 volts As a result, it is possible to extend the breakdown voltage to a voltage range far beyond the limits recognized in the prior art. (D) Substantially reduce the cost of serial production. (E) Reduce the time required for the production cycle without reducing reliability. (F) Enable reuse of functional blocks.

Advantages and Improvements Compared to Existing Methods, Materials and Products The invention described herein covers arrays and matrices of elementary cells. Here, an NMOS structure is used to realize functions generally required for power control, amplification, conversion, and switching. Also,
NMOS devices optimized for voltages that withstand cut-off conditions, ie, GSLDD / GSLDSD NMOS transistors, are also used.

The advantages of the present invention are as follows. A simpler than normally used to fabricate high voltage power devices and implement power control functions to form drain and source electrodes using only NMOS structures with a small amount of dopant diffusion, Alternatively, standard techniques with low complexity can be used.

A single basic electrical model for semiconductor structures can be used to simulate devices and circuits. Without any additional processing, it is possible to produce smart power integrated circuits that are compatible with standard CMOS technology. Microsystems compatible with conventional CMOS technology can be mass-produced without any additional processing. It is consistent with technology trends.
Simply adding a power control circuit library to an existing library opens up the possibility of implementing a smart power circuit using a number of standard CMOS processes that exist on the market.

The production of semi-custom smart power integrated circuits becomes possible. That is, semi-custom smart power integrated circuits can be easily configured with surface metal films using conventional CMOS technology processes that can be used to fabricate semi-custom digital circuits. The possibility of manufacturing semi-custom smart power circuits is created using many specialized technologies for manufacturing smart power circuits. The semi-custom smart power circuit only creates a power control circuit library,
It can be easily configured.

Using any CMOS technology for which a floating NMOS device is available, a smart power integrated circuit prototype can be quickly made. An optimal arrangement for high-voltage transistors compatible with standard CMOS technology can be obtained. The present invention is also applicable to a wider range of voltages than is generally established in standard CMOS technology.

[Detailed Description of the Invention] Hereinafter, the matrix used in the present invention will be described in detail. The basic cells of this matrix are based on optimized NMOS transistors. A technique for optimizing a device by shifting a polysilicon gate mask will also be described in detail. This technology gives rise to GSLDD and GSLDSD NMOS as abbreviations for optimized transistors of this type, which transistors are also part of the present invention.

The proposed circuit is based solely on the NMOS structure, and some of its topologies are also described in detail as an integral part of the present invention. This circuit is in the power control block of the smart power IC, and is a conventional circuit necessary to drive the power switching device, such as a clipper, a clamper, a level shifter, a high voltage floating driver, a charge pump, and a boot. It will be replaced with a strap.

[1. Switching Cell] The switching cell is based on the NMOS structure available in the matrix. Note that the NMOS structure can be formed of a metal film over the surface. There are numerous possible combinations of NMOS structures, and these combinations can be used to implement the most common switch load topologies. For example, high side (FIG. 1), low side (FIG. 1), band pass element (FIG. 1), push-pull (FIG. 2), half bridge (FIG. 2), full bridge (FIG. 3), n-type phase (FIG. 4) ) And other derived topologies are possible.

The matrix consists of an array of NMOS structures, which gives the interconnect properties suitable for the purpose. Although any single NMOS power transistor can generally be used as the unit cell for the matrix and array, in this specification the matrix and array are based on NMOS transistors that can be implemented using conventional CMOS technology. It is assumed that

[1. A. 1 Matrix Consisting of NMOS Structure] The matrix (FIG. 5) includes control signal interconnect channels (intermediate part 2I, side part 2L).
), And an array (1) of an NMOS structure separated by a pad (upper 3T, lower 3B, side 3L, corner 3C). The number of stacks in the NMOS structure and the number of columns in the array depend on the total power of the matrix to be designed.

The interconnection between the drain and the source is made by metal tracks (Metal 2) (4) (FIG. 6) overlaid on the NMOS structure array (1) (FIG. 5). There are a total of six metal tracks for each NMOS structure array, making interconnection more flexible. To connect the drain and source, or to the side pads (5 and 3L) adjacent to the corner between different arrays of NMOS structures, two or three at the top and bottom of the matrix (FIG. 6) The first metallization (upper part 6T, lower part 6B) as a connection track provided here is used. The number of tracks depends on the size of the matrix.

The width of the NMOS structure (1) is calculated such that the sum of the widths of the control signal interconnect channels corresponds to the width required to place the four pads (FIG. 6). Two of these pads are used exclusively for power connection (7A) and the other two are used for control and / or
Or, it is for a power signal (7B). Therefore, the number of pads is determined by the number of arrays, eight for each array, with four at the top and four at the bottom.
The number of pads (FIGS. 5, 3L) on the side of the matrix is lower (3B) and upper (3B).
3T) is the same as the number of pads. Control signal interconnect channels (2I and 2L
) (FIG. 5) is equal to the number of NMOS structure arrays (1) plus one. Therefore, control signal interconnect channels (FIG. 5) are present on both sides of the matrix, and control signal interconnect channels are located on pads (3
L).

[1. A. 2 Possible Interconnections] The interconnections between the NMOS structures and the connections to the pads of the NMOS structures are based on a grid-like shortest connection path determined by the minimum technically possible size and the specific constraints of each matrix. The width of the entire interconnect track in both the first metallization (Metal 1) and the second metallization (Metal 2)
It is a multiple of each track.

The control signal interconnect channel (FIG. 7) is made up of a metal 1 track (12) for horizontal connection and a vertical channel over a predetermined channel (17) (FIG. 7a). And a track (8) made of metal 2 which makes the above connection. For the metal2 / metal1 connection, a series of already existing vias (sets
of vias: 22) is used. These vias connect the first and second metallizations through the thick field oxide.

The interconnection by the matrix having such a pre-processed configuration is made up of a rectangular metal 2 inserted between the connection terminal group of the NMOS structure (16E) and the connection terminal group of the interconnection channel (16C), (8) consisting of two tracks (8)
Figure 7b). This allows vertical connections for access, such as channels (FIG. 5) or pads (3T, 3L) connecting the upper (6T) and lower (6B).
3B), or to lower the current level, the switching cells are locally interconnected to form a predetermined circuit topology.

In order to connect to the metal 2 tracks in the vertical channels, a small conductive path from the nearest via (22) needs to be added horizontally in this metallization. It is made of a rectangular metal (12) and has a number of vias (22) to form a metal 2 (21)
Are connected to the NMOS structure (16E) and the interconnect channel (16C).
) (FIG. 7b), interconnect the gate (16P), drain (16D), source (16F), metal 1 tracks (12) extending from the guard ring (11) of the NMOS structure. It can be connected to the horizontal metal 1 track (12) of the channel (FIGS. 7a and 7b).

The metal channel 1 track (12) of the interconnect channel is adjacent to the channel 2
The two NMOS structures are cut off in the middle so that they can be accessed independently (12I, FIG. 7a). The interconnect channels provide both horizontal interconnection between elementary cells in different arrays and vertical interconnection between elementary cells in the same array. Each control channel has two polysilicon resistors (2
There is 3). This polysilicon has a higher resistance than the polysilicon used to make the gate of the transistor, and its typical value is 45Ω / □ (
Figure 7a). The resistor (23) has a pair of contacts (2
3C) between different metal 1 tracks (12) (FIG. 7).
a).

P⁺Due to the ground plane (24) (FIG. 5) formed by the diffusion of
Any potential closed loop can be eliminated. Also for control
This P below the interconnect channel⁺The diffusion track (24) (FIG. 7b)
P located below the conductive channels at the top (6T) and bottom (6B) of the ricks⁺
Alternatingly connected to trucks.

[1. A. 3. Basic NMOS Structure] The basic NMOS structure consists of two LDSD (lightly doped source and drain) transistors juxtaposed (FIG. 8). These two transistors share only the protection ring (11) in which P ⁺ is diffused, and can be used separately. The protection ring also surrounds the whole (FIG. 8).

The internal connection to the NMOS structure is made by a plurality of metal 1 tracks provided horizontally across the entire NMOS structure. These tracks are NMOS
It is connected to the source (10) and drain (13) of the structure (FIG. 8), the majority of which are due to the connection of metal 1 / diffusion regions, which can be achieved by techniques according to layout rules. It is connected to the N ⁺ diffusion region. This method aims at reducing the contact resistance and making the current distribution along the terminals of the transistor uniform. In order to connect the metal 2 tracks (4) to the metal 1 tracks at the correct angles, 5-7 sets of vias (15) (FIG. 8) are provided as appropriate vias in a technically feasible manner. Current is less than the maximum current handled by this NMOS structure. The horizontal connection of adjacent arrays and / or extra-matrix arrays is via vias (16E) located at the ends of metal 1 tracks on either side of the NMOS structure (FIG. 7b). The gate electrode has at least two vias (
16P) (FIG. 7a), which creates redundancy and makes this connection more robust and has a lower resistance. Drain electrode (16D)
And the source electrode (16F) (FIG. 7a) has four or more vias with sufficient current capacity to allow the maximum current to be handled by a single NMOS structure.

The connection (18) from the gate of the transistor to the interconnect channel (FIGS. 7a and 8)
) Are made on both sides of the NMOS structure to facilitate pad access. By doing so, it is possible to clear the technical restriction that the metal 1 / polysilicon contact cannot generally be placed on the active region of the transistor.
On the polysilicon track of the gate, an extra connection terminal made of metal 1
Present along the NMOS structure.

In the substantially closed ring structure (FIG. 8), the source (10) of the external transistor and the protection ring (11) in which P ⁺ is diffused surround the whole. for that reason,
As in the case of the input / output protection structure provided in association with the I / O pad, it is less susceptible to occasional electrostatic discharge. This protection ring (11
) (FIG. 8) are shared by adjacent NMOS structures in the array. Metal 1 tracks may be added between the NMOS structures to provide another path for control signal interconnects.

The feature of the NMOS structure used is that the side transistors with lightly doped regions (due to the possible diffusion of lightly doped impurities into the CMOS technology process) have drain and source regions. Is that the peak value of the electric field on the surface below the gate oxide film in the passage of the current flowing through both of them is reduced. Thus, a pair of elementary LDSD devices used as low impedance bandpass transistors both have a floating drain electrode and a floating source electrode, and therefore both electrodes can withstand sufficiently higher voltages than the substrate. it can.

The LDSD NMOS transistor used is designed in consideration of the breakdown voltage.
Optimized by shifting the gate mask relative to the lightly doped well mask. By doing so, the effect of reducing the peak value of the electric field on the surface increases. Thus, the GSLDSD based on the basic LDSD transistor
A device called is obtained. GSLDSD is a gate-shifted L
Abbreviation for DSD, used as a low-impedance band-pass transistor. Therefore, the floating drain electrode and floating source electrode of this transistor can withstand a higher voltage than the substrate. This structure is described in detail in the next paragraph.

[1. B. GSLDD / GSLDSD NMOS Transistor] One feature of the gate-shifted LDSD or gate-shifted LDSD (GSLDD or GSLDSD) NMOS transistor is that the gate electrode has an N-type side diffusion region (31) as in CMOS technology. And that they are aligned. This is shown in FIG.

FIG. 9 is a cross-sectional view of an example of a basic NMOS structure including a GS-NMOS transistor. This structure can be obtained without changing the manufacturing process in any conventional CMOS technology of diffusing an N-type well into a P-type substrate. The source / drain (27) is an N ⁺ diffusion region (28) in which a high concentration impurity is diffused.
Consists of This region is commonly used as the drain and source of standard NMOS transistors known in the prior art. A low concentration impurity is diffused into the prior art N-well (26), which is typically used as the substrate of a PMOS transistor known in the prior art. The impurity concentration of the N-type well is the same as that of the substrate, but is slightly higher than that of the substrate.
Between the N ⁺ diffusion region (28) and the channel of the device, carriers
Across the drift region under the field oxide (29) formed by a process commonly known as COS (local oxidation of silicon), the end of the metal junction of the N-type well diffusion region (26) is reached.

The original arrangement of the gate (32) is claimed, and the conventional N
Avalanche amplification causes dielectric breakdown at much higher voltages than in MOS transistors and classic LDSD transistors. A polysilicon gate (32) is overlaid on the gate oxide (30), which is as thin as several hundred angstroms. The end of the gate (32) is connected to the side diffusion region (31) of the N-type well (26).
) Above and next to the source / drain (27) (in a classic LDSD transistor, it is exactly aligned with the mask of an N-type well) so that it can be used in a conventional NMOS transistor or a classical LDSD transistor. At higher voltages, it is possible to reach the critical electric field of silicon which causes device breakdown. Therefore, the layout of the mask of this device and the mask of the N-type well made of polysilicon never overlap, and the applicant has stated,
It is separated by what it proposes to call a "gate shift."
The term "gate shift" has given rise to the name of a gate-shifted NMOS, or GS-NMOS, proposed as a semiconductor device of this type. The structure discussed here is based on a classic LDSD transistor and is described above. The semiconductor device having the same gate structure as that described above is hereinafter referred to as a gate-shifted LDSD NMOS, that is, a GSLDSD NMOS.

[0052] As the distance between the masks increases, the breakdown voltage of the transistor increases. If the distance is not so great that the edge of the gate no longer overlaps the side diffusion region (31), the formation of the channel will be reliably prevented.
To increase the breakdown voltage as technically as possible without affecting channel formation in the device, gate shift tolerances of several hundred nanometers will be required, depending on the technology used. .

The configuration of the drain (35) of the GSLDSD is in all respects a source / drain (
It is the same as the configuration of 27), and it is desirable that the gate shift is on both the source / drain (27) side and the drain (35) side. If the device is symmetrical at the time of disconnection, the same voltage endurance is obtained on both the drain and source sides. Therefore, this device has characteristics of a high-side transistor. It should be noted that in manufacturing, it is important to strictly control the distance between adjacent N-type wells (26) and (37) to an acceptable minimum value. The distance between the diffusion regions must be adjusted according to the distance between the rectangular sections that determine the size of the diffusion region in the N-type well mask so that the device does not punch through. .

In the NMOS structure having the low-side transistor, the source of the GS-NMOS transistor may be constituted only by the N ⁺ diffusion region (39). This transistor is hereinafter referred to as GSLDD NMOS. This is because this transistor is based on the classic configuration of an LDD NMOS.
In this case, the source electrode (40) has a high impurity concentration commonly used for the drain and source diffusion regions of the PMOS transistor known in the prior art due to the first metal level known in the prior art. Through a terminal (42) connected to the P ⁺ diffusion region (41), it can be electrically connected to the substrate (25). With this configuration, the maximum allowable voltage in the off state is the same as that obtained by GSLDSD.

Utilizing the gate shift technology requires a GS compared to a general LDSD device.
This means that the on-state resistance of the LDSD device increases. Because
This is because it is necessary to lengthen a path through which carriers flow between the drain electrode and the end of the gate. In short, the breakdown voltage of the GSLDD / GSLDSD device is lower than that of the classical LDD / LDSD device because there is a well side diffusion region below the gate edge where the impurity concentration is much lower than the well surface. Higher than in. Thus, the electric field will spread because it will be in much less doped regions than in classical devices, resulting in much higher drain-source voltage values than before.

[2. Circuit based on NMOS structure] This is a circuit necessary for power control, that is, driving of a power device.
Provides rectification, clipping, clamping, adjustment, voltage level shifting, charge pump, and bootstrap functions. Examples of the topologies of these circuits, which are based on the NMOS structure and which claim to be novel, are described below. For the NMOS structure, basically, the LDSD NMOS transistor described in 1 is used. Examples of topologies for manufacturing this circuit using LDMOS transistors are also described. In the LDSD NMOS transistor, the body (P type) matches the substrate, whereas in the LDMOS transistor, the body (P type) is connected to the corresponding source, and the P type is the same as the drain electrode and the source electrode. It must be emphasized that the substrate becomes floating with respect to the substrate.

If the NMOS structure used is based on an LDSD NMOS transistor, the structure is represented by a symbol with four terminals. Then, the main body is inevitably connected to the substrate. If the NMOS structure used is based on an LDMOS transistor, the fourth terminal (of the body) will necessarily be connected to the source of this transistor. If the function of this circuit does not depend on the type of transistor, the transistor is represented by a three-terminal symbol, and the terminal of the transistor body is omitted.

[2. A. Zener Circuit and Zener Rectifier] A rectifier diode or a zener diode (FIG. 10) is used in a circuit for rectification, clipping, clamping, and adjustment, and its function is to make an NMOS structure a predetermined topology. Can emulate. Most NMOS structures have a control block (for driving NMOS transistors).
FIG. 11) is required. In many circuit topologies, the desired function is realized by using a parasitic diode unique to the NMOS structure. The control circuit usually includes two control blocks. One is an analog / digital control block. This block utilizes conventional circuitry and control techniques and is connected to the ground of this circuitry and operates at low voltage. The other is an output block of this control circuit.
This is a G-gain amplifier, which may include either a low-side transistor or a high-side transistor, and provides appropriate levels of voltage and current to operate this control circuit. 11a and 11b are circuit diagrams of the control circuit described above.

[2. A. 1 Zener Circuit] The Zener circuit (FIGS. 12 and 13) has the same function as the Zener diode realized by the PN junction (FIG. 10B). To realize a zener circuit (LDSD type in FIG. 12 and LDMOS type in FIG. 13) using NMOS transistors, N
The drain electrode (49), the gate electrode (50), and the source electrode (51) of the MOS structure (52/60) are connected to an electric control circuit (45/5) connected to the ground (56).
Connect to 4). Note that in general, the control circuit for the LDSD structure is different from the control circuit for the LDMOS structure. However, the operation principle is the same, and the LDSD transistor will be described below.

The operation of the control circuit (45) is programmable and operates as follows. That is, by controlling the voltage value between the gate G (50) and the source S (51) of the NMOS structure (52), the voltage value between the drain D (49) and the source S (51) is changed to a desired Zener voltage value. To To program this value in the Zener circuit, an analog or digital reference signal Ref is input as a voltage or current to the reference signal input (46) of the control circuit.

The control circuit (45) monitors the voltage between the drain (49) and the source (51).
Acts on the gate (50) of the NMOS structure, and the NMOS transistor (47)
) Controls the on-state resistance value. Between the drain D (49) and the source S (51)
Voltage value V_DSIf the control value exceeds the programmed value, the control circuit
By improving the conductivity of (47), V_DSIs maintained at a predetermined value. V_DS
Is lower than the value programmed in the control circuit, the NMOS structure (52)
No power is consumed internally and the current in the zener circuit takes a minimum value. This
This should be the same value as the bias current of the control circuit.

[2. A. 2. Rectifier Circuit] The operation of the rectifier diode (FIG. 10a) and the operation of the combination of the rectifier diode and the zener diode (FIG. 10c) are described in FIGS. 14 and 10 if the sizes of the transistors of the NMOS structures (52) and (60) are correct. 15, and emulated by the clipping circuit of FIGS.

The operation of the series-connected rectifier diode and zener diode shown in FIG. 10C is performed by a control unit (45) including an amplifier (G) and a monitor control circuit (FIG. 11).
) Can be reproduced. This circuit, as shown in FIG.
This can be realized by using the NMOS structure (52) based on the D NMOS transistor. This circuit can also be realized based on the LDMOS transistor for the NMOS structure shown in FIG. In this case, a similar control unit (54) is used.

An NMOS structure (52) based on an LDSD type NMOS transistor is:
Must operate floating within specifications. The drain electrode, gate electrode, and source electrode of the transistor in the NMOS structure configured as a diode are:
It must always operate at a positive voltage with respect to the ground terminal GND (56). The drive circuit G in the control circuit (45) includes a source (51) and a gate (50) controlled by a voltage applied between the equivalent anode (A ') (49) and the equivalent cathode (K') (51). By applying a sufficient voltage in between, it functions to reduce the impedance of the NMOS structure (52). In fact, the voltage of A '(49) is K' (5
When the voltage becomes larger than the voltage of 1), the control circuit performs an operation of emulating the forward biased diode. On the other hand, when the voltage of A '(49) is K' (51)
When the voltage becomes lower than the voltage of ()), the control circuit operates to set the transistor (47) to the cutoff state. This is equivalent to a diode under reverse bias. In many applications where the effect of a diode is required, the G gain control circuit (45) operating at a low voltage is not necessary, and as shown in FIGS. 16 and 17, between the drain (49) and the gate (50), or Drain (49) and source (5
It is reduced to a short circuit between 1).

[2. B level shifter] The level shifter frequently used in the smart power circuit includes a high-voltage PMOS or PNP transistor and a high-voltage NMOS or N as shown in FIG.
A PN transistor is used. The low impedance paths are activated alternately.

The claimed topology emulates a level shifter and implements two low impedance paths using only NMOS structures, as shown in FIGS. 19 and 20. This NMOS structure includes an NMOS transistor (7
8, 79, 80), resistors R1 and R2, a Zener diode DZ, and a rectifier diode DR. The resistor R2, the Zener diode DZ, the rectifier diode DR, or some of them can be omitted in some configurations, and thus various circuits suitable for a particular application can be manufactured.

The control signal (71) acts on the circuits D 1 and D 2 of the interface block (70) to drive the NMOS high voltage transistors (78) and (79). The relative delay time and the maximum current value and voltage value in the circuits D1 and D2 are respectively specially designed according to the application. In some applications, the interface block (
70) are connected in parallel with each other to form a single interface circuit (G
1 = G2).

In this paragraph, the operation of the circuit of FIG. 19 will be described. The control signal (71) has a logical value of 1
At this time, the transistors (78) and (79) are conducting, and the transistor (80)
) Is off because the voltage value of the gate (81) is almost at the ground potential (74). A low impedance OUT path (73) to the ground terminal (74) is realized by the transistor (79). When the control signal (71) has a logical value of 0, the transistors (78) and (79) have a high impedance, and the gate (81) of the transistor (80) has the lowest voltage value of V _z = HV × R2 / (R1 + R2). become. Then, the transistor (80) is connected to the HV terminal (7
A low impedance path is formed between 2) and the output OUT terminal (73). This condition, HV × R2 / (R1 + R2) -V T (80) ie _V Z _-V T (8
0) corresponds to the output voltage OUT (73) lower than 0). Note that V _T (
80) is the conduction threshold voltage between the gate and the source of the transistor (80).

In this paragraph, the function of the circuit in FIG. 19 when the configuration is such that the resistor R2 is omitted will be described. In FIG. 19, the cathode of the Zener diode or Zener circuit indicated by reference symbol DZ is the gate (81) of the transistor (80) and the ground terminal GND.
When connected between the (74), the Zener circuit limit, operates in the same manner as described above, the final value of the output voltage OUT (73) _is a V _Z -V T (80) Will be done. This value is independent of the value HV of the supply voltage (72) (H
If V is greater than _{V Z).}

When the resistor R2 and the Zener diode DZ are removed from the circuit, the output voltage O
The maximum value of the final value of UT (73) is limited to _HV-V T (80). Therefore, this final value under the conditions described above will depend on the supply voltage (72) from the HV.

The circuit topology claimed herein can be fabricated using high voltage NMOS transistors of the LDSD NMOS type (FIG. 19) or LDMOS type (FIG. 20). The level shifter circuit manufactured using the LDMOS transistor also includes the diode DR in the topology. FIG. 19 and FIG.
This element must be included for both topologies shown to work the same, so that when the transistor (79) is off, the output terminal O
The voltage of the UT (73) can take a value larger than HV.

The final output voltage OUT (73) of the claimed circuit is at the high side position (
In FIG. 18), which is slightly lower than a circuit made using PMOS or PNP transistors, this circuit can be used in a great many applications requiring level shifter circuits. As explained above, the ability to program the maximum final output voltage of the claimed topology is an advantage over the conventional topology shown in FIG.

The level shifter circuit (77) shown in FIGS. 19 and 20 also operates as a continuous voltage level shifter as shown in FIG. For example, if the control signal input terminal (71) is always connected to GND (74) in a special configuration, the output value OUT will be the voltage value programmed in the Zener circuit, that is, H
The voltage value is limited to a voltage value proportional to V. In this configuration, the circuit operates as an auxiliary continuous voltage source based on HV. This configuration can be used as an auxiliary power source in a charge pump circuit or a bootstrap circuit. Regarding this point, 2. C. 1 and 2. C. This will be described in 2.

[2. C drive circuit] [2. C. 1 Capacitor Type Charge Pump Circuit] FIGS. 22 and 23 show the operation principle of the capacitor type charge pump circuit. The basic circuit of FIG. 22a comprises at least two rectifiers, two capacitors and an auxiliary voltage source _VA.
LS is powered from _UX (level shifter) interface circuit (77
). Input signal CLK (8) to the LS interface circuit (77)
0) comes from the clock (81). This clock usually produces a small amplitude rectangular wave. The output signal (82) of the LS interface circuit (77) is
It depends on the size of the circuit and the characteristics of the NMOS structure used, and the value is V
_AUX or less. A capacitor _CTK can be connected across both ends (84) and (85) of the rectifier diode connected in series. This is indicated by the dotted line. Alternatively, the capacitor _CTK can be connected between the output terminal (85) and the ground terminal GND (74). Which one to use depends on the application.

FIG. 22 b shows the response course of the circuit when an ideal element is used, ie when the saturation voltage of the LS interface circuit is zero and an ideal rectifier is used (
The vertical axis indicates voltage, and the horizontal axis indicates time). In this case, when the pump cycle ends several _times, the voltage _{V G} of the both ends of the _{C TK is} directed to _{2V AUX.} This type of circuit is known as a voltage doubler circuit and is often used in both discrete and integrated circuits.

In order to design the charge pump circuit as accurately as possible, the voltage value between the drain and source of the NMOS transistors (79) and (80) of the LS interface circuit (77) (FIG. 20) and the voltage of the rectifier diode It is necessary to consider the drop, the charge loss of the capacitor, and the loss when connecting the elements. Normally, the LS interface circuit (77) includes an auxiliary voltage source V _AUX (83) based on the high voltage source HV.
Is supplied with power. The auxiliary voltage source _V AUX (83) is by changing the signal in the LS interface circuit (77) output _(82), as soon as possible _{C TK,} yet provides sufficient voltage to charge as efficiently as possible.

As shown in FIG. 21, the LS interface circuit composed of the high-voltage device shown in FIGS. 19 and 20 is directly _supplied from the high-voltage source HV or from the auxiliary voltage source V _AUX based on the HV. Power supply. These circuits are L
Since the output amplitude (82) from the S interface circuit (77) is extremely diversified, the capacitance needs to be smaller than that of a circuit manufactured using a logic CMOS cell.
In these circuits, the semiconductor device can be designed such properties of the final output voltage V _G of the charge pump circuit to the output voltage of the LS interface circuit (77) is reflected.

A multi-stage circuit realized using this principle has a final voltage value V
_G becomes a value obtained by multiplying the value obtained by adding 1 to the number of stages and V _AUX . This circuit is commonly known as a voltage multiplier. FIG. 23 shows a voltage tripler circuit. This circuit, compared to the circuit of FIG.
(77), an additional stage consisting of a diode D3 and an additional capacitor _CPP2 , but operates similarly. Circuit fabricated in an ideal device, the final voltage value V _G is,
It becomes 3 × V _AUX . With an actual device, the voltage V _G is slightly smaller than this value for the loss as described above.

The operating principle of the charge pump circuit has been described with reference to FIGS. 22A and 23. The charge pump circuit can be configured as a floating voltage source. The anode of the diode D1 disconnected from V _AUX becomes the negative pole of the floating voltage source FPS, and the cathode of the diode D2 in FIG. 22A or the cathode of the diode D3 in FIG. 23 becomes a positive pole. A capacitor C _TK can be connected between the negative pole (84) and the positive pole (85) or between the positive pole (85) and the ground (74) of the power source. This type of circuit (FPS) is a current source used to generate a voltage higher than the supply voltage from the high voltage circuit and to inject current into the gate of a high side or low side NMOS power transistor. Often used to supply power. About this, 2. C. This will be described in 2.

FIGS. 24, 25 and 26 show some examples of topologies claimed herein. These topologies operate as floating voltage sources and utilize only NMOS structures. In other words, the rectifier diode and the zener diode are used for 2. A is configured as described above. The interface circuits used are: B and 2C. The capacitors may or may not be integrated. Basically, these circuits are LDSD or LDMO
A level shifter circuit having an NMOS structure including an S NMOS transistor is used. The basic structure is shown in FIG. 27, from which the topology of the charge pump circuit claimed in this specification can easily be obtained.

[2. C. 2 Capacitor Bootstrap Circuit] FIG. 28a shows a typical capacitor bootstrap circuit described in the literature.
4 shows an electric circuit layout. This circuit typically comprises a capacitor C_Bo
ot(93) and interface circuits BH (91) and BL (99) (BH
And BL are respectively the buffer high side and the buffer low side) and the resistor R_B
oot(92), a control transistor MC (98), and two power transistors
The star ML (89) and the MH (88). The operation of this circuit is a capacitor
C_Boot(93) is determined based on the electric charge accumulated, and a sufficient voltage
They are kept between children. Therefore, the interface circuit BH (9
Power is supplied in a floating state to 1), and this interface
The circuit BH functions as a drive circuit for the NMOS power transistor MH (88),
The on state of this transistor is controlled. The drain of the transistor MC (98)
And resistor R_BootOne terminal of (92) is connected to the interface circuit BH (91
) Is connected to the input to form a level shifter. Capacitor C_Boot
The negative terminal of the floating voltage source formed by (93)
MH (88) is connected to the source electrode (90). Supply voltage V_AUX(9
5) is usually higher than the supply voltage to this logic circuit, but a pair of power transistors
The high voltage power supply HV (10) that determines the output level of the star MH (88) and ML (89)
It can be lower than the voltage of 1). V_AUX(95) Explained in B
As described above, it can be generated based on a high voltage power supply. The value is
V so that the transistor MH (88) becomes fully conductive._GS(MH) to (102)
It must be appropriate for the voltage applied.

The capacitor-type bootstrap circuit is generally used in applications where the operating frequency is determined and the control signal C _trl (97) is periodic. To explain the function of this circuit, consider the cycle of the control signal C _trl (97) in FIG. 28b, clearly divided into three phases. Hereinafter, the state of this circuit will be described for each phase.

[Phase 1: Charging of Capacitor C _Boot ] In this phase, the control signal C _trl (97) is at the high level, and the conduction of the power transistors MC (98) and ML (89) is guaranteed. In this phase, the capacitor C _Boot (93) is charged to approximately the voltage value of V _AUX (95) through the diode D1 (94). Power transistor MC (98)
While the is conducting, the interface circuit BH (91) keeps the high-side transistor MH (88) cut off and the transistor ML (89) cuts the low impedance path V _out (90) to ground (100). Form. Therefore, the capacitor C _Boot (93) is charged.

[Phase 2: Start of Bootstrap Operation] This phase is characterized in that the state is changed by the control signal C _trl (97). That is, the control signal C _trl (97) changes from the logical value 1 to 0. At this stage, the transistors ML (89) and MC (98) are cut off, and the input signal of the interface circuit BH (91) remains at the potential of the plus terminal of the capacitor C _Boot (93). Therefore, the output signal (102) of the BH interface (91) becomes this voltage, and the MH transistor (88) becomes conductive. The voltage V _out (90) increases with the current flowing in the load and reaches the final value HD-V _DS (MH). The voltage across the terminals of the capacitor C _Boot (93) is kept substantially constant while the transistor MH (88) is conducting. The voltage value V _G (102) of the gate of the transistor MH (88) is substantially equal to HV−V
_Ds (MH) -V _AUX is reached. During this period, the polarity of the diode D1 (94) is reversed and the diode D1 (94) is insulated from the power supply V _AUX (95).

[Phase 3: Free Conduction State of Transistor MH] In this phase, the transistor MH (88) starts free conduction. While the transistor MH (88) is conducting, the capacitor C _Boot (93) is discharged to supply current to the drive circuit (91) of the transistor MH (88). The maximum amount of time that this phase lasts is that the capacitor C _Boot (93) continues to supply sufficient voltage to the interface circuit BH (91), which in turn causes the interface circuit BH (91) to turn on the transistor MH. The voltage at the gate of (88) is maintained, so that it depends on how long transistor MH (88) can remain conductive. Capacitor C _Bo
Note that the discharge of _ot (93) is due to the transfer of charge to the gate of transistor MH (88) and losses caused by parasitic elements. Normally,
The size of the capacitor C _Boot (93) is designed so that the voltage on this capacitor is reduced by only 10% during an operating cycle.

The circuit shown in FIG. 28a is suitable for applications where the operating frequency is well-defined. This is because it is necessary to determine an appropriate capacity and operating frequency of the capacitor C _Boot (93) for each circuit. This technique has the advantage that it is simple and allows the transistor MH (88) to perform a rectifying function at a high frequency while using only a small number of high voltage elements. However, transistors ML (89) and M
Since an undesirable situation can occur in which both H (88) conduct simultaneously,
Limited to a few applications. Based on this, a circuit with more sophisticated control can avoid simultaneous conduction, so it is very necessary to make the transistors included in the high side full bridge and half bridge configuration rectify. Often used [13].

FIG. 29 shows a different topology than the circuit of FIG. 28, which is claimed herein to be novel. In this topology, only NMOS transistors are used. 2. The NMOS level shifter block (77) described in B provides the functions required for the interface BH (91) in FIG. 28a. FIG.
29A and the control circuit (96) of the bootstrap circuit shown in FIG. 29 can be programmed to drive the transistor ML (89) and then to drive the transistor MH (88) with an appropriate delay. Both can be prevented from conducting simultaneously. The diode D1 (94) has two components: It can be manufactured as described in A, or using a PN junction that can withstand high voltages in some process.

FIG. 30 a shows another topology for manufacturing a capacitor-type bootstrap circuit for controlling the conduction of the NMOS power transistor MH (88). To configure this circuit includes a capacitor _C Boot (93), a resistor _{R B
out} (92) and two level shifter interfaces LS1 (77A) and LS2 (77B) are required. As the level shifter, for example, 2. The level shifter (77) described in B is used. For this application, interface LS1 (77A) is programmed to reach a final voltage V _AUX (95). This is due to the fact that transistor MH (88) is fully conducting
_This is a voltage value to be applied to _GS (MH). The interface LS2 (77B) has an output voltage between the drain of the transistor MH (88) and the interface LS.
HV (72) supplying voltage to both 1 (77A) and LS2 (77B)
Program to reach a value as close as possible to (101 in FIG. 28a). FIG. 30B shows the control signal C _trl (71), the output voltage V _out (90), and the transistor MH (8) for one cycle of turning on and off the transistor MH (88).
It is a graph which shows the time change of the gate voltage (73) (102 of FIG. 28a) of 8). For further consideration, the cycle was divided into three phases as before.

In phase 1, the transistor MH (88) is off. The signals A (71A) and A '(71A') input to the interfaces LS1 (77A) and LS2 (77B) are at the same time at 1 level, and the output is low ground potential (
74) (100 in FIG. 28a). The voltage V _GS (MH) between the gate (73) and the source (90) of the transistor MH (88) is almost zero, and almost no current flows in the load Z _Load (104).

Phase 2 has two different phases. The first stage is the capacitor C _Boo
This corresponds to charging to _t (93). This occurs immediately after the control signal A (71) changes from the logical value 1 to the logical value 0. At this stage, 2. As described in B, the output of interface LS1 (77A) provides the energy to charge capacitor C _Boot (93) to the potential programmed into interface LS1 (V _AUX ). At the same time, a capacitor equivalent to the capacitor effect between the gate and the source of the transistor MH (88) is connected to the interface LS1 (77A).
) Output. The signal A ′ (71A ′) is output to the interface LS
1 (77A) and LS2 (77B) to charge the capacitor C _Boot (93) and remain at logic 1 for a time Δt sufficient to reach the voltage value determined for this layout, so that the transistor MH (88) becomes conductive. After the time Δt, the signal A ′ changes from the logical value 1 to the logical value 0, and the second phase of this phase starts. This second stage involves the voltage V _G (102)
It is characterized by Here, the negative terminal of the capacitor C _Boot (93) is set to the potential of the source of the transistor MH (88) through the resistor R _Boot (92). Therefore, the voltage V _GS (MH) is almost equal to the voltage of the capacitor C _Boot (93), and the high voltage source HV (72) supplies the maximum current to the load Z _Load (104) through the transistor MH (88).

Phase 3 of the operation of this circuit involves, as shown in FIG. 30b, the voltage V _G (73)
Signal A and the signal A ′ become logical 0 after the signal reaches almost the final value of HV + V _AUX.
It is characterized by staying in. This phase continues until signal A and signal A ′ simultaneously change from logic 0 to logic 1 and consequently capacitor C _Boot (
93) is discharged, and the transistor MH (88) is cut off. This characterizes the initial state of the new cycle. The level shifter LS1 (7
Note that the output levels of 7A) and LS2 (77B) are achieved by using NMOS transistors capable of output voltages greater than the supply voltage HV (72) to these interfaces.

As in the circuit of FIG. 29, a transistor ML (89) can be added to the circuit of FIG. 30a. In this case, the transistor ML (89) has a low-side configuration and the source (90) of the transistor MH (88) and the ground GND (74).
And control directly by the control circuit.

[2. D Floating Current Source] A current source is often used to control charging and discharging of an equivalent input capacitor _CGS of a power transistor that supplies power to an external load. It not control it or to release the charge from the capacitor or injecting charge into the capacitor C _GS to or to cut off or to conduct the transistors, but the circuit using a current source as a means for its control When used, control and switching can be performed using algorithms optimized for the type of charge supplied. High-voltage NMO by technology for manufacturing integrated smart power devices
Although an S transistor and a high-voltage PMOS transistor are manufactured, the presence of the high-voltage PMOS transistor manufactured by the technique makes it easy to manufacture a current source that supplies a current to the high-side transistor.

FIG. 31 shows a power device (High-Side t) of a high-side topology.
1 shows an example of a typical circuit that utilizes a floating current source (106) to inject current into an opposition power device (88) to render the device conductive. Another current source is connected to ground. The output level of this current source is determined by the transistor M4 (108), and is used to discharge the gate of the transistor MH (88) to cut off the transistor MH (88).

A current source manufactured in MOS technology is basically intended to control a voltage V _GS applied to a transistor. When the transistor is operating in the saturation region, the drain current of the transistor will be almost completely dependent on _VGS . Generally, the reference current source is formed by an analog circuit configured using a low-voltage transistor connected to the GND terminal (100). The current generated in (109) is accurately copied by a circuit composed of N-type (108 and 110) and P-type (111 and 112) MOS transistors and NPN bipolar transistors (113) operating at high voltage. You. In the circuit shown in FIG.
. As described in C, the capacitor C _{Boot of the} bootstrap circuit is used as a floating voltage source FPS that supplies power to the current source (106). Another option is already 2. C. One would use the capacitor type charge pump shown in FIG.

The present application claims a topology of a current source having a function of injecting and discharging a current in both a high-side transistor and a low-side transistor configured using only the NMOS structure. Among the various topologies possible,
FIG. 32 shows a topology for operating as a current source circuit by injecting a current into the gate of the NMOS transistor MH (88) in a high-side configuration.

[0097] 2. As already described in A, it is possible to fabricate a circuit that emulates the operation of a floating Zener diode using an NMOS structure. The value of the zener voltage of this circuit can be dynamically programmed using a low voltage control circuit. Also, 2. As already described in B, the floating current source can be manufactured using only the NMOS structure.

In FIG. 32, a group of elements is a floating current source (
121). The output of this current source (121) is connected to the gate (102) of the MH (88) and is used to inject current and make the transistor MH (88) conductive. Circuit (122) connected to ground (100)
Constitute a current source. The purpose of this current source is to pass the current through the transistor MH (88
) To make this transistor cut off.

The floating current source (121) basically includes a Zener circuit represented by DZP (115), a high-voltage transistor represented by MI (117), and a resistor R
I (116). These elements are powered by a floating voltage source (118) represented by FPS. The negative terminal of this power source is
V (101). The power source FPS (118) has an amplitude on the order of 10 volts. Element DZP (115) represents a programmable zener circuit with a control circuit connected to GND terminal (100). The function of this Zener circuit is to maintain the voltage V _GS (MI) at a predetermined program value and control the current injected into the gate (102) of the transistor MH (88) according to an algorithm determined according to the application. It is. It is important to emphasize that the control circuit acting on the Zener circuit (115) determines the value of the current flowing into the high voltage transistor MI (117). In particular, it is possible to generate a voltage in the Zener circuit DZP (115) so that no current flows into the high voltage transistor MI (117). The resistor RI (116) is typically a large value resistor whose function is to change the polarity of the Zener circuit DZP (115) to change the floating current source (121) to the sum of the voltages HV + V (FPS). That is, the potential is set based on the potential.

While current is injected into the gate (102) of the transistor MH (88), the transistor MI (117) operates as a current source. In the meantime, block (1
22) The switch CH1 (119) is open and the transistor M5 (120)
Has no influence on the gate of the transistor MH (88). While discharging from the gate (102) of the transistor MH (88), the Zener circuit D
As the voltage value of ZP (115) changes, the current flowing through transistor MH (88) decreases or goes to zero. Current source connected to ground (122)
Operates when the transistor MH (88) is in a cut-off state. Switch C
H1 (119) is turned off, and transistor M5 (120) is turned off by transistor MH.
Discharge is started from the gate (102) of (88). Therefore, the MH (88) is cut off as desired.

[Brief description of the drawings]

FIG. 1 is a diagram showing a general switching cell for realizing a power device topology.

FIG. 2 is a diagram showing a general switching cell for realizing a power device topology.

FIG. 3 is a diagram showing a general switching cell for realizing a power device topology.

FIG. 4 is a diagram showing a general switching cell for realizing a power device topology.

FIG. 5 shows the general matrix arrangement of the switching structure, in particular the spatial layout of the NMOS structure and the array, the location of the control signal and power interconnect channels, and the location of the pads.

FIG. 6 shows the details of the matrix, and in particular the metal 2 tracks covering the NMOS structures near the pads, focusing on the connection pads of the array.

FIG. 7a shows a control signal interconnect channel and shows a network of vias (metal1 / metal2 connections), metal tracks and polysilicon resistors.

7B is a cross-sectional view taken along the line A-A 'in FIG. 7A.

FIG. 8 is a diagram showing an example of a basic NMOS structure in which LDSD transistors are juxtaposed.

FIG. 9 is a cross-sectional view showing an example of an optimized basic cell proposed in the present invention based on a GSLDD / GSLDSD NMOS transistor.

FIG. 10a is a diagram showing a rectifier diode and its current characteristic curve I (V).

FIG. 10b is a diagram showing a Zener diode and its current characteristic curve I (V).

FIG. 10c is a diagram showing a rectifier diode connected in series with a zener diode, and a current characteristic curve I (V) thereof.

FIG. 11 is a control circuit for emulating a Zener diode and a rectifier diode,
FIG. 3 is a diagram illustrating an example of a control circuit in which a plurality of circuits are integrated.

FIG. 12 is a diagram showing an example of an NMOS structure emulating the operation of the floating zener circuit of FIG. 10B, which is reconfigured based on an NMOS transistor of LDSD.

FIG. 13 is a diagram showing an example of an NMOS structure emulating the operation of the floating zener circuit of FIG. 10b, which is reconfigured based on an LDMOS transistor.

FIG. 14 is a diagram illustrating an example of an NMOS structure emulating the operation of the series-connected rectifier diode and zener diode of FIG. 10c, which is reconfigured based on an NMOS transistor of LDSD.

FIG. 15 is a diagram showing an example of an NMOS structure emulating the operation of the series-connected rectifier diode and zener diode of FIG. 10c, which is reconfigured based on an LDMOS transistor.

FIG. 16 is an NMOS structure emulating the operation of the rectifier diode of FIG. 10a,
FIG. 4 is a diagram illustrating an example of an NMOS structure reconfigured based on an LDSD NMOS transistor.

FIG. 17 is an NMOS structure emulating the operation of the rectifier diode of FIG. 10a,
FIG. 3 is a diagram illustrating an example of an NMOS structure reconfigured based on an LDMOS transistor.

FIG. 18 is a diagram showing an example of a classic level shifter circuit disclosed in the literature, which is a circuit using a high-side high-voltage transistor in a PMOS (or PNP bipolar type).

FIG. 19 is a diagram showing an example of a level shifter circuit which is a circuit having a topology in which a high-voltage PMOS (or PNP bipolar transistor) is not used at a high side position and uses only NMOS transistors of LDSD.

FIG. 20 is a diagram illustrating an example of a level shifter circuit using only LDMOS transistors, although a diode DR is added in comparison with FIG. 19;

FIG. 21 is a diagram illustrating an example of a level shifter circuit that operates as an auxiliary continuous voltage source supplied with a voltage from the HV and functions as a continuous voltage level shifter in this configuration.

FIG. 22a illustrates an example of a typical capacitor-type charge pump that functions as a voltage doubler.

It is a diagram illustrating a voltage change at the capacitor _{C TK} in Figure 22b Figure 22a.

FIG. 23 illustrates an example of a typical capacitor charge pump that functions as a voltage tripler.

FIG. 24 illustrates an example of a charge pump that functions as a voltage doubler that can be realized using an NMOS structure.

FIG. 25 illustrates an example of a typical capacitor-type charge pump that functions as a voltage tripler that can be implemented using an NMOS structure.

26 is a diagram showing a charge pump that can be realized by using an NMOS structure, which functions as a floating voltage source based on the topology of FIG. 23 and has a rectifier bridge as an output; It is a figure showing an example.

FIG. 27 is a diagram showing an example of a basic circuit that can be realized by using an NMOS structure from which a charge pump topology that claims to be novel can be obtained.

FIG. 28a illustrates an example of a typical bootstrap circuit.

FIG. 28B is a diagram showing a time change of a control signal, an output, and a gate voltage during a transition of the power transistor MH to turn on and turn off.

FIG. 29 is a diagram illustrating an example of a bootstrap circuit that can be realized using an NMOS structure.

FIG. 30a is a diagram showing an example of a bootstrap circuit for a power device based on a high-side topology NMOS.

FIG. 30b is a diagram showing various waveforms during a transition of the power transistor MH between turn-on and turn-off.

FIG. 31 is a diagram showing an example of a standard floating current source for supplying a current to a power device having a high-side topology.

FIG. 32 is a diagram illustrating an example of a floating current source that can be realized by using an NMOS structure.

[Procedure amendment]

[Submission date] January 9, 2001 (2001.1.9)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Contents of correction]

Patent application title: Smart power circuit capable of changing mask configuration, application thereof, and GS-NMOS device

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

SUMMARY OF THE INVENTION The present invention provides a smart power circuit suitable for implementing the general functions required of a power control block, utilizing an array based on only one type of NMOS cell. It is about an important improvement when designing into a matrix. With this technology, a low-cost semi-custom design and a new IC configuration strategy that can be easily industrialized without any additional processing process, toward the digital integration of smart power circuits using standard CMOS technology. Becomes possible. This method can also be applied to the technology for rapidly producing sophisticated smart power circuit prototypes.

BACKGROUND OF THE INVENTION Advances in smart power circuits have been associated with the development of new technological processes, requiring digital and analog libraries. It should be noted that the potential of the new technological process depends on the exact characterization and availability of the power device, so a sophisticated and costly technical process is needed. With such sophisticated technologies, various types of semiconductors have been produced. To illustrate, to a small extent, N-MOS, P-MOS, HV-NMOS (
High-Voltage NMOS: High-voltage NMOS, HV-PMOS (High-Voltage PMOS: High-voltage PMOS), Field-effect transistor (NPN, PNP, HV-PNP, HV-
NPN), bipolar junction transistors (BJT, Zener diode, rectifier diode), IGBT, and MOS thyristor.

[0003] Research is actively under way around the world to find solutions that are compatible with CMOS technology. However, with any approach, it is not possible to achieve the functions required for the power control block in a smart power IC using devices that are completely compatible with standard CMOS, using only one type of cell. I can't.

[0004] Applicants have chosen another approach, which has been developed for low speed (high speed and highly integrated)
5 volts) custom digital IC with a single polysilicon layer, N
Mold well, high-side and low-side using low-cost and submicron standard CMOS technology with double metallization
It was evaluated whether it is possible to manufacture a smart power IC using a structure modified to obtain a switch arrangement of No. 1 and an optimized switching cell based on NMOS based on an extremely low cost.

[0005] The following list contains all references known to the applicant on this subject. Applicants believe that these references are representative and, in a sense, are considered to be the background of the invention.

[Reference] United States Patent No. 5,386,136 January 1995 Richard Williams et al. (Ri
chard Williams et al.). "Lightly doped drain MOSFET with improved breakdown characteristics (" L
ightly-Doped Drain MOSFET With Improved Breakdown Characteristics ")"

[Other Documents] Balun and M.C. Ducleruk, "High-Voltage Devices and Circuits in Standard CMOS Technology", Kruwer Academic Publishers, Dordrecht,
The Netherlands, 1999 (H. Ballan and M. Declercq "High Voltage Devices an
d Circuits in Standard CMOS Technologies ", Kiuwer Academic Publishers, D
ordrecht, The Netherlands, 1999).

B. J. Bariga "Overview of Smart Power Technology", IEEE on Electronic Devices
E Report, Vol. 38, No. 7, pp. 1568-1575, July 1991 (B.
J. Baliga "An Overview of Smart Power Technology", IEEE Trans. On Elect
ronic Devices, Vol. 38, n.7, pp. 1568-1575, July 1991).

W. Prebuild "Technology, design and application related to integrated smart power circuits"
, 22nd European Solid State Circuit Conference, ESSC IRC '96, Neuchatel, Switzerland, September 17-19, 1996 (W. Pribyl, "Integrated Smart P
ower Circuits Technology, Design and Application ", in Proceedings of the
22nd European Solid-State Circuits Conference, ESSCIRC'96, Neuchatel, S
witzerland, 17-19 September 1996).

A. B. Murati, F. Bertotto, G. A. Vignola (eds.) "Smart Power IC-Technology and Applications", Springer, Berlin, 1996 (A.B.
Murati, F. Bertotti and GA Vignola (Eds.), "Smart Power ICs-Techn
Technologies and Applications ", Springer, Berlin, 1996).

"Smart Power Markets and Applications", Electronic Trend Publications, 1996 ("Smart Power Markets and Applications", Electronic
Trend Publications, 1996). A. G. FIG. M. Dorney, O. H. Schade, B.S. Goldsmith, L.A. A. Goodman: Enhanced CM for application to analog-digital power ICs
OS ", IEEE Report on Electronic Devices, ED-33, 1985-1
Page 991, 1986 (AGM Dolny, OH Schade, B. Goldsmith, an
d LA Goodman, "Enhanced CMOS for analog-digital power IC applications
, "IEEE Trans. Electron Devices, vol. ED-33, pp. 1985-1991, 1986).

B. Z. Palpier, C.I. A. T. Salama, R. A. Haddaway, "Modeling and Characterization of High-Voltage Device Structures Compatible with CMOS", IEEE Report on Electronic Devices, ED-34, pp. 2335-2343, 19
87 (BZ Parpia, CAT Salama and RA Hadaway, "Modeling and
characterisation of CMOS-compatible high-voltage device structures ", IEE
E Trans. Electron Devices, vol.ED-34, pp. 2335-2343, 1987.
).

C. T. Efland, T.W. Keller, S.M. Keller, J.A. Rodriguez, "Optimized LDMOS-FET for Compensated 40 Volt Power Using Existing Manufacturing Steps in Submicron CMOS Technology," IEDM Technology Digest, pp. 399-402, 1994 (CT Efland, T. Keller, S. Keller and J. Rodriguez, "
Optimized complementary 40 V power LDMOS-FETs using existing fabrication
steps in submicron CMOS technology ", in IEDM Tech. Dig., pp. 1994).

S. Finco, F.C. H. Behrens, M .; I. Castrosimus, "Smart Power IC for DC-DC Power Regulation," The 27th Annual Meeting of the IEEE Society of Industrial Applications, IAS '92, pp. 1204-1121, Houston, Texas, USA, October 1992 (S Finco, FH Behrens, MI Castro Si
mas, "A Smart Power IC for DC-DC Power Regulation", in Proceedings IEEE
Industrial Applications Society 27th Annual Meeting, IAS '92, pp. 1204-1
211, Houston, Teas, USA, October 1992).

M. I. Castrosimus, J.M. Costa. Freire, S.M. Finco, F.C. H. Behrens, "Modeling and Characterization of NMOS Transistors for LDD and LDSD", The 28th Annual Meeting of the IEEE Society of Industrial Application, IAS'93, 11
83-1189, Toronto, Ontario, Canada, October 1993 (
MI Castro Simas, J. Costa Freire, S. Finco, FH Behrens, "Modeling
and Characterization of LDD and LDSD NMOS Transistors "in Proceedings IE
EE Industrial Applications Society 28th Annual Meeting, IAS '93, pp. 118
3-1189, Toronto, Ontario, Canada, October 1993).

[Description and Application of the Invention] Hereinafter, description will be made with reference to the drawings. The drawings are essential for explaining the present invention and are intended to facilitate understanding of the present invention. However, the present invention is not limited to the drawings. To evaluate the feasibility of quickly making smart power circuit prototypes, a single layer of polysilicon, intended for the production of high speed, highly integrated, low voltage (5 volt) custom digital circuits, Choose N-well, low cost, sub-micron standard CMOS technology with double metallization,
A smart power IC using a structure modified to obtain a high-side and low-side switch structure and an optimized switching cell on the side based on NMOS (that is, (GSLDD / GSLDSD-NMOS)) is extremely low. Power devices, ie GSLDSD, LDSD, or any other suitable combination of floating transistors, plus integrated or non-integrated passive elements in the same monolithic circuit Can be repeatedly formed to form an array, which can be incorporated into a matrix arrangement. The array can also be used, depending on the required function.
It can be easily programmed with a conventional metal mask.

In addition, circuits suitable for implementing the functions necessary to drive and protect these devices, and the functions necessary to detect and control according to a particular topology for controlling or amplifying power. Is a kind of NM thanks to its technological development
New blocks can be created using only OS cells. By the way, this NMOS cell is mainly GSLDSD or LDSD which is a floating transistor, or LDMOS which is another high-pass transistor. Standard CMOS technology was used to see if this method was feasible. Power device and drive circuit block for efficient drive, such as NMOS
Level shifter, reference voltage source, NMOS rectifier, NMOS-based charge pump, NMOS-based bootstrap, NMOS current source implemented using a matrix based on a programmable NMOS structure did. Only the surface metal mask was used to make the required interconnections.

These optimized NMOS devices, already in mature CMOS technology, have been incorporated into special structures in a matrix arrangement, resulting in a low cost and reliable solution. Furthermore, electronic design automation (EDA)
) Because tools are already available, error-free circuits can be realized in a short design cycle using automatic placement and routing, system and circuit simulators, and standard cell libraries.

The method is therefore very suitable for the design of semi-custom smart power circuits, thus making it possible to quickly produce a smart power circuit prototype using standard CMOS technology without any additional processing steps. It can be seen that the method is also very suitable for. In addition, this concept can be applied to dedicated technology for obtaining a ready-made solution for manufacturing custom ICs with low continuous production costs and short production cycles.

Scope of the Invention The present invention relates to a new strategy for performing semi-custom design of a smart power circuit. In short, the invention implements all the topologies needed for rectification, driving, protection, amplification, detection, and control, can handle high-voltage signals, interfaces with microprocessors, detects defects and processes. Combining only one type of cell as a basic array in a matrix arrangement that is easy to design because it can be easily programmed using only the surface metal mask, depending on the required function, such as enabling the monitoring of On making prototypes faster.

In this manner, a circuit based on the NMOS structure is obtained. In designing this circuit, the circuit is obtained by realizing appropriate interconnections that can be configured using the metal film on the surface in and between the basic cell arrays. In this way, the uniqueness of rapid prototype production of a smart power circuit using not only the CMOS technology but also the technology dedicated to the integrated power circuit is created.

If a prototype of a smart power circuit can be quickly manufactured, it can be immediately applied to low power and intermediate power applications. It has applications in the automotive, robotics, mobile communications and medical device industries, where high reliability and compactness are required.

[Object and Object of the Invention] The present invention relates to a monolithic smart power system.
The present invention relates to the design and realization of circuits for switching, driving, controlling, amplifying, detecting, and protecting using only the NMOS structure. (A) Providing a programmable matrix-arranged cell library based on an NMOS structure. It uses a convenient means of metal film interconnection,
This is to realize functions required for power conversion and amplification.

(B) Provide a circuit topology capable of realizing necessary functions such as handling a high voltage and controlling, driving, detecting, and protecting a device while using only an NMOS structure. (C) Optimizing LDSD and LDD NMOS transistors using standard CMOS technology, ie, using optimized NMOS devices (GSLDD and GSLDSD) to increase the breakdown voltage to 50 volts As a result, it is possible to extend the breakdown voltage to a voltage range far beyond the limits recognized in the prior art. (D) Substantially reduce the cost of serial production. (E) Reduce the time required for the production cycle without reducing reliability. (F) Enable reuse of functional blocks.

Advantages and Improvements Compared to Existing Methods, Materials and Products The invention described herein covers arrays and matrices of elementary cells. Here, an NMOS structure is used to realize functions generally required for power control, amplification, conversion, and switching. Also,
NMOS devices optimized for voltages that withstand cut-off conditions, ie, GSLDD / GSLDSD NMOS transistors, are also used.

The advantages of the present invention are as follows. A simpler than normally used to fabricate high voltage power devices and implement power control functions to form drain and source electrodes using only NMOS structures with a small amount of dopant diffusion, Alternatively, standard techniques with low complexity can be used.

A single basic electrical model for semiconductor structures can be used to simulate devices and circuits. Without any additional processing, it is possible to produce smart power integrated circuits that are compatible with standard CMOS technology. Microsystems compatible with conventional CMOS technology can be mass-produced without any additional processing. It is consistent with technology trends.
Simply adding a power control circuit library to an existing library opens up the possibility of implementing a smart power circuit using a number of standard CMOS processes that exist on the market.

The production of semi-custom smart power integrated circuits becomes possible. That is, semi-custom smart power integrated circuits can be easily configured with surface metal films using conventional CMOS technology processes that can be used to fabricate semi-custom digital circuits. The possibility of manufacturing semi-custom smart power circuits is created using many specialized technologies for manufacturing smart power circuits. The semi-custom smart power circuit only creates a power control circuit library,
It can be easily configured.

Using any CMOS technology for which a floating NMOS device is available, a smart power integrated circuit prototype can be quickly made. An optimal arrangement for high-voltage transistors compatible with standard CMOS technology can be obtained. The present invention is also applicable to a wider range of voltages than is generally established in standard CMOS technology.

[Detailed Description of the Invention] Hereinafter, the matrix used in the present invention will be described in detail. The basic cells of this matrix are based on optimized NMOS transistors. A technique for optimizing a device by shifting a polysilicon gate mask will also be described in detail. This technology gives rise to GSLDD and GSLDSD NMOS as abbreviations for optimized transistors of this type, which transistors are also part of the present invention.

The proposed circuit is based solely on the NMOS structure, and some of its topologies are also described in detail as an integral part of the present invention. This circuit is in the power control block of the smart power IC, and is a conventional circuit necessary to drive the power switching device, such as a clipper, a clamper, a level shifter, a high voltage floating driver, a charge pump, and a boot. It will be replaced with a strap.

[1. Switching Cell] The switching cell is based on the NMOS structure available in the matrix. Note that the NMOS structure can be formed of a metal film over the surface. There are numerous possible combinations of NMOS structures, and these combinations can be used to implement the most common switch load topologies. For example, high side (FIG. 1), low side (FIG. 1), band pass element (FIG. 1), push-pull (FIG. 2), half bridge (FIG. 2), full bridge (FIG. 3), n-type phase (FIG. 4) ) And other derived topologies are possible.

The matrix consists of an array of NMOS structures, which gives the interconnect properties suitable for the purpose. Although any single NMOS power transistor can generally be used as the unit cell for the matrix and array, in this specification the matrix and array are based on NMOS transistors that can be implemented using conventional CMOS technology. It is assumed that

[1. A. 1 Matrix Consisting of NMOS Structure] The matrix (FIG. 5) includes control signal interconnect channels (intermediate part 2I, side part 2L).
), And an array (1) of an NMOS structure separated by a pad (upper 3T, lower 3B, side 3L, corner 3C). The number of stacks in the NMOS structure and the number of columns in the array depend on the total power of the matrix to be designed.

The interconnection between the drain and the source is made by metal tracks (Metal 2) (4) (FIG. 6) overlaid on the NMOS structure array (1) (FIG. 5). There are a total of six metal tracks for each NMOS structure array, making interconnection more flexible. To connect the drain and source, or to the side pads (5 and 3L) adjacent to the corner between different arrays of NMOS structures, two or three at the top and bottom of the matrix (FIG. 6) The first metallization (upper part 6T, lower part 6B) as a connection track provided here is used. The number of tracks depends on the size of the matrix.

The width of the NMOS structure (1) is calculated such that the sum of the widths of the control signal interconnect channels corresponds to the width required to place the four pads (FIG. 6). Two of these pads are used exclusively for power connection (7A) and the other two are used for control and / or
Or, it is for a power signal (7B). Therefore, the number of pads is determined by the number of arrays, eight for each array, with four at the top and four at the bottom.
The number of pads (FIGS. 5, 3L) on the side of the matrix is lower (3B) and upper (3B).
3T) is the same as the number of pads. Control signal interconnect channels (2I and 2L
) (FIG. 5) is equal to the number of NMOS structure arrays (1) plus one. Therefore, control signal interconnect channels (FIG. 5) are present on both sides of the matrix, and control signal interconnect channels are located on pads (3
L).

[1. A. 2 Possible Interconnections] The interconnections between the NMOS structures and the connections to the pads of the NMOS structures are based on a grid-like shortest connection path determined by the minimum technically possible size and the specific constraints of each matrix. The width of the entire interconnect track in both the first metallization (Metal 1) and the second metallization (Metal 2)
It is a multiple of each track.

The control signal interconnect channel (FIG. 7) is made up of a metal 1 track (12) for horizontal connection and a vertical channel over a predetermined channel (17) (FIG. 7a). And a track (8) made of metal 2 which makes the above connection. The metal 2 / metal 1 connection has a set of existing vias (sets of
vias: 22) is used. These vias connect the first and second metallizations through the thick field oxide.

The interconnection by the matrix having such a pre-processed configuration is made up of a rectangular metal 2 inserted between the connection terminal group of the NMOS structure (16E) and the connection terminal group of the interconnection channel (16C), (8) consisting of two tracks (8)
Figure 7b). This allows vertical connections for access, such as channels (FIG. 5) or pads (3T, 3L) connecting the upper (6T) and lower (6B).
3B), or to lower the current level, the switching cells are locally interconnected to form a predetermined circuit topology.

In order to connect to the metal 2 tracks in the vertical channels, a small conductive path from the nearest via (22) needs to be added horizontally in this metallization. It is made of a rectangular metal (12) and has a number of vias (22) to form a metal 2 (21)
Are connected to the NMOS structure (16E) and the interconnect channel (16C).
) (FIG. 7b), interconnect the gate (16P), drain (16D), source (16F), metal 1 tracks (12) extending from the guard ring (11) of the NMOS structure. It can be connected to the horizontal metal 1 track (12) of the channel (FIGS. 7a and 7b).

The metal channel 1 track (12) of the interconnect channel is adjacent to the channel 2
The two NMOS structures are cut off in the middle so that they can be accessed independently (12I, FIG. 7a). The interconnect channels provide both horizontal interconnection between elementary cells in different arrays and vertical interconnection between elementary cells in the same array. Each control channel has two polysilicon resistors (2
There is 3). This polysilicon has a higher resistance than the polysilicon used to make the gate of the transistor, and its typical value is 45Ω / □ (
Figure 7a). The resistor (23) has a pair of contacts (2
3C) between different metal 1 tracks (12) (FIG. 7).
a).

The presence of the ground plane (24) (FIG. 5) formed by the diffusion of P.sup. ⁺ Eliminates any closed loops that may cause noise. Further, the P ⁺ diffusion track under the control interconnect channel (24) (FIG. 7b) are located beneath the conductive channel in the the bottom (6B) top of the matrix (6T) P ⁺
Alternatingly connected to trucks.

[1. A. 3. Basic NMOS Structure] The basic NMOS structure consists of two LDSD (lightly doped source and drain) transistors juxtaposed (FIG. 8). These two transistors share only the protection ring (11) in which P ⁺ is diffused, and can be used separately. The protection ring also surrounds the whole (FIG. 8).

The internal connection to the NMOS structure is made by a plurality of metal 1 tracks provided horizontally across the entire NMOS structure. These tracks are NMOS
Connected to the source (10) and drain (13) of the structure (FIG. 8), the majority of which is due to the connection of metal 1 / diffusion regions, which is possible with layout-based techniques. It is connected to the N ⁺ diffusion region. This method aims at reducing the contact resistance and making the current distribution along the terminals of the transistor uniform. In order to connect the metal 2 tracks (4) to the metal 1 tracks at the correct angles, 5-7 sets of vias (15) (FIG. 8) are provided as appropriate vias in a technically feasible manner. Current is less than the maximum current handled by this NMOS structure. The horizontal connection of adjacent arrays and / or extra-matrix arrays is via vias (16E) located at the ends of metal 1 tracks on either side of the NMOS structure (FIG. 7b). The gate electrode has at least two vias (
16P) (FIG. 7a), which creates redundancy and makes this connection more robust and has a lower resistance. Drain electrode (16D)
And the source electrode (16F) (FIG. 7a) has four or more vias with sufficient current capacity to allow the maximum current to be handled by a single NMOS structure.

The connection (18) from the gate of the transistor to the interconnect channel (FIGS. 7a and 8)
) Are made on both sides of the NMOS structure to facilitate pad access. By doing so, it is possible to clear the technical restriction that the metal 1 / polysilicon contact cannot generally be placed on the active region of the transistor.
On the polysilicon track of the gate, an extra connection terminal made of metal 1
Present along the NMOS structure.

In the substantially closed ring structure (FIG. 8), the source (10) of the external transistor and the protection ring (11) in which P ⁺ is diffused surround the whole. for that reason,
As in the case of the input / output protection structure provided in association with the I / O pad, it is less susceptible to occasional electrostatic discharge. This protection ring (11
) (FIG. 8) are shared by adjacent NMOS structures in the array. Metal 1 tracks may be added between the NMOS structures to provide another path for control signal interconnects.

The feature of the NMOS structure used is that the side transistors with lightly doped regions (due to the possible diffusion of lightly doped impurities into the CMOS technology process) have drain and source regions. Is that the peak value of the electric field on the surface below the gate oxide film in the passage of the current flowing through both of them is reduced. Thus, a pair of elementary LDSD devices used as low impedance bandpass transistors both have a floating drain electrode and a floating source electrode, and therefore both electrodes can withstand sufficiently higher voltages than the substrate. it can.

The LDSD NMOS transistor used is designed in consideration of the breakdown voltage.
Optimized by shifting the gate mask relative to the lightly doped well mask. By doing so, the effect of reducing the peak value of the electric field on the surface increases. Thus, the GSLDSD based on the basic LDSD transistor
A device called is obtained. GSLDSD is a gate-shifted L
Abbreviation for DSD, used as a low-impedance band-pass transistor. Therefore, the floating drain electrode and floating source electrode of this transistor can withstand a higher voltage than the substrate. This structure is described in detail in the next paragraph.

[1. B. GSLDD / GSLDSD NMOS Transistor] One feature of the gate-shifted LDSD or gate-shifted LDSD (GSLDD or GSLDSD) NMOS transistor is that the gate electrode has an N-type side diffusion region (31) as in CMOS technology. And that they are aligned. This is shown in FIG.

FIG. 9 is a cross-sectional view of an example of a basic NMOS structure including a GS-NMOS transistor. This structure can be obtained without changing the manufacturing process in any conventional CMOS technology of diffusing an N-type well into a P-type substrate. The source / drain (27) is an N ⁺ diffusion region (28) in which a high concentration impurity is diffused.
Consists of This region is commonly used as the drain and source of standard NMOS transistors known in the prior art. A low concentration impurity is diffused into the prior art N-well (26), which is typically used as the substrate of a PMOS transistor known in the prior art. The impurity concentration of the N-type well is the same as that of the substrate, but is slightly higher than that of the substrate.
Between the N ⁺ diffusion region (28) and the channel of the device, carriers
Across the drift region under the field oxide (29) formed by a process commonly known as COS (local oxidation of silicon), the end of the metal junction of the N-type well diffusion region (26) is reached.

The original arrangement of the gate (32) is claimed, and the conventional N
Avalanche amplification causes dielectric breakdown at much higher voltages than in MOS transistors and classic LDSD transistors. A polysilicon gate (32) is overlaid on the gate oxide (30), which is as thin as several hundred angstroms. The end of the gate (32) is connected to the side diffusion region (31) of the N-type well (26).
) Above and next to the source / drain (27) (in a classic LDSD transistor, it is exactly aligned with the mask of an N-type well) so that it can be used in a conventional NMOS transistor or a classical LDSD transistor. At higher voltages, it is possible to reach the critical electric field of silicon which causes device breakdown. Therefore, the layout of the mask of this device and the mask of the N-type well made of polysilicon never overlap, and the applicant has stated,
It is separated by what it proposes to call a "gate shift."
The term "gate shift" has given rise to the name of a gate-shifted NMOS, or GS-NMOS, proposed as a semiconductor device of this type. The structure discussed here is based on a classic LDSD transistor and is described above. The semiconductor device having the same gate structure as that described above is hereinafter referred to as a gate-shifted LDSD NMOS, that is, a GSLDSD NMOS.

[0052] As the distance between the masks increases, the breakdown voltage of the transistor increases. If the distance is not so great that the edge of the gate no longer overlaps the side diffusion region (31), the formation of the channel will be reliably prevented.
To increase the breakdown voltage as technically as possible without affecting channel formation in the device, gate shift tolerances of several hundred nanometers will be required, depending on the technology used. .

The configuration of the drain (35) of the GSLDSD is in all respects a source / drain (
It is the same as the configuration of 27), and it is desirable that the gate shift is on both the source / drain (27) side and the drain (35) side. If the device is symmetrical at the time of disconnection, the same voltage endurance is obtained on both the drain and source sides. Therefore, this device has characteristics of a high-side transistor. It should be noted that in manufacturing, it is important to strictly control the distance between adjacent N-type wells (26) and (37) to an acceptable minimum value. The distance between the diffusion regions must be adjusted according to the distance between the rectangular sections that determine the size of the diffusion region in the N-type well mask so that the device does not punch through. .

In the NMOS structure having the low-side transistor, the source of the GS-NMOS transistor may be constituted only by the N ⁺ diffusion region (39). This transistor is hereinafter referred to as GSLDD NMOS. This is because this transistor is based on the classic configuration of an LDD NMOS.
In this case, the source electrode (40) has a high impurity concentration commonly used for the drain and source diffusion regions of the PMOS transistor known in the prior art due to the first metal level known in the prior art. Through a terminal (42) connected to the P ⁺ diffusion region (41), it can be electrically connected to the substrate (25). With this configuration, the maximum allowable voltage in the off state is the same as that obtained by GSLDSD.

Utilizing the gate shift technology requires a GS compared to a general LDSD device.
This means that the on-state resistance of the LDSD device increases. Because
This is because it is necessary to lengthen a path through which carriers flow between the drain electrode and the end of the gate. In short, the breakdown voltage of the GSLDD / GSLDSD device is lower than that of the classical LDD / LDSD device because there is a well side diffusion region below the gate edge where the impurity concentration is much lower than the well surface. Higher than in. Thus, the electric field will spread because it will be in much less doped regions than in classical devices, resulting in much higher drain-source voltage values than before.

[2. Circuit based on NMOS structure] This is a circuit necessary for power control, that is, driving of a power device.
Provides rectification, clipping, clamping, adjustment, voltage level shifting, charge pump, and bootstrap functions. Examples of the topologies of these circuits, which are based on the NMOS structure and which claim to be novel, are described below. For the NMOS structure, basically, the LDSD NMOS transistor described in 1 is used. Examples of topologies for manufacturing this circuit using LDMOS transistors are also described. In the LDSD NMOS transistor, the body (P type) matches the substrate, whereas in the LDMOS transistor, the body (P type) is connected to the corresponding source, and the P type is the same as the drain electrode and the source electrode. It must be emphasized that the substrate becomes floating with respect to the substrate.

If the NMOS structure used is based on an LDSD NMOS transistor, the structure is represented by a symbol with four terminals. Then, the main body is inevitably connected to the substrate. If the NMOS structure used is based on an LDMOS transistor, the fourth terminal (of the body) will necessarily be connected to the source of this transistor. If the function of this circuit does not depend on the type of transistor, the transistor is represented by a three-terminal symbol, and the terminal of the transistor body is omitted.

[2. A. Zener Circuit and Zener Rectifier] A rectifier diode or a zener diode (FIG. 10) is used in a circuit for rectification, clipping, clamping, and adjustment, and its function is to make an NMOS structure a predetermined topology. Can emulate. Most NMOS structures have a control block (for driving NMOS transistors).
FIG. 11) is required. In many circuit topologies, the desired function is realized by using a parasitic diode unique to the NMOS structure. The control circuit usually includes two control blocks. One is an analog / digital control block. This block utilizes conventional circuitry and control techniques and is connected to the ground of this circuitry and operates at low voltage. The other is an output block of this control circuit.
This is a G-gain amplifier, which may include either a low-side transistor or a high-side transistor, and provides appropriate levels of voltage and current to operate this control circuit. 11a and 11b are circuit diagrams of the control circuit described above.

[2. A. 1 Zener Circuit] The Zener circuit (FIGS. 12 and 13) has the same function as the Zener diode realized by the PN junction (FIG. 10B). To realize a zener circuit (LDSD type in FIG. 12 and LDMOS type in FIG. 13) using NMOS transistors, N
The drain electrode (49), the gate electrode (50), and the source electrode (51) of the MOS structure (52/60) are connected to an electric control circuit (45/5) connected to the ground (56).
Connect to 4). Note that in general, the control circuit for the LDSD structure is different from the control circuit for the LDMOS structure. However, the operation principle is the same, and the LDSD transistor will be described below.

The operation of the control circuit (45) is programmable and operates as follows. That is, by controlling the voltage value between the gate G (50) and the source S (51) of the NMOS structure (52), the voltage value between the drain D (49) and the source S (51) is changed to a desired Zener voltage value. To To program this value in the Zener circuit, an analog or digital reference signal Ref is input as a voltage or current to the reference signal input (46) of the control circuit.

The control circuit (45) monitors the voltage between the drain (49) and the source (51), acts on the gate (50) of the NMOS structure, and controls the NMOS transistor (47).
) Controls the on-state resistance value. When the voltage value V _DS between the drain D (49) and the source S (51) exceeds the programmed value, the control circuit turns on the transistor (
47) The conductivity is improved so that V _DS is maintained at a predetermined value. If V _DS is lower than the value programmed in the control circuit, no power is consumed inside the NMOS structure (52) and the current in the zener circuit takes a minimum value. this is,
It should be the same value as the bias current of the control circuit.

[2. A. 2. Rectifier Circuit] The operation of the rectifier diode (FIG. 10a) and the operation of the combination of the rectifier diode and the zener diode (FIG. 10c) are described in FIGS. 14 and 10 if the sizes of the transistors of the NMOS structures (52) and (60) are correct. 15, and emulated by the clipping circuit of FIGS.

The operation of the series-connected rectifier diode and zener diode shown in FIG. 10C is performed by a control unit (45) including an amplifier (G) and a monitor control circuit (FIG. 11).
) Can be reproduced. This circuit, as shown in FIG.
This can be realized by using the NMOS structure (52) based on the D NMOS transistor. This circuit can also be realized based on the LDMOS transistor for the NMOS structure shown in FIG. In this case, a similar control unit (54) is used.

An NMOS structure (52) based on an LDSD type NMOS transistor is:
Must operate floating within specifications. The drain electrode, gate electrode, and source electrode of the transistor in the NMOS structure configured as a diode are:
It must always operate at a positive voltage with respect to the ground terminal GND (56). The drive circuit G in the control circuit (45) includes a source (51) and a gate (50) controlled by a voltage applied between the equivalent anode (A ') (49) and the equivalent cathode (K') (51). By applying a sufficient voltage in between, it functions to reduce the impedance of the NMOS structure (52). In fact, the voltage of A '(49) is K' (5
When the voltage becomes larger than the voltage of 1), the control circuit performs an operation of emulating the forward biased diode. On the other hand, when the voltage of A '(49) is K' (51)
When the voltage becomes lower than the voltage of ()), the control circuit operates to set the transistor (47) to the cutoff state. This is equivalent to a diode under reverse bias. In many applications where the effect of a diode is required, the G gain control circuit (45) operating at a low voltage is not necessary, and as shown in FIGS. 16 and 17, between the drain (49) and the gate (50), or Drain (49) and source (5
It is reduced to a short circuit between 1).

[2. B level shifter] The level shifter frequently used in the smart power circuit includes a high-voltage PMOS or PNP transistor and a high-voltage NMOS or N as shown in FIG.
A PN transistor is used. The low impedance paths are activated alternately.

The claimed topology emulates a level shifter and implements two low impedance paths using only NMOS structures, as shown in FIGS. 19 and 20. This NMOS structure includes an NMOS transistor (7
8, 79, 80), resistors R1 and R2, a Zener diode DZ, and a rectifier diode DR. The resistor R2, the Zener diode DZ, the rectifier diode DR, or some of them can be omitted in some configurations, and thus various circuits suitable for a particular application can be manufactured.

The control signal (71) acts on the circuits D 1 and D 2 of the interface block (70) to drive the NMOS high voltage transistors (78) and (79). The relative delay time and the maximum current value and voltage value in the circuits D1 and D2 are respectively specially designed according to the application. In some applications, the interface block (
70) are connected in parallel with each other to form a single interface circuit (G
1 = G2).

In this paragraph, the operation of the circuit of FIG. 19 will be described. The control signal (71) has a logical value of 1
At this time, the transistors (78) and (79) are conducting, and the transistor (80)
) Is off because the voltage value of the gate (81) is almost at the ground potential (74). A low impedance OUT path (73) to the ground terminal (74) is realized by the transistor (79). When the control signal (71) has a logical value of 0, the transistors (78) and (79) have high impedance, and the gate (81) of the transistor (80) has the lowest voltage value of V _Z = HV × R2 / (R1 + R2). become. Then, the transistor (80) is connected to the HV terminal (7
A low impedance path is formed between 2) and the output OUT terminal (73). This state is represented by HV × R2 / (R1 + R2) −V _T (80), that is, V _Z −V _T (80
) Is lower than the output voltage OUT (73). Note that V _T (8
0) is the conduction threshold voltage between the gate and the source of the transistor (80).

In this paragraph, the function of the circuit in FIG. 19 when the configuration is such that the resistor R2 is omitted will be described. In FIG. 19, the cathode of the Zener diode or Zener circuit indicated by reference symbol DZ is the gate (81) of the transistor (80) and the ground terminal GND.
When connected between the (74), the Zener circuit limit, operates in the same manner as described above, the final value of the output voltage OUT (73) is a V _Z -V _T (80) Will be done. This value is independent of the value HV of the supply voltage (72) (HV
Is greater than V _Z ).

When the resistor R2 and the Zener diode DZ are removed from the circuit, the output voltage O
The maximum value of the final value of UT (73) is limited to HV-V _T (80). Therefore, this final value under the conditions described above will depend on the supply voltage (72) from the HV.

The circuit topology claimed herein can be fabricated using high voltage NMOS transistors of the LDSD NMOS type (FIG. 19) or LDMOS type (FIG. 20). The level shifter circuit manufactured using the LDMOS transistor also includes the diode DR in the topology. FIG. 19 and FIG.
This element must be included for both topologies shown to work the same, so that when the transistor (79) is off, the output terminal O
The voltage of the UT (73) can take a value larger than HV.

The final output voltage OUT (73) of the claimed circuit is at the high side position (
In FIG. 18), which is slightly lower than a circuit made using PMOS or PNP transistors, this circuit can be used in a great many applications requiring level shifter circuits. As explained above, the ability to program the maximum final output voltage of the claimed topology is an advantage over the conventional topology shown in FIG.

The level shifter circuit (77) shown in FIGS. 19 and 20 also operates as a continuous voltage level shifter as shown in FIG. For example, if the control signal input terminal (71) is always connected to GND (74) in a special configuration, the output value OUT will be the voltage value programmed in the Zener circuit, that is, H
The voltage value is limited to a voltage value proportional to V. In this configuration, the circuit operates as an auxiliary continuous voltage source based on HV. This configuration can be used as an auxiliary power source in a charge pump circuit or a bootstrap circuit. Regarding this point, 2. C. 1 and 2. C. This will be described in 2.

[2. C drive circuit] [2. C. 1 Capacitor Type Charge Pump Circuit] FIGS. 22 and 23 show the operation principle of the capacitor type charge pump circuit. Basic circuit of Figure 22a comprises at least two rectifiers, two capacitors, LS to which electric power is supplied from the auxiliary voltage source V _{AU X} (level shifter) interface circuit (77)
And The input signal CLK (80) to the LS interface circuit (77)
) Comes from the clock (81). This clock usually produces a small amplitude rectangular wave. LS interface circuit output signal (77) (82) is determined by the characteristics of the NMOS structures used with the size of the circuit, the value is less than V _{AU X.} The capacitor C _TK is connected to both ends (84) of a rectifier diode connected in series.
) And (85). This is indicated by the dotted line. Alternatively, the capacitor C _TK is connected to the output terminal (85) and the ground terminal GND (
74). Which one to use depends on the application.

FIG. 22 b shows the response course of the circuit when an ideal element is used, ie when the saturation voltage of the LS interface circuit is zero and an ideal rectifier is used (
The vertical axis indicates voltage, and the horizontal axis indicates time). In this case, when the pump cycle ends several times, the voltage V _G of the both ends of the C _TK is directed to 2V _AUX. This type of circuit is known as a voltage doubler circuit and is often used in both discrete and integrated circuits.

In order to design the charge pump circuit as accurately as possible, the voltage value between the drain and source of the NMOS transistors (79) and (80) of the LS interface circuit (77) (FIG. 20) and the voltage of the rectifier diode It is necessary to consider the drop, the charge loss of the capacitor, and the loss when connecting the elements. Normally, the LS interface circuit (77) is supplied with power from an auxiliary voltage source V _AUX (83) based on the high voltage source HV. This auxiliary voltage source V _AUX (83) supplies a voltage sufficient for the LS interface circuit (77) to change the signal at the output (82) to charge C _TK as quickly and as efficiently as possible.

As shown in FIG. 21, the LS interface circuit composed of the high-voltage device shown in FIGS. 19 and 20 is directly connected from the high-voltage source HV or from the auxiliary voltage source V _AUX based on the HV. Power supply. These circuits are LS
Since the output amplitude (82) from the interface circuit (77) is extremely diversified, the capacity needs to be smaller than that of a circuit manufactured using a logic CMOS cell. In these circuits, the semiconductor device can be designed such properties of the final output voltage V _G of the charge pump circuit to the output voltage of the LS interface circuit (77) is reflected.

A multi-stage circuit realized using this principle has a final voltage value V _G Is the value obtained by adding 1 to the number of steps._AUXMultiplied by. This circuit is generally
Also known as a multiplier. FIG. 23 shows a voltage tripler circuit.
I have. This circuit has a single level shifter LS (7
7), diode D3 and additional capacitor C_PP2Although there is an additional stage consisting of
It works similarly. A circuit manufactured with ideal elements has a final voltage value V_GIs 3 × V_{A UX} Becomes When an actual device is used, the voltage V_GHas this problem due to the loss described above
Slightly smaller than the value.

The operating principle of the charge pump circuit has been described with reference to FIGS. 22A and 23. The charge pump circuit can be configured as a floating voltage source. The anode of the diode D1 disconnected from V _AUX becomes the negative pole of the floating voltage source FPS, and the cathode of the diode D2 in FIG. 22A or the diode D in FIG.
The cathode of No. 3 becomes a positive pole. The capacitor C _TK is connected between the negative pole (84) and the positive pole (85) of this power source or between the positive pole (85) and the ground (7).
4) can be connected. This type of circuit (FPS) is a current source used to generate a voltage higher than the supply voltage from the high voltage circuit and to inject current into the gate of a high side or low side NMOS power transistor. Often used to supply power. For this,
2. C. This will be described in 2.

FIGS. 24, 25 and 26 show some examples of topologies claimed herein. These topologies operate as floating voltage sources and utilize only NMOS structures. In other words, the rectifier diode and the zener diode are used for 2. A is configured as described above. The interface circuits used are: B and 2C. The capacitors may or may not be integrated. Basically, these circuits are LDSD or LDMO
A level shifter circuit having an NMOS structure including an S NMOS transistor is used. The basic structure is shown in FIG. 27, from which the topology of the charge pump circuit claimed in this specification can easily be obtained.

[2. C. 2 Capacitor Bootstrap Circuit] FIG. 28a shows a typical electric circuit layout of the capacitor bootstrap circuit described in the literature. This circuit typically comprises a capacitor C _Boot (93) and interface circuits BH (91) and BL (99) (BH and B
L is a buffer high side and a buffer low side, respectively, and a resistor R _Boot (
92), a control transistor MC (98), and two power transistors ML
(89) and MH (88). The operation of this circuit is determined by the capacitor C _Boot (
93), and a sufficient voltage is maintained between the two terminals. Therefore, power is supplied to the interface circuit BH (91) in a floating state, and this interface circuit BH
It functions as a drive circuit for the MOS power transistor MH (88) and controls the ON state of this transistor. Drain and one terminal of the resistor R _{Bo ot} (92) of the transistor MC (98) is connected to the input of the interface circuit BH (91), constitute a level shifter. The negative terminal of the floating voltage source formed by the capacitor C _Boot (93) is connected to the source electrode (90) of the transistor MH (88). The supply voltage V _AUX (95) is usually higher than the supply voltage to this logic circuit, but a pair of power transistors MH (88) and ML
The voltage of the high-voltage power supply HV (101) that determines the output level of (89) can be made lower. V _AUX (95) As described in B, it can be generated based on the high voltage power supply. The value must be a value that matches the voltage value applied to V _GS (MH) (102) so that the power transistor MH (88) becomes fully conductive.

The capacitor-type bootstrap circuit is generally used in applications where the operating frequency is determined and the control signal C _trl (97) is periodic. To illustrate the function of this circuit, consider the cycle of the control signal C _trl (97) in FIG. 28b, clearly divided into three phases. Hereinafter, the state of this circuit will be described for each phase.

[Phase 1: Charging of Capacitor C _Boot ] In this phase, the control signal C _trl (97) is at the high level, and the conduction of the power transistors MC (98) and ML (89) is guaranteed. In this phase, the capacitor C _Boot (93) is charged to substantially the voltage value of V _{AU X} (95) through the diode D1 (94). While the power transistor MC (98) is conducting, the interface circuit BH (91) outputs the high-side transistor MH (
88) is kept in the cut-off state, and the transistor ML (89) is connected to the ground (1).
Forming a low impedance path V _out (90) to V.00). Therefore, the capacitor C _Boot (93) is charged.

[Phase 2: Start of Bootstrap Operation] This phase is characterized in that the state is changed by the control signal C _trl (97). That is, the control signal C _trl (97) changes from the logical value 1 to 0. At this stage, the transistors ML (89) and MC (98) are cut off, and the input signal of the interface circuit BH (91) remains at the potential of the plus terminal of the capacitor C _Boot (93). Therefore, the output signal of the BH interface (91) (
102) becomes this voltage, and the MH transistor (88) becomes conductive. The voltage V _out (90) increases with the current flowing in the load, and the final value HD−V _DS
(MH). The voltage between both terminals of the capacitor C _Boot (93) is kept substantially constant while the transistor MH (88) is conducting. Transistor M
The gate voltage value V _G (102) of H (88) almost reaches HV−V _DS (MH) −V _AUX . During this period, the polarity of the diode D1 (94) is reversed, and the power supply V _AUX
(95).

[Phase 3: Free conduction state of transistor MH] In this phase, the transistor MH (88) starts free conduction. Tran
While the transistor MH (88) is conducting, the capacitor C_Boot(93) is discharged
Thus, a current is supplied to the drive circuit (91) of the transistor MH (88). This fe
The maximum value of the duration of the_Boot(93) is the interface
Circuit BH (91) continues to supply sufficient voltage, which in turn
Interface circuit BH (91) is connected to the gate of transistor MH (88).
Voltage, so that transistor MH (88) remains conductive
It depends on how long you can spend. Capacitor C_Boot(93)
Discharge causes the charge to move to the gate of the transistor MH (88),
Note that the loss is caused by the child. Usually, the capacitor C _Boot The magnitude of (93) is such that the voltage on this capacitor is only one during the operating cycle.
It is designed to be smaller by 0%.

The circuit shown in FIG. 28a is suitable for applications where the operating frequency is well-defined. This is because it is necessary to determine an appropriate capacity and operating frequency of the capacitor C _Boot (93) for each circuit. This technique has the advantage that it is simple and allows the transistor MH (88) to perform a rectifying function at a high frequency while using only a small number of high voltage elements. However, transistors ML (89) and MH (
88) is limited to a small number of applications because the undesirable situation of both conducting simultaneously can occur. Based on this, a circuit with more sophisticated control can avoid simultaneous conduction, so it is very necessary to make the transistors included in the high side full bridge and half bridge configuration rectify. Often used [13].

FIG. 29 shows a different topology than the circuit of FIG. 28, which is claimed herein to be novel. In this topology, only NMOS transistors are used. 2. The NMOS level shifter block (77) described in B provides the functions required for the interface BH (91) in FIG. 28a. FIG.
29A and the control circuit (96) of the bootstrap circuit shown in FIG. 29 can be programmed to drive the transistor ML (89) and then to drive the transistor MH (88) with an appropriate delay. Both can be prevented from conducting simultaneously. The diode D1 (94) has two components: It can be manufactured as described in A, or using a PN junction that can withstand high voltages in some process.

FIG. 30 a shows another topology for manufacturing a capacitor-type bootstrap circuit for controlling the conduction of the NMOS power transistor MH (88). To construct this circuit, a capacitor C _Boot (93) and a resistor R _Boot (
92) and two level shifter interfaces LS1 (77A) and LS
2 (77B) is required. As the level shifter, for example, 2. The level shifter (77) described in B is used. For this application, interface LS1 (77A) is programmed to reach final voltage V _AUX (95). This is because V _GS (MH) is required to make transistor MH (88) fully conductive.
Is the voltage value to be applied to. The interface LS2 (77B) has an output voltage between the drain of the transistor MH (88) and the interface LS1 (77A).
And LS2 (77B) are programmed to reach a value as close as possible to HV (72) (101 in FIG. 28a) supplying voltage. FIG. 30b shows the control signal C _trl (for one cycle of turning on and off the transistor MH (88).
71 is a graph showing a time change of the output voltage V _out (90) and the gate voltage (73) of the transistor MH (88) (102 in FIG. 28a). For further consideration, the cycle was divided into three phases as before.

In phase 1, the transistor MH (88) is off. Interface
Signal A (71A) and signal input to the source LS1 (77A) and LS2 (77B)
A '(71A') is at the same time at 1 level and the output is low ground potential (
74) (100 in FIG. 28a). Gate of transistor MH (88)
(73) and the voltage V between the source (90)_GS(MH) is almost zero, and the load Z _Load Almost no current flows in (104).

Phase 2 has two different phases. The first stage is the capacitor C _Boot (
93). This occurs immediately after the control signal A (71) changes from the logical value 1 to the logical value 0. At this stage, 2. As described in B, the output of interface LS1 (77A) provides the energy to charge capacitor C _Boot (93) to the potential programmed on interface LS1 (V _AUX ). At the same time, a capacitor equivalent to the capacitor effect between the gate and the source of the transistor MH (88) is charged by the output of the interface LS1 (77A). The signal A ′ (71A ′) is supplied to the interface LS1 (77A
) And LS2 (77B) to charge capacitor C _Boot (93),
In this layout, the transistor MH (88) becomes conductive because it stays at the logical value 1 for a time Δt sufficient to reach the voltage value determined in the layout. After the time Δt, the signal A ′ changes from the logical value 1 to the logical value 0, and the second phase of this phase starts. This second stage is characterized by the voltage V _G (102). Here, the negative terminal of the capacitor C _Boot (93) is connected to the resistor R _Boot (92)
To the potential of the source of the transistor MH (88). Therefore, the voltage V _GS (MH) is almost equal to the voltage of the capacitor C _Boot (93), and the high voltage source HV (72) supplies the maximum current to the load Z _Load (104) through the transistor MH (88).

Phase 3 of the operation of this circuit involves, as shown in FIG. 30b, the voltage V _G (73)
Are substantially equal to the final value of HV + V _AUX , the signal A and the signal A ′ remain at the logical value 0. This phase continues until signal A and signal A 'simultaneously change from logic 0 to logic 1 and consequently capacitor C _Boot (93)
Is discharged, and the transistor MH (88) is cut off. This characterizes the initial state of the new cycle. The level shifter LS1 (77A) used
And the output level of LS2 (77B) depend on the supply voltage HV to these interfaces.
Note that this can be achieved by using an NMOS transistor capable of a larger output voltage than (72).

As in the circuit of FIG. 29, a transistor ML (89) can be added to the circuit of FIG. 30a. In this case, the transistor ML (89) has a low-side configuration and the source (90) of the transistor MH (88) and the ground GND (74).
And control directly by the control circuit.

[2. D Floating Current Source] A current source is often used to control the charging and discharging of an equivalent input capacitor _CGS of a power transistor that supplies power to an external load. It not control it or to release the charge from the capacitor or injecting charge into the capacitor C _GS to or to cut off or to conduct the transistors, but the circuit using a current source as a means for its control When used, control and switching can be performed using algorithms optimized for the type of charge supplied. High-voltage NMOS transistors and high-voltage PMOS transistors are manufactured by the technology for manufacturing integrated smart power devices, but because high-voltage PMOS transistors are manufactured using this technology, current is supplied to the high-side transistor. The manufacture of the current source is facilitated.

FIG. 31 shows a high-side topology power device.
er device (88) using a floating current source (106) to inject current into the device and render the device conductive. Another current source is connected to ground. The output level of this current source is determined by the transistor M4 (108), and is used to discharge the gate of the transistor MH (88) to cut off the transistor MH (88).

A current source manufactured in MOS technology basically aims at controlling a voltage V _GS applied to a transistor. When the transistor is operating in the saturation region, the drain current of the transistor will depend almost entirely on V _GS . Generally, the reference current source is formed by an analog circuit configured using a low-voltage transistor connected to the GND terminal (100). The current generated in (109) is N-type (108 and 110) and P-type (111 and 11) operating at high pressure.
It is copied exactly by a circuit configured using the MOS transistor and the NPN bipolar transistor (113) of 2). In the circuit shown in FIG. C
As described above, the capacitor C _{Boot of the} bootstrap circuit is connected to the current source (10
6) is used as a floating voltage source FPS for supplying power. Another option is already 2. C. One would use the capacitor type charge pump shown in FIG.

The present application claims a topology of a current source having a function of injecting and discharging a current in both a high-side transistor and a low-side transistor configured using only the NMOS structure. Among the various topologies possible,
FIG. 32 shows a topology for operating as a current source circuit by injecting a current into the gate of the NMOS transistor MH (88) in a high-side configuration.

[0097] 2. As already described in A, it is possible to fabricate a circuit that emulates the operation of a floating Zener diode using an NMOS structure. The value of the zener voltage of this circuit can be dynamically programmed using a low voltage control circuit. Also, 2. As already described in B, the floating current source can be manufactured using only the NMOS structure.

In FIG. 32, a group of elements is a floating current source (
121). The output of this current source (121) is connected to the gate (102) of the MH (88) and is used to inject current and make the transistor MH (88) conductive. Circuit (122) connected to ground (100)
Constitute a current source. The purpose of this current source is to pass the current through the transistor MH (88
) To make this transistor cut off.

The floating current source (121) basically includes a Zener circuit represented by DZP (115), a high-voltage transistor represented by MI (117), and a resistor R
I (116). These elements are powered by a floating voltage source (118) represented by FPS. The negative terminal of this power source is
V (101). The power source FPS (118) has an amplitude on the order of 10 volts. Element DZP (115) represents a programmable zener circuit with a control circuit connected to GND terminal (100). The function of this Zener circuit is to maintain the voltage V _GS (MI) at a predetermined program value and control the current injected into the gate (102) of the transistor MH (88) according to an algorithm determined according to the application. It is. It is important to emphasize that the control circuit acting on the Zener circuit (115) determines the value of the current flowing into the high voltage transistor MI (117). In particular, it is possible to generate a voltage in the Zener circuit DZP (115) so that no current flows into the high voltage transistor MI (117). The resistor RI (116) is typically a large value resistor whose function is to change the polarity of the Zener circuit DZP (115) to change the floating current source (121) to the sum of the voltages HV + V (FPS). That is, the potential is set based on the potential.

While current is injected into the gate (102) of the transistor MH (88), the transistor MI (117) operates as a current source. In the meantime, block (1
22) The switch CH1 (119) is open and the transistor M5 (120)
Has no influence on the gate of the transistor MH (88). While discharging from the gate (102) of the transistor MH (88), the Zener circuit D
As the voltage value of ZP (115) changes, the current flowing through transistor MH (88) decreases or goes to zero. Current source connected to ground (122)
Operates when the transistor MH (88) is in a cut-off state. Switch C
H1 (119) is turned off, and transistor M5 (120) is turned off by transistor MH.
Discharge is started from the gate (102) of (88). Therefore, the MH (88) is cut off as desired.

[Brief description of the drawings]

FIG. 1 is a diagram showing a general switching cell for realizing a power device topology.

FIG. 2 is a diagram showing a general switching cell for realizing a power device topology.

FIG. 3 is a diagram showing a general switching cell for realizing a power device topology.

FIG. 4 is a diagram showing a general switching cell for realizing a power device topology.

FIG. 5 shows the general matrix arrangement of the switching structure, in particular the spatial layout of the NMOS structure and the array, the location of the control signal and power interconnect channels, and the location of the pads.

FIG. 6 shows the details of the matrix, and in particular the metal 2 tracks covering the NMOS structures near the pads, focusing on the connection pads of the array.

FIG. 7a shows a control signal interconnect channel and shows a network of vias (metal1 / metal2 connections), metal tracks and polysilicon resistors.

7B is a cross-sectional view taken along the line A-A 'in FIG. 7A.

FIG. 8 is a diagram showing an example of a basic NMOS structure in which LDSD transistors are juxtaposed.

FIG. 9 is a cross-sectional view showing an example of an optimized basic cell proposed in the present invention based on a GSLDD / GSLDSD NMOS transistor.

FIG. 10a is a diagram showing a rectifier diode and its current characteristic curve I (V).

FIG. 10b is a diagram showing a Zener diode and its current characteristic curve I (V).

FIG. 10c is a diagram showing a rectifier diode connected in series with a zener diode, and a current characteristic curve I (V) thereof.

FIG. 11 is a control circuit for emulating a Zener diode and a rectifier diode,
FIG. 3 is a diagram illustrating an example of a control circuit in which a plurality of circuits are integrated.

FIG. 12 is a diagram showing an example of an NMOS structure emulating the operation of the floating zener circuit of FIG. 10B, which is reconfigured based on an NMOS transistor of LDSD.

FIG. 13 is a diagram showing an example of an NMOS structure emulating the operation of the floating zener circuit of FIG. 10b, which is reconfigured based on an LDMOS transistor.

FIG. 14 is a diagram illustrating an example of an NMOS structure emulating the operation of the series-connected rectifier diode and zener diode of FIG. 10c, which is reconfigured based on an NMOS transistor of LDSD.

FIG. 15 is a diagram showing an example of an NMOS structure emulating the operation of the series-connected rectifier diode and zener diode of FIG. 10c, which is reconfigured based on an LDMOS transistor.

FIG. 16 is an NMOS structure emulating the operation of the rectifier diode of FIG. 10a,
FIG. 4 is a diagram illustrating an example of an NMOS structure reconfigured based on an LDSD NMOS transistor.

FIG. 17 is an NMOS structure emulating the operation of the rectifier diode of FIG. 10a,
FIG. 3 is a diagram illustrating an example of an NMOS structure reconfigured based on an LDMOS transistor.

FIG. 18 is a diagram showing an example of a classic level shifter circuit disclosed in the literature, which is a circuit using a high-side high-voltage transistor in a PMOS (or PNP bipolar type).

FIG. 19 is a diagram showing an example of a level shifter circuit which is a circuit having a topology in which a high-voltage PMOS (or PNP bipolar transistor) is not used at a high side position and uses only NMOS transistors of LDSD.

FIG. 20 is a diagram illustrating an example of a level shifter circuit using only LDMOS transistors, although a diode DR is added in comparison with FIG. 19;

FIG. 21 is a diagram illustrating an example of a level shifter circuit that operates as an auxiliary continuous voltage source supplied with a voltage from the HV and functions as a continuous voltage level shifter in this configuration.

FIG. 22a illustrates an example of a typical capacitor-type charge pump that functions as a voltage doubler.

FIG. 22B is a diagram showing a voltage change in the capacitor C _TK in FIG. 22A.

FIG. 23 illustrates an example of a typical capacitor charge pump that functions as a voltage tripler.

FIG. 24 illustrates an example of a charge pump that functions as a voltage doubler that can be realized using an NMOS structure.

FIG. 25 illustrates an example of a typical capacitor-type charge pump that functions as a voltage tripler that can be implemented using an NMOS structure.

26 is a diagram showing a charge pump that can be realized by using an NMOS structure, which functions as a floating voltage source based on the topology of FIG. 23 and has a rectifier bridge as an output; It is a figure showing an example.

FIG. 27 is a diagram showing an example of a basic circuit that can be realized by using an NMOS structure from which a charge pump topology that claims to be novel can be obtained.

FIG. 28a shows an example of a typical bootstrap circuit.

FIG. 28B is a diagram showing a time change of a control signal, an output, and a gate voltage during a transition of the power transistor MH to turn on and turn off.

FIG. 29 is a diagram illustrating an example of a bootstrap circuit that can be realized using an NMOS structure.

FIG. 30a is a diagram showing an example of a bootstrap circuit for a power device based on a high-side topology NMOS.

FIG. 30b is a diagram showing various waveforms during a transition of the power transistor MH between turn-on and turn-off.

FIG. 31 is a diagram showing an example of a standard floating current source for supplying a current to a power device having a high-side topology.

FIG. 32 is a diagram illustrating an example of a floating current source that can be realized by using an NMOS structure.

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[Submission date] January 17, 2001 (2001.1.17)

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[Claims]

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 19/0185 H03K 19/00 101B (81) Designated country EP (AT, BE, CH, CY, DE, DK) , ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE), OA (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR) , NE, SN, TD, TG), AP (GH, GM, KE, LS, MW, SD, SL, SZ, TZ, UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CR, CU, CZ, DE , DK, DM, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ , TM, TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW. 65 (72) Inventor Pedro, Casimiro Antonio, Portugal, p. 1000 267 Lisboa, Avenida Robisco Pais (72) Inventor Mendonsa Santos, Pedro Portugal, p. 1000 267 Lisboa, Avenida Robisco Pa Chair (72) Inventors Behrens, Frank Hermann Brazil, São Paulo, C セ epé 13089-500, Kaemi 143, 6, Rhodobia Escipé 65 (72) Inventors Manmana, Carlos, I. Ze. São Paulo, São Paulo, Brazil 13089-500, Kaemi 143, 6, Rhodevia Escipe 65 F term (reference) 5F038 BG03 BG05 BG06 EZ20 5F048 AA02 AA05 AB02 AB03 AB08 AC01 AC03 AC06 AC10 BA01 BB05 BC05 BC06 BC19 BC20 ABF11 A00 BB58 BB59 CC21 DD13 DD29 DD51 DD55 FF01 FF08 KK02

Claims (6)

[Claims] 1. A power cell for switching, a driving circuit and a protection circuit for the power cell, and other elements required for controlling, amplifying, and sampling an output variable to meet various application requirements. Circuit, comprising: a) a power integrated circuit (PIC) with or without "intelligence";
For the purpose of obtaining an array based on a combination of NMOS FETs, the NMOS structure utilizes a special layout of simple patterns and can perform various functions required for smart power ICs. B) providing a novel circuit topology that allows control of the PIC and power signal processing using only said NMOS structure, except in combination with passive elements in the same monolithic circuit or external passive elements, c) LDD or LDSD-NMOS or both, or LDMOS
Alternatively, a smart power IC using a basic cell based on the above-mentioned NMOS structure in which an FET such as an N-channel DMOS is combined. 2. The layout of a metal mask on the surface that defines a semi-custom array in which the NMOS structures are interconnected, and b) the specific functions to be added to the cell library to meet various applications. A novel topology of circuits intended for power signal processing interconnected by combining said NMOS structures, and c) a complete mask to define the basic combination based on NMOS and to help configure the system. The smart power IC according to claim 1, wherein the smart power IC is realized by a smart power array capable of programming a mask using the layout. 3. The topology of the circuit is obtained by appropriately configuring a smart power array according to claim 2 capable of programming a mask, the circuit comprising: a) a clipper based on an NMOS structure and A rectifier and programmable "Zener" required for the clamper; b) a level shifter based on an NMOS structure; c) a charge pump based on an NMOS structure; d) a bootstrap based on an NMOS structure; The smart power IC of claim 1, comprising a current source based on the structure, and further comprising a suitable method and simulation model for the design. 4. A basic combination using either LDD or LDSD type, or both, or only a set of NMOS transistors such as LDMOS or DMOS, the combination comprising: a) all terminals in the NMOS structure B) a P ⁺ guard ring connected to the substrate containing the base cell; c) a connection of the source in the transistor of the LDD type to said guard ring; d) a floating LDSD type transistor and floating LD
E) To enable the local interconnection of the drain electrode, gate electrode, and source electrode with the source of the MOS type transistor, to facilitate the interconnection through the columns between the basic cells, and to obtain a more complicated circuit. The smart power IC of claim 1, further comprising: a special layout that facilitates combining basic cells through appropriate interconnects. 5. An array with or without "intelligence" as claimed in claims 1 and 2 for performing power control, switching, driving, sampling, protection, power conversion and amplification, and claims 2 and 3. A smart power IC application utilizing the novel topology described in the above, wherein said array is provided by standard CMOS technology or by another CMOS technology requiring an additional processing process.
The array can be manufactured by technology, or by more sophisticated power circuit integration technology, or by special smart power circuit technology.
In order to perform various functions according to claim 3, the method is configured according to the method according to claim 4, and specifies an integrated or non-integrated passive element and a plurality of NMOS transistors according to the method. Numerous power switching that, when combined with the above configuration, creates a variety of switching topologies: high-side, low-side, bandpass devices, push-pull, half-bridge, full-bridge, n-phase bridge, and other derived topologies. Realizing the cells, realizing the various devices and circuits required to drive various power switching topologies, realizing the sampling and protection circuits required to make the power switching cells perform well, Smart power I for electrostatic discharge and latch-up operation An application of smart power ICs, characterized by increasing the durability of C and enabling rapid prototypes of smart power circuits and microsystems. 6. An N-channel metal oxide semiconductor field effect transistor of the LDD and LDSD type, wherein the transistor is a GSLDD with a shifted gate and a lightly doped drain or a shifted gate. Wherein the gate mask is shifted with respect to the edge of the N-type well mask in order to increase the breakdown voltage. 2, 3, 4 and 5 expand the range of application of the programmable smart power array, wherein the transistor comprises a very standard CMOS (N-well, P-type substrate, one layer of polysilicon, Good compatibility with at least two layers of metal film). A drain is formed by a high-concentration impurity diffusion region embedded in a lightly doped N-type well; a substrate and a source electrode are connected to realize the GSLDD; and a drain of the GSLDD is formed. Has a special mask layout that can handle high voltage, has a side planar configuration for the GSLDSD, and has a drain and a source embedded in a lightly doped N-type well. The source is isolated from the substrate to form the GSLDSD, and the layout of the special mask allows both the drain and the source of the GSLDSD to handle high voltages. Using gate shift technology, the lateral expansion of N-type wells Aligning the path and gate mask in a straight line has the advantage of reducing the maximum value of the surface electric field inherent in low-concentration regions, thereby increasing the maximum threshold voltage of the device. Transistor.