CN103474462A - Lateral double-diffused metal oxide semiconductor element and manufacturing method thereof - Google Patents

Abstract

The invention provides a laterally double diffused metal oxide semiconductor (LDMOS) element and a manufacturing method thereof. The LDMOS device is formed in the first conductive substrate and comprises a high-voltage well region, a first field oxide region, at least one second field oxide region, a source electrode, a drain electrode, a body region and an AND gate; wherein, from the top view, the second field oxide region is located between the first field oxide region and the drain, and the distribution of the second conductive type impurity concentration in the high-voltage well region is related to the position of the second field oxide region.

Description

Lateral double-diffused metal oxide semiconductor element and manufacturing method thereof

technical field

The invention relates to a lateral doublediffused metal oxide semiconductor (LDMOS) element and a manufacturing method thereof, in particular to an LDMOS element with a relatively high breakdown protection voltage and a manufacturing method thereof.

Background technique

1A-1C respectively show a cross-sectional view, a perspective view, and a top view of a lateral double diffused metal oxide semiconductor (LDMOS) device 100 in the prior art. As shown in FIGS. 1A-1C , there is an isolation region 12 in the P-type substrate 11, which surrounds a closed area (as shown in FIG. 1C , the thick black frame line of the isolation region 12) to define the functional area of the LDMOS element 100, The isolation region 12 and the field oxidation region 12a are, for example, a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure as shown in the figure. The LDMOS device 100 includes an N-type well region 14 , a gate 13 , a drain 15 , a source 16 , a body region 17 , a body electrode 17 a, and a field oxide region 12 a. Wherein, the N-type well region 14, the drain electrode 15 and the source electrode 16 are photoresist formed by lithography technology or/and part or all of the gate 13 is used as a shield to define each region, and the ion implantation technology is respectively used to N-type impurities, in the form of accelerated ions, are implanted in defined regions. Wherein, the drain electrode 15 and the source electrode 16 are respectively located under the two sides of the gate 13; the body region 17 and the body electrode 17a are formed by photolithography technology to form a photoresist or/and part or all of the gate 13 is used as a shield to define each region , and implant P-type impurities in the defined region in the form of accelerated ions by ion implantation technology. Moreover, in the LDMOS device, a part of the gate 13 is located on the field oxide region 12a. LDMOS components are high voltage components, ie they are designed to supply higher operating voltages. The higher the breakdown protection voltage of the LDMOS element, the lower the on-resistance value, and the wider its application range. Generally speaking, the breakdown protection voltage and the on-resistance cannot be balanced. To reduce the on-resistance of the LDMOS device, the ion implantation parameters must be changed, which will sacrifice the breakdown protection voltage; or increase the number of ion implantation steps in a specific area. , so that additional lithography and implantation steps are required, which will increase the manufacturing cost, in order to achieve the desired on-resistance and breakdown protection voltage.

In view of this, the present invention aims at the deficiencies of the above-mentioned prior art, and proposes an LDMOS element and a manufacturing method thereof, which can increase the breakdown protection voltage and increase the The scope of application of the component. In addition, the ion implantation parameters of the LDMOS device of the present invention can be shared with the low-voltage device, that is, can be integrated into the manufacturing process of the low-voltage device, so that the high-voltage device and the low-voltage device can be manufactured on the same wafer at the same time.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies and defects of the prior art, and propose a lateral double diffused metal oxide semiconductor (LDMOS) element and a manufacturing method thereof.

To achieve the above object, the present invention provides an LDMOS element formed in a first conductive type substrate, the substrate has an upper surface, and the LDMOS element includes: a second conductive type high voltage well region formed on the upper surface In the lower substrate; a first field oxidation region is formed on the upper surface, and viewed from a plan view, the first field oxidation region is located in the high voltage well region; a grid is formed on the upper surface, and The gate includes a first part located on the first field oxide region; a second conductivity type source and a second conductivity type drain respectively formed under the upper surface on both sides of the gate; a first a conductive body region formed in the substrate under the upper surface, on the same side of the gate as the source, and the source is located in the body region; and at least one second field oxide region formed on the upper surface From the top view, the second field oxide region is located between the first field oxide region and the drain.

From another point of view, the present invention also provides a method for manufacturing a lateral double diffused metal oxide semiconductor (LDMOS) element, comprising: providing a substrate of a first conductivity type, the substrate having an upper surface; Forming a first field oxidation region and at least one second field oxidation region on the upper surface; forming a second conductivity type high voltage well region in the substrate under the upper surface, viewed from a top view, the second conductivity type The range of the high voltage well region includes the first field oxide region and the at least one second field oxide region; a gate is formed on the upper surface, and the gate includes a first part located on the first field oxide region; And forming a second conductivity type source and a second conductivity type drain under the upper surface on both sides of the gate, and forming a first conductivity type body region in the substrate under the upper surface, and the source The electrode is located on the same side of the gate, and the source is located in the body region, wherein the drain is located outside the second field oxide region farthest from the gate; wherein, the high voltage well region is formed in the first field After the oxidation region and the second field oxidation region are formed, the distribution of the impurity concentration of the second conductivity type in the high voltage well region is related to the position of the second field oxidation region.

In one of the preferred embodiments, at least one opening region is defined between the first field oxidation region and the at least one second field oxidation region, and the second conductivity type impurity concentration of the opening region is below the upper surface. , higher than the second conductivity type impurity concentration below the first field oxide region and the second field oxide region.

In the preferred embodiment above, the gate may further include a second portion located on the upper surface above the opening region, and the second portion has a dielectric layer connected to the upper surface.

In the foregoing embodiments, the gate may further include a third portion located above the second field oxide region.

In a preferred embodiment, the LDMOS element preferably includes a plurality of second field oxide regions, and between the first field oxide region and adjacent second field oxide regions, and adjacent second field oxide regions Between the regions, a plurality of opening regions are defined, and the impurity concentration of the second conductivity type under the upper surface of the opening region is higher than the concentration of the second conductivity type impurity under the first field oxidation region and the second field oxidation region.

In the above preferred embodiment, viewed from the top view, the area of the opening region relatively closer to the drain is larger than the area of the opening region relatively closer to the first field oxidation region.

In yet another embodiment, the body region and the substrate can be separated by the high pressure well region, so that the body region and the substrate are not directly electrically connected; or at least part of the body region can be connected to the substrate, or The substrate can be connected through a first conductive type connection well region, so that the body region is electrically connected with the substrate.

The following will be described in detail through specific embodiments, so that it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

Description of drawings

1A-1C respectively show a cross-sectional view, a perspective view, and a top view of an LDMOS device 100 in the prior art;

2A-2D show a first embodiment of the present invention;

Figure 3 shows a second embodiment of the present invention;

Figure 4 shows a third embodiment of the present invention;

Figure 5 shows a fourth embodiment of the present invention;

Fig. 6 shows the fifth embodiment of the present invention;

Fig. 7 shows the sixth embodiment of the present invention;

Fig. 8 shows the seventh embodiment of the present invention;

Fig. 9 shows the eighth embodiment of the present invention;

Fig. 10 shows the ninth embodiment of the present invention;

Figure 11 shows a tenth embodiment of the present invention;

12A-12C show a characteristic curve of a prior art LDMOS device;

13A-13C show a characteristic curve of an LDMOS device using the present invention.

Explanation of symbols in the figure

11,21,31,41,51,61,91 substrates

12,22,32,42,52,62,72,82,92,102,112 isolation area

12a, 22a, 22b, 32a, 32b, 42a, 42b, 42c, 52a, 52b, 52c, 62a, 62b, 62c, 62d, 72a, 72b, 82a, 82b, 82c, 82d, 92a, 92b, 102a, 102b, 112a, 112b field oxidation area

13,23,33,43,53,63,73,83,93,103,113 grid

14,24,34,44,54,64,74,84,94,104,114 high pressure well area

15,25,35,45,55,65,75,85,95,105,115 drain

16,26,36,46,56,66,76,86,96,106,116 source

17,27,37,47,57,67,77,87,97,107,117 body area

17a, 27a, 37a, 47a, 57a, 67a, 77a, 87a, 97a, 107a, 117a body pole

21a, 31a, 41a, 51a, 61a, 91a, 101a upper surface

108 connecting well area

100,200,300,400,600,700,800,900,1000,1100LDMOS components

221,321,421,422 opening area

Detailed ways

The drawings in the present invention are all schematic, mainly intended to represent the manufacturing process steps and the upper and lower sequence relationship between each layer, as for the shape, thickness and width, they are not drawn to scale.

Please refer to FIGS. 2A-2D , which show a first embodiment of the present invention. This embodiment shows a schematic diagram of a manufacturing method of an LDMOS device 200 applying the present invention. 2A-2B are schematic perspective views, FIG. 2C is a schematic cross-sectional view, and FIG. 2D is a schematic top view. First, as shown in FIG. 2A, a substrate 21 is provided, which has an upper surface 21a, and the conductivity type of the substrate 21 is, for example, P-type but not limited to P-type (in other implementations, it can also be N-type); and, The substrate 21 may be, for example, a non-epitaxial silicon substrate or an epitaxial substrate. Next, please continue to refer to FIG. 2A. The same but not limited to the same process steps can be used to form the isolation region 22 and the field oxide regions 22a and 22b on the upper surface 21a. Viewed from a top view (see FIG. 2D), the field oxide region 22a and 22b are located in the high pressure well region 24 formed in subsequent process steps; wherein, the isolation region 22 and the field oxide regions 22a and 22b are, for example, STI structures or LOCOS structures as shown in the figure. Next, using ion implantation technology, such as but not limited to N-type impurities in the form of accelerated ions, are implanted into the defined region to form an N-type high voltage well region 24 in the substrate 21 under the upper surface 21 a. It should be noted that because the field oxide regions 22a and 22b have a shielding effect on the above-mentioned accelerated ions; therefore, the high voltage well region 24 is formed after the field oxide regions 22a and 22b are formed, and the N-type impurity concentration in the high voltage well region 24 is Distribution, relative to the position of the field oxidation region 22b; in this embodiment, between the field oxidation regions 22a and 22b, below the upper surface 21a of the defined opening region 221 (see FIG. 2C and FIG. 2D), N-type The impurity concentration is higher than the N-type impurity concentration under the field oxide regions 22a and 22b. Next, referring to FIGS. 2B , 2C and 2D , a gate 23 , a drain 25 , a source 26 , a body region 27 , and a body electrode 27 a are formed. Wherein, as shown in the figure, the gate 23 is formed on the upper surface 21a, and part of the gate 23 is located on the field oxide region 22a. The drain 25 and the source 26 are, for example, N-type but not limited to N-type, and are respectively located below the upper surface 21a on both sides of the gate 23, and viewed from the top view of FIG. 2D, the drain 25 and the source 26 are connected by the gate 23 and The field oxide regions 22a and 22b are separated; wherein, the body region 27 is formed in the high voltage well region 24 under the upper surface 21a, and the source 26 is located on the same side of the gate 23, and the source 26 is located in the body region 27, wherein the drain The electrode 25 is located outside the field oxide region 22 b farthest from the gate 23 ; the drain 25 is formed in the high voltage well region 24 on the other side of the gate 23 . Wherein, the N-type source 26 and the N-type drain 25 are formed under the upper surface 21a, and each area is defined by lithography technology and/or with part or all of the gate 23, field oxide regions 22a and 22b as shields, The N-type impurities are implanted into defined regions in the form of accelerated ions by ion implantation technology. The P-type body region 27 and the P-type body pole 27a are formed below the upper surface 21a, and are defined by lithography technology and/or shielded by part or all of the grid 23 and isolation region 22, and ion implantation technology , which is formed by implanting P-type impurities in the form of accelerated ions into the defined region. Wherein, the source electrode 26 and the drain electrode 25 can be completed by the same or different photolithography process steps and ion implantation steps, and the order of the process steps for forming the source electrode 26, the drain electrode 25, the body region 27 and the body electrode 27a can be changed.

In the aforementioned prior art LDMOS device 100, the drift region between the body region 17 and the drain 15 is completely covered by the gate 13 and the field oxide region 12a. Different from the prior art, in this embodiment, the drift region in the LDMOS element 200 is not completely covered by the gate 23 and the field oxide regions 22a and 22b, but the opening region 221 between the field oxide regions 22a and 22b , exposing part of the upper surface 21a of the high-voltage well region 24, so that in the ion implantation process step of forming the high-voltage well region 24, more impurities are implanted into the substrate at the opening region 221, so that the upper surface of the opening region 221 Below the surface 21a, the N-type impurity concentration is relatively high. The advantages of this arrangement include: In terms of component specifications, compared with the prior art, the application of the present invention can improve the breakdown protection voltage of the LDMOS component, especially for alleviating the Kirk effect, which is more obvious, so that the conduction collapse The protection voltage can be greatly improved; in terms of process, the field oxide region 22b can be formed by the same process steps as the field oxide region 22a and the isolation region 22, without adding additional process steps, so the manufacturing cost can be reduced.

FIG. 3 shows a second embodiment of the present invention, which is a schematic cross-sectional view of an LDMOS device 300 applying the present invention. As shown in the figure, the functional region of the LDMOS device 300 of this embodiment is defined by the isolation region 32; the LDMOS device 300 includes field oxide regions 32a and 32b, a gate 33, a high voltage well region 34, a drain 35, and a source 36 , the body region 37, and the body pole 37a. The difference from the first embodiment is that in this embodiment, the gate 33 includes a first portion 33a located above the field oxide region 32a, a second portion 33b located on the upper surface 31a above the opening region 321, and The third portion 33c is located above the field oxide region 32b. It should be noted that the second part 33b preferably has a dielectric layer (that is, the gate 33 includes a gate electrode and a gate dielectric layer), and the dielectric layer is connected to the upper surface 31a to prevent the gate 33 from contacting the high-voltage well region. 34 are directly electrically connected. In addition, the third portion 33c may not exist, which is also included in the scope of the present invention.

FIG. 4 shows a third embodiment of the present invention, which is a schematic cross-sectional view of an LDMOS device 400 applying the present invention. As shown in the figure, in the LDMOS element 400 of this embodiment, its functional area is defined by the isolation region 42; pole 46, body region 47, and body pole 47a. The difference from the first embodiment is that in this embodiment, there are multiple field oxide regions 42b and 42c located between the field oxide region 42a and the drain 45, and between the field oxide region 42a and the adjacent field oxide region 42b Between, and between the adjacent field oxidation regions 42b and 42c, a plurality of opening regions are defined, such as the opening regions 421 and 422 shown in the figure, and the N-type impurity concentration of the opening regions 421 and 422 below the upper surface 41a, It is higher than the N-type impurity concentration below the field oxide region 42a and the field oxide regions 42b and 42c.

FIG. 5 shows a fourth embodiment of the present invention, which is a schematic cross-sectional view of an LDMOS device 500 applying the present invention. As shown in the figure, in the LDMOS element 500 of this embodiment, its functional area is defined by the isolation region 52; pole 56, body region 57, and body pole 57a. The difference from the third embodiment is that in this embodiment, similar to the second embodiment, the gate 53 covers the field oxide regions 52a, 52b, and 52c and a plurality of open regions therebetween. Of course, it is still necessary to pay attention to Part of the gate 53 located on the opening region preferably has a dielectric layer (that is, the gate 53 includes a gate electrode and a gate dielectric layer), and the dielectric layer is connected to the upper surface 51a, so that the gate 53 and the high voltage well region 54 Not directly electrically connected.

FIG. 6 shows a fifth embodiment of the present invention, which is a schematic cross-sectional view of an LDMOS device 600 applying the present invention. As shown in the figure, the functional region of the LDMOS device 600 in this embodiment is defined by the isolation region 62; the LDMOS device 600 includes field oxide regions 62a, 62b, 62c and 62d, a gate 63, a high voltage well region 64, and a drain 65 , source electrode 66, body region 67, and body electrode 67a. This embodiment is intended to illustrate that in the LDMOS device 600 of the present invention, the opening regions defined between the plurality of field oxide regions 62a, 62b, 62c and 62d can use the size of the field oxide regions 62a, 62b, 62c and 62d to control N type impurity implanted into the high-voltage well region 64, so that the best performance of the present invention can be applied. For example, the opening region relatively closer to the drain electrode 65 can be designed to be larger, and the opening region relatively closer to the field oxide region 62a can be designed to be smaller. small to optimize the turn-on breakdown protection voltage of the LDMOS device 600 .

FIG. 7 shows a sixth embodiment of the present invention, which is a schematic top view of an LDMOS high voltage device 700 applying the present invention. As shown in the figure, the functional region of the LDMOS element 700 of this embodiment is defined by the isolation region 72; the LDMOS element 700 includes field oxide regions 72a and 72b, a gate 73, a high voltage well region 74, a drain 75, and a source 76 , the body region 77, and the body pole 77a. This embodiment is intended to illustrate that in the LDMOS element 700 of the present invention, different numbers of openings can be formed in different positions in the field oxide region 72b according to requirements, so as to increase the breakdown protection voltage of the LDMOS element. This field oxide region The arrangement of 72b is also within the scope of the present invention.

FIG. 8 shows a seventh embodiment of the present invention, which is a schematic top view of an LDMOS device 800 applying the present invention. As shown in the figure, the functional region of the LDMOS voltage element 800 of this embodiment is defined by the isolation region 82; the LDMOS element 800 includes field oxide regions 82a, 82b, 82c and 82d, a gate 83, a high voltage well region 84, a drain 85, source electrode 86, body region 87, and body electrode 87a. This embodiment is intended to illustrate that in the LDMOS device 800 of the present invention, the positions of the field oxide regions 82a, 82b, 82c, and 82d can be used to adjust the width of the opening region according to the electrical requirements viewed from the top view.

FIG. 9 shows an eighth embodiment of the present invention, which is a schematic cross-sectional view of an LDMOS device 900 applying the present invention. As shown in the figure, the functional region of the LDMOS device 900 in this embodiment is defined by the isolation region 92; the LDMOS device 900 includes field oxide regions 92a and 92b, a gate 93, a high voltage well region 94, a drain 95, and a source 96 , the body region 97, and the body pole 97a. Different from the first embodiment, in the first embodiment, the body region 27 and the substrate 21 are separated by the high voltage well region 24, so that the body region 27 is electrically disconnected from the substrate 21, so that the LDMOS element 200 can As the upper bridge (high side) element in the power supply circuit. Differently, as shown in the figure, in the LDMOS element 900 of this embodiment, part of the body region 97 is connected to the substrate 91, so that the body region 97 is electrically connected to the substrate 91, which enables the LDMOS element 900 to be used as a power supply circuit. Lower bridge (low side) components.

FIG. 10 shows a ninth embodiment of the present invention, which is a schematic cross-sectional view of an LDMOS device 1000 applying the present invention. As shown in the figure, the functional region of the LDMOS element 1000 of this embodiment is defined by the isolation region 102; the LDMOS element 1000 includes field oxide regions 102a and 102b, a gate 103, a high voltage well region 104, a drain 105, and a source 106 , the body region 107, and the body pole 107a. The difference from the eighth embodiment is that in this embodiment, part of the body region 107 is connected to the substrate 101 via the P-type connection well region 108, so that the body region 107 is electrically connected to the substrate 101, which makes the LDMOS The element 1000 can be used as a low side element in a power supply circuit.

FIG. 11 shows a tenth embodiment of the present invention, which is a schematic top view of an LDMOS high voltage device 1100 applying the present invention. As shown in the figure, the functional region of the LDMOS device 1100 in this embodiment is defined by the isolation region 112; the LDMOS device 1100 includes field oxide regions 112a and 112b, a gate 113, a high voltage well region 114, a drain 115, and a source 116 , the body region 117, and the body pole 117a. This embodiment is intended to illustrate that in the LDMOS element 1100 of the present invention, in the field oxidation region 112b, according to requirements, the shape of the opening region is not limited to the rectangle in the previous embodiments, as seen from the top view of FIG. It can be in any shape, and the arrangement of the field oxide region 112b is also within the scope of the present invention.

12A-12C show characteristic curves of a prior art LDMOS device. Please refer to FIG. 12A, which shows the characteristic curve of the drain current versus the drain voltage when the LDMOS device of the prior art is operated in a non-conducting state. According to the characteristic curve, the non-conduction breakdown of the LDMOS device of the prior art can be known. The protection voltage is about 76V. Next, please refer to FIG. 12B , which shows the characteristic curves of drain current (left vertical axis) and conductance (right vertical axis) versus gate voltage of this prior art LDMOS element. According to this characteristic curve, it can be known that this prior art The threshold voltage of LDMOS components is about 1V. Next, please refer to FIG. 12C , which shows the characteristic curve of the drain current versus the drain voltage when the prior art LDMOS device is operated in the conduction state. According to this characteristic curve, it can be known that the conduction breakdown of the prior art LDMOS device The protection voltage is about 54V.

On the other hand, FIGS. 13A-13C show characteristic curves of an LDMOS device using the present invention, the basic operating voltage of which is the same as that of the prior art LDMOS device shown in FIGS. 12A-12C. Please refer to FIG. 13A, which shows the characteristic curve of the drain current versus the drain voltage when the LDMOS device of the present invention is operated in a non-conductive state. According to this characteristic curve, it can be known that the non-conductive collapse of the LDMOS device of the present invention The protection voltage is about 100V. Next, please refer to FIG. 13B , which shows the characteristic curves of drain current (left vertical axis) and conductance (right vertical axis) of the LDMOS element of the present invention versus gate voltage. According to the characteristic curves, it can be known that the present invention utilizes The threshold voltage of the LDMOS device is also about 1V, and its on-resistance is comparable to that of the prior art LDMOS device shown in FIGS. 12A-12C . Next, please refer to FIG. 13C , which shows the characteristic curve of the drain current versus the drain voltage when the LDMOS device of the present invention is operated in the conduction state. According to the characteristic curve, it can be known that the conduction breakdown of the LDMOS device of the present invention is used The protection voltage is about 75V.

Comparing the characteristic curves of the prior art LDMOS elements shown in Figs. 12A-12C with those shown in Figs. on-resistance.

The present invention has been described above with reference to preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. For example, without affecting the main characteristics of the device, other process steps or structures can be added, such as threshold voltage adjustment regions, etc.; as another example, lithography technology is not limited to photomask technology, and can also include electron beam lithography technology; another example , viewed from the top view, the LDMOS device to which the present invention is applied is not limited to a rectangle, and may also be circular or serpentine. The scope of the present invention is intended to cover the above and all other equivalent variations.

Claims (14)

1. A lateral double-diffused metal oxide semiconductor element formed in a substrate of a first conductivity type, the substrate having an upper surface, characterized in that it comprises: a second conductive type high voltage well formed in the substrate under the upper surface; A first field oxidation region formed on the upper surface, viewed from a plan view, the first field oxidation region is located in the high pressure well region; a gate formed on the upper surface, and the gate includes a first portion located on the first field oxide region; a second conductivity type source and a second conductivity type drain respectively formed under the upper surface on both sides of the gate; a body region of the first conductivity type formed in the substrate under the upper surface, on the same side as the gate on the same side as the source, and the source is located in the body region; and At least one second field oxide region is formed on the upper surface. Viewed from a plan view, the second field oxide region is located between the first field oxide region and the drain. 2. The lateral double-diffused metal oxide semiconductor device according to claim 1, wherein at least one opening region is defined between the first field oxide region and the at least one second field oxidation region, and the opening region is on the The second conductivity type impurity concentration below the surface is higher than the second conductivity type impurity concentration below the first field oxidation region and the second field oxidation region. 3. The lateral double diffused metal oxide semiconductor device as claimed in claim 2, wherein the gate further comprises a second portion located on the upper surface above the opening region, and the second portion has a dielectric layer, connected to the upper surface. 4. The lateral double diffused metal oxide semiconductor device as claimed in claim 3, wherein the gate further comprises a third portion located above the second field oxide region. 5. The lateral double diffused metal oxide semiconductor device according to claim 1, wherein the lateral double diffused metal oxide semiconductor device comprises a plurality of second field oxide regions, and the first field oxide region and the adjacent first field oxide region Between the two field oxidation regions and between the adjacent second field oxidation regions, a plurality of opening regions are defined, and the impurity concentration of the second conductivity type in the opening regions below the upper surface is higher than that between the first field oxidation region and the first field oxidation region. The impurity concentration of the second conductivity type under the second field oxide region. 6. The lateral double-diffused metal-oxide-semiconductor device as claimed in claim 5, wherein, viewed from a plan view, the area of the opening region relatively closer to the drain electrode is larger than the opening region relatively closer to the first field oxide region area. or At least part of the body region is connected to the substrate, or connected to the substrate through a first conductive type connection well region, so that the body region is electrically connected to the substrate. 8. A method for manufacturing a lateral double-diffused metal oxide semiconductor element, characterized in that it comprises: providing a first conductive type substrate, the substrate has an upper surface; forming a first field oxidation region and at least one second field oxidation region on the upper surface; A second conductive type high voltage well region is formed in the substrate under the upper surface. Viewed from a plan view, the range of the second conductive type high voltage well region includes the first field oxidation region and the at least one second field oxidation region ; forming a gate on the upper surface, and the gate includes a first portion on the first field oxide region; and Forming a second conductivity type source and a second conductivity type drain below the upper surface on both sides of the gate, and forming a first conductivity type body region in the substrate under the upper surface, and the source Located on the same side of the gate, and the source is located in the body region, wherein the drain is located outside the second field oxide region farthest from the gate; Wherein, the high voltage well region is formed after the formation of the first field oxide region and the second field oxide region, so that the distribution of the second conductivity type impurity concentration in the high voltage well region is related to that of the second field oxide region. Location. 9. The method for manufacturing a lateral double-diffused metal oxide semiconductor device as claimed in claim 8, wherein at least one opening is defined between the first field oxide region and the at least one second field oxidation region, and the opening region is between The impurity concentration of the second conductivity type under the upper surface is higher than the impurity concentration of the second conductivity type under the first field oxidation region and the second field oxidation region. 10. The method for manufacturing a lateral double-diffused metal oxide semiconductor device as claimed in claim 9, wherein the gate further comprises a second portion located on the upper surface above the opening region, and the second portion has a The dielectric layer is connected with the upper surface. 11. The method of manufacturing a lateral double-diffused metal-oxide-semiconductor device as claimed in claim 10, wherein the gate further comprises a third portion located above the second field oxide region. 12. The method for manufacturing a lateral double-diffused metal oxide semiconductor device according to claim 8, wherein the lateral double-diffused metal oxide semiconductor device comprises a plurality of second field oxide regions, and between the first field oxide region and the adjacent A plurality of opening regions are defined between the second field oxidation regions and adjacent second field oxidation regions, and the second conductivity type impurity concentration of the opening regions below the upper surface is higher than that of the first field oxidation regions. region and the second conductivity type impurity concentration below the second field oxide region. 13. The method for manufacturing a lateral double-diffused metal-oxide-semiconductor device as claimed in claim 8, wherein, viewed from a top view, the area of the opening region relatively closer to the drain electrode is larger than the area of the opening region relatively closer to the first field oxide region Opening area. 14. The method for manufacturing a lateral double-diffused metal oxide semiconductor device as claimed in claim 8, wherein the body region and the substrate are separated by the high voltage well region, so that the body region and the substrate are not electrically directly connected ; or at least part of the body region is connected to the substrate, or connected to the substrate through a first conductive type connection well region, so that the body region is electrically connected to the substrate.

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