JP2002374430A - Synchronization detection device - Google Patents

Abstract

(57) [Problem] To provide a VSB demodulation system capable of correctly performing synchronization detection and waveform equalization even when a proximity ghost occurs and a synchronization signal included in a received signal is disturbed. SOLUTION: An input signal DT includes a segment synchronization signal conforming to the ATSC standard. The clock multiplier 111 multiplies the clock CK. The switchable sampling unit 112 selects a sample point from a plurality of timings defined by the multiplied clock, and samples the input signal DT at the selected sample point. Further, the switching-type sampling unit 112 switches the sampling points while the synchronization is not established. After the segment synchronization is established, the synchronization detection device
Until the field synchronization detection fails, the synchronization establishment state may be maintained, and based on the bit error rate RT of the input signal,
The synchronization detection signal may be shifted in the time direction and output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization detection device for detecting a synchronization signal from an input signal including the synchronization signal,
More specifically, the present invention relates to a synchronization detecting device built in a receiver or the like compliant with the U.S.A. digital terrestrial broadcasting standard.

[0002]

2. Description of the Related Art FIG. 15 is a block diagram showing a configuration of a conventional synchronization detecting device built in a digital broadcast receiver. The synchronization detection device 100 shown in FIG. 15 includes a field synchronization detection unit 101, a pattern matching unit 102, and a counting unit 1.
03, a rear protection stage number holding unit 104, a front protection stage number holding unit 105, a synchronization determination unit 106, and a synchronization detection signal generation unit 107. The synchronization detection device 100 is used by being incorporated in a digital demodulation system of a receiver conforming to the US terrestrial digital broadcasting standard. As a modulation method of the digital demodulation system, a VSB (Vestigial Side Band) method is adopted. The synchronization detection device 100 is an ATSC (Adva
nced Television Systems Committee) Detects two types of synchronization signals (field synchronization signal and segment synchronization signal) from an input signal DT having a frame structure conforming to the standard, and outputs a field synchronization detection signal FS and a segment synchronization detection signal S
And S are output.

In FIG. 15, a field synchronization detector 1
01 detects a field synchronization signal included in the input signal DT and outputs a field synchronization detection signal FS.
The components other than the field synchronization detection unit 101 constitute the segment synchronization detection unit 109. The segment synchronization detection unit 109 has a synchronization backward protection function and a forward protection function. The backward protection function is a function of transiting from the synchronization non-established state to the synchronization established state when the pattern matching with the synchronization signal succeeds a predetermined number of times (referred to as “the number of backward protection stages”) continuously in the synchronization non-established state. Say. The forward protection function is a function of transitioning from the synchronization established state to the synchronization non-established state when the pattern matching with the synchronization signal fails continuously for a predetermined number of times (referred to as “the number of forward protection stages”) in the synchronization established state. Say.

The pattern matching section 102 performs pattern matching between the input signal DT and the segment synchronization signal, and outputs a matching result signal 202 indicating the success or failure of the matching. Counting section 103
Using the built-in counter, the number of times the pattern matching with the segment sync signal was successfully succeeded in the synchronization non-established state and the number of times the pattern matching with the segment sync signal was continuously failed in the synchronized state were established. count. The rear protection stage number holding unit 104 holds the rear protection stage number 204 described above, and the front protection stage number holding unit 105 holds the front protection stage number 205 described above.

[0005] The synchronization determination unit 106 determines, based on the count value 203 of the counting unit 103, the number of rear protection stages 204, and the number of front protection stages 205, whether a synchronization is established or a synchronization is not established. More specifically, the synchronization determination unit 10
6 is determined to transition to the synchronization established state when the count value 203 becomes equal to or more than the backward protection stage number 204 in the synchronization non-established state, and when the count value 203 becomes more than the forward protection stage number 205 in the synchronization established state. It is determined that the state transits to the synchronization non-established state. The synchronization state signal 206 output from the synchronization determination unit 106 is supplied to the counting unit 103 and the synchronization detection signal generation unit 107.

The synchronization detection signal generation section 107 outputs a segment synchronization detection signal SS when receiving the collation result signal 202 (which may indicate either collation success or collation failure) in the synchronization established state.

[0007]

However, the above-mentioned conventional VSB demodulation system incorporating the synchronization detecting device includes:
There are the following problems. If there is any object near the antenna of the digital broadcast receiver, the VSB demodulation system receives both the original radio wave and the reflected wave from the object, and no image is displayed on the screen of the receiver. This phenomenon is called a proximity ghost. When the receiver receives a radio wave that causes a proximity ghost, the segment synchronization pattern is disturbed in the input signal of the VSB demodulation system (see FIG. 9). Therefore, even if pattern matching is performed only on the upper 1 bit (sign bit) between the input signal and the segment synchronization signal, the synchronization signal cannot be correctly detected, or the synchronization signal is detected at an incorrect timing. Occurs.

[0008] The segment synchronization detection signal SS output from the synchronization detection device is input to a waveform equalization unit provided at a subsequent stage of the synchronization detection device. However, if the segment synchronization signal is detected at an incorrect timing, the waveform equalizer
It only functions to correct the timing of segment synchronization detection, and cannot perform the original function of removing ghosts by the transmission path.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a synchronization detection device having excellent synchronization detection capability and synchronization retention capability, and to provide a VSB demodulation system having high proximity ghost interference removal capability using the same.

[0010]

A first aspect of the present invention is a synchronization detecting apparatus for detecting a synchronization signal from an input signal including the synchronization signal, wherein the synchronization detection apparatus receives supply of a clock signal and an input signal. A sampling unit that samples an input signal at any of a plurality of sample points within one cycle of a clock signal, and an output signal of the sampling unit includes the same signal pattern as that of the synchronization signal in the same cycle as the synchronization signal. The pattern matching unit that checks whether or not the pattern matching unit receives the matching result in the pattern matching unit, and determines the number of times that pattern matching has succeeded continuously in the synchronization non-established state and the number of times that pattern matching has failed continuously in the synchronization established state. A counting unit that counts, a rear protection stage number holding unit that holds the number of synchronization rear protection stages, and a front protection stage number holding unit that holds the number of synchronization front protection stages. Based on the count value of the counting unit, the number of rear protection stages, and the number of front protection stages, a synchronization determination unit that determines whether or not a synchronization is established.In the synchronization establishment state, a synchronization detection signal is generated at the timing of pattern matching in the pattern matching unit. A synchronization detection signal generation unit that generates the synchronization detection signal, and wherein the sampling unit switches the sample point of the input signal while the synchronization is not established. According to the first aspect, in the synchronization non-established state, the sampling point of the input signal is switched, and the detection of the synchronization signal is performed on the sampled input signal. Thus, the synchronization signal can be detected with high accuracy. Also, by applying this synchronization detection device to a VSB demodulation system, a segment synchronization signal can be detected with high accuracy,
The proximity ghost interference removal ability can be enhanced.

In a second aspect based on the first aspect, the sampling section uses the clock multiplication section for multiplying the clock signal, and uses the multiplied clock signal to convert the input signal every minimum time when the input signal changes. A switching-type sampling unit that switches the sampling point of the input signal during a plurality of timings defined by the multiplied clock signal while sampling and while the synchronization is not established. According to the second aspect, the clock signal is multiplied, and the input signal is sampled using the multiplied clock signal. Thereby, a large number of sample points can be set at equal intervals within one cycle of the clock signal, and the synchronization detection ability can be improved.

In a third aspect based on the first aspect, the sampling section selects and outputs one of a non-inverted signal and an inverted signal of the clock signal, and outputs the clock signal while the synchronization is not established. A clock switching unit that switches a signal to be output between a non-inverted signal and an inverted signal of the same, and a fixed sampling unit that samples an input signal at every minimum time when an input signal changes using an output signal of the clock switching unit And According to the third aspect, the input signal is sampled by either the non-inverted signal or the inverted signal of the clock signal. As a result, the synchronization detection capability can be improved with a simple configuration.

In a fourth aspect based on the first aspect, the input signal is data having a frame structure conforming to the ATSC standard, and the synchronization signal is a segment synchronization signal conforming to the ATSC standard. . According to the fourth aspect, it is possible to provide a VSB demodulation system that detects a segment synchronization signal with high accuracy and has a high near-ghost interference removal capability.

According to a fifth aspect, in the first aspect, the quality information indicating the quality of the input signal is supplied, and when the quality of the input signal is better than a predetermined standard, the output of the sampling unit is transmitted to the pattern matching unit. A synchronous detection signal is output when an input signal is supplied instead of a signal.
According to the fifth aspect, one of the two types of segment synchronization detection signals is selected and output according to the quality of the input signal. Thus, when the quality of the input signal is poor, the synchronization signal is detected with high accuracy using the sampled input signal. When the quality of the input signal is good, the synchronization signal is detected using the input signal as it is. be able to. That is, by switching the synchronization detection method according to the quality of the input signal, the synchronization signal can be detected according to the situation. In addition, by applying this synchronization detection device to a VSB demodulation system, a segment synchronization signal can be detected with high accuracy, and the ability to remove proximity ghost interference can be enhanced.

In a sixth aspect based on the fifth aspect, the input signal is data having a frame structure conforming to the ATSC standard, the synchronization signal is a segment synchronization signal conforming to the ATSC standard, and the quality information is: It is characterized by indicating whether or not a proximity ghost has occurred in an input signal. According to the sixth aspect, it is possible to provide a VSB demodulation system that detects a segment synchronization signal with high accuracy and has a high near-ghost interference removal capability.

A seventh aspect of the present invention is a synchronization detecting device for detecting a synchronization signal from an input signal including the synchronization signal, wherein the input signal includes the same signal pattern as the synchronization signal in the same cycle as the synchronization signal. A pattern matching unit for checking whether or not the pattern matching unit receives the matching result in the pattern matching unit,
A counting unit that counts the number of times that pattern matching has failed successively in the synchronization established state, a backward protection stage number holding unit that holds the number of backward protection stages of synchronization, a forward protection stage number holding unit that holds the number of forward protection stages of synchronization, Based on the count value of the counting unit, the number of rear protection stages, and the number of front protection stages, a synchronization determination unit that determines whether or not a synchronization is established.In the synchronization establishment state, a synchronization detection signal is generated at the timing of pattern matching in the pattern matching unit. A synchronization detection signal generation unit that generates, a shift amount control unit that receives supply of quality information indicating the quality of a result of processing the input signal using the synchronization detection signal, and calculates a shift amount of the synchronization detection signal based on the quality information; A synchronization detection signal shift unit that shifts the synchronization detection signal in the time direction according to the shift amount obtained by the shift amount control unit. According to the seventh aspect, the synchronization detection signal is output after being shifted in the time direction based on the quality information, and the shift amount of the synchronization detection signal is determined so that the quality indicated by the quality information is improved. You. This makes it possible to detect the segment synchronization signal with high accuracy. In addition, by applying this synchronization detection device to a VSB demodulation system, a segment synchronization signal can be detected with high accuracy, and the ability to remove proximity ghost interference can be enhanced.

In an eighth aspect based on the seventh aspect, the shift amount control section changes the shift amount of the synchronization detection signal when the quality of the result of processing the input signal is lower than a predetermined standard. Features.

In a ninth aspect based on the seventh aspect, the shift amount control section determines the shift amount of the synchronization detection signal so that the quality of the result of processing the input signal is optimized. . According to the eighth and ninth aspects, the shift amount of the synchronization detection signal is determined so that the quality indicated by the quality information is improved. This makes it possible to detect the segment synchronization signal with high accuracy.

In a tenth aspect based on the ninth aspect, the input signal is data having a frame structure conforming to the ATSC standard, and the synchronization signal is a segment synchronization signal conforming to the ATSC standard. .

According to an eleventh aspect, in the tenth aspect,
The quality information is characterized by being error rate information on a signal obtained by waveform-equalizing the input signal using the synchronization detection signal. According to the tenth and eleventh aspects, it is possible to provide a VSB demodulation system that detects a segment synchronization signal with high accuracy and has a high near-ghost interference removal capability.

A twelfth invention is a synchronization detecting device for detecting a synchronization signal from an input signal including the synchronization signal, wherein the input signal includes the same signal pattern as the synchronization signal at the same period as the synchronization signal. A pattern matching unit that checks whether or not the pattern matching has been performed, a counting unit that receives the matching result of the pattern matching unit and counts the number of times that pattern matching has succeeded continuously in a non-established state, and a back protection that holds the number of back protection stages for synchronization. A stage number holding unit, a long period synchronization detection unit that detects a long period synchronization signal included in the input signal with a period longer than the synchronization signal, and synchronization establishment when the count value of the counting unit is equal to or greater than the number of backward protection stages. A synchronization determining unit that determines to transition to the non-synchronization state when the synchronization detection fails in the long cycle synchronization detection unit. And a synchronization detection signal generator for generating a sync detection signal at the timing of the pattern matching in the matching section. According to the twelfth aspect, once the synchronization is established, the state where the synchronization is established is maintained unless the detection of the long-period synchronization signal fails. As a result, it is possible to prevent the segment synchronization once established from being lost. That is, the ability to maintain synchronization can be increased.
Also, by applying this synchronization detection device to a VSB demodulation system, the ability to hold a segment synchronization signal is increased,
The proximity ghost interference removal ability can be enhanced.

According to a thirteenth aspect, in the twelfth aspect,
The input signal is data having a frame structure compliant with the ATSC standard, the synchronization signal is a segment synchronization signal compliant with the ATSC standard, and the long-period synchronization signal is a field synchronization signal compliant with the ATSC standard. And According to the thirteenth aspect, it is possible to provide a VSB demodulation system which detects that the once established segment synchronization signal is held and has a high near-ghost interference removal capability.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block diagram showing a configuration of a synchronization detecting device according to a first embodiment of the present invention. The synchronization detection device 110 shown in FIG. 1 includes a field synchronization detection unit 101, a clock multiplication unit 111, a switching type sampling unit 112, a pattern matching unit 102, a counting unit 103, a rear protection stage number holding unit 104, a front protection stage number holding unit 105, A synchronization determination unit 106 and a synchronization detection signal generation unit 107 are provided. Synchronization detection device 110
Is characterized by sampling an input signal with a multiplied clock in order to detect a segment synchronization signal, and switching a sample point of the input signal while synchronization is not established.

Before describing the synchronization detection device 110, a digital demodulation system incorporating this device will be described. FIG. 2 shows a V having a built-in synchronization detection device 110.
FIG. 2 is a block diagram illustrating a configuration of an SB demodulation system. FIG.
The VSB demodulation system shown in FIG. 1 includes a receiving antenna 10, a tuner 20, a down converter 30, and a digital demodulation unit 4.
0 and an error correction unit 50, and constitutes a part of a receiver conforming to the ATSC standard, which is the US terrestrial digital broadcasting standard. For the US terrestrial digital broadcasting standard, refer to “ATSC Standard: Digital Television Standar”.
d, Revision B ", Doc. A / B53, August 2001, the details of which are provided.

Each component of the VSB demodulation system operates as follows. The receiving antenna 10 receives a terrestrial broadcast wave modulated by VSB. The tuner 20 selects a channel desired by the viewer. Down converter 3
0 converts the frequency of the output of the tuner 20 to a frequency band in which the digital demodulation unit 40 can operate normally. The digital demodulation unit 40 outputs the output of the down converter 30
Demodulate. The error correction unit 50 uses the error correction code,
Correct the error that occurred in the transmission path. The VSB demodulated signal output from the error correction unit 50 is converted into a video / audio signal by an MPEG decoding unit (not shown).

The digital demodulation unit 40 includes an A / D converter 4
1. gain control unit 42, digital detection unit 43, clock recovery unit 44, signal interpolation unit 45, NTSC interference removal unit 4.
6, a synchronization detecting device 110, a waveform equalizing unit 47, a phase noise removing unit 48, and a bit error rate measuring unit 49. Among them, the synchronization detection device 110 is the one shown in FIG.

Each component of the digital demodulation unit 40 operates as follows. The down-converter 30 at the preceding stage of the digital demodulation unit 40 outputs a baseband VSB modulated signal as an input signal DI. A / D converter 41
Converts the input signal DI into digital data. The gain control unit 42 obtains a gain adjustment value GA based on the level of the digital data output from the A / D converter 41. The gain adjustment value GA is supplied to the tuner 20 and is used to adjust the amplitude of a signal received by the receiving antenna 10.

The digital detection unit 43 includes an A / D converter 41
The baseband signal is extracted from the digital data output from, and the frequency error is removed. The clock reproducing unit 44 detects a phase shift of the sampling clock in the A / D converter 41 based on the signal detected by the digital detecting unit 43, and reproduces the clock. The reproduced clock is supplied to the signal interpolation unit 45 and the synchronization detection device 110. The signal interpolation unit 45 performs an up-sampling process on the signal detected by the digital detection unit 43 using the clock recovered by the clock recovery unit 44.
Accordingly, the signal detected by the digital detection unit 43 is
Interpolated at a predetermined ratio. The NTSC interference removal unit 46
NTS included in the signal interpolated by the signal interpolation unit 45
The level of the C interference wave is detected, and the interference wave is removed using a built-in filter.

The synchronization detecting device 110 includes a clock recovery unit 4
The signal interpolation unit 4 uses the clock CK supplied from the
A field synchronization signal and a segment synchronization signal are detected from the input signal DT interpolated in step 5, and a field synchronization detection signal FS and a segment synchronization detection signal SS are output. The two types of synchronization detection signals output from the synchronization detection device 110 are used as synchronization signals for the entire digital demodulation unit 40 and are also supplied to the waveform equalization unit 47.

The waveform equalizer 47 includes an NTSC interference remover 4
6. The transmission line distortion contained in the output signal of No. 6 is detected, and the distortion is removed. More specifically, the waveform equalizing unit 47 specifies the position of the field synchronization signal using the two types of synchronization detection signals output from the synchronization detection device 110, and uses the signal pattern of the field synchronization signal to determine the waveform and the like. The coefficient of the built-in filter is controlled according to the conversion algorithm. In addition, the waveform equalizer 47 has a function of improving the waveform equalization capability using a signal pattern other than the field synchronization signal.

FIG. 3 is a block diagram showing a detailed configuration of the waveform equalizing section 47. The waveform equalization unit 47 illustrated in FIG. 3 includes a waveform equalization filter 471, a training control unit 472,
A blind control unit 473 and a coefficient updating unit 474 are provided. The waveform equalizing filter 471 is a digital filter for removing a ghost due to a transmission path.
Each of the training control unit 472 and the blind control unit 473 has the 2
Kind of synchronization detection signal is supplied. The training control unit 472 obtains tap coefficients of the waveform equalization filter 471 based on these synchronization detection signals according to a waveform equalization algorithm using a signal pattern of a field synchronization signal. The blind control unit 473 calculates a tap coefficient of the waveform equalization filter 471 according to a waveform equalization algorithm using a signal pattern other than the field synchronization signal. The coefficient updating unit 474 converts one of the tap coefficient obtained by the training control unit 472 and the tap coefficient obtained by the blind control unit 473 into a filter 471 for waveform equalization.
Set to.

As described above, the tap coefficient of the waveform equalizing filter 471 improves the waveform equalizing ability according to the signal pattern of the field synchronization signal or the waveform equalization algorithm using a signal pattern other than the field synchronization signal. Is controlled as follows. Thereby, the waveform equalizer 47
The ghost due to the transmission path included in the output signal of the NTSC interference removal unit 46 can be removed.

The phase noise removing section 48 detects a phase noise component included in the output signal of the waveform equalizing section 47 and removes it. The resulting output signal DO is output to error correction section 50. The error correction unit 50 outputs the output signal D
When an error is detected for O, an error detection signal ER indicating that fact is output. The bit error rate measuring unit 49
The bit error rate of the output signal DO is determined based on the error detection signal ER.

FIG. 4 is a diagram showing a format of data having a frame structure defined by the ATSC standard.
As shown in FIG. 4, in the data defined by the ATSC standard, one frame is composed of two fields, one field is composed of 313 segments, and one segment is 83 segments.
It is composed of two symbols (one symbol is about 10.76 MHz). At the head of each segment, a segment synchronization signal for four symbols is arranged. In addition, a field synchronization signal for one segment is arranged for every 313 segments. Data is transmitted and received using symbols that are neither included in the segment synchronization signal nor in the field synchronization signal.

FIG. 5 is a diagram showing details of a segment including a field synchronization signal. FIG. 6 is a diagram showing details of a segment including data. As shown in FIGS. 5 and 6, in the 8-level VSB system, the signal level of each symbol can take 8 values of ± 7, ± 5, ± 3, and ± 1.
However, the signal level of the symbols included in the segment synchronization signal or the field synchronization signal (excluding the last 12 symbols) can take only two values of ± 5. As shown in FIGS. 5 and 6, the signal levels of the four symbols included in the segment synchronization signal are +5, -5, -5,
+5.

Hereinafter, with reference to FIG.
The operation of 0 will be described. The field synchronization detection unit 101
A field synchronization signal included in the input signal DT is detected, and the field synchronization detection signal FS is detected at the detected timing.
Is output.

Components other than the field synchronization detector 101 constitute a segment synchronization detector 119. The segment synchronization detection unit 119 has a synchronization backward protection function and a forward protection function, and additionally has a clock multiplication function and a sample point switching type sampling function.
The pattern matching unit 102, the counting unit 103, the backward protection stage number holding unit 104, the front protection stage number holding unit 105, the synchronization determination unit 106, and the synchronization detection signal generation unit 107 1
The operation is the same as that of the segment synchronization detection unit 109 in the conventional synchronization detection device 100 except that the signal is output from the unit 12.

The pattern matching section 102 performs pattern matching between the output signal of the switchable sampling section 112 and the segment synchronization signal, and outputs a matching result signal 202 indicating the success or failure of the matching. More specifically, the pattern matching unit 102 checks whether the same signal pattern as the segment synchronization signal is included in the output signal of the switching-type sampling unit 112 at the same cycle as the segment synchronization signal, and indicates the result. A collation result signal 202 is output. The matching result signal 202 is output at the same cycle as the segment synchronization signal.

Although the signal pattern of the segment synchronization signal is ideally +5, -5, -5, and +5 in order from the head, the segment synchronization signal included in the input signal DT must take this ideal value. Is rare. Therefore, if pattern matching between the input signal DT and the segment synchronization signal is performed at eight levels (3 bits), practical segment synchronization detection cannot be performed. Therefore, the pattern matching unit 102
Performs pattern matching on only the upper one bit (sign bit). Note that, depending on the application form of the synchronization detection device 110, the pattern matching may be performed on upper several bits.

The counting section 103 includes a counter and a control circuit for the counter. Using a built-in counter, the counting section 103 counts the number of times that pattern matching with the segment synchronization signal has succeeded continuously and the number of times that pattern matching has failed successively. More specifically, the counting unit 103
, The collation result signal 202 and the synchronization state signal 206 output from the synchronization determination unit 106 are input. The synchronization state signal 206 is a signal indicating whether the state is a synchronization establishment state or a synchronization non-establishment state.

The counting section 103 operates according to the following four cases. First, when the counting unit 103 receives the matching result signal 202 indicating the matching is successful in the synchronization non-established state, the counting unit 103 updates the counter by one. Secondly, when the counting unit 103 receives the matching result signal 202 indicating the matching failure in a non-synchronization state, the counting unit 103 initializes the counter. Third, when the counting unit 103 receives the matching result signal 202 indicating the matching failure in the synchronization established state, the counting unit 103 updates the counter by one. Fourth, the counting unit 103
When a matching result signal 202 indicating successful matching is received in a synchronization established state, the counter is initialized. In order to count the number of successes and the number of failures, the counting unit 103
One counter may be provided, or one counter may be used by switching to two uses.

The number of backward protection stages holding unit 104 holds the number of backward protection stages 204 (that is, the number of times that the pattern matching with the synchronization signal is required to transition from the synchronization non-establishment state to the synchronization establishment state, and succeeds in succession). are doing. The forward protection stage number holding unit 105 stores the forward protection stage number 205 (that is, necessary to transition from the synchronization established state to the synchronization non-established state,
(The number of times that pattern matching with the synchronization signal fails consecutively). The number of protection stages held by these holding units may be variable or fixed. When the number of protection stages is variable, each holding unit is configured by a storage circuit, and when the number of protection stages is fixed, each holding unit is configured by a circuit that outputs a fixed value. When the number of rear protection stages 204 and the number of front protection stages 205 have the same value, the two holding units may be configured by one circuit.

The synchronization determining unit 106 includes a counting unit 103
, The number of rear protection stages 204 held in the rear protection stage number holding unit 104, and the front protection stage number holding unit 1
05 and the number of forward protection steps 205 held in the storage area are input.
Based on these inputs, the synchronization determination unit 106 determines whether a synchronization is established or a state where synchronization is not established, and outputs a synchronization state signal 206 indicating the result. More specifically, the synchronization determination unit 106 determines that the synchronization is not established in the initial state. When the count value 203 becomes equal to or larger than the number of backward protection stages 204 in the synchronization non-establishment state, the synchronization determination unit 106 determines that the state transitions to the synchronization establishment state. Further, the synchronization determination unit 106 determines that the count value 2
When 03 is equal to or greater than the forward protection stage number 205, it is determined that the state transits to the synchronization non-established state.

The synchronization detection signal generator 107 receives the comparison result signal 202 and the synchronization state signal 206. The synchronization detection signal generator 107 outputs the segment synchronization detection signal SS when receiving the collation result signal 202 in the synchronization established state. In the synchronization established state, the synchronization detection signal generation unit 107 not only receives the collation result signal 202 indicating successful collation but also receives the segment synchronization detection signal 202 indicating failed collation. Signal SS
Is output. The segment synchronization detection signal SS has a value of 0 (or 1) for one symbol time, for example, in accordance with the timing at which the beginning of the segment synchronization signal is detected.
May be a signal having a value of 0 (or a value of 1) for a time corresponding to 4 symbols in accordance with the length of the segment synchronization signal.

In the synchronization detection device 110, the input signal DT is input in synchronization with the clock CK. However, depending on the state of the input signal DT, this synchronization may be lost before and after.
The cycle of the clock CK is the same as the cycle of the input signal DT, or an integral multiple thereof (two, four, etc.). In consideration of such a temporal relationship between the clock CK and the input signal DT, some mechanism is required to correctly detect the segment synchronization signal.

Therefore, the synchronization detecting device 110 includes a clock multiplying unit 111 and a switching type sampling unit 112 as characteristic components. Clock multiplier 111
Is supplied with the clock CK reproduced by the clock reproducing unit 44. The clock multiplication unit 111 multiplies the clock CK by a factor of two or an integer multiple of two or more. The multiplied clock is supplied to the switching-type sampling unit 112.

The switching type sampling section 112 samples the input signal DT using the multiplied clock. At this time, the switching-type sampling unit 112 switches the sampling point of the input signal DT while the synchronization state signal 206 indicates the synchronization non-establishment state. The details are
It is as follows.

Assume that the cycle of the clock CK is T, the clock multiplying unit 111 multiplies the clock CK by N times, and the switching type sampling unit 112 samples the input signal DT at the rising edge of the multiplied clock. A set of times separated by an integer multiple of the period T from a certain rising time of the multiplied clock is defined as a first sample point set. Next, a set of times delayed by time T / N from each time included in the first sample point set is defined as a second sample point set. Next, a set of times that are further delayed by the time T / N from the times included in the second sample point set is referred to as a third set.
Is defined as a sample point set. Hereinafter, similarly, the fourth to N-th sample point sets are defined (see FIG. 7).

The switching-type sampling section 112 selects one of the first to N-th sample point sets, and samples the input signal DT at each time included in the selected sample point set. Switchable sampling unit 112
Switches the selection of the sample point set every predetermined time S while the synchronization state signal 206 indicates the synchronization non-establishment state. For example, if the synchronization state signal 206 does not change to the synchronization established state after a predetermined time S in a state where the first sample point set is selected, the switching-type sampling unit 112 Select a set of sample points. Thereafter, if the synchronization state signal 206 does not change to the synchronization established state even after a lapse of the predetermined time S, the switching type sampling section 112
Selects a third set of sample points. Similarly, if the synchronization state signal 206 does not change to the synchronization established state even after the predetermined time S has elapsed, the switching-type sampling unit 112 sequentially selects the fourth to N-th sample point sets. Thereafter, the first to N-th sample point sets are selected repeatedly. At time S, 1
A time longer than the time per segment multiplied by the number of backward protection stages 204 is used.

The order of selecting the set of sample points in the switching type sampling unit 112 is arbitrary. For example,
When the clock multiplying unit 111 multiplies the clock CK by 8, the switching-type sampling unit 112 may select a set of sample points in order from the first to the eighth as in the above-described example. Alternatively, the switching type sampling unit 112
Are the first, fifth, third, seventh, second, sixth, fourth, eighth
, A sample point set temporally separated from the currently selected sample point set may be selected as the next sample point set.

Referring to FIGS. 8 and 9, the effect of the synchronization detecting device 110 will be described. FIG. 8 shows the synchronization detecting device 110.
FIG. 3 is a diagram illustrating an example of a segment synchronization signal input to the LM. The white circles in FIG. 8 indicate the digital values of the signal amplitude when the input signal DT is sampled with the correct clock. The ideal values of these four symbols are +5, -5, -5, and +5 in order from the top. When a segment synchronization signal having such a signal pattern is input, even a conventional synchronization detection device can correctly detect the segment synchronization signal.

However, in general, it is rare that a segment synchronizing signal having an ideal signal pattern is input due to a distortion due to a transmission line, a frequency error of a tuner, thermal noise, or the like. For example, as shown in FIG. 9, a ghost wave (broken line) delayed by 1/4 cycle from an ideal wave (solid line).
Is present, a synthesized wave (thick line) having a larger amplitude and a delayed phase than the ideal wave is input to the synchronization detection device 110.

In the following, it is assumed that the synchronization detection device 110 doubles the clock CK and samples the input signal DT at the rising edge of the doubled clock. Further, for a clock obtained by doubling the clock CK, a set of times matching the rising edge of the clock CK is defined as a first sample point set, and a set of times matching the falling edge of the clock CK is defined as a second sample point set. .

When the synthesized wave shown in FIG. 9 is sampled at each time included in the first sample point set, the upper one bit (sign bit) of the sampling result is positive, ×, negative, × Becomes Where the symbol x is
This represents a state where the amplitude of the signal is close to 0 and cannot be determined as either positive or negative. On the other hand, when the same synthesized wave is sampled at each time included in the second sample point set,
The sign bits are positive, negative, negative, and positive in order from the top.
Since the signal pattern of the segment synchronization signal is +5, -5, -5, and +5 in order from the beginning, the sign bits of this pattern are positive, negative, negative, and positive in order from the beginning.

Therefore, when the synthesized wave shown in FIG. 9 is input, even if the synthesized wave is sampled at the rising edge of the original clock CK, the segment synchronizing signal cannot be detected. It can be seen that if the input signal is sampled at the rising edge, the segment synchronization signal can be correctly detected.

As described above, the synchronization detecting device 110
It has a clock multiplication function and a sampling point switching type sampling function. Therefore, the synchronization detecting device 11
If the segment sync signal cannot be detected using the first set of sample points, 0 switches the sample point to the second set of sample points and detects a segment sync signal. Therefore, according to the synchronization detection device 110, even when a signal that causes a proximity ghost is input, the segment synchronization signal can be detected with high accuracy.

As described above, the synchronization detection device according to the present embodiment multiplies the clock signal, samples the input signal with the multiplied clock, and switches the sampling point of the input signal while the synchronization is not established. It is characterized by the following. Therefore, according to this synchronization detection device, a segment synchronization signal can be detected with high accuracy. Further, a VSB demodulation system having a high proximity ghost interference removal capability can be provided by using the synchronization detection device.

(Second Embodiment) FIG. 10 is a block diagram showing a configuration of a synchronization detecting device according to a second embodiment of the present invention. The synchronization detection device 120 shown in FIG. 10 includes a field synchronization detection unit 101, a clock switching unit 121, a fixed type sampling unit 122, a pattern matching unit 102, a counting unit 103, a rear protection stage number holding unit 104, a front protection stage number holding unit 105, A synchronization determination unit 106 and a synchronization detection signal generation unit 107 are provided. The synchronization detection device 120 includes:
In order to detect a segment synchronization signal, a non-inverted signal or an inverted signal of a clock is selected, and an input signal is sampled using the selected signal. Among the components of the present embodiment, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

The synchronization detection device 120 is used by being built in the VSB demodulation system, like the synchronization detection device 110 according to the first embodiment. That is, the synchronization detection device 120
Is used instead of the synchronization detection device 110 in the VSB demodulation system shown in FIG.

In FIG. 10, the field synchronization detector 1
Components other than 01 constitute the segment synchronization detection unit 129. The clock switching unit 121 and the fixed sampling unit 122 are characteristic components of the synchronization detection device 120.

The clock switching section 121 is supplied with the clock CK reproduced by the clock reproduction section 44. The clock switching unit 121 selects and outputs either a non-inverted signal or an inverted signal of the clock CK based on the synchronization state signal 206. The fixed sampling unit 122 samples the input signal DT using the output signal of the clock switching unit 121 as a clock.

The clock switching method of the clock switching unit 121 is the same as that of the synchronization detecting device 11 according to the first embodiment.
This is the same as the sampling point switching method of 0. That is, the clock switching unit 121 should output the non-inverted signal of the clock CK when the synchronization state signal 206 does not change to the synchronization established state after a predetermined time S has elapsed. The signal is switched to an inverted signal of the clock CK. In addition, the clock switching unit 121
If the synchronization state signal 206 does not change to the synchronization established state after a predetermined time S while the inverted signal of K is being output, the signal to be output is switched to the non-inverted signal of the clock CK. .

The effect of the synchronization detection device 120 is the same as the effect of the synchronization detection device 110 according to the first embodiment. FIG. 11 shows the same segment synchronization signal as in FIG. 9 again. 9 is compared with FIG. 11, the set of rising times of the non-inverted signal of the clock CK is associated with the first sample point set, and the set of times of rising of the inverted signal of the clock CK is defined as the second set. Correspond to the sample point set. As a result, the synchronization detection device 120
It is easily derived that the segment synchronization signal can be detected from the composite wave shown in FIG.

As described above, the synchronization detection apparatus according to the present embodiment is characterized in that either the non-inverted signal or the inverted signal of the clock is selected, and the input signal is sampled using the selected signal. Therefore, according to this synchronization detection device, a segment synchronization signal can be detected with high accuracy. Also, using this synchronization detection device,
It is possible to provide a VSB demodulation system having a high proximity ghost interference removal capability.

(Third Embodiment) FIG. 12 is a block diagram showing a configuration of a synchronization detecting device according to a third embodiment of the present invention. The synchronization detection device 130 shown in FIG. 12 includes a field synchronization detection unit 101, a first segment synchronization detection unit 1
39a, a second segment synchronization detecting section 139b, and a selector 131. Synchronization detection device 130
Is characterized by comprising two types of segment synchronization detection units, and selecting and outputting one of two types of segment synchronization detection signals according to whether or not a proximity ghost has occurred. Among the components of the present embodiment, the same components as those of the first embodiment are denoted by the same reference numerals, and
Description is omitted.

The synchronization detection device 130 is used in the VSB demodulation system, similarly to the synchronization detection device 110 according to the first embodiment. That is, the synchronization detection device 130
Is used instead of the synchronization detection device 110 in the VSB demodulation system shown in FIG. However, in the present embodiment, the waveform equalizer 47
It is assumed that a switching signal SW indicating whether or not a proximity ghost has occurred in the input signal is supplied. The switching signal SW is an example of quality information indicating the quality of the input signal DT.

The first segment synchronization detecting section 139a
A clock multiplying unit 111, a switching type sampling unit 112,
A pattern matching unit 102a, a counting unit 103a, a rear protection stage number holding unit 104a, a front protection stage number holding unit 105a,
Synchronization determination section 106a and synchronization detection signal generation section 10
7a. First segment synchronization detection section 139
“a” performs the same operation as the segment synchronization detection unit 119 of the synchronization detection device 110 according to the first embodiment, and outputs a first segment synchronization detection signal 207a.

The second segment synchronization detector 139b
A pattern matching unit 102b, a counting unit 103b, a rear protection stage number holding unit 104b, a front protection stage number holding unit 105b,
Synchronization determination section 106b and synchronization detection signal generation section 10
7b. Second segment synchronization detector 139
b performs the same operation as the segment synchronization detection unit 109 of the conventional synchronization detection device 100, and outputs a second segment synchronization detection signal 207b.

The selector 131 receives a first segment synchronization detection signal 207a, a second segment synchronization detection signal 207b, and a switching signal SW. Selector 1
31 selects a signal to be output according to the following two cases.

When the occurrence of a proximity ghost is detected, the waveform equalization section 47 outputs a switching signal SW indicating that fact. In this case, the selector 131 sets the first segment synchronization detection signal 239 as the segment synchronization detection signal SS.
a is output. Therefore, the waveform equalizer 47 specifies the position of the field synchronization signal with reference to the segment synchronization detection signal detected by the synchronization detection device 110 according to the first embodiment, and uses the signal pattern of the field synchronization signal. According to the waveform equalization algorithm, the waveform equalization ability is improved.

On the other hand, when the occurrence of a proximity ghost is not detected, the waveform equalizing section 47 outputs a switching signal SW indicating that fact. In this case, the selector 131
Outputs the second segment synchronization detection signal 239b as the segment synchronization detection signal SS. For this reason, the waveform equalizing unit 47 specifies the position of the field synchronization signal with reference to the segment synchronization detection signal detected by the conventional synchronization detection device 100, and uses the waveform equalization algorithm using the signal pattern of the field synchronization signal. Accordingly, the waveform equalizing ability is improved.

As described above, the synchronization detection apparatus according to the present embodiment selects and outputs one of two types of segment synchronization detection signals depending on whether or not a proximity ghost has occurred. Features. Therefore, according to this synchronization detecting device, when a proximity ghost has occurred, the segment synchronization signal is detected with high accuracy using the multiplied clock. The segment synchronization signal can be detected by the technique. That is, by switching the synchronization detection method depending on whether or not a proximity ghost has occurred, the segment synchronization signal can be detected according to the situation. Further, a VSB demodulation system having a high proximity ghost interference removal capability can be provided by using the synchronization detection device.

In the synchronization detection device 130, the segment synchronization detection unit 119 of the synchronization detection device 110 according to the first embodiment is used as the first segment synchronization detection unit 139a.
However, instead of this, the segment synchronization detection unit 12 of the synchronization detection device 120 according to the second embodiment is used.
9 may be used.

Further, the synchronization detection device 130 has two types of segment synchronization detection units, but instead has one segment synchronization detection unit having two functions that can be switched by the switching signal SW. It may be that. Specifically, the following three modifications can be considered. As a first modified example, in the synchronization detection device 110 according to the first embodiment, when the proximity ghost has not occurred, the switching type sampling unit 112 does not switch the sample point. it can. As a second modified example, in the synchronization detection device 120 according to the second embodiment, when a proximity ghost does not occur, the synchronization detection device that does not switch the signal to be output by the clock switching unit 121 is described. Can be configured. As a third modification, in the synchronization detection devices 110 and 120 according to the first or second embodiment, the input signal to the pattern matching unit 102 is changed according to the switching signal SW to the output signal of the preceding stage and the input signal DT. And a selector for switching between the two.

In any of the synchronization detection devices according to these various modifications, when no proximity ghost is generated, the same segment synchronization detection signal as when the input signal DT is supplied to the pattern matching unit 102 is output. Output. Therefore, these synchronization detecting devices are also synchronized detection devices 13.
Has the same effect as 0.

(Fourth Embodiment) FIG. 13 is a block diagram showing a configuration of a synchronization detecting device according to a fourth embodiment of the present invention. The synchronization detection device 140 shown in FIG. 13 includes a field synchronization detection unit 101, a pattern matching unit 102, a counting unit 103, a rear protection stage number holding unit 104, a front protection stage number holding unit 105, a synchronization determination unit 106, and a synchronization detection signal generation unit 107. , A shift amount control unit 141, and a synchronization detection signal shift unit 142. The synchronization detection device 140
The segment synchronization detection signal is shifted in the time direction and output based on the input error rate. Among the components of the present embodiment, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

The synchronization detection device 140 is used by being incorporated in a VSB demodulation system, like the synchronization detection device 110 according to the first embodiment. That is, the synchronization detection device 140
Is used instead of the synchronization detection device 110 in the VSB demodulation system shown in FIG. However, in the present embodiment, it is assumed that the bit error rate RT for the output signal DO is supplied from the bit error rate measuring unit 49 to the synchronization detection device 140. The error rate RT is an example of quality information indicating the quality of the result of processing the input signal using the segment synchronization detection signal SS.

In FIG. 13, components other than the field synchronization detector 101 of the synchronization detector 140 constitute a segment synchronization detector 149. Shift amount control section 141
And the synchronization detection signal shift unit 142
0 is a characteristic component.

The shift rate control section 141 receives the error rate RT from the bit error rate measurement section 49. The shift amount control section 141 determines the shift amount 241 in the synchronization detection signal shift section 142 based on the error rate RT. The synchronization detection signal shift unit 142 includes a synchronization detection signal generation unit 107
And the shift amount 241 determined by the shift amount control unit 141 are input. The synchronization detection signal shift unit 142 calculates the shift amount 241
, The segment synchronization detection signal 207 is shifted forward or backward in the time direction, and the result is output as the segment synchronization detection signal SS.

The shift amount control section 141 determines the shift amount 241 as follows, for example. As a first example,
The shift amount control unit 141 controls the error rate RT at predetermined time intervals.
When the error rate RT is equal to or smaller than the predetermined value X, the current shift amount 241 is maintained. When the error rate RT exceeds the predetermined value X, the shift amount 241 is changed by a predetermined method. It is good also as making it do. Alternatively, as a second example, the shift amount control unit 141 sequentially selects selectable shift amounts, obtains an error rate after a lapse of a predetermined time for each shift amount, and determines a shift that minimizes the obtained error rate. The amount may be selected as the new shift amount 241.

As described above, the synchronization detection apparatus according to the present embodiment shifts the segment synchronization detection signal in the time direction based on the input error rate and outputs the signal. The shift amount of the segment synchronization detection signal is determined so that the error rate is reduced. Therefore, according to this synchronization detection device, a segment synchronization signal can be detected with high accuracy. Also,
By using this synchronization detection device, it is possible to provide a VSB demodulation system having high proximity ghost interference removal capability.

(Fifth Embodiment) FIG. 14 is a block diagram showing a configuration of a synchronization detecting device according to a fifth embodiment of the present invention. 14 includes a field synchronization detection unit 101, a pattern matching unit 102, a counting unit 151, a rear protection stage number holding unit 104, and a synchronization determination unit 1.
52, and a synchronization detection signal generation unit 107. The synchronization detecting device 150 is characterized in that once the segment synchronization is established, the state where the segment synchronization is established is maintained unless the detection of the field synchronization fails. Among the components of the present embodiment, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

The synchronization detection device 150 is used by being built in the VSB demodulation system, like the synchronization detection device 110 according to the first embodiment. That is, the synchronization detection device 150
Is used instead of the synchronization detection device 110 in the VSB demodulation system shown in FIG.

In FIG. 14, the field synchronization detector 1
The components other than 01 constitute the segment synchronization detection unit 159. The counting unit 151 and the synchronization determining unit 152
This is a characteristic component of the synchronization detection device 150. Also,
Another feature of the synchronization detection device 150 is that it does not include a front protection stage number holding unit.

The counting section 151 includes a counter and a control circuit for the counter. The counting unit 151 is different from the counting unit 103 according to the first to fourth embodiments in that the counting unit 151 does not count the number of times that pattern matching with the segment synchronization signal has failed successively. Counting unit 151
Is the same as the counting unit 103 in other respects.

The synchronization determining section 152 includes a counting section 151.
In addition to the count value 251 and the number 204 of rear protection stages,
The field synchronization detection signal FS output from the field synchronization detection unit 101 is input. The synchronization determination unit 152
Based on these inputs, it is determined whether a synchronization is established or a synchronization is not established, and a synchronization status signal 252 indicating the result is output. More specifically, the synchronization determination unit 152
Determines that the synchronization is not established in the initial state.
When the count value 203 becomes equal to or greater than the backward protection stage number 204 in the synchronization non-establishment state, the synchronization determination unit 152 determines that the state shifts to the synchronization establishment state. In addition, the synchronization determination unit 1
52, when the field synchronization detection unit 101 fails to detect the field synchronization signal in the synchronization established state,
It is determined that the state transits to the synchronization non-established state. Synchronization determination unit 15
For example, when detecting that the field synchronization detection signal FS is not input at a predetermined period, the field synchronization detection unit 101 determines that the field synchronization detection unit 101 has failed in detecting the field synchronization signal. Thereby, in the synchronization determination unit 152,
The number of forward protection stages becomes infinite, and the state where the segment synchronization is established is maintained unless the field synchronization detection fails.

As described above, in the synchronization detecting device according to the present embodiment, once the segment synchronization is established, the state where the segment synchronization is established is maintained unless the detection of the field synchronization signal fails. Therefore, in this synchronization detecting device, the segment synchronization once established is hardly lost. That is, this synchronization detecting device has a high synchronization holding capability. Also, using this synchronization detection device,
It is possible to provide a VSB demodulation system having a high proximity ghost interference removal capability.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a synchronization detection device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a VSB demodulation system incorporating a synchronization detection device according to first to fifth embodiments of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a waveform equalization unit of the VSB demodulation system illustrated in FIG. 2;

FIG. 4 is a diagram showing a format of data having a frame structure specified by the ATSC.

FIG. 5 is a diagram showing details of a segment including a field synchronization signal specified by the ATSC.

FIG. 6 is a diagram showing details of a segment including data specified by the ATSC.

FIG. 7 is a diagram for explaining a sample point set in the synchronization detection device according to the first embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of a segment synchronization signal input to the synchronization detection device.

FIG. 9 is a diagram illustrating a state where segment synchronization is detected by the synchronization detection device according to the first embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a synchronization detection device according to a second embodiment of the present invention.

FIG. 11 is a diagram illustrating a state in which segment synchronization is detected by a synchronization detection device according to a second embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of a synchronization detection device according to a third embodiment of the present invention.

FIG. 13 is a block diagram illustrating a configuration of a synchronization detection device according to a fourth embodiment of the present invention.

FIG. 14 is a block diagram illustrating a configuration of a synchronization detection device according to a fifth embodiment of the present invention.

FIG. 15 is a block diagram illustrating a configuration of a conventional synchronization detection device.

[Explanation of symbols]

100, 110, 120, 130, 140, 150: Synchronization detection device 101: Field synchronization detection unit 102: Pattern matching unit 103, 151 ... Count unit 104: Rear protection stage number holding unit 105: Front protection stage number holding unit 106, 152 ... Synchronization determination unit 107: synchronization detection signal generation unit 109, 119, 129, 139, 149, 159: segment synchronization detection unit 111: clock multiplication unit 112: switchable sampling unit 121: clock switching unit 122: fixed sampling unit 131: Selector 141 shift amount control unit 142 synchronization detection signal shift unit 202 collation result signal 203, 251 count value 204 rear protection stage number 205 front protection stage number 206, 252 synchronization state signal 207, 239 segment synchronization detection signal 241 ... shift amount

Continuing on the front page (72) Inventor Hisaya Kato 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Naoya Tokunaga 1006 Okadoma Kadoma Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (72) Invention Person Kazuaki Suzuki 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture, Japan Matsushita Electric Industrial Co., Ltd. (72) Inventor Kazuya Ueda 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture F-term, Matsushita Electric Industrial Co., Ltd. BA30 DA01

Claims (13)

[Claims] 1. A synchronization detecting device for detecting a synchronization signal from an input signal including a synchronization signal, comprising: receiving a clock signal and the input signal; receiving a plurality of samples in one cycle of the clock signal; A sampling unit for sampling the input signal at one of the points; and a pattern matching unit for checking whether an output signal of the sampling unit includes the same signal pattern as the synchronization signal in the same cycle as the synchronization signal. And the number of times the pattern matching unit receives the matching result in the pattern matching unit and succeeds in pattern matching continuously in a synchronization non-established state,
A counting unit that counts the number of times pattern matching has failed consecutively in the synchronization established state, a rear protection stage number holding unit that holds the number of synchronization rear protection stages, a front protection stage number holding unit that holds the number of synchronization front protection stages, A synchronization determination unit that determines whether or not a synchronization is established based on the count value of the counting unit, the number of rear protection stages, and the number of front protection stages. A synchronization detection signal generation unit configured to generate a synchronization detection signal, wherein the sampling unit switches a sample point of the input signal while the synchronization is not established. 2. The sampling unit, comprising: a clock multiplication unit that multiplies the clock signal; and a sampling unit that samples the input signal at every minimum time when the input signal changes, using the multiplied clock signal. 2. The synchronization detection device according to claim 1, further comprising: a switchable sampling unit that switches a sample point of the input signal among a plurality of timings defined by the multiplied clock signal during the established state. 3. 3. The sampling section selects and outputs one of a non-inverted signal and an inverted signal of the clock signal, and a non-inverted signal and an inverted signal of the clock signal during a synchronization non-established state. A clock switching unit that switches a signal to be output between the clock switching unit and a fixed sampling unit that samples the input signal every minimum time when the input signal changes using an output signal of the clock switching unit. The synchronization detection device according to claim 1. 4. The input signal is data having a frame structure conforming to an ATSC standard, and the synchronization signal is an ATSC signal.
2. The synchronization detection device according to claim 1, wherein the synchronization detection device is a segment synchronization signal conforming to the SC standard. 5. When the quality information indicating the quality of the input signal is supplied, and the quality of the input signal is better than a predetermined reference, the pattern matching unit receives the input signal instead of the output signal of the sampling unit. 2. The synchronization detection signal when a signal is supplied is output.
Synchronization detection device according to item 1. 6. The input signal is data having a frame structure conforming to the ATSC standard, and the synchronization signal is an ATSC signal.
The synchronization detection device according to claim 5, wherein the synchronization information is a segment synchronization signal conforming to the SC standard, and the quality information indicates whether or not a proximity ghost has occurred in the input signal. 7. A synchronization detection device for detecting the synchronization signal from an input signal including the synchronization signal, wherein the input signal has the same signal pattern as the synchronization signal,
A pattern matching unit that checks whether or not the synchronization signal is included in the same cycle, and receives the matching result in the pattern matching unit, and the number of times that the pattern matching has succeeded successively in a synchronization non-established state.
A counting unit that counts the number of times pattern matching has failed consecutively in the synchronization established state, a rear protection stage number holding unit that holds the number of synchronization rear protection stages, a front protection stage number holding unit that holds the number of synchronization front protection stages, A synchronization determination unit that determines whether or not a synchronization is established based on the count value of the counting unit, the number of rear protection stages, and the number of front protection stages. A synchronization detection signal generation unit that generates a synchronization detection signal, and receives supply of quality information indicating a quality of a result of processing the input signal using the synchronization detection signal, and shifts the synchronization detection signal based on the quality information. And a synchronization detection signal shift unit that shifts the synchronization detection signal in the time direction according to the shift amount obtained by the shift amount control unit. With a synchronization detection device. 8. The method according to claim 7, wherein the shift amount controller changes a shift amount of the synchronization detection signal when a quality of a result of processing the input signal is lower than a predetermined standard. Synchronous detection device according to 1. 9. The shift amount control unit according to claim 7, wherein the shift amount of the synchronization detection signal is determined so that the quality of a result of processing the input signal is optimized.
Synchronous detection device according to 1. 10. The input signal is data having a frame structure conforming to the ATSC standard, and the synchronization signal is
The synchronization detection device according to claim 9, wherein the synchronization detection device is a segment synchronization signal conforming to the TSC standard. 11. The synchronization detection device according to claim 10, wherein the quality information is error rate information for a signal obtained by waveform-equalizing the input signal using the synchronization detection signal. 12. A synchronization detecting device for detecting a synchronization signal from an input signal including a synchronization signal, wherein the input signal has the same signal pattern as the synchronization signal,
A pattern matching unit that checks whether or not the synchronization signal is included in the same cycle, a counting unit that receives the matching result in the pattern matching unit, and counts the number of times that pattern matching has succeeded continuously in a synchronization non-established state; A backward protection stage number holding unit for holding the number of synchronization backward protection stages, a long period synchronization detection unit for detecting a long period synchronization signal included in the input signal with a period longer than the synchronization signal, and a count value of the counting unit When is equal to or more than the number of backward protection stages, when it is determined to transition to the synchronization established state, when the synchronization detection failed in the long-period synchronization detection unit,
A synchronization detection device, comprising: a synchronization determination unit that determines to transition to a synchronization non-establishment state; and a synchronization detection signal generation unit that generates a synchronization detection signal at the timing of pattern matching in the pattern matching unit in the synchronization establishment state. 13. The input signal is data having a frame structure conforming to the ATSC standard, and the synchronization signal is
13. The synchronization detection device according to claim 12, wherein the synchronization detection device is a segment synchronization signal conforming to the TSC standard, and the long-period synchronization signal is a field synchronization signal conforming to the ATSC standard.