JP2002329843A - Ferroelectric transistor type nonvolatile memory element and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a high-quality storage element having good storage retention characteristics while avoiding process damage to a ferroelectric substance. SOLUTION: A ferroelectric for turning on and off a field effect transistor utilizing remanent polarization of a ferroelectric substance 11 electrically connected to a gate electrode 6 of a field effect transistor formed on a semiconductor substrate 1. In the body transistor type nonvolatile memory element, one or more metal wirings 8 connected to the source region 3 and the drain region 4 of the field-effect transistor are formed via an insulating layer, and then, via the insulating layer. A capacitor having a structure in which the ferroelectric substance 11 is sandwiched between electrodes is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric transistor type nonvolatile memory element and a method of manufacturing the same,
The present invention relates to a nonvolatile memory using a ferroelectric substance.

[0002]

2. Description of the Related Art Recently developed FeRAM
(Ferroelectric Random Access Memory) is mostly DR
The AM capacitor is replaced with a ferroelectric capacitor (Japanese Patent Application Laid-Open No. 2-113496), and the operation detects a difference in charge amount between when the polarization of the ferroelectric capacitor is inverted and when it is not inverted. It is done by doing. For this reason, destructive reading is performed in which information held when information is read is destroyed. Also, in order to compare the amount of electric charge discharged from the ferroelectric capacitor, it is necessary to arrange a pair of reference cells in each cell. Therefore, two transistors and two capacitors are required to constitute one memory cell. Becomes Therefore, there is a problem that the memory cell area is twice or more as large as that of a DRAM having the same processing accuracy.

On the other hand, a ferroelectric transistor in which a ferroelectric substance is disposed at a gate portion of a field effect transistor (FET) has a cell area because a single transistor can constitute a memory cell. Not only can be reduced, but also because the FET is kept on and off by the polarization of the ferroelectric, non-destructive reading is possible in which information is not destroyed by the reading operation.

[0004]

What is common to these FeRAMs and ferroelectric transistors is that the ferroelectric is LS
There is a problem in that the original ferroelectric characteristics cannot be maintained until the final step due to process damage in the manufacturing process of I. For this reason, in the conventional technology, annealing is frequently performed even after the ferroelectric material is formed to take measures such as recovering the function of the ferroelectric material and selecting a ferroelectric material or an electrode material that is not easily damaged by the process. Have been. However, these countermeasures have not achieved sufficient results, and therefore, have a great problem that it is difficult to guarantee the reliability of the device.

As described above, the FeRAM and the ferroelectric transistor have a problem that the ferroelectric undergoes process damage in an LSI manufacturing process, and it is difficult to maintain ferroelectric characteristics.

SUMMARY OF THE INVENTION The present invention has been made to solve such an unresolved problem of the conventional technology, and has been proposed to reduce the process damage to the ferroelectric material in the LSI manufacturing process, thereby improving the reliability. An object of the present invention is to provide a ferroelectric transistor-type nonvolatile memory element having high memory retention characteristics and an excellent method of manufacturing the same.

[0007]

SUMMARY OF THE INVENTION A ferroelectric transistor type nonvolatile memory element according to the present invention provides a remanent polarization of a ferroelectric which is electrically connected to a gate electrode of a field effect transistor formed on a semiconductor substrate. In the ferroelectric transistor-type nonvolatile memory element for turning on and off the field-effect transistor, one or more layers connected to a source region and a drain region of the field-effect transistor After the metal wiring is formed via the insulating layer, a capacitor having a structure in which the ferroelectric substance is sandwiched between the electrodes using the insulating layer is provided.

Further, the nonvolatile memory element of the ferroelectric transistor type according to the present invention utilizes the remanent polarization of a ferroelectric which is electrically connected to a gate electrode of a field effect transistor formed on a semiconductor substrate. In a ferroelectric transistor-type nonvolatile memory element that performs on / off operation of an effect transistor, a capacitor having a structure in which the ferroelectric is sandwiched between electrodes is connected to the gate electrode,
It is characterized by being provided on two or more contact plugs.

The operation of the present invention will be described with reference to FIG. The field-effect transistor formed on the semiconductor substrate 1 has, for example, a laminated structure in which a gate electrode 6 made of a conductor is formed on a gate insulating film 5. Control the current flowing through the switch to turn on and off. In the present invention, a ferroelectric capacitor (capacitance) is connected to the gate electrode 6, and a non-volatile memory is formed by utilizing the residual polarization of the ferroelectric. The ferroelectric capacitor has a lower electrode 1
0, a ferroelectric material 11, and an upper electrode 12, and are connected to the gate electrode 6 by a plug 7 and a wiring 8 layer for connecting between wirings or between a wiring and a substrate. The wiring 8, the plug 7, and the like are separated by an interlayer insulating film 9. 13 is a metal wiring layer,
2 is a field oxide film.

A ferroelectric is a kind of dielectric (insulator), and internal polarization is generated by an electric field applied from the outside, but the internal polarization remains even when the external electric field is removed. This is called remanent polarization, and the remnant polarization can be used to function as a so-called non-volatile memory that can maintain the on / off state of the field effect transistor even when an external electric field is removed.

By employing the structure of the present invention, the ferroelectric capacitor can be formed after the wiring structure is formed, so that the process damage of the ferroelectric can be further suppressed. Conventionally, in a memory device using a ferroelectric capacitor, after forming the ferroelectric capacitor, forming an interlayer insulating film, forming wiring and plugs, and processing, the ferroelectric material is damaged, and the ferroelectric material originally has The remaining remanent polarization is reduced to about one third, the fatigue resistance is deteriorated, and the memory retention characteristics are deteriorated.

On the other hand, in a memory device using a conventional ferroelectric capacitor, since a ferroelectric capacitor is formed without a wiring step after forming a field-effect transistor, heat treatment at a relatively high temperature is possible. However, in the case of the structure of the present invention, it is required to perform a heat treatment at a relatively low temperature so that the wiring is not damaged.

In the present invention, the gate insulating film 5 is made of silicon.
In addition to oxide-based oxide films, a large dielectric constant
Silicon nitride that can apply higher voltage
Use an insulating thin film mainly composed of
Can be. Further, the lower electrode 10 of the ferroelectric capacitor
And the upper electrode 12 is preferably platinum or iridium.
Or iridium oxide, or a mixture thereof, or
These laminated structures are used. Also, the ferroelectric thin film 11
ABO_ThreeType, A_TwoB_TwoO₇Ferroelectric with mold structure
Body or ferroelectric with a layered perovskite structure
Can be used. Here, A and B represent metal elements.
You. The metal elements corresponding to A and B are, for example, `` S
r, Bi "," Nb, Ta ". Layered perovskite
The perovskite lattice has a layered structure such as Bi-O
It is sandwiched between structures, specifically SrBi
_TwoTa_TwoO₉And those with Nb added to it
You. In particular, Sr_TwoTa_TwoO₇Or Sr_Two(NbTa)
_TwoO₇Or SrBi_TwoTa_TwoO ₉Relatively inviting like
It is more preferable to use a ferroelectric material having a low electric conductivity.
The reason is that the structure of the gate part is a ferroelectric thin film
11 and a capacitor in which the gate insulating film 5 is connected in series
When a voltage is applied, the voltage is applied to each thin film.
Pressure is applied in inverse proportion to volume. Therefore, the ratio of ferroelectric
The smaller the dielectric constant and the smaller the capacitance, the higher the applied voltage
And can sufficiently saturate the polarization,
This is advantageous.

This will be described more specifically.
The gate insulating film 6 of the field effect transistor has
Although it depends on design rules, it generally has a relative dielectric constant of about 5 and a film thickness of 10 nm or less. On the other hand, since the ferroelectric thin film has a thickness of at least about 100 nm, the relative dielectric constant is 50
It is desirable that it be less than about. The reason is that at least about half of the voltage applied to the gate electrode 8 needs to be applied to the ferroelectric, and for this, the capacitance of the ferroelectric capacitor is equal to the capacitance of the gate insulating film. This is because it is desirable to be equal or less.

Furthermore, by making the area of the ferroelectric capacitor smaller than the gate area, the effective capacity of the ferroelectric capacitor can be reduced, and more voltage can be applied to the ferroelectric capacitor. Become.

If the amount of remanent polarization of the ferroelectric is too large, the potential on the upper surface of the gate insulating film 5 fluctuates greatly, and the memory retention characteristics tend to be unstable. this is,
Even if the semiconductor portion under the gate insulating film 5 is large,
This is due to the inability to generate about cm2 of charge. Therefore, it is preferable that the ferroelectric film 11 has a residual polarization of 10 μC / cm 2 or less.

The above-mentioned ferroelectric thin film can be formed by an RF sputtering method using a ceramic target, a spin-on method in which a chemical solution composed of a metal organic substance is applied onto a wafer and then sintered, or a raw material composed of a metal organic substance is vaporized into a wafer. It can be obtained by using a chemical vapor deposition method or the like in which a film is transferred to form a film. In particular, since the chemical vapor deposition method has excellent step coverage, it is advantageous when the surface of the base insulating film has irregularities. When the surface of the base insulating film is flattened by a chemical mechanical polishing method (CMP method), the RF sputtering method and the spin-on method are also useful.

As described above, according to the present invention, it is possible to achieve a problem that is difficult to achieve with a conventional ferroelectric memory element by using an easy structure and driving method.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 A ferroelectric transistor (sample A) according to the present example as shown in FIG. 2 and a ferroelectric transistor (sample B) as shown in FIG. 3 as a comparative example were prototyped. . Both ferroelectric transistors
Using a p-type silicon (100) single crystal substrate 14, a field oxide film 15 was formed by a thermal oxidation method, and an active region where a transistor was to be formed was opened by photolithography and etching. Next, a gate insulating film 18 is formed to a thickness of 12 nm by a thermal oxidation method, a polycrystalline silicon film is formed as a gate electrode 19, and etching is performed. Then, phosphorus is ion-implanted by ion implantation using the gate portion as a mask. Implantation and activation annealing were performed to form a source 16 and a drain 17.

In the case of sample A, tungsten plug 2
0, the aluminum wiring layer 21 is formed in two stages. On this occasion,
The connection to the upper part of the gate electrode 19 is independently pulled up to the chip surface via a plug. Next, as the lower electrode 23, a Ti / Pt laminated film was formed by a sputtering method, and as the ferroelectric thin film 24, a SrBi ₂ Ta ₂ O ₉ film was formed by applying a metal organic material and baking it. The sintering temperature was about 430 ° C., and sintering was performed in a reduced pressure oxygen atmosphere by infrared heating. As the upper electrode 25, a Pt film was formed by a sputtering method. This was dry-etched in the order of the upper electrode 25, the ferroelectric film 24, and the lower electrode 23 to produce a capacitor structure. Here, damage recovery annealing is performed at about 400 ° C. in an oxygen atmosphere, and a silicon oxide film is formed as an interlayer insulating film by CVD (Chemical Vapor Dep.
osition) method. Then, a contact hole is opened by a dry etching method, and an aluminum wiring 26 connected to the upper electrode 25 of the ferroelectric capacitor is formed.

In the case of sample B, a contact hole is opened in the interlayer insulating film, and only a tungsten plug 20 connected to the upper part of the gate electrode 19 is formed. Next, sample A
A ferroelectric capacitor is formed in the same manner as described above. About 40 here
Perform damage recovery annealing in an oxygen atmosphere at 0 ° C.
A silicon oxide film was formed as an interlayer insulating film by a CVD method. Next, the tungsten plug 20 and the aluminum wiring 21 are formed in two steps to complete the process.

In both samples A and B, the ferroelectric film thickness was 2
00 nm, and the area of the ferroelectric capacitor was set to be 1/5 of the area of the gate electrode.

Next, the memory retention characteristics are evaluated. With respect to the samples A and B, a voltage is applied between the upper electrode 26 and the silicon single crystal substrate 14 to generate polarization of the ferroelectric and write information. Thereafter, the source portion was grounded, a voltage of 1 V was applied to the drain portion, a write voltage was applied, and a current value flowing through the drain after holding for a certain time was observed. The result is shown in FIG. As is clear from the result, it is understood that the storage time of the sample A is longer than that of the sample B. This can be considered to be a difference caused by whether or not the ferroelectric film 24 has undergone process damage.

Example 2 A ferroelectric transistor as shown in FIG. 5 was prototyped. The ferroelectric transistor has p
A field oxide film 15 was formed by thermal oxidation using a type silicon (100) single crystal substrate 14, and an active region where a transistor was to be formed was opened by photolithography and etching. Next, a gate insulating film 27 is formed to a thickness of 12 nm by nitrogen ion implantation and thermal oxidation.
It was a membrane. After forming and etching a mixed crystal film of polycrystalline silicon and tungsten as the gate electrode 19, phosphorus is ion-implanted by ion implantation using the gate portion as a mask, and activation annealing is performed to form the source 16 and the drain 17. did.

Next, a two-stage tungsten plug 20 and an aluminum wiring layer 21 are formed. At this time, the gate electrode 1
The connection to the upper part 9 is independently pulled up to the chip surface via a plug. Next, as the lower electrode 23,
A Ti and Pt laminated film was formed by a sputtering method, and a Sr ₂ (NbTa) ₂ O ₇ film as a ferroelectric thin film 28 was formed by a method of applying a metal organic material and baking it. The sintering temperature was about 450 ° C., and sintering was performed in a reduced pressure oxygen atmosphere by infrared heating. As the upper electrode 25, a Pt film was formed by a sputtering method. This was dry-etched in the order of the upper electrode 25, the ferroelectric film 28, and the lower electrode 23 to produce a capacitor structure. Here, damage recovery annealing is performed in an oxygen atmosphere at about 400 ° C., and a silicon oxide film is formed as an interlayer insulating film by CVD (Chemical Vapor Deposition).
The film was formed by the method. A contact hole is opened in this by a dry etching method, and the upper electrode 2 of the ferroelectric capacitor is formed.
5 is completed by forming an aluminum wiring to be connected.

Next, the memory retention characteristics were evaluated, and the same result as that of Sample A in Example 1 was obtained.

[0028]

According to the present invention, it is possible to provide a high-quality ferroelectric transistor-type nonvolatile memory having good storage retention characteristics while avoiding process damage to the ferroelectric material.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of an element structure according to the present invention.

FIG. 2 is a diagram showing a structure of a sample A in Example 1.

FIG. 3 is a diagram showing a structure of a sample B in Example 1.

FIG. 4 is a diagram showing a measurement result of a memory retention characteristic of a prototype sample in Example 1.

FIG. 5 is a diagram illustrating a structure of a sample according to a second embodiment.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 field insulating film 3 source region 4 drain region 5 gate insulating film 6 gate electrode 7 plug 8 metal wiring layer 9 interlayer insulating film 10 lower electrode 11 ferroelectric film 12 upper electrode 13 metal wiring layer 14 p-type single crystal Silicon substrate 15 Field oxide film 16 Source region 17 Drain region 18 Gate insulating film (SiO ₂ ) 19 Polycrystalline silicon gate electrode 20 Tungsten plug 21 Aluminum wiring layer 22 Silicon oxide interlayer insulating layer 23 Pt / Ti lower electrode 24 SrBi ₂ Ta ₂ O ₉ ferroelectric film 25 Pt upper electrode 26 Aluminum wiring layer 27 SiON gate insulating film 28 Sr ₂ (NbTa) ₂ O ₇ ferroelectric film

Claims (11)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the steps of: turning on a field effect transistor using a remanent polarization of a ferroelectric electrically connected to a gate electrode of the field effect transistor formed on a semiconductor substrate;
In a ferroelectric transistor-type nonvolatile memory element that performs an off operation, after forming one or more layers of metal wiring connected to a source region and a drain region of the field-effect transistor via an insulating layer, A ferroelectric transistor-type nonvolatile memory element, comprising: a capacitor having a structure in which the ferroelectric is sandwiched between electrodes using a layer. 2. The method according to claim 1, further comprising using a remanent polarization of a ferroelectric substance electrically connected to a gate electrode of the field effect transistor formed on the semiconductor substrate to turn on and off the field effect transistor.
In the ferroelectric transistor-type nonvolatile memory element to be turned off, a capacitor having a structure in which the ferroelectric is sandwiched between electrodes is provided on two or more contact plugs connected to the gate electrode. A non-volatile memory element of the ferroelectric transistor type. 3. The ferroelectric transistor according to claim 1 or 2, wherein a material having a relative dielectric constant of 50 or less is used as a ferroelectric material of the nonvolatile memory element of the ferroelectric transistor type. Nonvolatile memory element. 4. The ferroelectric material of the ferroelectric transistor type nonvolatile memory element according to claim 1 or 2, wherein the ferroelectric material has a remanent polarization of 10 μC / cm ² or less. Body transistor type nonvolatile memory element. 5. A ferroelectric material having an ABO ₃ type structure (A and B are metal elements) as a ferroelectric material of the ferroelectric transistor type nonvolatile memory element according to claim 1 or 2. A ferroelectric transistor-type nonvolatile memory element using a ferroelectric material having a ₂ B ₂ O ₇ (A and B are metal elements) type structure or a layered perovskite type material. 6. The method for driving a ferroelectric transistor type nonvolatile memory element according to claim 1, wherein
Sr ₂ Nb ₂ O ₇ , as a ferroelectric substance of the ferroelectric element,
Alternatively, Sr ₂ Ta ₂ O ₇ or Sr ₂ (NbTa) ₂
A method for driving a ferroelectric transistor-type nonvolatile memory element, characterized by using a material mainly composed of O ₇ or SrBi ₂ Ta ₂ O ₉ . 7. A ferroelectric transistor type nonvolatile memory according to claim 1, wherein an organic ferroelectric material is used as a ferroelectric material of the ferroelectric transistor type nonvolatile memory element. element. 8. The ferroelectric transistor type nonvolatile memory element according to claim 1, wherein a material mainly composed of a silicon single crystal is used as a semiconductor substrate. Memory element. 9. The ferroelectric transistor type nonvolatile memory element according to claim 1, wherein platinum, iridium or titanium is used as an electrode of the capacitor.
Alternatively, a ferroelectric transistor-type nonvolatile memory element using a structure in which these oxides are mixed or stacked. 10. A method for manufacturing a ferroelectric transistor type nonvolatile memory element according to claim 1, wherein the ferroelectric is formed using a chemical vapor deposition method. Of manufacturing a ferroelectric transistor type nonvolatile memory element. 11. The method for manufacturing a nonvolatile memory element according to claim 1, wherein the base insulating film of the capacitor is planarized by a chemical mechanical polishing method. A method for manufacturing a ferroelectric transistor-type nonvolatile memory element.