JP2002313722A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen the frequency of heat processing a high temperatures (over 600 deg.C) and realize lower temperature processing (600 deg.C or less), process simplification and throughput improvement. SOLUTION: The method comprises forming impurity regions 108 containing a rare gas element (called rare gas) and one or a plurality of kinds of additives selected from H, H2 , O, O2 , P in a semiconductor film having a crystal structure, using a mask 106b, heat treating to getter a metal element contained in the semiconductor film to segregate it in the impurity regions 108 and patterning with use of the mask to form a semiconductor layer 109 of the semiconductor film having a crystal structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device using a gettering technique and a semiconductor device obtained by the method. In particular, the present invention relates to a method for manufacturing a semiconductor device using a crystalline semiconductor film which is manufactured by adding a metal element having a catalytic action in crystallization of a semiconductor film, and a semiconductor device.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art A thin film transistor (hereinafter, referred to as TFT) is known as a typical semiconductor element using a semiconductor film having a crystalline structure (hereinafter, referred to as a crystalline semiconductor film). TFTs are attracting attention as a technique for forming an integrated circuit on an insulating substrate such as glass, and a drive circuit integrated liquid crystal display device and the like are being put into practical use. In conventional technology,
The crystalline semiconductor film is manufactured by heating or laser annealing an amorphous semiconductor film deposited by a plasma CVD method or a low pressure CVD method (a technique of crystallizing a semiconductor film by irradiation with laser light).

[0004] The crystalline semiconductor film thus produced is an aggregate of a large number of crystal grains, and the crystal orientation is uncontrollable because it is oriented in an arbitrary direction, which is a factor limiting TFT characteristics. . To solve such problems, Japanese Patent Application Laid-Open
The technology disclosed in Japanese Patent Application Laid-Open No. 183540 discloses a method of manufacturing a crystalline semiconductor film by adding a metal element such as nickel which has a catalytic effect on crystallization of a semiconductor film. In addition to the effect of lowering the crystal orientation, the orientation of the crystal orientation can be increased in a single direction.
When a TFT is formed using such a crystalline semiconductor film, not only the field effect mobility is improved, but also the subthreshold coefficient (S value) is reduced, and the electrical characteristics can be dramatically improved. .

However, since a metal element having a catalytic action is added, there is a problem that the metal element remains in the film of the crystalline semiconductor film or on the film surface, and the characteristics of the obtained element are varied. . As an example, there is a problem that the off-state current increases in the TFT, and the TFT varies among individual elements. That is, once the crystalline semiconductor film is formed, the metal element having a catalytic action on crystallization becomes unnecessary.

Gettering using phosphorus has been effectively utilized as a technique for removing such a metal element from a specific region of a crystalline semiconductor film. For example, TFT
Is added to the source / drain region of
By performing the heat treatment at 0 ° C., the metal element can be easily removed from the channel formation region.

[0007] Phosphorus is obtained by an ion doping method (a method in which PH ₃ or the like is dissociated by plasma and ions are accelerated by an electric field and injected into a semiconductor, and basically means a method in which mass separation of ions is not performed). The phosphorus is injected into the crystalline semiconductor film, and the phosphorus concentration required for gettering is 1 × 10 ²⁰ / cm ³ or more. Although the addition of phosphorus by the ion doping method causes the crystalline semiconductor film to become amorphous, an increase in the phosphorus concentration hinders recrystallization by subsequent annealing, which is a problem. In addition, the addition of a high concentration of phosphorus causes an increase in the processing time required for doping, which causes a problem in that the throughput in the doping process is reduced.

[0008]

SUMMARY OF THE INVENTION The present invention is directed to high temperature (60
It is an object to reduce the number of heat treatments (0 ° C. or more) to realize a further low-temperature process (600 ° C. or less), and to realize a simplified process and an improvement in throughput.

[0009]

The gettering technique is positioned as a major technique in the technique of manufacturing an integrated circuit using a single crystal silicon wafer. Gettering is known as a technique in which metal impurities taken into a semiconductor are segregated at a gettering site with some energy to reduce the impurity concentration in an active region of an element.
It is Extrinsic G gettering
ettering) and intrinsic gettering (Intrinsic
Gettering). The extrinsic gettering is to provide a gettering effect by applying a strain field or a chemical action from the outside. This is the case with a phosphorus getter that diffuses high-concentration phosphorus from the back surface of a single-crystal silicon wafer, and the above-described gettering using phosphorus on a crystalline semiconductor film can also be regarded as a kind of extrinsic gettering.

[0010] On the other hand, intrinsic gettering is known to utilize a strain field of a lattice defect involving oxygen generated inside a single crystal silicon wafer.
The present invention focuses on intrinsic gettering utilizing such lattice defects or lattice distortion, and employs the following means in order to apply it to a crystalline semiconductor film having a thickness of about 10 to 100 nm. It is.

The present invention provides a means for forming a semiconductor film having a crystal structure using a metal element, a means for selectively adding a rare gas element to form a gettering site, and a method for forming a gettering site by adding a metal element to a gettering site. Means for gettering.

As a method for adding a rare gas element, an ion doping method or an ion implantation method may be used.

Further, in addition to the rare gas elements, H, H ₂ , O,
One or more selected from O ₂ and P may be added. When one or more selected from H, H ₂ , O, and O ₂ are added in addition to the rare gas element, the addition may be performed in an atmosphere containing water vapor in addition to the rare gas element, for example. FIG. 24 shows the results of measurement using an electromagnetic field orthogonal mass analyzer (E × (cross) B mass analyzer) when water vapor was added to the atmosphere and a rare gas element (argon) was added using the ion doping method. . The electromagnetic field orthogonal mass analyzer is a mass analyzer in which a magnetic field and an electric field are perpendicular to each other, and each is arranged to be perpendicular to an ion beam axis. The beam is deflected by an electric field, and mass spectrometry is performed such that ions to be detected return to the center axis by a magnetic field.

In addition to the rare gas elements, H, H ₂ , O,
When adding one or more selected from O ₂ and P, for example, the addition may be performed in an atmosphere containing water vapor and phosphine in addition to the rare gas element. As described above, a gettering effect can be obtained synergistically by adding a plurality of elements.

In particular, it is effective to add oxygen (O, O ₂ ), and in the gettering step, the metal element that promotes crystallization tends to move to the gettering site where the oxygen concentration is high. .

In the present invention, the semiconductor film having a crystal structure may be obtained by adding a metal element to a semiconductor film having an amorphous structure and then performing crystallization by heat treatment or irradiation with strong light. After crystallization, an etchant containing hydrofluoric acid, for example, dilute hydrofluoric acid or FPM (hydrofluoric acid, hydrogen peroxide,
(Mixture with pure water) to remove or reduce the segregated metal element. When the surface is etched with an etchant containing hydrofluoric acid, it is desirable to irradiate strong light to flatten the surface.

After the above-mentioned crystallization, irradiation with laser light or strong light may be performed to further improve the crystallization. After the irradiation of laser light or strong light for improving the crystallization, the metal element segregated by an etchant containing hydrofluoric acid may be removed or reduced, and the surface may be flattened by further irradiation with strong light. .

Next, an insulating film containing silicon as a main component is formed on the semiconductor film having a crystal structure. Note that the insulating film may be extremely thin, and may be formed by oxidizing with carbon, that is, a solution containing ozone used for surface treatment called hydrocleaning for removing organic substances. This insulating film is for doping a trace amount of an impurity element (boron or phosphorus) in order to control the threshold value of the TFT. This insulating film may be formed and irradiated with intense light for activation after channel doping.

One of the features of the present invention is a process of forming a gettering site by adding a rare gas element to a crystalline semiconductor thin film, and a process of performing heat treatment (including heat treatment by irradiation with strong light). And the metal contained in the crystalline semiconductor thin film is moved by the heat treatment to obtain a gettering site (a region to which ions of a rare gas element are added).
And removing or reducing metal from the crystalline semiconductor thin film other than the gettering sites. Note that strong light may be applied instead of the heat treatment, or strong light may be applied simultaneously with the heat treatment. At the time of this gettering, the impurity element added by channel doping may be activated.

Further, according to the present invention, an impurity region in which a rare gas element (also referred to as a rare gas) is added to a semiconductor film having a crystal structure by using a mask is formed, and a metal contained in the semiconductor film is formed in the impurity region by heat treatment. After gettering for segregating elements, the semiconductor film is patterned using the mask. In order to reduce the number of masks or simplify the process, it is preferable to use the same mask for selectively adding a rare gas element and the mask used for patterning a semiconductor film. Are likely to be segregated at the boundary of the region to which the rare gas is added. Therefore, separate masks may be used as shown in FIG.

As a method for adding the rare gas element, an ion doping method or an ion implantation method can be used.
As the rare gas element, one or more kinds selected from He, Ne, Ar, Kr, and Xe can be used. Above all, it is desirable to use Ar which is an inexpensive gas. In the case of using the ion doping method, the concentration occupied by one of the rare gas elements contained in the doping gas is 30% or more, preferably 100%. For example, Kr gas 30%, A
A doping gas having a concentration of r gas of 70% may be used.

Further, according to the present invention, when patterning a semiconductor film, a region to which a rare gas is added, that is, a region where a metal element is segregated at a high concentration is removed, covered with a mask, and a metal element is reduced. The formed region is formed as a semiconductor layer having a desired shape. Note that if overetching is performed at the time of forming the semiconductor layer, a portion where the metal existing at the edge of the semiconductor layer is segregated can be removed. After the patterning, the mask is removed.

Next, after cleaning the surface of the semiconductor layer with an etchant containing hydrofluoric acid, an insulating film containing silicon as a main component and serving as a gate insulating film is formed. It is desirable that the surface cleaning and the formation of the gate insulating film be performed continuously without exposure to the air. Before or after this surface cleaning, an activation step may be added to activate the added impurity element by channel doping.

Next, after cleaning the surface of the gate insulating film,
A gate electrode is formed, and a source region and a drain region are formed by appropriately adding an impurity element imparting p-type or n-type. If necessary, an LDD region may be formed. After the addition, heat treatment, strong light irradiation, or laser light irradiation may be performed to activate the impurity elements. In addition, plasma damage to the gate insulating film and plasma damage to the interface between the gate insulating film and the semiconductor layer can be recovered simultaneously with the activation. In particular, room temperature to 300
It is very effective to activate the impurity element by irradiating the second harmonic of the YAG laser from the front surface or the back surface in an atmosphere of ° C. YAG lasers are preferred because they require less maintenance.

In the subsequent steps, an interlayer insulating film is formed, hydrogenation is performed, contact holes reaching the source region and the drain region are formed, and a source electrode and a drain electrode are formed to complete a TFT.

According to the present invention, when crystallization is performed using heat treatment and activation is performed by a method other than heat treatment, it is possible to suppress the high-temperature heat treatment to twice (crystallization and gettering).
When crystallization is performed by intense light and activation is performed by a method other than the heat treatment, it can be suppressed to one high-temperature heat treatment (gettering).

In addition, the treatment time for adding a rare gas is as short as about 1 minute or 2 minutes, so that a high concentration rare gas element can be added to a semiconductor film. And the throughput is significantly improved.

An experiment was conducted on the ability of gettering by a rare gas element. After applying a 10 ppm nickel acetate-containing aqueous solution to a 50 nm amorphous silicon film,
A crystalline semiconductor film crystallized by a dehydrogenation treatment at 500 ° C. for 1 hour and a heat treatment at 550 ° C. for 4 hours was used. After patterning this crystallized semiconductor film, 90n
m silicon oxide film was formed. The region to be gettered is set to a width of 50 μm, and argon is implanted by a mask so as to sandwich the region by an ion doping method (acceleration voltage of 80 keV and dose of 5 × 10 ¹⁵ / cm ² ). A sample provided with a ring site (5 μm width) was prepared. Argon used was 99.9999% or more, and the time required for the injection was preferably 1 to 2 minutes. Then, in a nitrogen atmosphere, the heating temperature is set to 350 ° C., 400 ° C., 450 ° C., 500 ° C., 5 ° C.
The gettering was performed at 50 ° C. for 4 hours, 6 hours, and 8 hours. After gettering, the silicon oxide film was removed, and then the substrate was treated with FPM. The gettering effect was confirmed by the number of etch pits in the gettering region of the crystalline semiconductor film. That is, it is known that most of the added nickel remains in the crystalline semiconductor film as nickel silicide, but this is etched by FPM (a mixed solution of hydrofluoric acid, hydrogen peroxide, and pure water). Therefore, the effect of gettering can be confirmed by processing the gettered region with FPM and confirming the presence or absence of an etch pit. In this case, the smaller the number (density) of the etch pits, the higher the gettering effect. FIG. 26 shows the result. FIG.
From FIG. 6, it can be seen that the longer the heating time, the lower the density of the etch pits, and that the heat treatment at 500 ° C., preferably 550 ° C., has sufficiently reduced the density of the etch pits.

The width of the region to be gettered is set to 30.
FIG. 27 shows the result of a similar experiment performed with μm. 27 and 26, if the region to be gettered is 30 μm, the density of the etch pits is sufficiently reduced even at 500 ° C.

FIG. 29 is a simplified diagram of a sample in which etch pits are formed. Note that in FIG. 29, a rare gas element added region 10401 indicates a region to which argon is added. Gettered area (area to be gettered)
The number of the etch pits 10403 existing in the 10402 was counted while observing with an optical microscope to obtain an etch pit density.

Further experiments were conducted to compare with the gettering ability of phosphorus. By changing the doping conditions and the heating conditions, the etch pit density was obtained in the same manner as in the above experiment. Here, phosphorus is ion-doped at a gettering site (width 5 μm) (5% PH ₃ diluted with hydrogen, acceleration voltage 80 keV, dose 1.3 × 10 ¹⁵ / cm ² ).
Ion-doped sample (80 keV)
In the accelerating ^{voltage, 1 × 10 1 5, 5} × 10 15 / cm 2, 5 × 10
Each sample was injected at a dose of ¹⁵ / cm ² ), and these were compared and evaluated. At this time, the time required for phosphorus injection is about 8 minutes. And heating temperature 500
Gettering was performed at 24 ° C. for 24 hours. In addition, a sample in which the width of each gettered region is 30 μm,
The comparison was made with a sample of 50 μm. FIG. 28 shows the result. FIG. 28 shows that argon has a higher gettering ability even though the dose is smaller than that of phosphorus. Further, even if the addition amount of argon is small, that is, even if the dose amount is 5 × 10 ¹⁵ / cm ² , if the heating time is long, gettering is sufficiently performed, and the density of etch pits can be reduced.

Thus, gettering using phosphorus and
In comparison, the getterin of the present invention by adding a rare gas element
High performance, and higher concentration, for example, 1 × 10²⁰~ 5x
10 ^{twenty one}/cm^ThreeMetal source used for crystallization
The amount of element added can be increased. That is, for crystallization
Crystallization by increasing the amount of metal element
Processing time can be further reduced. Ma
If the crystallization processing time is not changed,
By adding more metal elements
It can be crystallized at very low temperatures. Also used for crystallization
By increasing the amount of metal element added,
Generation can be reduced and a good crystalline semiconductor film can be formed.
Can be achieved.

In the gettering of the present invention, not only the gettering of the metal element used for crystallization but also the gettering of another heavy metal element is performed.

The semiconductor film having a crystalline structure is also annealed by the gettering of the present invention.

Further, since the high-temperature heat treatment is performed before the island is formed, no shrinkage of the substrate occurs in the process after the island is formed, and the patterning deviation can be minimized. The yield is improved. In addition, the present invention, in which the number of heat treatments is small, can be used without any problem even if the thickness of the substrate is small (for example, 0.7 mm or 0.5 mm) because the influence on the substrate is small.

The structure of the invention relating to the manufacturing process disclosed in this specification includes a first step of adding a metal element to a semiconductor film having an amorphous structure, and a semiconductor film having a crystal structure by crystallizing the semiconductor film. A second step of forming an impurity region by selectively adding a rare gas element to the semiconductor film having the crystal structure, and a crystallizing process by gettering the metal element in the impurity region. A fourth method for selectively removing or reducing the metal element in the semiconductor film having a structure;
And a fifth step of removing the impurity region.

In the above structure, the rare gas element is H
e, Ne, Ar, Kr, and Xe.

In the above structure, in addition to the rare gas element in the third step, H, H ₂ , O, O ₂ ,
One or more selected from P and H ₂ O are added.

Further, in the above structure, the third step is performed in an atmosphere containing a rare gas element and water vapor.

In each of the above structures, after the fifth step, a step of irradiating the semiconductor film with intense light or laser light from the front side or the back side to activate the impurity element is provided. And

In each of the above structures, the second step is a heat treatment.

In each of the above structures, the second step is a step of irradiating the semiconductor film having the amorphous structure with strong light.

Further, in each of the above structures, the second step is a step of performing a heat treatment and irradiating the semiconductor film having the amorphous structure with strong light.

In each of the above structures, the fourth step is a heat treatment.

In each of the above structures, the fourth step is a step of irradiating the semiconductor film with strong light.

Further, in each of the above structures, the fourth step is a step of performing a heat treatment and irradiating the semiconductor film with strong light.

In each of the above structures, the strong light is
The light is emitted from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp.

In each of the above structures, the metal element is Fe, Ni, Co, Ru, Rh, Pd, Os, Ir,
It is characterized by one or more selected from Pt, Cu and Au.

Another aspect of the invention relating to a manufacturing method includes a first step of adding a metal element to a semiconductor film having an amorphous structure, and forming a semiconductor film having a crystal structure by crystallizing the semiconductor film. A second step of forming a first mask on the semiconductor film having the crystal structure;
A fourth step of selectively adding a rare gas element to the semiconductor film having a crystal structure to form an impurity region; and obtaining the impurity element in the semiconductor film having a crystal structure by gettering the metal element to the impurity region. A fifth step of selectively removing or reducing a metal element, a sixth step of forming a second mask over the semiconductor film having the crystal structure, and a seventh step of selectively removing the semiconductor film. A method for manufacturing a semiconductor device, comprising:

In the above structure, the seventh step is a step of removing the impurity region and a part of the semiconductor film having the crystal structure.

Further, in the above structure, the second mask is provided at a position inside the end of the first mask.

Another aspect of the invention relating to a manufacturing method includes a first step of forming a first mask on a semiconductor film having an amorphous structure, and selecting a metal element for the semiconductor film having an amorphous structure. And a third step of crystallizing the semiconductor film to form a semiconductor film having a crystalline structure.
A fourth step of selectively adding a rare gas element to the semiconductor film having the crystal structure to form an impurity region;
A fifth step of selectively removing or reducing the metal element in the semiconductor film having a crystal structure by gettering the metal element in the impurity region, and forming a second mask on the semiconductor film having the crystal structure. A method for manufacturing a semiconductor device, comprising: a sixth step of forming; and a seventh step of selectively removing the semiconductor film.

Another structure of the invention relating to a manufacturing method includes a first step of forming a first mask on a semiconductor film having an amorphous structure, and a step of selecting a metal element for the semiconductor film having an amorphous structure. And a third step of crystallizing the semiconductor film to form a semiconductor film having a crystalline structure.
A fourth step of forming a second mask on the semiconductor film having the crystal structure; and a fifth step of selectively adding a rare gas element to the semiconductor film having the crystal structure to form an impurity region. A sixth step of selectively removing or reducing the metal element in the semiconductor film having a crystal structure by gettering the metal element in the impurity region, and a third step of forming a third element on the semiconductor film having the crystal structure. 7th to form the mask of
A method for manufacturing a semiconductor device, including a step and an eighth step of selectively removing the semiconductor film.

According to another aspect of the present invention, there is provided a semiconductor device provided with a TFT including a semiconductor layer, an insulating film in contact with the semiconductor layer, and a gate electrode in contact with the insulating film on a substrate,
The semiconductor device is characterized in that the substrate has a region containing a rare gas element at least partially. In addition,
This substrate is an insulating substrate or a semiconductor substrate. Also,
This structure is obtained by adding the rare gas element to the substrate in the step of adding the rare gas element. At this time,
FIG. 14C is a simplified diagram showing a state immediately after the addition of the rare gas element. In addition to the rare gas elements, H, H ₂ , O,
Similarly, when one or more kinds selected from O ₂ , P, and H ₂ O are added, H, H ₂ , O,
One or more selected from O ₂ , P and H ₂ O are added. However, compared to the rare gas elements, these are more easily diffused by the subsequent heat treatment.

In the above structure, the mask for forming the region containing the rare gas element and the mask for forming the semiconductor layer are the same. Thus, a semiconductor device can be obtained without increasing the number of masks.

Another aspect of the present invention is a semiconductor device including a TFT including an insulating film in contact with a substrate and a semiconductor layer, wherein the insulating film contains a rare gas element at least partially. A semiconductor device having a region.

The above insulating film is a base insulating film provided as a blocking layer. FIG. 14B shows a state in which a rare gas is added to the base insulating film.

In the above structure, the substrate has a region containing a rare gas element at least partially. That is, in a region where the mask is not formed, the rare gas element is added to both the substrate and the base insulating film. Further, when one or more kinds selected from H, H ₂ , O, O ₂ , P, and H ₂ O are added in addition to the rare gas element, H, H ₂ , One or more selected from O, O ₂ , P and H ₂ O are added. However, compared to the rare gas elements, these are more easily diffused by the subsequent heat treatment.

Also, the mask for forming the region containing the rare gas element and the mask for forming the semiconductor layer are the same.

[0060]

Embodiments of the present invention will be described below.

FIGS. 1 and 2 are views for explaining one embodiment of the present invention. After a metal element having a catalytic action is added to the entire surface of the amorphous semiconductor film and crystallized, gettering is performed. How to do it.

In FIG. 1A, a substrate 101 can be made of barium borosilicate glass, aluminoborosilicate glass, quartz, or the like. On the surface of the substrate 101, an inorganic insulating film is
It is formed with a thickness of 00 nm. An example of a suitable blocking layer is a silicon oxynitride film formed by a plasma CVD method, in which a first silicon oxynitride film formed from SiH ₄ , NH ₃ , and N ₂ O is formed to a thickness of 50 nm, The second silicon oxynitride film formed from SiH ₄ and N ₂ O with a thickness of 100 nm is applied. Blocking layer 10
Reference numeral 2 is provided to prevent the alkali metal contained in the glass substrate from diffusing into the semiconductor film formed thereover, and may be omitted when quartz is used as the substrate.

The semiconductor film 103 having an amorphous structure formed on the blocking layer 102 uses a semiconductor material containing silicon as a main component. Typically, an amorphous silicon film or an amorphous silicon germanium film is applied,
It is formed to a thickness of 10 to 100 nm by a plasma CVD method, a low pressure CVD method, or a sputtering method. In order to obtain high-quality crystals, it is necessary to reduce the concentration of impurities such as oxygen, nitrogen, and carbon contained in the semiconductor film 103 having an amorphous structure as much as possible. It is desirable to use a CVD apparatus compatible with high vacuum.

Next, the semiconductor film 10 having an amorphous structure
To the surface of No. 3, a metal element having a catalytic action to promote crystallization is added. Metal elements having a catalytic action to promote crystallization of a semiconductor film include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), and rhodium (R).
h), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), gold (A
u) and the like, and one or more selected from them can be used. Typically, nickel is used, and a nickel acetate solution containing 3 to 50 ppm by weight of nickel is applied by a spinner to form the catalyst-containing layer 104. (FIG. 1A) Since the gettering ability performed in a later step is extremely high, a solution containing high-concentration nickel can be used. Further, the number of rotations of the spinner may be reduced to apply a high-concentration solution. In this case, in order to improve the familiarity of the solution, as a surface treatment of the semiconductor film 103 having an amorphous structure, an extremely thin oxide film is formed with an aqueous solution containing ozone, and the oxide film is formed with hydrofluoric acid and aqueous hydrogen peroxide. After forming a clean surface by etching with a mixed solution of the above, an ultrathin oxide film is formed by treating again with an ozone-containing aqueous solution. Since the surface of a semiconductor film such as silicon is hydrophobic in nature, a nickel acetate solution can be uniformly applied by forming an oxide film in this manner.

Of course, the catalyst-containing layer 104 is not limited to the above-described coating method, but may be formed by a sputtering method, a vapor deposition method, a plasma treatment, or the like.

Next, heat treatment or intense light irradiation is performed to perform crystallization. In this case, crystallization forms silicide in a portion of the semiconductor film in contact with a metal element serving as a catalyst,
Crystallization proceeds with the nucleus. Thus, FIG.
A crystalline semiconductor film 105 shown in FIG. In the case of performing crystallization by heat treatment, this amorphous silicon film may be dehydrogenated (500 ° C., 1 hour) and then thermally crystallized (550 ° C. to 650 ° C. for 4 to 24 hours). .
When crystallization is performed by irradiation with strong light, infrared light,
It is possible to use any one of visible light or ultraviolet light or a combination thereof, but typically, a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp,
Alternatively, light emitted from a high-pressure mercury lamp is used. (FIG. 1B) If necessary, heat treatment for releasing hydrogen contained in the semiconductor film 103 having an amorphous structure may be performed before the first strong light irradiation. Further, the crystallization may be performed by simultaneously performing the heat treatment and the irradiation with strong light.

Immediately after the crystallization, the metal element serving as a catalyst may be reduced or removed by etching using an etchant containing fluorine in order to reduce the metal element contained in the semiconductor film.

Next, the crystalline semiconductor film 105 is irradiated with light in order to increase the crystallization rate (the ratio of crystal components in the total volume of the film) and repair defects remaining in the crystal grains. (FIG. 1C) As the light, excimer laser light having a wavelength of 400 nm or less, or the second or third harmonic of a YAG laser is used. Further, a continuous wave gas laser or solid laser may be used. Cr, N as solid-state lasers
d, Er, Ho, Ce, Co, YAG which Ti or Tm is doped, YVO _4, YLF, laser using crystals such as YAlO ₃ applies. The fundamental wave of the laser depends on the material to be doped, and a laser beam having a fundamental wave of about 1 μm can be obtained. Harmonics with respect to the fundamental wave can be obtained by using a nonlinear optical element.
Here, pulse laser light having a repetition frequency of about 10 to 1000 Hz is used, and the laser light is
The crystalline semiconductor film 105 may be subjected to laser treatment with a concentration of 0 to 400 mJ / cm ² and an overlap ratio of 90 to 95%. Further, intense light may be applied instead of laser light, or laser light and intense light may be applied simultaneously.

When a solid-state laser capable of continuous oscillation is used, laser light emitted from a continuous oscillation YVO ₄ laser having an output of 10 W is converted into a harmonic by a nonlinear optical element. There is also a method in which a YVO ₄ crystal and a non-linear optical element are put in a resonator to emit harmonics. Then, the laser light is preferably shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and the laser light is irradiated onto the object to be processed. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed by moving the semiconductor film relatively to the laser light at a speed of about 0.5 to 2000 cm / s.

Next, immediately after the process of repairing the defect, in order to reduce the metal element contained in the crystalline semiconductor film, the metal element serving as a catalyst may be reduced or removed by etching using an etchant containing fluorine. . Further, if the etching causes irregularities on the surface, the surface may be flattened by irradiating strong light.

Next, cleaning is performed to remove organic substances on the surface of the semiconductor film with a solution containing ozone to form an extremely thin oxide film on the surface. It is desirable to control the threshold value of the TFT by performing channel doping in which a very small amount of an impurity element (boron or phosphorus) is added to the semiconductor film by passing through this extremely thin oxide film. After channel doping, strong light irradiation may be performed to activate the impurity element. Further, similar cleaning may be performed before adding nickel, and channel doping may be performed after forming an extremely thin oxide film.

Next, 100 to 20 is deposited on the crystalline semiconductor film.
A silicon oxide film 106a having a thickness of 0 nm is formed. (Figure 1
(D) The method of forming the silicon oxide film is not limited, but for example, tetraethyl orthosilicate (Tetraethyl Ortho Silicate)
icate: TEOS) and O _2, and the reaction pressure is 40 Pa,
A substrate temperature of 300 to 400 ° C. and a high frequency (13.56 MHz)
z) It is formed by discharging at a power density of 0.5 to 0.8 W / cm ² .

Next, a mask 107 made of a resist is formed on the silicon oxide film. After patterning using this mask to form an insulating layer 106b made of silicon oxide covering a portion to be a semiconductor layer of the TFT, a gettering site 108 is formed by adding a rare gas element to the semiconductor film.
(FIG. 2A) Here, it is preferable that the concentration of the rare gas element added to the semiconductor film be 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ³ using an ion doping method or an ion implantation method. At this time, doping with a rare gas element may be performed while a mask made of a resist is left as it is,
After removing the resist mask, doping with a rare gas element may be performed. After the doping with the rare gas element, the resist mask is removed. Further, in addition to the rare gas element, a periodic table group 15 element or a periodic table group 13 element may be added. Although FIG. 2A shows that the rare gas element is added only to the semiconductor film, in actuality, FIG.
14A to 14C, the concentration distribution of the metal element can be controlled. FIG. 14A is obtained under the condition that the concentration distribution 120 has a peak at a shallow position of the semiconductor film, and FIG. 14B shows the concentration distribution 121 having a peak at an intermediate position of the semiconductor film. This is an example in which a rare gas element is also added to the blocking layer 102 because it was performed under such conditions. FIG. 14C illustrates an example in which the rare gas element is added to the blocking layer 102 and the substrate 101 because the concentration distribution 122 has a peak at a deep position in the semiconductor film. FIG. 14 (B) and FIG.
As shown in FIG. 4C, stress can be reduced by adding a rare gas element to the blocking layer or the substrate.

Next, gettering is performed. (Figure 2
(B)) gettering is performed at 450 to 800 in a nitrogen atmosphere.
When heat treatment is performed at a temperature of 1 to 24 hours, for example, at 550 ° C. for 14 hours, a metal element can be segregated at the gettering site 108. By this gettering, a metal element contained in the semiconductor film covered with the insulating layer 106b is removed or the concentration of the metal element is reduced. Further, strong light may be applied instead of the heat treatment. In addition, intense light may be applied in addition to the heat treatment. However, when the RTA method using light emitted from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp is used as the heating means for gettering, the heating temperature of the semiconductor film is reduced. 400
It is desirable to irradiate intense light at a temperature of from 550C to 550C. Alternatively, heat treatment may be performed instantaneously by exposing to an inert gas heated to 450 to 800 ° C. for a short time. If the heating temperature is too high, the strain in the semiconductor film is lost, and the effect of causing nickel to jump out of the gettering site (nickel silicide) and the effect of capturing nickel disappear, thereby lowering the gettering efficiency. .

After the gettering is completed, the gettering site is removed by using the above mask as it is to form a semiconductor layer 109 having a desired shape composed of a region where the metal element is reduced, and finally made of silicon oxide. The insulating layer is removed. (FIG. 2C) When removing the insulating layer, it is desirable that the surface of the semiconductor layer be slightly etched. FIG.
After gettering to 6, FPM (hydrofluoric acid, hydrogen peroxide,
An optical microscope photograph when nickel silicide was etched with a mixed solution of pure water) was shown. From FIG. 36, since a large number of etch pits are observed at the peripheral portion of the semiconductor layer, it is expected that nickel is easily segregated at the peripheral portion of the semiconductor layer by gettering. FIG. 36 shows a base insulating film having a thickness of 50 nm and a thickness of 50 nm on a glass substrate.
Polysilicon film (crystallized after nickel addition) is formed, and argon is accelerated to 10 keV, 1
X 10 ¹⁵ / cm ^{2 at} a dose of 550
After gettering at 4 ° C. for 4 hours, FPM treatment was performed.

Further, at the stage when a mask made of a resist is formed, a gettering site may be formed by doping a rare gas element through a silicon oxide film. In this case, after the doping, the mask is removed and gettering is performed, then the silicon oxide film is removed, and thereafter, only a region (a gettering site) of the semiconductor film to which a rare gas element is added is selectively removed. Thus, a semiconductor layer is formed. When a dash solution, a Sato solution, a Seco solution, or the like is used as an etchant, a region to which a rare gas element is added is amorphous, and therefore, a region which is a crystalline semiconductor film (a rare gas is not added). It can be selectively etched.

Next, after the surface of the semiconductor layer 109 is washed with an etchant containing hydrofluoric acid, an insulating film 110 mainly containing silicon to be a gate insulating film is formed. (Figure 2
(D) The surface cleaning of the semiconductor layer 109 and the formation of the gate insulating film are preferably performed continuously without exposure to the air. Before or after this surface cleaning, an activation step may be added to activate the added impurity element by channel doping.

Next, after the surface of the insulating film 110 is washed and a gate electrode is formed, an impurity element imparting n-type or p-type is added to the semiconductor layer 109 as appropriate to form a source region and a drain region. If necessary, an LDD region may be formed. After addition of the impurity element imparting n-type or p-type, heat treatment, irradiation with strong light, or irradiation with laser light may be performed to activate the impurity element. In particular, it is very effective to activate the impurity element by irradiating the second or third harmonic of the YAG laser from the front or back surface in an atmosphere at room temperature to 300 ° C.

In the subsequent steps, a TFT is completed by forming an interlayer insulating film, hydrogenating, forming a contact hole reaching a source region and a drain region, forming a source electrode and a drain electrode, and the like.

The TFT thus formed is used as a switching element in a pixel portion or a TFT constituting a driving circuit, and is mounted on various electronic devices.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0082]

[Embodiment 1] Here, a method for simultaneously manufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT) of a driving circuit provided around the pixel portion on the same substrate is described with reference to FIGS. This will be described with reference to FIG.

First, in this embodiment, Corning # 70
A substrate 200 made of glass such as barium borosilicate glass typified by 59 glass or # 1737 glass or aluminoborosilicate glass is used. Note that the substrate 200 is not limited as long as it has a light-transmitting property, and a quartz substrate may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a silicon oxide film is formed on the substrate 200,
A base film 201 including an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. Although a two-layer structure is used as the base film 201 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. For the first layer of the base film 201, a plasma CVD
iH _4, NH _3, a and N ₂ O silicon oxynitride film 201a is formed as the reaction gas 10 to 200 nm (preferably 50 to 100 nm) is formed. In this embodiment, the film thickness 5
0 nm silicon oxynitride film 201a (composition ratio Si = 3
2%, O = 27%, N = 24%, H = 17%). Next, as a second layer of the base film 201, a silicon oxynitride film 201b formed using SiH ₄ and N ₂ O as a reaction gas is formed by a plasma CVD method to a thickness of 50 to 200 n.
m (preferably 100 to 150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 201b (composition ratio: Si = 32%, O = 59%, N = 7)
%, H = 2%).

Next, the semiconductor layers 202 to 20 are formed on the underlying film.
6 is formed. The semiconductor layers 202 to 206 are formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCV
D method or plasma CVD method)
A crystalline semiconductor film obtained by performing a known crystallization treatment (such as a laser crystallization method, a thermal crystallization method, or a thermal crystallization method using a catalyst such as nickel) is patterned and formed into a desired shape. . The thickness of the semiconductor layers 202 to 206 is 2
It is formed with a thickness of 5 to 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably silicon or silicon germanium (Si _x Ge).
_It is good to form with _1-X (X = 0.0001-0.02) alloy etc. In this embodiment, a plasma CVD method is used,
After a 55-nm amorphous silicon film was formed, a solution containing nickel was held on the amorphous silicon film. After dehydrogenation (500 ° C., 1 hour) of this amorphous silicon film, thermal crystallization (550 ° C., 4 hours) is performed, and further, laser annealing treatment for improving crystallization is performed. Thus, a crystalline silicon film was formed. Then, as shown in the embodiment, after forming a mask made of a silicon oxide film,
After gettering by selectively adding a rare gas element to the crystalline silicon film using a mask, patterning of the crystalline silicon film was performed, and then the mask was removed. In addition,
When adding a rare gas element, ion doping is performed as a source gas containing argon and a small amount of water vapor. Thus, semiconductor layers 202 to 206 made of a crystalline silicon film were formed. The state where the patterning of the semiconductor layers 202 to 206 is completed corresponds to FIG. 1C in the embodiment. After the oxide film is formed, a small amount of an impurity element (boron or phosphorus) may be appropriately doped to control the threshold value of the TFT.

Next, after the surfaces of the semiconductor layers 202 to 206 are washed with a hydrofluoric acid-based etchant such as buffered hydrofluoric acid, the thickness is 40 to 150 nm using plasma CVD or sputtering, and silicon is used as a main component. Insulating film 2
07 is formed. In this embodiment, a silicon oxynitride film (composition ratio Si) having a thickness of 115 nm is formed by a plasma CVD method.
= 32%, O = 59%, N = 7%, H = 2%). Needless to say, the insulating film serving as the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 3A, a first conductive film 208 having a thickness of 20 to 100 nm and a second conductive film 20 having a thickness of 100 to 400 nm are formed on the gate insulating film 207.
9 are laminated. In this embodiment, a 30 nm-thick T
a first conductive film 208 made of an aN film and a film thickness of 370 nm
The second conductive film 209 made of the W film was formed by lamination. T
The aN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. In addition, thermal CV using tungsten hexafluoride (WF ₆ )
It can also be formed by Method D.

In this embodiment, the first conductive film 208
Is TaN and the second conductive film 209 is W, but there is no particular limitation, and any of Ta, W, Ti, Mo, Al, Cu,
A single layer or a stacked layer may be formed using an element selected from Cr and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. Also,
The first conductive film is formed of a tantalum (Ta) film, the second conductive film is formed of a W film, the first conductive film is formed of a titanium nitride (TiN) film, and the second conductive film is formed of a W film. A combination of forming a first conductive film with a tantalum nitride (TaN) film and forming a second conductive film with an Al film,
The conductive film may be formed of a tantalum nitride (TaN) film and the second conductive film may be formed of a Cu film.

Next, masks 210 to 215 made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, the first etching condition is I
Using a CP (Inductively Coupled Plasma) etching method, using CF ₄ , Cl _2, and O _{2 as} etching gases, and using a gas flow ratio of 25/2.
At 5/10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil-type electrode area size (here, a quartz disk provided with a coil) is a disk having a diameter of 25 cm. In addition, as the etching gas, Cl ₂ , BCl ₃ , SiCl ₄ ,
Chlorine gas such as CCl ₄ or CF ₄ , SF
₆ , a fluorine-based gas such as NF ₃ , or O ₂ can be used as appropriate. Here, a dry etching apparatus using ICP manufactured by Matsushita Electric Industrial Co., Ltd. (Mode
lE645- □ ICP) was used. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under the first etching conditions to make the end of the first conductive layer tapered. The etching rate for W under the first etching condition is 200.39 nm / mi.
n, the etching rate for TaN is 80.32 nm /
min and the selectivity ratio of W to TaN is about 2.5. Further, the taper angle of W is about 26 ° under the first etching condition.

Then, a mask 210 made of resist is formed.
The second etching condition was changed without removing 215, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow rates were set to 30/30 (sccm), and a coil-type electrode was formed at a pressure of 1 Pa. RF (13.56 MHz) power of 500 W was applied to generate plasma, and etching was performed for about 30 seconds. The substrate side (sample stage) also has a 20 W RF (13.56
MHz) power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, by making the shape of the resist mask appropriate,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion may be 15 to 45 degrees.

As described above, the first shape conductive layers 216 to 221 (the first conductive layers 216 a to 221 a and the second conductive layer 216 b) composed of the first conductive layer and the second conductive layer are formed by the first etching process. To 221b). Although not shown, a region of the insulating film 207 serving as a gate insulating film which is not covered with the first shape conductive layers 216 to 221 is 10 to
A thin region is formed by etching about 20 nm.

Then, a first doping process is performed without removing the resist mask to add an impurity element imparting n-type to the semiconductor layer. (FIG. 3B) The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose is 1 × 10 ¹³
１1 × 10 ¹⁵ / cm ² and acceleration voltage of 60-100 keV
Do as. In this embodiment, the dose is set to 5 × 10 ¹⁴ / cm ² and the acceleration voltage is set to 80 keV. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive layers 216 to 221
A high-concentration impurity region 222 to 233 is formed in a self-aligned manner as a mask for the impurity element imparting the mold.
The high-concentration impurity regions 222 to 233 have 3 × 10 ^{19 to} 3 ×
An impurity element imparting n-type is added in a concentration range of 10 ²⁰ / cm ³ .

Next, a second etching process is performed without removing the resist mask. Here, SF ₆ , Cl _2, and O ₂ are used as etching gases, and the respective gas flow ratios are set to 24/12/24 (sccm).
700W RF (13.56MHZ) on coil type electrode at pressure of Pa
z) Apply power and generate plasma to perform etching 2
Performed for 5 seconds. 10W RF on substrate side (sample stage)
(13.56 MHz) Power is applied and a substantially negative self-bias voltage is applied. In the second etching process, the etching rate for W is 227.3 nm / min, the etching rate for TaN is 32.1 nm / min, and T
The selectivity ratio of W to aN is 7.1, and the insulating film 207
The etching rate for SiON is 33.7 nm.
/ Min, and the selectivity ratio of W to TaN is 6.83.
It is. As described above, when SF ₆ is used as the etching gas, the selectivity with respect to the insulating film 207 is high, so that the film loss can be suppressed. In the TFT of the driving circuit, the taper - because of the high longer reliable Longer width in the channel length direction of the section, taper - when forming the parts, SF ₆
It is effective to perform dry etching with an etching gas containing.

The taper angle of W became 70 ° by the second etching process. The second conductive layers 234b to 239b are formed by the second etching process. On the other hand, the first conductive layer is hardly etched,
Of conductive layers 234a to 239a are formed. Although not shown, in practice, the width of the first conductive layer is reduced by about 0.15 μm, that is, about 0.3 μm in the entire line width as compared with before the second etching process.

In the second etching process, CF ₄ , Cl ₂ and O ₂ can be used as an etching gas. In that case, if the gas flow ratio of each gas is 25/25/10 (sccm), and RF (13.56 MHz) power of 500 W is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Good. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. C
When F ₄ , Cl ₂ and O ₂ are used, the etching rate for W is 124.62 nm / min, the etching rate for TaN is 20.67 nm / min, and TaN
Is 6.05. Therefore, the W film is selectively etched.

Next, after removing the resist mask, a second doping process is performed to obtain the state shown in FIG. Doping is performed on the second conductive layers 234b to 239b.
Is used as a mask for the impurity element, and the semiconductor layer below the tapered portion of the first conductive layer is doped so that the impurity element is added. In this embodiment, P (phosphorus) is used as an impurity element, and the doping condition is set at a dose amount of 1.5.
Plasma doping was performed at × 10 ¹⁴ / cm ² , an acceleration voltage of 90 keV, an ion current density of 0.5 μA / cm ² , a phosphine (PH ₃ ) 5% hydrogen dilution gas, and a gas flow rate of 30 sccm. Thus, the low-concentration impurity regions 241 to 254 overlapping with the first conductive layer are formed in a self-aligned manner. Phosphorus (P) added to these low-concentration impurity regions 241 to 254
Is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ , and
The first conductive layer has a concentration gradient according to the thickness of the tapered portion. Note that in the semiconductor layer overlapping with the tapered portion of the first conductive layer, the impurity concentration (P concentration) gradually decreases from the end of the tapered portion of the first conductive layer toward the inside. Further, an impurity element is also added to the high-concentration impurity regions 222 to 233, and the high-concentration impurity regions 255 to 266 are added.
To form

Next, a semiconductor layer which will be an active layer of an n-channel TFT later is masked with a resist mask 267-26.
9 and a third doping process is performed. Due to this third doping process, the semiconductor layer serving as the active layer of the p-channel TFT has a conductivity type (p-type) opposite to the one conductivity type (n-type).
P-type impurity regions 270 to 273 (high-concentration impurity regions 270a to 273a)
And low-concentration impurity regions 270b to 273b). Since doping is performed by passing through the tapered portion, p
The low-concentration impurity regions 270b to 273b have the same concentration gradient as the n-type low-concentration impurity regions 241 to 254. (FIG. 4A) First conductive layers 234a, 236
Using b as a mask for the impurity element, an impurity element imparting p-type is added to form a p-type impurity region.
In this embodiment, the p-type impurity regions 270 to 273 use diborane (B ₂ H ₆ ) and the doping condition is a dose of 1 × 1.
It is formed by an ion doping method at 0 ¹⁵ / cm ² and an acceleration voltage of 30 keV. Note that phosphorus is added to the impurity regions 270a to 273a at different concentrations by the first doping process and the second doping process, but the boron concentration is 6 × 10 ^{19 to} 6
By performing the doping treatment so as to have a density of × 10 ²⁰ / cm ³ , there is no problem because it functions as a source region and a drain region of the p-channel TFT.

Further, when the film is not reduced by the second etching process, for example, when SF ₆ is used as an etching gas,
In order to facilitate the doping of boron, etching (C) for thinning the insulating film 207 before the third doping process is performed.
Reactive ion etching using HF ₃ gas (RIE
Method)).

Next, a mask 274 made of a resist is formed and a third etching process is performed. In the third etching process, only the tapered portion of the first conductive layer is selectively etched. The third etching process is performed using an ICP etching apparatus using Cl ₃ having a high selectivity to W as an etching gas. In this embodiment, the gas flow ratio of Cl ₃ is set to 80 (sccm), RF power (13.56 MHz) of 350 W is applied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma, and etching is performed for 30 seconds. went. A 50 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. By the third etching, the first conductive layers 237c to 237c to
239c are formed. (FIG. 4 (B))

By the third etching process, the pixel portion does not overlap with the first conductive layers 237c to 239c,
Low concentration impurity region (LDD region) 24 having concentration gradient
7 to 254 are formed. Note that, in the driver circuit, the low-concentration impurity regions (GOLD regions) 241 to 246 remain over the first conductive layers 234a to 236a.
As described above, the structure of the TFT is separately formed according to each circuit.

The electrode formed by the first conductive layer 237c and the second conductive layer 237b becomes a gate electrode of an n-channel TFT of a sampling circuit formed in a later step. Similarly, an electrode formed of the first conductive layer 238c and the second conductive layer 238b serves as a gate electrode of an n-channel TFT in a pixel portion formed in a later step,
The electrode formed by the conductive layer 239c and the second conductive layer 239b of the above becomes one electrode of a storage capacitor of a pixel portion formed in a later step.

In this embodiment, the third etching process is performed after the third doping process.
After performing the third etching process, the third doping process may be performed.

Next, the mask 274 made of resist is removed to form a first interlayer insulating film 275. This first
The interlayer insulating film 275 is formed of an insulating film containing silicon with a thickness of 10 to 200 nm by a plasma CVD method or a sputtering method. The first interlayer insulating film functions as an etching stopper to prevent the semiconductor layer from being over-etched when a contact hole is formed later in the reduced insulating film. In this embodiment, a 50 nm-thick silicon oxide film is formed by a plasma CVD method. Of course, the first interlayer insulating film 27
Reference numeral 5 is not limited to a silicon oxide film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Next, as shown in FIG. 4C, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by irradiating the back surface with a YAG laser or an excimer laser.
Irradiation from the back surface can activate an impurity region which overlaps with the gate electrode via the insulating film.

Further, laser light may be irradiated using a reflection plate. In that case, a solid state laser, typically YAG
Laser). When a reflecting plate is used, as shown in a simplified diagram in FIG. 8, a reflecting plate 504 having a mirror surface is used to form a second linear YAG laser from the front side of the substrate 501 and from the back side. A method of simultaneously irradiating a harmonic or a third harmonic was used. Since the YAG laser emits visible light, it is not absorbed if the substrate has a light-transmitting property, and is absorbed by amorphous silicon. In particular,
When a low-concentration impurity region is provided below a gate electrode as in this embodiment, it is very difficult to activate an impurity region overlapping with the gate electrode via an insulating film. Activation of the impurity element included in the impurity region 506 or the channel formation region 505 can be performed by an activation method using a reflector shown in FIG. 8, reference numeral 502 denotes a base film, 503, a high-concentration impurity region, and 507, a cylindrical lens. Note that a rapid thermal annealing method (RTA method) can be applied instead of the YAG laser annealing method.

In this embodiment, the example in which the first interlayer insulating film is formed before the activation is described. However, as a step of forming the first interlayer insulating film after the activation, Is also good.

Next, a second interlayer insulating film 276 made of a silicon nitride film is formed and heat-treated (heat treatment at 300 to 550 ° C. for 1 to 12 hours) to perform a step of hydrogenating the semiconductor layer. In this embodiment, in a nitrogen atmosphere, 410 ° C.
Heat treatment was performed for one hour. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the second interlayer insulating film 276. The semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, a third interlayer insulating film 277 made of an organic insulating material is formed on the second interlayer insulating film 276. In this embodiment, an acrylic resin film having a thickness of 1.6 μm was formed. Next, each of the impurity regions (257, 258, 26
1-263, 265, 270a, 271a, 272a,
Patterning is performed to form a contact hole reaching 273a). In this embodiment, a plurality of etching processes are performed. In this embodiment, after the third interlayer insulating film is etched using the second interlayer insulating film as an etching stopper, the second interlayer insulating film is etched using the first interlayer insulating film as an etching stopper, and then the first interlayer insulating film is etched. The insulating film was etched.

Next, the impurity regions (257, 258, 2
61-263, 270a, 271a, 272a, 273
a) Electrodes 278-286 each electrically connected to a)
And pixel electrode 28 electrically connected to impurity region 265
7 is formed. The materials of these electrodes and pixel electrodes are A
A material having excellent reflectivity, such as a film containing l or Ag as a main component or a laminated film thereof is used.

As described above, the n-channel TFT 30
A drive circuit 301 having a logic circuit portion 303 including 6-channel and p-channel TFTs 305, a sampling circuit portion 304 including an n-channel TFT 308 and a p-channel TFT 307, and a pixel TFT and a storage capacitor 310 including an n-channel TFT 309. Pixel section 3 having
02 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In this embodiment, the structure of the TFT differs depending on each circuit.

The n-channel TFT 309 in the pixel portion includes:
It is required to keep power consumption low, and it is desirable to have a TFT structure with a sufficiently low off-current value. In this embodiment, the low-concentration impurity regions 249 to 252 have a concentration gradient and do not overlap with the gate electrodes (238b, 238c). Also, an n-channel TFT 309
The end of the gate electrode is sandwiched between the gate insulating film,
It substantially coincides with the interface between the channel formation region and the low concentration impurity region. In the concentration distribution of each of the low-concentration impurity regions 249 to 252, the impurity concentration increases as the distance from the channel formation regions 292 and 293 increases.

In this embodiment, the n-channel TFT 3
Reference numeral 09 denotes a structure having two channel formation regions between the source region and the drain region (double gate structure). However, this embodiment is not limited to the double gate structure, and the number of channel formation regions is one. One single gate structure or three triple gate structures may be used.

The impurity regions 253, 254, 265, and 266 functioning as one electrode of the storage capacitor 310 are each doped with an impurity element imparting n-type. The storage capacitor 310 uses the insulating film 207 as a dielectric,
The electrodes 239b and 239c and the semiconductor layer are formed. In this embodiment, the impurity regions and the electrodes 239b, 2
Although the structure does not overlap with 39c, the capacity can be further increased if the structure is made to overlap. Note that the present invention is not limited to the structure for forming the storage capacitor in this embodiment,
It is also possible to use a known structure, for example, a capacitor using a capacitor wiring.

The sampling circuit section 304, typically, an n-channel TFT 308 of an analog switch circuit
It is also preferable that the off-state current value is similarly low. In this embodiment, the low-concentration impurity regions 247 and 248 have a concentration gradient, and have a structure that does not overlap with the gate electrodes (237b and 237c). Further, each low concentration impurity region 24
7 and 248, the impurity concentration increases as the distance from the channel formation region 291 increases.
Note that a structure in which a low-concentration impurity region overlaps with a gate electrode may be used if importance is attached to an on-current value or reliability.

The p-channel TFT 307 has a structure in which the low-concentration impurity regions 272b and 273b overlap the gate electrodes 236a and 236b in order to emphasize the on-current value or reliability. Further, each low-concentration impurity region 272
In the concentration distributions b and 273b, the impurity concentration increases as the distance from the channel formation region 290 increases. The end of the gate electrode of the p-channel TFT 307 has low-concentration impurity regions 272b and 273b and high-concentration impurity regions 272a and 272a with a gate insulating film interposed therebetween.
It substantially coincides with the interface with 3a.

The p-channel type TF of the logic circuit portion
T305 emphasizes on-current value or reliability.
The low concentration impurity regions 270b and 271b are
4a and 234b. In the concentration distribution of each of the low concentration impurity regions 270b and 271b, the impurity concentration increases as the distance from the channel formation region 288 increases.

Similarly, the n-channel TFT 306
Has a structure in which the low-concentration impurity regions 272b and 273b overlap the gate electrodes 235a and 235b. In the concentration distribution of each of the low concentration impurity regions 272b and 273b, the impurity concentration increases as the distance from the channel formation region 289 increases.

As described above, in the present embodiment, it was possible to simultaneously form a drive circuit having a highly reliable TFT 306 and a pixel portion having a pixel TFT 309 with a reduced off-current value on the same substrate. .

In this embodiment, since a large amount of the rare gas element is added, the rare gas element is also added to the base film and the substrate. In addition,
In addition to a rare gas element, hydrogen, oxygen, or water is added to the base film and the substrate, but is easily diffused by heat treatment after doping or the like. On the other hand, the rare gas element hardly diffuses and desorbs even by a relatively high-temperature heat treatment or the like. The rare gas element is added to a region of the base film and the substrate other than a region covered with the mask 106b, that is, a region other than a region where the semiconductor layers 202 to 206 are arranged.

[Embodiment 2] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. FIG. 6 is used for the description.

First, according to the first embodiment, after obtaining the active matrix substrate in the state shown in FIG. 5, an alignment film 401 is formed on the active matrix substrate shown in FIG. 5, and a rubbing process is performed. In this embodiment, before forming the alignment film 401,
An organic resin film such as an acrylic resin film was patterned to form columnar spacers at desired positions for maintaining a substrate interval. Also, instead of columnar spacers,
Spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 400 is prepared. The opposite substrate is provided with a color filter in which a coloring layer 402 and a light shielding layer 403 are arranged corresponding to each pixel.
Further, a light-blocking layer 403 is provided also in a portion of the driver circuit. A flattening film 404 is provided to cover the color filter and the light shielding layer. Next, a counter electrode 405 made of a transparent conductive film was formed in the pixel portion over the planarization film 404, an alignment film 406 was formed over the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with a sealing material 407.
Paste in. A filler is mixed in the sealant 407, and the two substrates are bonded at a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 408 is injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 408. Thus, the active matrix type liquid crystal display device shown in FIG. 6 is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, a polarizing plate and the like were appropriately provided using a known technique. Then, an FPC was attached using a known technique.

The configuration of the liquid crystal module thus obtained will be described with reference to the top view of FIG. Note that the same reference numerals are used for portions corresponding to FIG.

FIG. 7A is a top view showing a pixel portion, a driving circuit, an FPC (Flexible Printed Wiring Board: Flexible
External input terminal 4 for pasting Printed Circuit) 411
09, an active matrix substrate on which a wiring 410 for connecting an external input terminal to an input portion of each circuit is formed, and a counter substrate 400 provided with a color filter and the like are bonded to each other with a sealant 407 interposed therebetween.

A light-shielding layer 403a is provided on the counter substrate side so as to overlap with the gate wiring side driving circuit 301a, and a light-shielding layer 403b is formed on the counter substrate side so as to overlap with the source wiring side driving circuit 301b. In the color filter 402 provided on the counter substrate side on the pixel portion 302, a light-shielding layer and colored layers of red (R), green (G), and blue (B) are provided for each pixel. Have been. When actually displaying, a red (R) colored layer, a green (G) colored layer,
A color display is formed by three colors of a blue (B) colored layer.
The arrangement of the colored layers of these colors is arbitrary.

[0129] Here, the color filter 402 is provided on the opposing substrate in order to achieve colorization. However, the present invention is not particularly limited. When an active matrix substrate is manufactured, a color filter may be formed on the active matrix substrate.

Further, a light-shielding layer is provided between adjacent pixels in the color filter to shield portions other than the display area from light. Further, here, the light-blocking layers 403a and 403b are provided also in a region covering the driver circuit. However, the region covering the driver circuit is covered with a cover when the liquid crystal display device is later incorporated as a display portion of an electronic device. A structure without a light-blocking layer may be employed. When an active matrix substrate is manufactured, a light-blocking layer may be formed on the active matrix substrate.

Further, without providing the above-mentioned light-shielding layer, a colored layer constituting a color filter is appropriately arranged between the opposing substrate and the opposing electrode so as to shield light by a laminated layer of a plurality of layers, and a portion other than the display region ( The gap between each pixel electrode) and the driving circuit may be shielded from light.

An FPC 411 composed of a base film and wiring is bonded to the external input terminal with an anisotropic conductive resin. Furthermore, the mechanical strength is enhanced by the reinforcing plate.

The liquid crystal module manufactured as described above can be used as a display unit of various electronic devices.

[Embodiment 3] This embodiment is different from Embodiment 1 in that
An example in which steps after formation of the insulating film 106a serving as a mask are different will be described. This embodiment is an example in which a rare gas element is added after removing a mask made of a resist. Since the other steps are the same, the same reference numerals as in FIG. 2 are used in FIG.

First, the same state as in FIG. 1D is obtained according to the embodiment. Next, a mask made of a resist is formed according to the embodiment, and the silicon oxide film is patterned to form a mask made of a silicon oxide film. Next, after removing the resist mask, a rare gas element is added. (FIG. 9A)

The subsequent steps are performed according to the embodiment, as shown in FIG.
9 (D) are obtained, and according to the first embodiment, the active matrix substrate shown in FIG. 6 is obtained.

This embodiment can be combined with the second embodiment.

[Embodiment 4] This embodiment is different from Embodiment 1 in the steps after forming a resist mask.

In this embodiment, after a mask made of a resist is formed, the rare gas is passed through the insulating film 106a made of a silicon oxide film without etching the insulating film made of a silicon oxide film as in the first embodiment. Add elements.
(FIG. 10A) FIG. 20 shows a nickel concentration profile subjected to SIMS analysis at this time. FIG. 20 shows the nickel concentration immediately after the addition of the rare gas element (Ar in this case) through the insulating film (0.9 μm in thickness).
Nickel is contained in the semiconductor film in an amount of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / c.
m ³ exists. The added conditions are as follows: argon gas 100% as doping gas, dose amount 4 × 10 ¹⁵ / cm
^{2. The} acceleration voltage is 90 kV.

Next, gettering is performed in a state where it is covered with the insulating film 106a made of silicon oxide. (FIG. 10B) The gettering here is 550
FIG. 21 shows the results obtained by performing SIMS analysis at 4 ° C. for 4 hours and then by SIMS analysis. FIG. 21 shows that nickel in the semiconductor film was removed to the lower detection limit by gettering.

Next, the insulating film 106a is removed. (FIG. 10 (C))

Next, a portion (gettering site) 108 which is made amorphous by adding a rare gas element in the previous step.
Is selectively etched. (FIG. 10 (D))

As an etchant, dash solution, Sato solution,
Seco solution or the like can be used. However, the Seco solution is not industrially suitable because it contains chromium.

According to the above steps, only the semiconductor layer 109 made of crystalline silicon can be left.

This embodiment can be combined with the second embodiment.

[Embodiment 5] In this embodiment, an example in which the crystallization process and the gettering process are performed by the same process is shown in FIG.

First, a blocking layer 602 and an amorphous semiconductor film 603 are formed over a substrate 601 according to the embodiment. Next, a nickel-containing layer 604 is formed. Here, a nickel thin film was formed by a sputtering method.

Next, an insulating film containing silicon as a main component is formed, and a mask 606 made of a resist is formed on the insulating film. Next, etching is performed using a mask made of a resist to selectively remove the insulating film, so that a mask 605 made of an insulating film is formed.

Next, a rare gas element is added to the amorphous semiconductor film by using a mask 606 made of a resist and a mask 605 made of an insulating film. In FIG. 11C, a region to which a rare gas element is selectively added is illustrated as an impurity region 607.

Next, both crystallization and gettering are performed.
Heat treatment or strong light irradiation. Perform by heat treatment
In this case, the temperature is 500 to 650 ° C. for 4 to 24 hours, for example, 5 hours.
It may be performed at 50 ° C. for 4 hours. Insulation by this heat treatment
The amorphous semiconductor film in contact with the mask 605 made of a film
Crystallized by the action of nickel. In this heat treatment
Means that nickel in the amorphous semiconductor film is transferred simultaneously with crystallization.
Move to getterin in the impurity region to which the rare gas element is added.
Is Nickel moves in the direction of the arrow in FIG.
I do. Note that the region to which the rare gas element was added
Does not crystallize. In our experiments, noble gases were added.
If the heat treatment is performed compared to the case where phosphorus is added
Crystallinity is difficult to recover. The comparison results are shown in FIGS.
3. FIG. 22 shows each condition (condition 1 = acceleration power).
Pressure 80 kV, 1.5 × 10¹⁵/ Cm ^TwoPhosphorus dose
Doping, condition 2 = acceleration voltage 80 kV, 1.5 × 1
0¹⁵/ Cm^TwoDoping with phosphorus at a dose of
Pressure 90kV, 2 × 10¹⁵/ Cm^TwoArgon with dose of
Doping, condition 3 = acceleration voltage 80 kV, 1.5 × 1
0¹⁵/ Cm^TwoDoping with phosphorus at a dose of
Pressure 90kV, 4 × 10^{1 Five}/ Cm^TwoArgon with dose of
Doping, condition 4 = acceleration voltage 90 kV, 4 × 10¹⁵
/ Cm^TwoDoping with argon at a dose of
FIG. 23 shows the Raman spectrum immediately after
Immediately after heat treatment at 550 ° C for 4 hours
The spectrum is shown.

Next, impurity region 609 is removed using mask 606, and semiconductor layer 6 made of a crystalline semiconductor film is removed.
10 can be obtained.

In this embodiment, since crystallization and gettering are performed simultaneously, the throughput is remarkably improved.

Further, the blocking layer 602, the amorphous semiconductor film 603, the nickel-containing layer 604, and the insulating film containing silicon as a main component are continuously exposed to the CV without being exposed to the air.
It may be formed by Method D.

This embodiment corresponds to the first embodiment or the second embodiment.
And can be freely combined.

[Embodiment 6] In this embodiment, an example in which a metal element is selectively added using a mask is shown in FIG.

First, a base film (blocking layer) 902 is formed on a substrate 901 according to the embodiment mode or the first embodiment.
A semiconductor film 903 having an amorphous structure is formed. Next, an insulating film containing silicon as a main component is formed. Note that it is preferable that the base film 902, the semiconductor film 903, and the insulating film be successively formed without being released to the atmosphere because impurities are not mixed.

Next, a mask 906 made of a resist is formed, and the insulating film is selectively removed by etching to form a mask 905 made of an insulating film. (FIG. 12
(A))

Next, a metal-containing layer 907 is formed according to the embodiment mode or Example 1. (FIG. 12B) Next, crystallization is performed according to the embodiment mode or Example 1, and a semiconductor film 908 having a crystal structure is obtained. (FIG. 12C) In this crystallization, the crystal grows in the direction indicated by the arrow in FIG. 12C. Note that high-concentration nickel exists in a region not covered with the mask 905.

Then, according to the embodiment, mask 90 is used.
5 to form an impurity region 909 by adding a rare gas element. (FIG. 12 (D))

Then, gettering is performed according to the embodiment. (FIG. 12E) At this time, in the semiconductor film having a crystal structure, the region other than the region 910, that is, the region other than the impurity region 909, was reduced in metal element by gettering.

Next, after the impurity region 909 is removed using the mask 905, the mask 905 is removed to form a semiconductor layer 911. (FIG. 12 (F))

This embodiment corresponds to the first embodiment or the second embodiment.
And can be freely combined.

[Embodiment 7] Unlike the first embodiment, this embodiment is an example in which a mask for selectively adding a rare gas element and a mask used for patterning a semiconductor film are separated. FIG. 13 shows a simplified process diagram of this embodiment.

First, according to Embodiment 1, FIG.
And get the same state.

Next, a mask 1107 made of a resist larger than that in Embodiment Mode 1 is formed, and the silicon oxide film is etched using the mask to form a mask 1106b. Next, a gettering site 1108 is formed by selectively adding a rare gas element using the mask 1106b.

Next, gettering is performed after the mask 1107 is removed. Gettering may be performed according to the first embodiment.

Next, the mask 1106b is removed, and a mask 1111 made of resist is formed again. This mask is for patterning the semiconductor film,
It is provided inside the mask 1107.

Next, the semiconductor film other than the area covered with the mask 1111 is removed. When the gettering is performed, the semiconductor element in the vicinity of the region to which the rare gas element is added is also removed because the metal element tends to segregate at the boundary of the region to which the rare gas element is added. Thus, a semiconductor film 1109 having a crystal structure is formed.

In the subsequent steps, an insulating film 1110 covering the semiconductor film 1109 may be formed in accordance with Embodiment Mode 1.
Then, an active matrix substrate is manufactured according to the first embodiment.

The TFT on the active matrix substrate thus obtained has excellent electric characteristics. FIG. 25 shows voltage / current characteristics and electrical characteristics of the TFT (L / W = 7 μm / 8 μm, n-channel TFT of a driver circuit, and a gate insulating film thickness of 115 nm).

In FIG. 25, the threshold value of the TFT (Vt
h) is 1.222 V, S value is 0.175 V / de
c, the field effect mobility (μFE) is 179.9 cm ² /
Vs, the on-current value is 2.34 × 10 ⁻⁴ A when Vds (voltage difference between the source region and the drain region) = 14 V, and the off-current value is 3.7 × 10 ⁻¹² A when Vds = 14 V. became. These values all indicate good TFT characteristic values.

This embodiment can be combined with any one of Embodiments 1 to 6.

[Eighth Embodiment] In the first embodiment, an example of a reflective display device in which the pixel electrode is formed of a reflective metal material is described. In the present embodiment, the pixel electrode is formed of a light-transmitting conductive material. FIG. 15 shows an example of a transmission type display device formed of a film.

Since the steps up to the step of forming the interlayer insulating film 800 are the same as those of the first embodiment, the description is omitted here. Example 1
After forming the interlayer insulating film 277 according to the above, a pixel electrode 801 made of a light-transmitting conductive film is formed. Examples of the light-transmitting conductive film include ITO (indium tin oxide alloy) and indium zinc oxide alloy (In ₂ O ₃ —Z).
nO), zinc oxide (ZnO), or the like may be used.

Thereafter, a contact hole is formed in interlayer insulating film 800. Next, a connection electrode 802 overlapping with the pixel electrode 801 is formed. This connection electrode 802 is connected to the drain region through a contact hole. In addition, a source electrode or a drain electrode of another TFT is formed simultaneously with the connection electrode 802.

Although an example in which all the driving circuits are formed on the substrate has been described, several ICs may be used as a part of the driving circuit.

An active matrix substrate is formed as described above. Using this active matrix substrate, a liquid crystal module is manufactured according to the second embodiment, a backlight 804 and a light guide plate 805 are provided, and the cover is covered with a cover 806. Thus, an active matrix liquid crystal display device shown in FIG. 15 is completed. Note that the cover 806 and the liquid crystal module are attached to each other using an adhesive or an organic resin. Further, when the substrate and the counter substrate are attached to each other, an organic resin may be filled between the frame and the substrate so as to be adhered. Further, since it is a transmission type, the polarizing plate 803 is attached to both the active matrix substrate and the counter substrate.

This embodiment can be combined with any one of Embodiments 1 to 7.

[Embodiment 9] In this embodiment, the EL (Electr
FIG. 16 shows an example of manufacturing a light-emitting display device provided with an (o Luminescence) element.

FIG. 16A is a top view showing the EL module, and FIG. 16B is a cross-sectional view of FIG. 16A taken along the line AA ′. A pixel portion 702 and a source-side driver circuit 70 are provided over a substrate 700 having an insulating surface (eg, a glass substrate, a crystallized glass substrate, or a plastic substrate).
1 and a gate-side drive circuit 703 are formed. These pixel portions and driving circuits can be obtained according to the embodiment. Reference numeral 718 denotes a sealing material, and 719 denotes a DLC film. The pixel portion and the driving circuit portion are covered with a sealing material 718, and the sealing material is covered with a protective film 719. Further, it is sealed with a cover material 720 using an adhesive.
The cover material 720 may be a base material of any composition such as plastic, glass, metal, and ceramic. In addition, the shape of the cover member 720 and the shape of the support are not particularly limited, and may have a flat surface, a curved surface, a bendable shape, or a film shape. The cover material 720 is preferably made of the same material as the substrate 700, for example, a glass substrate in order to withstand deformation due to heat or external force, and is processed into a concave shape (depth 3 to 10 μm) shown in FIG. . A recess (depth of 50 to 2) into which a desiccant 721 can be installed by further processing
00 μm). In the case where an EL module is manufactured by multi-cavity bonding, a substrate and a cover material may be bonded to each other, and then cut using a CO ₂ laser or the like so that the end faces are aligned.

Although not shown here, in order to prevent the background from being reflected due to the reflection of the metal layer (here, the cathode or the like) used, a circularly polarizing plate made of a phase difference plate (λ / 4 plate) or a polarizing plate is used. A so-called circularly polarizing means may be provided on a substrate (a substrate or a cover material that allows light to pass therethrough).

Reference numeral 708 denotes wiring for transmitting signals input to the source-side drive circuit 701 and the gate-side drive circuit 703, and a video signal or a clock signal from an FPC (flexible print circuit) 709 serving as an external input terminal. Receive. Further, the light emitting device of this embodiment
Digital drive or analog drive may be used, and the video signal may be a digital signal or an analog signal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light emitting device in this specification includes not only the light emitting device main body but also the F
This also includes the state where a PC or PWB is attached. Although a complicated integrated circuit (CPU, controller, or the like) can be formed over the same substrate as the pixel portion and the driver circuit, manufacturing with a small number of masks is difficult. Therefore, an IC including a CPU, a controller, and the like
Chips are mounted on COG (chip on glass) or TAB (tap)
e automated bonding) or wire bonding.

Next, the cross-sectional structure will be described with reference to FIG. An insulating film 710 is provided over a substrate 700. A pixel portion 702 and a gate driver circuit 703 are formed over the insulating film 710. The pixel portion 702 is electrically connected to a current controlling TFT 711 and a drain thereof. And a plurality of pixels including the pixel electrode 712. Further, one pixel may have a structure in which a plurality of, ie, two, three, or more TFTs and various circuits (such as a current mirror circuit) are incorporated. The gate driver circuit 703 is formed using a CMOS circuit in which an n-channel TFT 713 and a p-channel TFT 714 are combined.

The TFTs (711, 713, 714)
) May be manufactured according to the embodiment mode or Example 1. Although an example of a top gate type TFT is shown here, the present invention is not particularly limited thereto, and a bottom gate type TFT and a forward stagger type TFT may be used.

The pixel electrode 712 functions as an anode of the EL element. Further, banks 715 are provided at both ends of the pixel electrode 712.
Are formed, and an EL layer 716 and a cathode 717 of an EL element are formed on the pixel electrode 712.

[0186] As the EL layer 716, an EL layer (a layer for emitting light and moving carriers for light emission) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, a low molecular organic EL material or a high molecular organic EL material may be used. Further, as the EL layer, a thin film made of a light-emitting material (singlet compound) that emits light (fluorescence) by singlet excitation or a thin film made of a light-emitting material that emits light (phosphorescence) by triplet excitation can be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

The cathode 717 also functions as a common wiring for all pixels, and is electrically connected to the FPC 709 via the connection wiring 708. Further, elements included in the pixel portion 702 and the gate driver circuit 703 are all covered with a cathode 717, a sealant 718, and a protective film 719.

It is preferable to use a material that is as transparent or translucent as possible to visible light as the sealant 718. It is preferable that the sealant 718 be a material that does not transmit moisture or oxygen as much as possible.

After the light emitting element is completely covered with the sealing material 718, at least the DL is changed as shown in FIG.
It is preferable to provide a protective film 719 made of a C film or the like on the surface (exposed surface) of the sealant 718. Further, a protective film may be provided on the entire surface including the back surface of the substrate. Here, care must be taken so that the protective film is not formed in a portion where the external input terminal (FPC) is provided. The protection film may be prevented from being formed by using a mask, or the protection film may be prevented from being formed by covering the external input terminal portion with a tape such as Teflon (registered trademark) used as a masking tape in a CVD apparatus. Is also good.

With the above structure, the EL element is sealed with the sealing material 7.
By enclosing the EL element with the protective film 18 and the protective film 719, the EL element can be completely shut off from the outside, and it is possible to prevent a substance such as moisture or oxygen, which promotes deterioration of the EL layer from being oxidized, from entering from the outside. Therefore, a highly reliable light-emitting device can be obtained.

Further, the pixel electrode is made to have an anode (Pt, Cr, W,
9, an EL layer, a light-transmitting cathode (a thin metal layer (AgMg or AlLi) and a transparent conductive film (ITO or ZnO) are stacked, and light is emitted in the direction opposite to that in FIG. 9). The pixel electrode may be a cathode,
An EL layer and an anode may be stacked to emit light in a direction opposite to that in FIG. FIG. 17 shows an example. Note that the top views are the same, and thus are omitted.

The sectional structure shown in FIG. 17 will be described below. As the substrate 1000, a semiconductor substrate or a metal substrate can be used in addition to a glass substrate or a quartz substrate. An insulating film 1010 is provided over the substrate 1000;
A pixel portion 1002 and a gate-side driver circuit 1003 are formed over the insulating film 1010. The pixel portion 1002 is formed by a plurality of pixels including a current control TFT 1011 and a pixel electrode 1012 electrically connected to a drain thereof. Is done. The gate side driver circuit 1003 is formed using a CMOS circuit in which an n-channel TFT 1013 and a p-channel TFT 1014 are combined. Although an example of a top gate type TFT is shown here, the present invention is not particularly limited, and a bottom gate type TFT and a forward stagger type TFT may be used.

The pixel electrode 1012 functions as a cathode of the EL element. Bank 1 is provided at both ends of the pixel electrode 1012.
015 is formed, and the EL layer 10 is formed on the pixel electrode 1012.
16 and an anode 1017 of the EL element are formed.

The anode 1017 also functions as a wiring common to all pixels, and is connected to the FPC 1009 via the connection wiring 1008.
Is electrically connected to Further, the elements included in the pixel portion 1002 and the gate side driver circuit 1003 are all covered with an anode 1017, a sealant 1018, and a protective film 1019 made of DLC or the like. Also, the cover material 1021
And the substrate 1000 were bonded with an adhesive. Further, a concave portion is provided in the cover material, and a desiccant 1021 is provided.

It is preferable that a material that is as transparent or translucent as possible to visible light be used as the sealant 1018. It is preferable that the sealant 1018 be a material that does not transmit moisture or oxygen as much as possible.

In FIG. 17, the pixel electrode is a cathode,
Since the EL layer and the anode are stacked, the light emission direction is the direction of the arrow shown in FIG.

This embodiment can be combined with any one of Embodiments 1 to 8.

[Embodiment 10] In this embodiment, an example different from Embodiment 1 is shown in FIG.

First, a conductive film is formed on a substrate 11 having an insulating surface, and is patterned to form a scanning line 12.
To form The scanning line 12 also functions as a light shielding layer for protecting an active layer formed later from light. Here, a quartz substrate is used as the substrate 11, and a polysilicon film (50 nm thick) and tungsten silicide (W
-Si) A laminated structure of a film (film thickness 100 nm) was used. The polysilicon film protects the substrate from contamination from tungsten silicide.

Next, an insulating film 13a covering the scanning line 12,
13b with a thickness of 100 to 1000 nm (typically 300
To 500 nm). Here, a 100-nm-thick silicon oxide film formed by a CVD method and a 280-nm-thick silicon oxide film formed by an LPCVD method were stacked.

Next, the amorphous semiconductor film is formed to a thickness of 10 to 10
Formed at 0 nm. Here, an amorphous silicon film (amorphous silicon film) having a thickness of 69 nm was formed by an LPCVD method. Next, crystallization, gettering, and patterning are performed by using the technique described in the embodiment mode or the example 1 as a technique for crystallizing the amorphous semiconductor film, and unnecessary portions of the crystalline silicon film are removed. Semiconductor layer 14
To form

Next, in order to form a storage capacitor, a mask is formed and a part of the semiconductor layer (a region to be a storage capacitor) is doped with phosphorus.

[0203] Next, after removing the mask and forming an insulating film covering the semiconductor layer, a mask is formed and the insulating film on a region to be a storage capacitor is selectively removed.

Then, the mask is removed and thermal oxidation is performed to form an insulating film (gate insulating film) 15. Due to this thermal oxidation, the final thickness of the gate insulating film became 80 nm. Note that an insulating film thinner than other regions was formed over the region to be the storage capacitor.

Next, a channel doping step of adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the TFT was performed entirely or selectively. This channel doping step is a step for controlling the TFT threshold voltage. Here, boron was added by an ion doping method in which diborane (B ₂ H ₆ ) was not plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used.

Next, the insulating film 15, the insulating film 13a,
A mask is formed on 13b, and a contact hole reaching the scanning line 12 is formed. After the formation of the contact holes, the mask is removed.

Next, a conductive film is formed and patterned to form a gate electrode 16 and a capacitor wiring 17.
Here, a silicon film doped with phosphorus (having a thickness of 150
nm) and tungsten silicide (150 nm in film thickness). Note that the storage capacitor is formed by the capacitor wiring 17 and a part of the semiconductor layer using the insulating film 15 as a dielectric.

Next, the gate electrode 16 and the capacitance wiring 1
Using phosphorus as a mask, phosphorus is added at a low concentration in a self-aligning manner. The concentration of phosphorus in the region added to this low concentration is 1 ×
10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ , typically 3
It is adjusted so as to be from × 10 ^{17 to} 3 × 10 ¹⁸ atoms / cm ³ .

Next, a mask is formed and phosphorus is added at a high concentration to form a high-concentration impurity region serving as a source region or a drain region. The concentration of phosphorus in the high concentration impurity region is adjusted to be ^{1 × 10 20 ~1 × 10 21} atoms / cm 3 ( typically 3 to ^{× 10 19 ~3 × 10 2 0} / cm 3). In the semiconductor layer 14, a region overlapping with the gate electrode 16 becomes a channel formation region, and a region covered with the mask becomes a low-concentration impurity region and functions as an LDD region. After the addition of the impurity element, the mask is removed.

Next, in order to form a p-channel TFT used for a driving circuit formed on the same substrate as a pixel,
A region to be an n-channel TFT is covered with a mask, and boron is added to form a source region or a drain region.

Next, after removing the mask 412, a passivation film 18 covering the gate electrode 16 and the capacitor wiring 17 is formed. Here, the silicon oxide film is 70 n
m. Next, heat treatment or intense light irradiation treatment for activating the n-type or p-type impurity element added to the semiconductor layer at each concentration is performed. Here, activation was performed by irradiating a YAG laser from the back surface.
An excimer laser may be applied instead of the YAG laser.

Next, an interlayer insulating film 19 made of an organic resin material is formed. Here, an acrylic resin film having a thickness of 400 nm was used. Next, after forming a contact hole reaching the semiconductor layer, an electrode 20 and a source wiring 21 are formed. In this embodiment, the electrode 20 and the source wiring 21 are
i film at 100 nm, aluminum film containing Ti at 300 nm
and a Ti film having a thickness of 150 nm were continuously formed by a sputtering method.

Then, after performing a hydrogenation treatment, an interlayer insulating film 22 made of acrylic is formed. Next, a light-shielding conductive film 100 nm is formed over the interlayer insulating film 22 to form a light-shielding layer 23. Next, an interlayer insulating film 24 is formed. Next, a contact hole reaching the electrode 20 is formed. Next, a 100 nm transparent conductive film (here, an indium tin oxide (ITO) film) is formed and then patterned to form a pixel electrode 25.

It is needless to say that this embodiment is an example and the present invention is not limited to the steps of this embodiment. For example, as each conductive film, tantalum (Ta), titanium (Ti),
Molybdenum (Mo), tungsten (W), chromium (C
r), an element selected from silicon (Si), or an alloy film (typically, a Mo—W alloy or a Mo—Ta alloy) in which the above elements are combined can be used. As each insulating film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an organic resin material (eg, polyimide, acrylic, polyamide, polyimide amide, or BCB (benzocyclobutene)) can be used.

In the present embodiment, the insulating film 13 is used.
Noble gas elements were also added to a and 13b. Note that the region to which the rare gas element is added is other than the region where the semiconductor layer 14 is provided.

This embodiment can be combined with any one of Embodiments 1 to 9.

[Embodiment 11] In the embodiment 1, the top gate type TFT has been described as an example, but the present invention can also be applied to a bottom gate type TFT shown in FIG.

FIG. 19A is an enlarged top view of one of the pixels in the pixel portion. In FIG.
The portion cut at A ′ corresponds to the cross-sectional structure of the pixel portion in FIG.

In the pixel portion shown in FIG.
The part is formed of an N-channel TFT. On board 51
A gate electrode 52, a first insulating film 53a made of silicon nitride, and a second insulating film 53 made of silicon oxide
b is provided. On the second insulating film, a source or drain region 54 to 56 as an active layer, channel forming regions 57 and 58, an LDD region 59 between the source or drain region and the channel forming region,
60 are formed. In addition, channel forming regions 57 and 58
Is protected by the insulating layers 61 and 62. After forming a contact hole in the first interlayer insulating film 63 covering the insulating layers 61 and 62 and the active layer, a wiring 64 connected to the source region 54 is formed, a wiring 65 is connected to the drain region 56, and further thereon. Then, a passivation film 66 is formed. Then, a second interlayer insulating film 67 is formed thereon. Further, a third interlayer insulating film 68 is formed thereon,
A pixel electrode 69 made of a transparent conductive film such as O or SnO ₂ is connected to the wiring 65. Reference numeral 70 denotes a pixel electrode adjacent to the pixel electrode 69.

In this example, an active layer is formed according to the above embodiment.

In this embodiment, an example of a channel stop type bottom gate type TFT is shown as an example, but there is no particular limitation.

In this embodiment, the pixel TFT in the pixel portion is
Has a double-gate structure, but a multi-gate structure such as a triple-gate structure may be used in order to reduce variation in off-state current. Further, a single gate structure may be used to improve the aperture ratio.

The capacitance portion of the pixel portion is formed by the capacitance wiring 71 and the drain region 56 using the first insulating film and the second insulating film as dielectrics.

Note that the pixel portion shown in FIG. 19 is merely an example, and it is needless to say that the present invention is not particularly limited to the above configuration.

This embodiment can be combined with any one of Embodiments 1 to 10.

[Embodiment 12] In this embodiment, an example in which an active matrix substrate is manufactured by a process different from that of Embodiment 1 is shown in FIGS.

In this embodiment, the base film 16 is formed on the substrate 1600.
01 (lamination of the silicon oxynitride film 1601a and the silicon oxynitride film 1601b), and the semiconductor layer 16
02 to 1606, an insulating film 1607 is formed, and a first conductive film 1608 and a second conductive film 16 are formed on the insulating film.
09 is the same as that of the first embodiment.
The semiconductor layer may be formed according to the embodiment. Therefore, a detailed description is omitted here. In addition,
FIG. 30A shows the same state as FIG.

Next, a first etching process is performed in the same manner as in Embodiment 3 to form first shape conductive layers 1616 to 1621 (first conductive layer) composed of a first conductive layer and a second conductive layer. 1616a to 1621a and second conductive layer 1616b
To 1621b). (FIG. 30B) The steps up to this step are the same as in the first embodiment.

In this embodiment, after the first etching process, the second etching process is performed without removing the resist mask. Here, SF ₆ , Cl _2, and O ₂ are used as etching gases, the respective gas flow rates are 24/12/24 (sccm), and 700 W RF ( (13.56 MHz) The power was supplied to generate plasma, and etching was performed for 25 seconds. 10W RF (13.56MH) also on the substrate side (sample stage)
z) Turn on the power and apply a substantially negative self-bias voltage. In the second etching process, the etching rate with respect to W is 227.3 nm / min, the etching rate with respect to TaN is 32.1 nm / min, the selectivity ratio of W with respect to TaN is 7.1, and SiON which is the insulating film 1607 is SiON. Etching rate for 33.7 nm / mi
n and the selectivity ratio of W to TaN is 6.83. As described above, when SF ₆ is used as the etching gas, the selectivity to the insulating film 1607 is high, so that film reduction can be suppressed. In the TFT of the driving circuit, the taper - because of the high longer reliable Longer width in the channel length direction of the section, taper - when forming the parts, SF ₆
It is effective to perform dry etching with an etching gas containing.

The taper angle of W became 70 ° by the second etching process. By this second etching process, second conductive layers 1622b to 1627b are formed.
On the other hand, the first conductive layer is hardly etched to form first conductive layers 1622a to 1627a. Also,
In the second etching process, CF ₄ , Cl ₂ and O
₂ can be used as an etching gas.

Next, after removing the resist mask, a first doping process is performed to obtain the state shown in FIG. Doping is performed on the first conductive layers 1622a to 1622a
By using 27a as a mask for the impurity element, the semiconductor layer below the tapered portion of the first conductive layer is doped so that the impurity element is not added. In this embodiment, P (phosphorus) is used as an impurity element, and phosphine (PH ₃ ) is used.
Plasma doping was performed with a 5% hydrogen dilution gas and a gas flow rate of 30 sccm. Thus, a low-concentration impurity region (n− region) 1628 overlapping with the first conductive layer is formed in a self-aligned manner. The concentration of phosphorus (P) added to low-concentration impurity region 1628 is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ .

[0232] In the first doping treatment, doping may be performed so that an impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer. In that case, the first
Has a concentration gradient according to the thickness of the tapered portion of the conductive layer.

Next, a mask 1629 made of resist is used.
After forming the layers 1632, a second doping process is performed to add an impurity element imparting n-type to the semiconductor layer.
(FIG. 31A) Note that a semiconductor layer to be an active layer of a p-channel TFT later is covered with masks 1629 and 1630.
The doping treatment may be performed by an ion doping method or an ion implantation method. Here, phosphorus is used as an impurity element imparting n-type conductivity, and phosphine (PH ₃ ) is added by an ion doping method using 5% hydrogen dilution gas.

By the second doping process, a semiconductor layer 1603 to be an n-channel TFT of a logic circuit portion later
The conductive layer 1623 serves as a mask for phosphorus, and the self-aligned high-concentration impurity regions (n ⁺ regions) 1643,
644 are formed. In addition, at the time of the second doping treatment, low concentration impurity regions (n ⁻ regions) 1633 and 1634 are also formed by adding them below the tapered portion. Therefore,
N-channel TFT of logic circuit part formed later
Has only a region (GOLD region) overlapping the gate electrode. Note that a low-concentration impurity region (n ⁻ region) 1633,
In 1634, in the semiconductor layer overlapping the tapered portion of the first conductive layer, the impurity concentration (P concentration) gradually decreases from the end of the tapered portion of the first conductive layer toward the inside.

By the second doping process, high-concentration impurity regions 1645 and 1646 are formed in the semiconductor layer 1605 which will later become the n-channel TFT of the sampling circuit portion in a region not covered with the mask 1631. The region covered with the low-concentration impurity region (n
^- region) 1635,1636 are formed. Therefore, the n-channel TFT of the sampling circuit portion later includes only a low-concentration impurity region (LDD region) that does not overlap with the gate electrode.

The second doping process allows
In a semiconductor layer 1606 that becomes an n-channel TFT in a pixel portion,
Indicates that high-density impurities exist in the area not covered by the mask 1632.
Object regions 1647 to 1650 are formed and a mask 1632
In the region covered with the low concentration impurity region (n^-(Area) 16
37 to 1640 are formed. Therefore, n
The channel type TFT has a low concentration non-concentration that does not overlap with the gate electrode.
Only a pure region (LDD region) is provided. Also, after the pixel
The high-concentration impurities are self-aligned
A region 1650 is formed, and a low concentration is formed below the tapered portion.
Impurity region (n ^-Regions) 1641 and 1642 are formed.
You.

By the second doping process, 3 × 10 ¹⁹ to 1 × 10
An impurity element imparting n-type is added in a concentration range of ²¹ / cm ³ .

Further, a rare gas element may be added before and after the second doping treatment. In that case, gettering can be further performed by a heat treatment performed later. In that case, a mask which is added to the end portions of all the semiconductor layers is formed in the second layer.
It is desirable to use it in the doping process.

Next, after removing the masks 1629 to 1632, the semiconductor layer which will later become the active layer of the n-channel TFT is covered with masks 1651 to 1653 made of resist, and a third doping process is performed. (FIG. 31B) A p-type impurity element is added through the tapered portion to form regions containing low-concentration p-type impurity elements (regions (GOLD regions) 1654b to 1657b overlapping with the gate electrode). You. With this third doping treatment, n
Regions 1654a to 1657a containing p-type impurity elements at a high concentration are formed. Although the regions 1654a to 1657a contain low-concentration phosphorus, doping treatment is performed so that the boron concentration becomes 6 × 10 ^{19 to} 6 × 10 ²⁰ / cm ^3, and the source region and the drain region of the p-channel TFT are formed. No problem arises as it functions as an area.

In the present embodiment, the first doping process, the second doping process, and the third doping process are performed in this order. However, the present invention is not particularly limited, and the process order may be freely changed.

Next, a mask 1651 made of resist is used.
Are removed, and a first interlayer insulating film 1658 is formed. The thickness of the first interlayer insulating film 1658 is 10 to 2
The insulating film containing silicon is formed to have a thickness of 00 nm.

Next, as shown in FIG. 31C, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by irradiating the back surface with a YAG laser or an excimer laser. Irradiation from the back surface can activate an impurity region which overlaps with the gate electrode via the insulating film.

In this embodiment, the example in which the first interlayer insulating film is formed before the activation is described. However, after the activation, the step of forming the first interlayer insulating film is performed. Is also good.

Next, a second interlayer insulating film 1659 made of a silicon nitride film is formed and heat-treated (300 to 550 ° C.).
Is performed for 1 to 12 hours) to perform a step of hydrogenating the semiconductor layer. In this embodiment, in a nitrogen atmosphere,
A heat treatment was performed at 1 ° C. for 1 hour. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the second interlayer insulating film 1659. The semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, a third interlayer insulating film 1660 made of an organic insulating material is formed on the second interlayer insulating film 1659. In this embodiment, an acrylic resin film having a thickness of 1.6 μm was formed. Next, patterning for forming a contact hole reaching each high-concentration impurity region is performed. In this embodiment, a plurality of etching processes are performed. In this embodiment, after the third interlayer insulating film is etched using the second interlayer insulating film as an etching stopper, the second interlayer insulating film is etched using the first interlayer insulating film as an etching stopper, and then the first interlayer insulating film is etched. The insulating film was etched.

Next, electrodes 1661 to 1669 electrically connected to the high-concentration impurity regions and pixel electrodes 1670 electrically connected to the high-concentration impurity regions 1649 are formed. As a material for these electrodes and pixel electrodes, a material having excellent reflectivity, such as a film containing Al or Ag as a main component or a laminated film thereof is used.

As described above, the n-channel TFT 17
A logic circuit portion 1703 composed of an N-channel TFT 1708 and a p-channel TFT 1705
A driving circuit 1701 having a sampling circuit portion 1704 including a channel type TFT 1707;
Pixel TFT composed of FT 1709 and storage capacitor 1710
Can be formed over the same substrate. (FIG. 32)

In this embodiment, the n-channel TFT 1
Reference numeral 709 denotes a structure having two channel formation regions between a source region and a drain region (double gate structure). However, this embodiment is not limited to the double gate structure, and one channel formation region is provided. One single gate structure or three triple gate structures may be used.

The present embodiment is characterized in that high-concentration impurity regions suitable for each circuit are separately formed by a second doping process in a self-aligned manner or by a mask. n
TF of channel type TFT 1706, 1708, 1709
The structure of T is a low-concentration drain (LDD: Lightl
y Doped Drain) structure. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source or drain region formed by adding an impurity element at a high concentration.
This is called a DD area. Further, an n-channel TFT 17
Reference numeral 06 denotes a so-called GOLD (Gate-drain OLED) in which an LDD region is arranged so as to overlap with a gate electrode via a gate insulating film.
verlapped LDD) structure. Also, n-channel type TF
T1708 and T1709 have a structure including only a region (LDD region) that does not overlap with the gate electrode. Note that in this specification, a low-concentration impurity region (n ⁻ region) that overlaps with a gate electrode via an insulating film is referred to as a GOLD region, and a low-concentration impurity region (n ⁻ region) that does not overlap with the gate electrode is LD.
It is called D area. A region that does not overlap with this gate electrode (LD
The width of the (D region) in the channel direction can be freely set by appropriately changing the mask in the second doping process. If the conditions of the first doping process are changed so that an impurity element is also added below the tapered portion, the n-channel TFTs 1708 and 1709 have a region overlapping with the gate electrode (a GOLD region) and a gate electrode. And a region (LDD region) that does not overlap with the first region.

This embodiment can be freely combined with any one of Embodiments 1 to 12.

[Embodiment 13] A drive circuit and a pixel portion formed by carrying out the present invention are composed of various modules (an active matrix type liquid crystal module, an active matrix type E module).
L module, active matrix type EC module). That is, by implementing the present invention, all electronic devices incorporating them are completed.

Examples of such electronic devices include a video camera, a digital camera, a head mounted display (goggle type display), a car navigation, a projector, a car stereo, a personal computer, a portable information terminal (a mobile computer, a mobile phone, an electronic book, etc.). ). Examples of those are shown in FIGS.

FIG. 33A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like.

FIG. 33B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on.

FIG. 33C shows a mobile computer (mobile computer) including a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like.

FIG. 33D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on.

FIG. 33E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games and the Internet.

FIG. 33F shows a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown), and the like.

FIG. 34A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention is applied to the liquid crystal module 2808 which forms a part of the projection device 2601, and the entire device can be completed.

FIG. 34B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The entire device can be completed by applying the present invention to the liquid crystal module 2808 which constitutes a part of the device 702.

FIG. 34 (C) is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 34 (A) and 34 (B). Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal module 2808, retardation plate 280
9, the projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, or an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 34D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 34D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 34, a case where a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and an EL module are not shown.

FIG. 35A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 290
6. Image input unit (CCD, image sensor, etc.) 2907
And so on.

FIG. 35B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on.

FIG. 35C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. In addition, the electronic apparatus of the present embodiment includes
The present invention can be realized by using any combination of the twelve combinations.

[0268]

According to the present invention, when crystallization is performed by using heat treatment and activation is performed by a method other than heat treatment, high-temperature heat treatment can be suppressed to two times (crystallization and gettering). When crystallization is performed and activation is performed by a method other than the heat treatment, it can be suppressed to one high-temperature heat treatment (gettering).

[0269] The treatment time for adding a rare gas is as short as about 1 minute or 2 minutes, so that a high-concentration rare gas element can be added to a semiconductor film. And the throughput is significantly improved.

Also, compared to gettering using phosphorus,
The gettering ability of the present invention by adding a rare gas element
Is high, even higher concentration, for example 1 × 10²⁰~ 5 × 10^{twenty one}
/cm ^ThreeCan be added by adding a metal element used for crystallization.
The added amount can be increased. That is, gold used for crystallization
At the time of crystallization treatment by increasing the amount of addition of elemental elements
The time can be further reduced. Also, crystal
If the processing time for crystallization is not changed, the metal used for crystallization
By increasing the amount of element added,
Can be crystallized. Also, the metal source used for crystallization
By increasing the amount of element added, the generation of natural nuclei is reduced.
A good crystalline semiconductor film can be formed.
Can be.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a semiconductor layer.

FIG. 2 is a diagram illustrating a manufacturing process of a semiconductor layer.

FIG. 3 is a view showing a manufacturing process of an AM-LCD.

FIG. 4 is a view showing a manufacturing process of an AM-LCD.

FIG. 5 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 6 is a sectional structural view of an active matrix liquid crystal display device.

FIG. 7 is a diagram illustrating an appearance of a liquid crystal module.

FIG. 8 is a view showing an activation step.

FIG. 9 illustrates a manufacturing process of a semiconductor layer.

FIG. 10 illustrates a manufacturing process of a semiconductor layer.

FIG. 11 illustrates a manufacturing process of a semiconductor layer.

FIG. 12 illustrates a manufacturing process of a semiconductor layer.

FIG. 13 illustrates a manufacturing process of a semiconductor layer.

FIG. 14 is a diagram showing a concentration distribution of a rare gas element.

FIG. 15 is a diagram showing an example of a transmission type.

FIG. 16 is a top view and a cross-sectional view illustrating an EL module.

FIG. 17 is a cross-sectional view illustrating an EL module.

FIG. 18 is a cross-sectional structural view of an active matrix liquid crystal display device.

FIG. 19 is a cross-sectional structural view of an active matrix liquid crystal display device.

FIG. 20 is a graph showing nickel concentration before annealing.

FIG. 21 is a graph showing the nickel concentration after annealing.

FIG. 22 is a graph showing a Raman spectrum before annealing.

FIG. 23 is a graph showing a Raman spectrum after annealing.

FIG. 24 is a graph showing E × B spectrum data.

FIG. 25 is a diagram showing voltage / current characteristics of a TFT.

FIG. 26 is a view showing a relationship between an etch pit density, a heating temperature, and a heating time in a region to be gettered (width: 50 μm).

FIG. 27 is a diagram showing a relationship between an etch pit density, a heating temperature, and a heating time in a region to be gettered (width: 30 μm).

FIG. 28 is a diagram showing a relationship between an etch pit density, a heating temperature, and a heating time in a region to be gettered (width: 30 μm).

FIG. 29 is a simplified diagram showing etch pits observed by FPM processing after gettering.

FIG. 30 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 31 is a view showing a manufacturing process of an AM-LCD.

FIG. 32 is a view showing a manufacturing process of an AM-LCD.

FIG. 33 illustrates an example of an electronic device.

FIG. 34 illustrates an example of an electronic device.

FIG. 35 illustrates an example of an electronic device.

FIG. 36 is an observation photograph after FPM processing is performed after gettering.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shunpei Yamazaki 398 Hase, Hase, Atsugi-shi, Kanagawa Prefecture Inside the Semi-Conductor Energy Laboratory Co., Ltd. (72) Inventor Satoshi Murakami 398 Hase, Atsugi-shi, Kanagawa F-term in Semiconductor Energy Laboratory Co., Ltd. MA07 MA08 MA10 MA12 MA18 MA19 MA22 MA27 MA28 MA29 MA30 MA37 NA21 NA22 NA26 NA27 NA29 PA01 PA09 5F052 AA02 AA11 AA17 AA24 DA02 DA03 DB02 DB03 DB07 EA16 FA06 HA06 JA01 5F110 AA17 BB02 BB04 CC02 CC03 DD03 DD01 DD01 DD01 DD02 EE03 EE04 EE06 EE23 EE28 EE44 EE45 FF02 FF04 FF09 FF23 FF28 FF30 GG 01 GG02 GG13 GG25 GG28 GG29 GG32 GG43 GG45 GG47 GG51 GG52 HJ01 HJ04 HJ12 HJ13 HJ23 HL02 HL03 HL04 HL06 HL11 HL23 HM13 HM15 PP18 NN03 NN04 NN23 NN24 NN27 NN27 NN34 NN27 QQ09 QQ23 QQ25 QQ28

Claims (14)

[Claims] A first step of adding a metal element to a semiconductor film having an amorphous structure; a second step of crystallizing the semiconductor film to form a semiconductor film having a crystal structure; A third step of selectively adding a rare gas element to the semiconductor film to form an impurity region; and obtaining the metal element in the impurity region to select the metal element in the semiconductor film having a crystal structure. A method of manufacturing a semiconductor device, comprising: a fourth step of removing or reducing the impurity; and a fifth step of removing the impurity region. 2. The method according to claim 1, wherein one or more of H, H ₂ , O, O ₂ , and P are added in addition to the rare gas element in the third step. A method for manufacturing a semiconductor device. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the third step is performed in an atmosphere containing a rare gas element and water vapor. 4. The semiconductor device according to claim 1, wherein the impurity element is activated by irradiating the semiconductor film with intense light or laser light from a front side or a back side after the fifth step. A method for manufacturing a semiconductor device, comprising the steps of: 5. The semiconductor device according to claim 1, further comprising a step of oxidizing a surface of the semiconductor film having a crystal structure with a solution containing ozone after the second step. Method of manufacturing. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the second step is heat treatment. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the second step is a step of irradiating the semiconductor film having the amorphous structure with intense light. . 8. The semiconductor device according to claim 1, wherein the second step is a step of performing a heat treatment and irradiating the semiconductor film having the amorphous structure with strong light. Of manufacturing a semiconductor device. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the fourth step is a heat treatment. 10. The method according to claim 1, wherein
The method for manufacturing a semiconductor device, wherein the fourth step is a process of irradiating the semiconductor film with strong light. 11. The method according to claim 1, wherein
The method for manufacturing a semiconductor device, wherein the fourth step is a step of performing a heat treatment and irradiating the semiconductor film with strong light. 12. The high-intensity light according to claim 5, wherein the intense light is light emitted from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. A method for manufacturing a semiconductor device, comprising: 13. The method according to claim 1, wherein the metal element is Fe, Ni, Co, Ru, Rh, P
A method for manufacturing a semiconductor device, which is one or more kinds selected from d, Os, Ir, Pt, Cu, and Au. 14. The method for manufacturing a semiconductor device according to claim 1, wherein the rare gas element is one or more kinds selected from He, Ne, Ar, Kr, and Xe. .