JP2002314092A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TFT and a manufacturing method therefor wherein the electrical characteristics of the TFT which are susceptible to a channel formation region in proximity to the boundary between a semiconductor and a gate insulating film do not vary widely. SOLUTION: A region or layer containing an inert element, that is, a rare gas element is formed in proximity to the boundary between a channel formation region and a gate insulating film of a top gate-type TFT. Like an example illustrated in Fig. 1, the rare gas element is contained at least in the upper layer of the channel formation region 102. As a result, variation in the electrical characteristics of the TFT is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs) and a method for manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic device equipped with such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a thin film transistor (TFT) has been constructed using a semiconductor thin film (thickness of several to several hundred nm) formed on a substrate having an insulating surface, and a large-area integrated circuit formed by the TFT has been developed. The development of a semiconductor device having the same is progressing. Active matrix liquid crystal modules, EL modules, and contact image sensors are known as typical examples. In particular, a TFT having a crystalline silicon film (typically, a polysilicon film) as an active layer (hereinafter, referred to as a polysilicon TFT) has high field-effect mobility and thus forms circuits having various functions. It is also possible.

For example, a liquid crystal module mounted on a liquid crystal display device includes a pixel circuit for displaying an image for each functional block, and a pixel circuit such as a shift register circuit, a level shifter circuit, a buffer circuit, and a sampling circuit based on a CMOS circuit. A driver circuit for controlling the circuit is formed over one substrate.

In addition, the pixel circuit of the active matrix type liquid crystal module has tens to millions of pixels for each pixel.
An FT (pixel TFT) is provided, and each of the pixel TFTs is provided with a pixel electrode. A counter electrode is provided on the counter substrate side sandwiching the liquid crystal, and forms a kind of capacitor using the liquid crystal as a dielectric. Then, the voltage applied to each pixel is controlled by the switching function of the TFT, the liquid crystal is driven by controlling the charge to the capacitor, and the amount of transmitted light is controlled to display an image.

[0006]

The electrical characteristics of a TFT are easily affected by a channel forming region near an interface between a semiconductor and a gate insulating film. The present invention provides a TFT with less variation in electrical characteristics and a method for manufacturing the TFT.

[0007]

The present invention is characterized in that a region or layer containing an inert element, that is, a rare gas element, is formed in a channel formation region. Further, in the present invention, a rare gas element is entirely or selectively added by using an ion doping method or an ion implantation method. Further, in the present invention, a rare gas element which is not bonded to another atom is added to a semiconductor film having a crystal structure, so that the rare gas element is inserted between lattices in the semiconductor film. Gettering can also be performed using a strain field formed when the rare gas element is added. In addition, it is formed by adding a rare gas element by annealing at a relatively high temperature, irradiating a laser beam (pulse oscillation laser beam or continuous oscillation laser beam), or irradiating strong light. The applied strain field may be reduced or eliminated. Note that the added rare gas element hardly diffuses in the film or desorbs from the film even when heat treatment is performed at a relatively high temperature.

A silicon film having a crystal structure, that is, a polysilicon film contains lattice defects such as grain boundaries and stacking faults. The lattice defects act as carrier traps and deteriorate electrical characteristics. Therefore, even in the channel formation region of the TFT, the volume, existence form, and the like of the lattice defect are one of the major causes of the variation in characteristics. According to the present invention, a rare gas element is added to improve uniformity so that lattice defects are uniformly dispersed in a channel formation region without being locally gathered.

According to the structure of the invention disclosed in this specification, in a semiconductor device having a semiconductor layer having a crystal structure on an insulating surface, the semiconductor layer includes a source region, a drain region,
And a channel forming region, wherein the channel forming region is formed of a rare gas element (concentration range: 1 × 10 ^{15 to} 5 × 10 ²¹ / cm 2).
³ , preferably less than 6.6 × 10 ¹⁸ / cm ³ , and more preferably 5 × 10 ¹⁷ / cm ³ or less). Note that the concentration of the rare gas element is 6.6 ×
If it is 10 ¹⁸ / cm ³ or more, the TFT characteristics slightly deteriorate. Note that the channel formation region has a concentration gradient, and the rare gas element is contained at a high concentration on the side near the gate electrode existing above the channel formation region via the gate insulating film.

Another aspect of the invention is a semiconductor device having a semiconductor layer having a crystal structure on an insulating surface.
The semiconductor device is characterized in that the semiconductor layer has a source region, a drain region, and a channel formation region, and has a region containing a rare gas element between the channel formation region and the insulating film. Note that since this region contains a rare gas element, the region has higher electric resistance than the channel formation region.

In another aspect of the invention, a first semiconductor layer having a crystal structure on an insulating surface, a second semiconductor layer in contact with the first semiconductor layer, and a second semiconductor layer in contact with the second semiconductor layer A semiconductor device having an insulating film and an electrode in contact with the insulating film, wherein the second semiconductor layer contains a rare gas element.

In the above structure, the semiconductor layer has a two-layer cross-sectional structure, and one of the layers has a rare gas element added thereto. The semiconductor layer having the two-layer structure is used as an active layer of the TFT. When a rare gas element is added by a plasma doping method, an ion shower doping method, an ion implantation method, a laser doping method, or the like, the semiconductor layer is in an amorphous state depending on the addition conditions. Alternatively, a semiconductor layer having a crystalline structure can be obtained by recrystallizing the amorphous semiconductor layer by heating means (irradiation of laser light or intense light, or heat treatment at a relatively high temperature).

In each of the above structures, the semiconductor device includes a top gate type TFT having a semiconductor layer having a crystal structure, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. It is characterized by:

In each of the above structures, the semiconductor layer is characterized in that the semiconductor layer contains a metal element added at 5 × 10 ¹⁸ / cm ³ or less to promote crystallization of the semiconductor layer.

[0015] Further, the invention relating to a manufacturing method for realizing the above structure includes a first step of adding a metal element to a first semiconductor film having an amorphous structure, and a step of crystallizing the first semiconductor film. A second step of forming a first semiconductor film having a crystal structure by a step, a third step of forming a barrier layer on a surface of the first semiconductor film having the crystal structure, and a second step of forming a second layer on the barrier layer. A fourth step of forming a semiconductor film, a fifth step of adding a rare gas element to the second semiconductor film, and a first step of gettering the metal element to the second semiconductor film and having a crystal structure. A method of manufacturing a semiconductor device, comprising: a sixth step of removing or reducing the metal element in the semiconductor film; and a seventh step of removing the second semiconductor film.

Further, in the fifth step in the structure relating to the above manufacturing method, a rare gas element is added to the first semiconductor film, or a rare gas element is selectively added to a part of the first semiconductor film. Or a layer containing a rare gas element is also formed by adding a rare gas element to the first semiconductor film.

Further, in the above-described structure relating to the manufacturing method, in the sixth step, a heat treatment, a treatment for irradiating the semiconductor film with strong light, or a heat treatment is performed;
The method is characterized in that the process is a process of irradiating the semiconductor film with strong light.

[0018] In the above-described structure relating to the manufacturing method, the intense light is light emitted from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. I have.

Further, a rare gas element may be added to the first semiconductor film in the same step as the formation of the second semiconductor film. Another structure of the present invention is the first semiconductor film having an amorphous structure. A first step of adding a metal element to a semiconductor film, a second step of crystallizing the first semiconductor film to form a first semiconductor film having a crystal structure, and a first semiconductor having the crystal structure A third step of forming a barrier layer on the surface of the film, a fourth step of forming a second semiconductor film containing a rare gas element on the barrier layer, and a heat treatment to form a second semiconductor film on the second semiconductor film. A fifth step of removing or reducing the metal element in the first semiconductor film having a crystal structure by gettering the metal element; and a sixth step of removing the second semiconductor film. This is a method for manufacturing a semiconductor device.

In the fourth step in the structure relating to the above-described manufacturing method, it is preferable that the film formation conditions are such that a rare gas element is also added to the upper layer of the first semiconductor film. For example, using a sputtering method or a PCVD method,
A second semiconductor film containing a rare gas element (typically, an amorphous silicon film containing argon) may be formed by introducing a rare gas element into a deposition chamber.

In each of the above structures, the metal element is Fe, Ni, Co, Ru, Rh, Pd, Os, Ir,
It is characterized by one or more selected from Pt, Cu and Au.

In each of the above structures, the rare gas element is one or more selected from He, Ne, Ar, Kr, and Xe.

[0023]

Embodiments of the present invention will be described below.

FIG. 1 shows an example of the TFT structure of the present invention.
Here, description is made using a top-gate n-channel TFT.

On a substrate 100 having an insulating surface, a base film (101a, 101b) composed of two layers is provided, and a semiconductor layer (channel forming region 102, source region 1) is formed on the base insulating film.
03, and the drain region 104). The semiconductor device further includes a gate insulating film 105 which covers the semiconductor layer, and a gate electrode 106 which overlaps with a channel formation region with the gate insulating film interposed therebetween. Further, an interlayer insulating film 107 covering the gate electrode is provided. It has a source electrode 108 in contact with the source region by a contact hole provided in the interlayer insulating film 107 and a drain electrode 109 in contact with the drain region.

The present invention has a layer 110 to which a rare gas element is added near the interface between the gate insulating film 105 and the channel formation region 102, that is, above the channel formation region. The upper layer of the channel formation region is a semiconductor film having an amorphous structure or a crystalline structure. On the other hand, the lower layer of the channel formation region is a semiconductor film having a crystal structure.

As a manufacturing method for obtaining the above configuration, it is desirable to use the method shown in FIG.

In FIG. 2A, 200 is a substrate having an insulating surface, 201 is a base insulating film, and 202 is a semiconductor film having an amorphous structure.

First, a base insulating film 201 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed as a blocking layer on the substrate 200. Here, a two-layer structure (film thickness 5
0 nm silicon oxynitride film 201a, thickness 100 nm
The silicon oxynitride film 201b) is used, but a single layer film or a structure in which two or more layers are stacked may be used. However,
When there is no need to provide a blocking layer, the base insulating film need not be formed.

Next, a semiconductor film 202 having an amorphous structure is formed on the base insulating film by a known means (sputtering method, LPCV
D method or plasma CVD method). According to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652, a metal element for promoting crystallization is added to the entire surface or a part of a semiconductor film having an amorphous structure. Here, an amorphous silicon film (amorphous silicon film) is formed, and a nickel-containing solution is applied over the amorphous silicon film to form a nickel-containing layer 203. As means other than the formation method by coating, a means for forming an extremely thin film by a sputtering method, an evaporation method, or a plasma treatment may be used.

Next, heat treatment or intense light irradiation is performed to perform crystallization. In this case, crystallization forms silicide in a portion of the semiconductor film in contact with a metal element serving as a catalyst,
Crystallization proceeds with the nucleus. Thus, FIG.
A crystalline semiconductor film 204 shown in FIG. In the case of performing crystallization by heat treatment, this amorphous silicon film may be dehydrogenated (500 ° C., 1 hour) and then thermally crystallized (550 ° C. to 650 ° C. for 4 to 24 hours). .
When crystallization is performed by irradiation with strong light, infrared light,
It is possible to use any one of visible light or ultraviolet light or a combination thereof, but typically, a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp,
Alternatively, light emitted from a high-pressure mercury lamp is used. The lamp light source is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and is repeated once to ten times, and the semiconductor film is heated to about 600 to 1000 ° C. instantaneously. Note that heat treatment for releasing hydrogen contained in the semiconductor film 202 having an amorphous structure may be performed before irradiation with strong light, if necessary. Further, the crystallization may be performed by simultaneously performing the heat treatment and the irradiation with strong light.

Next, in order to increase the crystallization rate (the ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains, the semiconductor film 204 having a crystal structure is irradiated with laser light. It is desirable. Excimer laser light having a wavelength of 400 nm or less, or a second or third harmonic of a YAG laser is used as the laser light. In any case, pulse laser light having a repetition frequency of about 10 to 1000 Hz is used, and the laser light is applied to the optical system by 100 to 40 Hz.
The laser processing may be performed on the crystalline semiconductor film 204 with a concentration of 0 mJ / cm ² and an overlap ratio of 90 to 95%.

Although an example using a pulsed laser is shown here, a continuous wave laser may be used. In order to obtain a crystal having a large grain size when crystallizing an amorphous semiconductor film, a continuous wave laser is used. Using a solid-state laser capable of oscillation,
It is preferable to apply the harmonic to the fourth harmonic. Typically, the second of a Nd: YVO ₄ laser (fundamental wave 1064 nm)
A harmonic (532 nm) or a third harmonic (355 nm) may be applied. When a continuous wave laser is used, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method in which a YVO ₄ crystal and a non-linear optical element are put in a resonator to emit harmonics. Then, the laser light is preferably shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and the laser light is irradiated onto the object to be processed. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relatively to the laser light at a speed of about 10 to 2000 cm / s.

Here, a technique of irradiating a laser beam after performing thermal crystallization using nickel as a metal element for promoting crystallization of silicon was used, but a continuous oscillation laser was added without adding nickel. (The second harmonic of the YVO ₄ laser) may crystallize the amorphous silicon film.

Next, an extremely thin oxide film 205 is formed using an aqueous solution containing ozone, and a semiconductor film 206 is formed on the oxide film 205.
To form (FIG. 2C) The oxide film 205 functions as an etching stopper when only the semiconductor film 206 is selectively removed in a later step. The semiconductor film 20
6 may be a semiconductor film having an amorphous structure or a semiconductor film having a crystalline structure.

Next, a gettering site is formed by adding a rare gas element to the semiconductor film 206 by an ion doping method or an ion implantation method. (FIG. 2D) One or a plurality of rare gas elements selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. Here, in order to form a gettering site, these inert gases are used as an ion source and injected into the semiconductor film by an ion doping method or an ion implantation method. There are two meanings to implant ions of these inert gases. One is to form a dangling bond by implantation and to give a strain to the semiconductor film,
The other is to give a distortion by implanting the ions between lattices of the semiconductor film. The ion implantation of an inert gas can satisfy both of them at the same time. In particular, the latter is remarkably obtained when an element having a larger atomic radius than silicon, such as argon (Ar), krypton (Kr), or xenon (Xe), is used. Can be Further, by injecting the rare gas element, not only lattice distortion but also dangling bonds are formed, which contributes to gettering action. In the case where phosphorus, which is an impurity element of one conductivity type, is injected into a semiconductor film in addition to a rare gas element, gettering can be performed using Coulomb force of phosphorus.

In the step of FIG. 2D, the rare gas element added has a concentration peak as shown in FIG. 7 which shows the acceleration voltage dependency when adding an argon element in the ion doping method. Utilizing this, a rare gas element is also added to the upper layer of the semiconductor film 204 having a crystal structure as shown in FIG. However, it is desirable to maintain the crystal structure as much as possible without adding a rare gas element to the lower layer.
Note that the concentration profile and cross-sectional view shown in FIG.
(D), and the same reference numerals are used for the same parts.

Next, gettering is performed. (Figure 2
(E)) The step of performing gettering is performed at 450 to 800 ° C. for 1 to 24 hours, for example, 550 ° C. in a nitrogen atmosphere.
May be performed for 14 hours. Further, instead of heat treatment using a furnace (including furnace annealing), intense light from a lamp light source may be applied. In addition, intense light may be applied in addition to the heat treatment. As a result of this gettering, FIG.
(E) Nickel moves in the direction of the arrow in FIG.
The removal of the metal element contained in the semiconductor film 204 covered with 5 or the reduction of the concentration of the metal element is performed. This heat treatment also serves as annealing. Here, the semiconductor film 204
Although a small amount of a rare gas element is also added to the semiconductor film 204, it is desirable that all nickel be moved to the semiconductor film 207 so as not to segregate in the semiconductor film 204 and that gettering be sufficiently performed so that nickel contained in the semiconductor film 204 does not exist. .

FIG. 8 shows that a 100 ppm nickel acetate solution is applied on an amorphous silicon film having a thickness of 300 nm.
After crystallizing by heat treatment at 550 ° C. for 4 hours to form a semiconductor film having a crystal structure, argon is used under conditions (acceleration voltage 10 keV, dose 2 × 1) by ion doping.
0 ¹⁵ / cm ² ) is a diagram in which the concentration distribution of argon in the depth direction in the film was measured by SIMS analysis of the sample added. From FIG. 8, it can be seen that argon is 1 × 10 ¹⁸ / cm
It can be seen that it is added at a concentration of ³ or more and is added to a depth of about 80 nm from the surface of the semiconductor film having a crystal structure.

FIG. 8 shows that this sample was heated at 550 ° C.
The argon concentration distribution after the heat treatment for 4 hours is also shown. The argon concentration before and after the heat treatment did not change, and the content did not change.

On the other hand, FIG. 9 shows the results of SIMS analysis of the nickel concentration contained in this sample before and after the heat treatment. The nickel concentration in the film, which was about 5 × 10 ¹⁸ / cm ³ , was measured. Is reduced by heat treatment to 1 × 10
It has been reduced to ¹⁸ / cm ³ . The distribution of nickel concentration changes after the heat treatment, and the nickel concentration peak in the region where argon is added increases. From these facts, it can be seen that the nickel distributed in the film by the heat treatment moved to the region to which argon was added.
Thus, FIG. 9 clearly shows the gettering effect by the addition of argon and the heat treatment.

Next, after selectively removing only the semiconductor film indicated by 207 using the oxide film 205 as an etching stopper, the semiconductor film 204 is formed into a semiconductor layer 208 having a desired shape by a known patterning technique.

Next, after the surface of the semiconductor layer is washed with an etchant containing hydrofluoric acid, an insulating film containing silicon as a main component to be a gate insulating film 209 is formed. It is desirable that the surface cleaning and the formation of the gate insulating film be performed continuously without exposure to the air.

Next, after cleaning the surface of the gate insulating film,
The gate electrode 210 is formed, and the source region 211 and the drain region 212 are formed by appropriately adding an impurity element (P, As, or the like) which imparts n-type to a semiconductor, here, phosphorus. After the addition, heat treatment, strong light irradiation, or laser light irradiation is performed to activate the impurity elements. In addition, plasma damage to the gate insulating film and plasma damage to the interface between the gate insulating film and the semiconductor layer can be recovered simultaneously with the activation. In particular, it is very effective to activate the impurity element by irradiating the second harmonic of the YAG laser from the front surface or the back surface in an atmosphere at room temperature to 300 ° C. A YAG laser is a preferred activation means because of its low maintenance.

In the subsequent steps, an interlayer insulating film 214 is formed, hydrogenation is performed, contact holes reaching the source region and the drain region are formed, and a source electrode 215 and a drain electrode 216 are formed to complete a TFT. .

As shown in FIG. 1, the TFT thus obtained contains a rare gas element at least in the upper layer of the channel forming region 213. The region containing the rare gas element has a lower electrical resistance than the insulating film, and becomes a buffer layer higher than the underlying semiconductor layer. Note that the depth at which the rare gas element exists can be freely determined by appropriately selecting conditions in the ion doping method or the ion implantation method.

Although an example in which a rare gas element is added at the time of gettering is shown here, a semiconductor layer crystallized by a known crystallization technique, for example, a laser crystallization method or a thermal crystallization method is obtained. After that, a rare gas element may be appropriately added.

The present invention is not limited to the structure shown in FIG.
If necessary, a lightly doped drain (LDD) structure having an LDD region between a channel formation region and a drain region (or a source region) may be employed. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source or drain region formed by adding an impurity element at a high concentration. This region is referred to as an LDD region. Calling. Furthermore, a so-called GOLD (Gate-drain Overlapped) in which an LDD region is arranged so as to overlap with a gate electrode via a gate insulating film.
(LDD) structure. Further, a region or a layer containing a rare gas element may be formed in these LDD regions or GOLD regions.

Although the description has been made using the n-channel type TFT here, it goes without saying that a p-channel type TFT can be formed by using a p-type impurity element instead of the n-type impurity element.

Although a top gate type TFT has been described here as an example, the present invention can be applied regardless of the TFT structure. For example, a bottom gate type (reverse stagger type) TFT or a forward stagger type TFT can be used. It is possible to apply.

The concentration of the rare gas element contained in the upper layer of the semiconductor layer of the present invention is 3 × 10 ¹⁴ to 2 × 10 ²⁰ / c.
m ³ , preferably 1 × 10 ¹⁵ to 1 × 10 ²⁰ / cm ³ , at least as long as at least the lower limit of detection of SIMS.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

(Embodiment) [Embodiment 1] Here, a pixel portion and a driving circuit TFT (n-channel TFT) provided around the pixel portion on the same substrate are used.
And a method for simultaneously fabricating a p-channel TFT) will be described with reference to FIGS.

First, in this embodiment, Corning # 70
A substrate 200 made of glass such as barium borosilicate glass typified by 59 glass or # 1737 glass or aluminoborosilicate glass is used. Note that the substrate 300 is not limited as long as it is a light-transmitting substrate, and a quartz substrate may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a silicon oxide film is formed on the substrate 300,
A base film 301 including an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. Although a two-layer structure is used as the base film 301 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. For the first layer of the base film 301, a plasma CVD
iH _4, NH _3, a and N ₂ O silicon oxynitride film 301a is formed as the reaction gas 10 to 200 nm (preferably 50 to 100 nm) is formed. In this embodiment, the film thickness 5
0 nm silicon oxynitride film 301a (composition ratio Si = 3
2%, O = 27%, N = 24%, H = 17%). Next, as a second layer of the base film 301, a silicon oxynitride film 301b formed using SiH ₄ and N ₂ O as a reaction gas by plasma CVD is used to form a _second layer of 50 to 200 n.
m (preferably 100 to 150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 301b (composition ratio: Si = 32%, O = 59%, N = 7)
%, H = 2%).

Next, the semiconductor layers 302 to 30 are formed on the underlying film.
6 is formed. The semiconductor layers 302 to 306 are formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCV
D method or plasma CVD method)
A crystalline semiconductor film obtained by performing a known crystallization treatment (such as a laser crystallization method, a thermal crystallization method, or a thermal crystallization method using a catalyst such as nickel) is patterned and formed into a desired shape. . The thickness of the semiconductor layers 302 to 306 is 2
It is formed with a thickness of 5 to 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably silicon or silicon germanium (Si _x Ge).
_It is good to form with _1-X (X = 0.0001-0.02) alloy etc.

In this embodiment, a plasma CVD method is used.
After a 55-nm amorphous silicon film was formed, a solution containing nickel was held on the amorphous silicon film. After dehydrogenation (500 ° C., 1 hour) of this amorphous silicon film, thermal crystallization (550 ° C., 4 hours) is performed, and further, laser annealing treatment for improving crystallization is performed. Thus, a crystalline silicon film was formed. Then, as described in the embodiment, after forming an extremely thin oxide film on the surface with a solution containing ozone, an amorphous silicon film is formed on the oxide film, and a rare gas element is added to the amorphous silicon film. After performing gettering by adding to the entire surface and performing heat treatment, only the amorphous silicon film was removed, the crystalline silicon film was patterned, and then the oxide film was removed. When a rare gas element is added, ion doping is performed using argon as a source gas. Thus, the semiconductor layer 30 made of the crystalline silicon film
2 to 306 were formed. The state where the patterning of the semiconductor layers 302 to 306 is completed corresponds to FIG. 2F in the embodiment. After forming the oxide film, TF
In order to control the threshold value of T, a small amount of impurity element (boron or phosphorus) may be appropriately doped (also referred to as channel doping).

Next, after the surfaces of the semiconductor layers 302 to 306 are washed with a hydrofluoric acid-based etchant such as buffered hydrofluoric acid, the thickness is set to 40 to 150 nm by plasma CVD or sputtering, and silicon is used as a main component. Insulating film 3
07 is formed. In this embodiment, a silicon oxynitride film (composition ratio Si) having a thickness of 115 nm is formed by a plasma CVD method.
= 32%, O = 59%, N = 7%, H = 2%). Needless to say, the insulating film serving as the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 4A, a first conductive film 208 having a thickness of 20 to 100 nm and a second conductive film 30 having a thickness of 100 to 400 nm are formed on the gate insulating film 307.
9 are laminated. In this embodiment, a 30 nm-thick T
a first conductive film 308 made of an aN film and a film thickness of 370 nm
A second conductive film 309 made of a W film was formed by lamination. T
The aN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. In addition, thermal CV using tungsten hexafluoride (WF ₆ )
It can also be formed by Method D.

In this embodiment, the first conductive film 308
Is TaN, and the second conductive film 309 is W. However, the present invention is not particularly limited, and any of Ta, W, Ti, Mo, Al, Cu,
A single layer or a stacked layer may be formed using an element selected from Cr and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. Also,
The first conductive film is formed of a tantalum (Ta) film, the second conductive film is formed of a W film, the first conductive film is formed of a titanium nitride (TiN) film, and the second conductive film is formed of a W film. A combination of forming a first conductive film with a tantalum nitride (TaN) film and forming a second conductive film with an Al film,
The conductive film may be formed of a tantalum nitride (TaN) film and the second conductive film may be formed of a Cu film.

Next, masks 310 to 315 made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, the first etching condition is I
Using a CP (Inductively Coupled Plasma) etching method, using CF ₄ , Cl _2, and O _{2 as} etching gases, and using a gas flow ratio of 25/2.
At 5/10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. The film is formed into a desired tapered shape by appropriately adjusting the etching conditions (the amount of electric power applied to the coil-type electrode, the amount of electric power applied to the substrate-side electrode, the temperature of the substrate-side electrode, etc.) using the ICP etching method. Can be etched. In addition, Cl ₂ , BCl ₃ , SiCl ₄ , C
Chlorine gas such as Cl ₄ or CF ₄ , S
Fluorine gas such as F ₆ , NF ₃ , or O ₂
Can be used as appropriate. Here, a dry etching apparatus using ICP manufactured by Matsushita Electric Industrial Co., Ltd. (Mode
lE645- □ ICP) was used. Apply 150W RF (13.56MHz) power to the substrate side (sample stage),
A substantially negative self-bias voltage is applied. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil-type electrode area size (here, a quartz disk provided with a coil) is a disk having a diameter of 25 cm. The W film is etched under the first etching conditions to make the end of the first conductive layer tapered. The etching rate for W under the first etching condition is 200.39.
nm / min, the etching rate for TaN is 80.
It is 32 nm / min and the selectivity ratio of W to TaN is about 2.5. Further, the taper angle of W is about 26 ° under the first etching condition.

Thereafter, a mask 310 made of resist is formed.
The second etching condition was changed without removing 315, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow ratios were 30/30 (sccm), and the pressure was 1 Pa to form a coil-type electrode. RF (13.56 MHz) power of 500 W was applied to generate plasma, and etching was performed for about 30 seconds. The substrate side (sample stage) also has a 20 W RF (13.56
MHz) power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, by making the shape of the mask made of resist suitable,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion may be 15 to 45 degrees.

As described above, the first shape conductive layers 316 to 321 (the first conductive layers 316 a to 321 a and the second conductive layer 316 b) composed of the first conductive layer and the second conductive layer are formed by the first etching process. To 321b). Although not shown, a region of the insulating film 307 serving as a gate insulating film which is not covered with the first shape conductive layers 316 to 321 is 10 to
A thin region is formed by etching about 20 nm.

In this embodiment, the second etching process is performed after the first etching process without removing the resist mask. Here, SF ₆ , Cl _2, and O ₂ are used as etching gases, the respective gas flow rates are 24/12/24 (sccm), and 700 W RF ( (13.56 MHz) The power was supplied to generate plasma, and etching was performed for 25 seconds. 10W RF (13.56MH) also on the substrate side (sample stage)
z) Turn on the power and apply a substantially negative self-bias voltage. In the second etching process, the etching rate for W is 227.3 nm / min, the etching rate for TaN is 32.1 nm / min, the selectivity ratio of W to TaN is 7.1, and the insulating film 307 is made of S.
The etching rate for iON is 33.7 nm / min.
And the selectivity ratio of W to TaN is 6.83.
As described above, when SF ₆ is used as the etching gas, the selectivity with respect to the insulating film 307 is high, so that film reduction can be suppressed. In the TFT of the driver circuit, the longer the width of the tapered portion in the channel length direction is, the higher the reliability is. Therefore, when forming the tapered portion, dry etching can be performed with an etching gas containing SF _6. It is valid.

The taper angle of W became 70 ° by the second etching process. The second conductive layers 322b to 327b are formed by the second etching process. On the other hand, the first conductive layer is hardly etched,
Of the conductive layers 322a to 327a are formed. In the second etching process, CF ₄ , Cl _2, and O ₂ can be used as an etching gas.

Next, after removing the resist mask, a first doping process is performed to obtain the state shown in FIG. The doping is performed for the first conductive layers 322a to 327a.
Is used as a mask for the impurity element so that the semiconductor layer below the tapered portion of the first conductive layer is doped so that the impurity element is not added. In this embodiment, P (phosphorus) was used as an impurity element, and plasma doping was performed with a phosphine (PH ₃ ) 5% hydrogen dilution gas and a gas flow rate of 30 sccm. Thus, a low-concentration impurity region (n ⁻ region) 328 overlapping with the first conductive layer is formed in a self-aligned manner. The concentration of phosphorus (P) added to low-concentration impurity region 328 is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ .

In the first doping process, doping may be performed so that an impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer. In that case, the first
Has a concentration gradient according to the thickness of the tapered portion of the conductive layer.

Next, a resist mask 329 to 329 is formed.
After forming 330, a second doping process is performed to add an impurity element imparting n-type to the semiconductor layer. (FIG. 5
(A)) Note that a semiconductor layer to be an active layer of a p-channel TFT later is covered with masks 329 and 330. The doping treatment may be performed by an ion doping method or an ion implantation method. Here, phosphorus is used as an impurity element imparting n-type conductivity, and phosphine (PH ₃ ) is added by an ion doping method using 5% hydrogen dilution gas.

By the second doping process, the conductive layer 323 serves as a mask for phosphorus in the semiconductor layer 303 which will later become the n-channel TFT of the logic circuit portion, and the self-aligned high-concentration impurity region (n ⁺ region) 343 , 344 are formed. At the time of the second doping process, low concentration impurity regions (n ⁻ regions) 333 and 334 are also formed by being added below the tapered portion. Therefore, an n-channel TFT of a logic circuit portion formed later includes only a region (a GOLD region) overlapping with a gate electrode. Note that in the low-concentration impurity regions (n ⁻ regions) 333 and 334, in the semiconductor layer overlapping with the tapered portion of the first conductive layer, the impurity concentration (from the end of the tapered portion of the first conductive layer toward the inside). P concentration) gradually decreases.

Further, by the second doping process, high-concentration impurity regions 345 and 346 are formed in regions not covered with the mask 331 in the semiconductor layer 305 which will later become the n-channel TFT of the sampling circuit portion. 33
In the region covered with 1, a low concentration impurity region (n ⁻ region) 3
35, 336 are formed. Therefore, the n-channel TFT of the sampling circuit portion later includes only a low-concentration impurity region (LDD region) that does not overlap with the gate electrode.

Further, by the second doping process, high-concentration impurity regions 347 to 350 are formed in regions of the semiconductor layer 306 which will later become n-channel TFTs in the pixel portion, without being covered with the mask 332. Low concentration impurity regions (n ⁻ regions) 337 to 34
0 is formed. Therefore, the n-channel type T
FT is a low-concentration impurity region (L
DD area). A high-concentration impurity region 350 is formed in a self-aligned manner in a region which will later become a capacitor portion of the pixel portion, and a low-concentration impurity region (n
^- regions) 341 and 342 are formed.

By the second doping process, the high-concentration impurity regions 343 to 350 have a density of 3 × 10 ¹⁹ to 1 × 10 ²¹ / c.
An impurity element imparting n-type is added in the concentration range of m ³ .

In addition, a rare gas element may be added before and after the second doping treatment. In this case, gettering can be further performed by a heat treatment performed later. In that case, a mask which is added to the end portions of all the semiconductor layers is formed in the second layer.
It is desirable to use it in the doping process.

Next, after removing the masks 329 to 332, the semiconductor layer which will later become the active layer of the n-channel TFT is covered with masks 351 to 353 made of resist, and a third doping process is performed. (FIG. 5B) A region containing the p-type impurity element at a low concentration and passing through the tapered portion and containing the p-type impurity element (a region overlapping with the gate electrode (GOL)
D regions) 354b to 357b) are formed. This third
Region 35 containing the n-type impurity element at a low concentration and the p-type impurity element at a high concentration
4a to 357a are formed. The regions 354a to 357a contain a low concentration of phosphorus.
Since doping treatment is performed so as to be 10 ^{19 to} 6 × 10 ²⁰ / cm ³ and functions as a source region and a drain region of the p-channel TFT, no problem occurs.

In the present embodiment, the first doping process, the second doping process, and the third doping process are performed in this order. However, the present invention is not particularly limited, and the process order may be freely changed.

Next, masks 351 to 351 made of resist are used.
By removing 353, a first interlayer insulating film 358 is formed. As the first interlayer insulating film 358, plasma C
The thickness is 10 to 200 n using the VD method or the sputtering method.
m is formed of an insulating film containing silicon.

Next, as shown in FIG. 5C, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by irradiating the back surface with a YAG laser or an excimer laser.
Irradiation from the back surface can activate an impurity region which overlaps with the gate electrode via the insulating film.

In this embodiment, the example in which the first interlayer insulating film is formed before the above activation is shown. However, after the above activation, the step of forming the first interlayer insulating film is performed. Is also good.

Next, a second interlayer insulating film 359 made of a silicon nitride film is formed and heat-treated (heat treatment at 300 to 550 ° C. for 1 to 12 hours) to perform a step of hydrogenating the semiconductor layer. In this embodiment, in a nitrogen atmosphere, 410 ° C.
Heat treatment was performed for one hour. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the second interlayer insulating film 359. The semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, a third interlayer insulating film 360 made of an organic insulating material is formed on the second interlayer insulating film 359. In this embodiment, an acrylic resin film having a thickness of 1.6 μm was formed. Next, patterning for forming a contact hole reaching each high-concentration impurity region is performed. In this embodiment, a plurality of etching processes are performed. In this embodiment, after the third interlayer insulating film is etched using the second interlayer insulating film as an etching stopper, the second interlayer insulating film is etched using the first interlayer insulating film as an etching stopper, and then the first interlayer insulating film is etched. The insulating film was etched.

Next, electrodes 361 to 369 electrically connected to the high-concentration impurity regions and pixel electrodes 370 electrically connected to the high-concentration impurity regions 349 are formed.
As a material for these electrodes and pixel electrodes, a material having excellent reflectivity, such as a film containing Al or Ag as a main component or a laminated film thereof is used.

As described above, the n-channel TFT 40
A driving circuit 401 having a logic circuit portion 403 including 6-channel and p-channel TFTs 405, a sampling circuit portion 404 including an n-channel TFT 408 and a p-channel TFT 407, and a pixel TFT and a storage capacitor 410 including an n-channel TFT 409. Pixel section 4 having
02 can be formed over the same substrate. (FIG. 6)

In this embodiment, the n-channel TFT 4
Reference numeral 09 denotes a structure having two channel formation regions between the source region and the drain region (double gate structure). However, this embodiment is not limited to the double gate structure, and the number of channel formation regions is one. One single gate structure or three triple gate structures may be used.

The present embodiment is characterized in that high-concentration impurity regions suitable for each circuit are separately formed by a second doping process in a self-aligned manner or by a mask. n
Each of the TFT structures of the channel type TFTs 406, 408, and 409 has a lightly doped drain (LDD).
d Drain) structure. Furthermore, n-channel type TF
T406 has a so-called GOLD structure in which an LDD region is overlapped with a gate electrode with a gate insulating film interposed therebetween. The n-channel TFTs 408 and 409 have a structure including only a region (LDD region) that does not overlap with the gate electrode. In this specification, a low-concentration impurity region (n ⁻ region) overlapping with a gate electrode with an insulating film interposed therebetween is referred to as GO.
A low concentration impurity region (n ⁻ region) that does not overlap with the gate electrode is called an LD region. The width of the region (LDD region) that does not overlap with the gate electrode in the channel direction can be freely set by appropriately changing the mask used in the second doping process. If the conditions of the first doping process are changed so that an impurity element is added below the tapered portion, the n-channel TFT 40
8, 409 can have a structure including both a region (GOLD region) overlapping the gate electrode and a region (LDD region) not overlapping the gate electrode.

[Embodiment 2] In this embodiment, an example in which a semiconductor layer is formed in a step different from that of Embodiment 1 is shown in FIG.

First, a base insulating film 501, an amorphous semiconductor film 502, and a metal-containing layer 503 are sequentially formed on a substrate 500 in the same manner as in the first embodiment. (FIG. 10A) Next, crystallization is performed in the same manner as in Example 1 to form a semiconductor film 504 having a crystal structure. (FIG. 10B)

Next, after forming an insulating film mainly containing silicon, a mask 505 made of a resist is formed. Next, a mask 506 is formed by wet etching using the mask 505. (FIG. 10C) The end of the mask 505 is tapered, and the end of the mask 506 made of an insulating film containing silicon as a main component is formed inside the end of the mask 505 by this wet etching. I do. This mask 506 is used when patterning the crystalline semiconductor film. Then
A rare gas element is added to the semiconductor film by an ion doping method or an ion implantation method, but is added only to a region which does not overlap with the mask 505, so that a gettering site 507 is formed. (FIG. 10D) Also, as shown in FIG. 10D, the space between the mask 506 and the gettering site 507 is left. It is important to keep this interval when gettering is performed later.

Further, the thickness of the masks 505 and 506 may be reduced, and a rare gas element may be added to a region overlapping with the mask 505.

Next, after removing the resist mask 505, a heat treatment is performed to perform gettering. The metal element contained in the film by this heat treatment is shown in FIG.
Move in the direction of the arrow inside. By this gettering, metal elements in the semiconductor film having a crystal structure covered with the mask 506 are removed or reduced.

Next, a small amount of a rare gas element is added again to the semiconductor film through the mask 506. By adding the second rare gas element, at least the channel formation region contains the rare gas element. Here, the addition of the second rare gas element is performed after gettering. However, the addition of the second rare gas element is performed after patterning the semiconductor layer in a later step or after forming a gate insulating film to be formed later. May go. Note that a small amount of impurity element (boron or phosphorus) may be appropriately doped (also referred to as channel doping) to control the threshold value of the TFT. Further, at the time of this channel doping, a rare gas element may be added to the semiconductor layer.

Next, the semiconductor film having a crystal structure is patterned into a desired shape using the mask 506 to form a semiconductor layer 508. (FIG. 10F) At the time of this patterning, the semiconductor film having a crystal structure near the boundary with the gettering site is also removed at the same time as the gettering site 507 is removed. At the time of gettering in this embodiment, the metal element segregates at the gettering site, but tends to segregate particularly at the boundary of the gettering site. Therefore, it is very effective that the space between the gettering site and the mask 506 is wide as in this embodiment.

Next, after the surface of the semiconductor layer is washed with an etchant containing hydrofluoric acid, an insulating film containing silicon as a main component to be a gate insulating film 509 is formed. It is desirable that the surface cleaning and the formation of the gate insulating film be performed continuously without exposure to the air.

Next, after cleaning the surface of the gate insulating film,
A gate electrode 510 is formed, and an impurity element for imparting n-type to a semiconductor, here, phosphorus is appropriately added to form a source region 5.
11 and a drain region 512 are formed. After adding
Heat treatment, intense light irradiation,
Alternatively, laser light irradiation is performed. In addition, plasma damage to the gate insulating film and plasma damage to the interface between the gate insulating film and the semiconductor layer can be recovered simultaneously with the activation. In particular, it is very effective to activate the impurity element by irradiating the second harmonic of the YAG laser from the front surface or the back surface in an atmosphere at room temperature to 300 ° C.
A YAG laser is a preferred activation means because of its low maintenance.

In the subsequent steps, an interlayer insulating film 514 is formed, hydrogenation is performed, contact holes reaching the source region and the drain region are formed, and a source electrode 515 and a drain electrode 516 are formed to complete a TFT. .

The TFT thus obtained contains a rare gas element at least in the channel formation region 513.

[Embodiment 3] In this embodiment, an example in which a rare gas element is added by using a mask having a smaller opening than in Embodiment 2 is shown in FIG.

First, a base insulating film 601, an amorphous semiconductor film 602, and a metal-containing layer 603 are sequentially formed on a substrate 600 in the same manner as in the first embodiment. (FIG. 11A) Next, crystallization is performed in the same manner as in Example 1 to form a semiconductor film 604 having a crystal structure. (FIG. 11B)

Next, after forming an insulating film mainly containing silicon, a mask 605 made of a resist is formed. Next, a mask 606 is formed by etching using the mask 605. Next, a gettering site 607 is formed by selectively adding a rare gas element. (Figure 1
1 (C))

Next, after the mask 605 made of resist is removed, a heat treatment is performed to perform gettering. The metal element contained in the film by this heat treatment is shown in FIG.
Move in the direction of the arrow inside. By this gettering, metal elements in the semiconductor film having a crystal structure covered with the mask 606 are removed or reduced.

Next, after removing the mask 606, a mask 608 made of a resist is formed and a semiconductor film having a crystal structure is patterned to obtain a semiconductor layer 609. (FIG. 11E)

Next, the mask 608 is removed. Subsequent steps may follow the embodiment mode or the first embodiment.

[Embodiment 4] In this embodiment, an example in which crystallization is performed by a method different from that in Embodiment 1 is shown in FIG.

First, a base insulating film 701 and an amorphous semiconductor film 702 are formed on a substrate 700 as in the first embodiment. Next, an insulating film containing silicon as a main component is formed, and a mask 703 made of a resist is formed. Next, the mask 7
03 is used to selectively remove the insulating film to form a mask 704. (FIG. 12 (A))

Next, after removing the mask 703, a metal-containing layer 705 is formed. Here, a metal element is selectively added to the amorphous semiconductor film located in a region which is not covered with the mask 704.

Next, a semiconductor film 706 having a crystal structure is formed by heat treatment and crystallization. For this heat treatment, heat treatment in an electric furnace or irradiation with strong light may be used.
In the case of heat treatment in an electric furnace, the temperature is 500 ° C to 650 ° C.
It may be performed at 550 ° C. for 4 hours for 24 hours. Nickel diffuses in the direction indicated by the arrow in FIG. 12C and crystallization proceeds. By this heat treatment, the amorphous semiconductor film in contact with the mask 704 made of an insulating film is crystallized by the action of nickel.

Next, after removing the mask 704, patterning is performed to obtain a semiconductor layer 707. Subsequent steps may follow the embodiment mode or the first embodiment.

This embodiment corresponds to the first embodiment or the second embodiment.
It is possible to combine with Note that it is also possible to combine with the third embodiment. When combined with the third embodiment, the mask used for adding the metal element and the mask used for adding the rare gas element can be the same.

[Embodiment 5] In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. FIG. 13 is used for the description.

First, according to the first embodiment, after obtaining the active matrix substrate in the state shown in FIG. 6, an alignment film is formed on the active matrix substrate shown in FIG. 6, and a rubbing process is performed. In this example, before forming the alignment film, an organic resin film such as an acrylic resin film was patterned to form a columnar spacer at a desired position for maintaining the distance between the substrates. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate is prepared. The opposite substrate is provided with a color filter in which a coloring layer and a light shielding layer are arranged corresponding to each pixel. Further, a light-shielding layer was provided also in a portion of the driving circuit. A flattening film was provided to cover the color filter and the light shielding layer. Next, a counter electrode made of a transparent conductive film was formed in the pixel portion on the flattening film, an alignment film was formed on the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are bonded with a sealant. A filler is mixed in the sealing material, and the two substrates are bonded together at a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material is injected between the two substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, an active matrix type liquid crystal display device is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, a polarizing plate and the like were appropriately provided using a known technique. Then, an FPC was attached using a known technique.

The configuration of the liquid crystal module thus obtained will be described with reference to the top view of FIG. In addition, the same code | symbol was used for the part corresponding to FIG.

A top view shown in FIG. 13 shows a pixel portion, a driving circuit, and an FPC (Flexible Printed Wiring Board: Flexible P.C.).
rinted circuit) 811 to attach external input terminal 80
9, an active matrix substrate on which a wiring 810 connecting the external input terminal to the input portion of each circuit is formed;
An opposing substrate 800 provided with a color filter and the like is attached to each other with a sealant 807 interposed therebetween.

A light-shielding layer 803a is provided on the counter substrate side so as to overlap with the gate wiring side driving circuit 401a, and a light-shielding layer 803b is formed on the counter substrate side so as to overlap with the source wiring side driving circuit 401b. In the color filter 802 provided on the counter substrate side over the pixel portion 402, a light-shielding layer and colored layers of red (R), green (G), and blue (B) are provided for each pixel. Have been. When actually displaying, a red (R) colored layer, a green (G) colored layer,
A color display is formed by three colors of a blue (B) colored layer.
The arrangement of the colored layers of these colors is arbitrary.

Here, the color filter 802 is provided on the opposite substrate in order to achieve colorization. However, the present invention is not particularly limited. When an active matrix substrate is manufactured, a color filter may be formed on the active matrix substrate.

Further, a light-shielding layer is provided between adjacent pixels in the color filter so as to shield a portion other than the display area from light. Here, the light-blocking layers 803a and 803b are provided also in a region covering the driving circuit. However, the region covering the driving circuit is covered with a cover when the liquid crystal display device is later incorporated as a display portion of an electronic device. A structure without a light-blocking layer may be employed. When an active matrix substrate is manufactured, a light-blocking layer may be formed on the active matrix substrate.

Further, without providing the light-shielding layer, a colored layer constituting a color filter is appropriately arranged between the opposing substrate and the opposing electrode so as to shield the light by a stacked layer of a plurality of layers, and a portion other than the display area ( The gap between each pixel electrode) and the driving circuit may be shielded from light.

Further, an FPC 811 comprising a base film and wiring is bonded to the external input terminal with an anisotropic conductive resin. Furthermore, the mechanical strength is enhanced by the reinforcing plate.

The liquid crystal module manufactured as described above can be used as a display unit of various electronic devices.

This embodiment can be freely combined with any one of Embodiments 1 to 4.

[Embodiment 6] In the embodiment 1, the example of the reflection type display device in which the pixel electrode is formed of a reflective metal material is shown. In the present embodiment, the pixel electrode is formed of a conductive material having translucency. An example of a transmission type display device formed of a film is shown.

Example 1 up to the step of forming an interlayer insulating film
Therefore, the description is omitted here. After forming an interlayer insulating film according to the first embodiment, a pixel electrode made of a light-transmitting conductive film is formed. As the light-transmitting conductive film, ITO (indium tin oxide alloy), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like may be used.

Thereafter, a contact hole is formed in the interlayer insulating film. Next, a connection electrode overlapping with the pixel electrode is formed. This connection electrode is connected to the drain region through a contact hole. In addition, a source electrode or a drain electrode of another TFT is formed simultaneously with the connection electrode.

Although the example in which all the driving circuits are formed on the substrate is shown here, several ICs may be used as a part of the driving circuit.

An active matrix substrate is formed as described above. Using this active matrix substrate, a liquid crystal module is manufactured according to Embodiment 5, a backlight and a light guide plate are provided, and the cover is covered with a cover, whereby an active matrix type liquid crystal display device is completed. Note that the cover and the liquid crystal module are attached to each other using an adhesive or an organic resin. Further, when the substrate and the counter substrate are attached to each other, an organic resin may be filled between the frame and the substrate so as to be adhered. In addition, since it is a transmission type, the polarizing plate is attached to both the active matrix substrate and the counter substrate.

This embodiment can be freely combined with any one of Embodiments 1 to 4.

[Embodiment 7] In this embodiment, the EL (Electr
FIG. 14 shows an example of manufacturing a light-emitting display device provided with an (o Luminescence) element. The light emitting device is an organic light emitting device (O
ELD: Organic EL Display or Organic Light Emitting Diode (OLED: Organic Light Emitting)
Diode).

FIG. 14A is a top view showing the EL module, and FIG. 14B is a cross-sectional view of FIG. 14A taken along the line AA ′. A pixel portion 902 and a source-side driver circuit 90 are provided over a substrate 900 having an insulating surface (eg, a glass substrate, a crystallized glass substrate, or a plastic substrate).
1 and a gate-side drive circuit 903 are formed. These pixel units and drive circuits can be obtained according to the above embodiment. Reference numeral 918 denotes a sealant, and 919 denotes a protective film for blocking oxygen and moisture typified by a DLC film. The pixel portion and the drive circuit portion are covered with a sealant 918, and the sealant is covered with a protective film 919. ing. Further, it is sealed with a cover material 920 using an adhesive. In order to withstand deformation due to heat, external force, or the like, the cover material 920 is provided on the substrate 900.
It is desirable to use a material of the same material as that described above, for example, a glass substrate, and it is processed into a concave shape (depth 3 to 10 μm) shown in FIG. A concave part (depth: 50 to 200 μm) into which a desiccant 921 can be placed by further processing
It is desirable to form m). In addition, EL
In the case of manufacturing a module, after bonding the substrate and the cover material, the module may be cut using a CO ₂ laser or the like so that the end faces coincide.

Reference numeral 908 denotes wiring for transmitting signals input to the source-side driving circuit 901 and the gate-side driving circuit 903. Receive. Although only the FPC is shown here, this FPC has a printed wiring board (P
WB) may be attached. The light emitting device in this specification includes not only the light emitting device body but also an FPC
Alternatively, this also includes a state where the PWB is attached.

Next, the cross-sectional structure will be described with reference to FIG. An insulating film 910 is provided over a substrate 900, and a pixel portion 902 and a gate driver circuit 903 are formed over the insulating film 910. The pixel portion 902 is electrically connected to a current controlling TFT 911 and a drain thereof. And a plurality of pixels including the pixel electrode 912. The gate side driving circuit 903 is an n-channel TFT 91
3 combined with p-channel TFT 914
It is formed using an S circuit.

Here, the display driving method is as follows.
A time-division grayscale driving method, which is one of the line sequential driving methods, is used. Further, the video signal input to the source line may be an analog signal or a digital signal, and a driving circuit or the like may be appropriately designed in accordance with the video signal.

The TFTs (911, 913, 914)
) May be produced according to the above embodiment. Note that the present invention is not limited to the pixel structure illustrated in FIG. 14, and more than one pixel (two, three, or four or more)
And various circuits (such as a current mirror circuit) may be incorporated.

The pixel electrode 912 functions as an anode of the EL element. Further, banks 915 are provided at both ends of the pixel electrode 912.
Are formed, and an EL layer 916 and a cathode 917 of an EL element are formed on the pixel electrode 912.

As the EL layer 916, an EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, a low molecular organic EL material or a high molecular organic EL material may be used. Further, as the EL layer, a thin film made of a light-emitting material (singlet compound) that emits light (fluorescence) by singlet excitation or a thin film made of a light-emitting material that emits light (phosphorescence) by triplet excitation can be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

The cathode 917 also functions as a common wiring for all pixels, and is electrically connected to the FPC 909 via the connection wiring 908. Further, elements included in the pixel portion 902 and the gate driver circuit 903 are all covered with a cathode 917, a sealant 918, and a protective film 919.

It is preferable to use a material that is as transparent or translucent as possible to visible light as the sealant 918. Further, it is preferable that the sealant 918 be a material that does not transmit moisture or oxygen as much as possible.

After the light emitting element is completely covered with the sealing material 918, at least the DL as shown in FIG.
It is preferable to provide a protective film 919 made of a C film or the like on the surface (exposed surface) of the sealant 918. Further, a protective film may be provided on the entire surface including the back surface of the substrate. Here, care must be taken so that the protective film is not formed in a portion where the external input terminal (FPC) is provided. The protection film may be prevented from being formed by using a mask, or the protection film may be prevented from being formed by covering the external input terminal portion with a tape such as Teflon (registered trademark) used as a masking tape in a CVD apparatus. Is also good.

With the above structure, the EL element is sealed with the sealing material 9.
By enclosing the EL element 18 and the protective film, the EL element can be completely shut off from the outside, and it is possible to prevent a substance that accelerates the deterioration of the EL layer due to oxidation, such as moisture and oxygen, from entering from the outside. Therefore, a highly reliable light-emitting device can be obtained.

Further, the pixel electrode may be used as a cathode, and an organic compound layer and a light-transmitting anode may be stacked to emit light in a direction opposite to that of FIG. Further, the pixel electrode may be used as a cathode, and an EL layer and an anode may be stacked to emit light in a direction opposite to that in FIG. FIG. 15 shows an example. In addition,
Since the top views are the same, they are omitted.

The sectional structure shown in FIG. 15 will be described below. As the substrate 1000, a semiconductor substrate or a metal substrate can be used in addition to a glass substrate or a quartz substrate. An insulating film 1010 is provided over the substrate 1000;
A pixel portion 1002 and a gate-side driver circuit 1003 are formed over the insulating film 1010. The pixel portion 1002 is formed by a plurality of pixels including a current control TFT 1011 and a pixel electrode 1012 electrically connected to a drain thereof. Is done. The gate side driver circuit 1003 is formed using a CMOS circuit in which an n-channel TFT 1013 and a p-channel TFT 1014 are combined.

The pixel electrode 1012 functions as a cathode of the EL element. Bank 1 is provided at both ends of the pixel electrode 1012.
015 is formed, and the EL layer 10 is formed on the pixel electrode 1012.
16 and an anode 1017 of the EL element are formed.

The anode 1017 also functions as a wiring common to all pixels, and is connected to the FPC 1009 via the connection wiring 1008.
Is electrically connected to Further, the elements included in the pixel portion 1002 and the gate side driver circuit 1003 are all covered with an anode 1017, a sealant 1018, and a protective film 1019 made of DLC or the like. Also, the cover material 1020
And the substrate 1000 were bonded with an adhesive. Further, a concave portion is provided in the cover material, and a desiccant 1021 is provided.

It is preferable to use a material that is as transparent or translucent as possible to visible light as the sealant 1018. It is preferable that the sealant 1018 be a material that does not transmit moisture or oxygen as much as possible.

In FIG. 15, the pixel electrode is a cathode,
Since the EL layer and the anode are stacked, the light emission direction is the direction of the arrow shown in FIG.

This embodiment can be combined with any one of Embodiments 1 to 6.

[Embodiment 8] A drive circuit and a pixel portion formed by carrying out the present invention are composed of various modules (an active matrix type liquid crystal module, an active matrix type EL device).
Module, active matrix EC module)
Can be used. That is, by implementing the present invention, all electronic devices incorporating them are completed.

Examples of such electronic devices include a video camera, a digital camera, a head-mounted display (goggle type display), a car navigation, a projector, a car stereo, a personal computer, a portable information terminal (a mobile computer, a mobile phone, an electronic book, etc.). ). Examples of those are shown in FIGS.

FIG. 16A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like.

FIG. 16B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on.

FIG. 16C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like.

FIG. 16D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on.

FIG. 16E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games and the Internet.

FIG. 16F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like.

FIG. 17A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention is applied to the liquid crystal module 2808 which forms a part of the projection device 2601, and the entire device can be completed.

FIG. 17B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The entire device can be completed by applying the present invention to the liquid crystal module 2808 which constitutes a part of the device 702.

FIG. 17C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 17A and 17B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal module 2808, retardation plate 280
9, the projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in an optical path indicated by an arrow in FIG. Good.

FIG. 17D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 17C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 17D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 17, a case in which a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and an EL module are not shown.

FIG. 18A shows a mobile phone, and the main body 29 is shown.
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 290
6. Image input unit (CCD, image sensor, etc.) 2907
And so on.

FIG. 18B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on.

FIG. 18C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. In addition, the electronic apparatus of the present embodiment includes
6 can be realized by using any combination of configurations.

[0164]

According to the present invention, the electric characteristics are good,
In addition, a TFT with less variation can be obtained.

[Brief description of the drawings]

FIG. 1 shows the present invention.

FIG. 2 illustrates a manufacturing process of the present invention.

FIG. 3 is a diagram showing a concentration profile.

FIG. 4 is a view showing a manufacturing process of an AM-LCD.

FIG. 5 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 6 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 7 is a graph showing acceleration voltage dependency.

FIG. 8 is a diagram showing a concentration profile of argon.

FIG. 9 is a view showing a concentration profile of nickel.

FIG. 10 illustrates a manufacturing process of the present invention.

FIG. 11 illustrates a manufacturing process of the present invention.

FIG. 12 illustrates a manufacturing process of the present invention.

FIG. 13 is a diagram illustrating an appearance of a liquid crystal module.

FIG. 14 is a diagram showing an upper surface and a cross section of an EL module.

FIG. 15 is a diagram showing a cross section of an EL module.

FIG. 16 illustrates an example of an electronic device.

FIG. 17 illustrates an example of an electronic device.

FIG. 18 illustrates an example of an electronic device.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 627Z (72) Inventor Shunpei 398 Hase, Atsugi-shi, Kanagawa Pref. (72) Inventor Hideaki Kuwahara 398 Hase, Atsugi-shi, Kanagawa F-term in Semiconductor Energy Laboratory Co., Ltd. AA11 AA17 AA24 BA02 BB03 BB07 DA02 DA03 DB02 DB03 DB07 EA16 FA06 FA19 HA06 JA01 5F110 AA30 BB02 BB04 CC02 CC05 CC07 DD01 DD02 DD03 DD13 DD14 DD15 DD17 EE01 EE02 EE03 EE04 EE06 EE09 EE14 FF23 GG19 GG33 GG34 GG36 GG43 GG45 GG47 GG51 GG52 HJ01 HJ04 HJ12 HJ18 HJ23 HL02 HL03 HL07 HL11 H M13 HM15 NN03 NN04 NN24 NN27 NN34 NN35 NN72 PP01 PP02 PP03 PP04 PP05 PP06 PP10 PP29 PP34 PP35 QQ04 QQ11 QQ23 QQ25 QQ28

Claims (19)

[Claims] 1. A semiconductor device having a semiconductor layer having a crystal structure on an insulating surface, wherein the semiconductor layer has a source region, a drain region, and a channel formation region, and the channel formation region is a rare gas element. And a concentration gradient. 2. A semiconductor device having a semiconductor layer having a crystal structure on an insulating surface, wherein the semiconductor layer has a source region, a drain region, and a channel formation region. A semiconductor device having a region containing a rare gas element between the semiconductor devices. 3. A first semiconductor layer having a crystal structure on an insulating surface, a second semiconductor layer in contact with the first semiconductor layer,
A semiconductor device having an insulating film in contact with the second semiconductor layer and an electrode in contact with the insulating film, wherein the second semiconductor layer contains a rare gas element. 4. The semiconductor device according to claim 3, wherein said second semiconductor layer has a crystal structure. 5. The semiconductor device according to claim 3, wherein said second semiconductor layer has an amorphous structure. 6. The rare gas element is He, Ne, Ar, K
The semiconductor device according to claim 1, wherein the semiconductor device is one or more selected from r and Xe. 7. The semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal module. 8. The semiconductor device according to claim 1, wherein the semiconductor device is an EL module. 9. A semiconductor device according to claim 1, wherein the semiconductor device is a video camera, a digital camera, a projector, a goggle type display, a car navigation, a personal computer, a portable information terminal, or an electronic game machine. A semiconductor device, characterized in that: 10. A first step of adding a metal element to a first semiconductor film having an amorphous structure, and crystallizing the first semiconductor film to form a first semiconductor film having a crystalline structure. A second step, a third step of forming a barrier layer on a surface of the first semiconductor film having the crystal structure, a fourth step of forming a second semiconductor film on the barrier layer, A fifth step of adding a rare gas element to the semiconductor film of step (a), and removing or reducing the metal element in the first semiconductor film having a crystal structure by gettering the metal element to the second semiconductor film. A method for manufacturing a semiconductor device, comprising: a sixth step; and a seventh step of removing the second semiconductor film. 11. The method for manufacturing a semiconductor device according to claim 10, wherein in the fifth step, a rare gas element is also added to the first semiconductor film. 12. The method of manufacturing a semiconductor device according to claim 10, wherein in the fifth step, a region in which a rare gas element is selectively added is formed in a part of the first semiconductor film. 13. The method according to claim 10, wherein in the fifth step, a rare gas element is added to the first semiconductor film to form a layer containing the rare gas element. . 14. The method for manufacturing a semiconductor device according to claim 10, wherein said sixth step is a heat treatment. 15. The semiconductor device according to claim 10, wherein the sixth step is a process of irradiating the semiconductor film with strong light.
5. The method for manufacturing a semiconductor device according to any one of 4. 16. The semiconductor device according to claim 10, wherein the sixth step is a step of performing a heat treatment and irradiating the semiconductor film with strong light. Production method. 17. The light source according to claim 10, wherein the intense light is light emitted from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. A method for manufacturing a semiconductor device according to any one of the above. 18. The metal element may be Fe, Ni, Co, R
18. The method for manufacturing a semiconductor device according to claim 10, wherein the method is one or more selected from u, Rh, Pd, Os, Ir, Pt, Cu, and Au. 19. The rare gas element is He, Ne, Ar, K
19. The method for manufacturing a semiconductor device according to claim 10, wherein the method is one or more selected from r and Xe.