JP2002305202A - Silicon epitaxial wafer, and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon epitaxial layer where the haze of an epitaxial layer and the defect level of LPD, etc., are reduced and also oxygen precipitation is controlled under the condition that it be put into a temperature-lowered and time-shortened device process, and to provide its manufacturing method. SOLUTION: The manufacturing method for the silicon epitaxial wafer and the epitaxial wafer manufactured by this method are provided in the manufacturing method for the silicon epitaxial wafer where an epitaxial layer is made on the surface of the silicon wafer, obtained by slicing a silicon single crystal, epitaxial growth is performed, after removal of at least a layer distorted in processing which has arisen in slicing of a silicon single-crystal ingot, and next heat treatment for oxygen precipitation is performed, and then the surface of the epitaxial layer is polished into a mirror-surface face.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a silicon epitaxial wafer and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the recent increase in the degree of integration of semiconductor elements, the device process has been reduced in temperature and time. Furthermore, in the near future silicon wafer era of 300 mm in diameter, a low-temperature and short-time device process is indispensable in order to suppress the occurrence of slip dislocation due to the weight of the wafer. Then, the BMD (Bulk M
The gettering effect by the formation and growth of micro defects (internal minute defects due to oxygen precipitates) cannot be expected. Therefore, it is important to provide a gettering effect by increasing the BMD density by subjecting the wafer to an oxygen precipitation heat treatment in advance to feed the wafer to a low-temperature, short-time device process. If this processing is performed by a wafer maker, the merits of the device maker are extremely large.

In addition, with the recent increase in the degree of integration of semiconductor elements, it has become important to reduce crystal defects in semiconductor wafers, particularly crystal defects at and near the surface. Therefore, epitaxial wafers with few crystal defects (hereinafter, referred to as
Demand (sometimes abbreviated as epi wafer) is increasing year by year. Therefore, it is expected that the demand for the epi-wafer which has been subjected to the heat treatment for accelerating the oxygen precipitation is expected to increase. However, conventionally, the epi-wafer has been manufactured, for example, according to the flow shown in FIG.

That is, for example, a silicon single crystal ingot pulled up by the CZ method is sliced (a) and then subjected to a chemical etching (b) step to perform a chemical etched wafer (hereinafter referred to as “Chemical Etched Wafer”).
CW), and mirror-polished (f) to give a mirror-polished wafer (Mirror Polishe).
d Wafer (hereinafter sometimes abbreviated as PW), an oxygen precipitation heat treatment (d) (hereinafter sometimes abbreviated as HT) is performed, and finally, epitaxial growth (c) is performed.
(Epitaxial Growth, hereinafter sometimes abbreviated as EP), to produce a silicon epitaxial wafer.

However, when an epitaxial wafer is manufactured in accordance with this process sequence, defects are induced in the wafer in the oxygen precipitation heat treatment process, and an epitaxial layer (hereinafter, sometimes referred to as an epi layer) grown thereon.
, Causing an epi-layer defect. In particular, when nitrogen is doped into a crystal, minute oxygen precipitates are formed at a high density (for example, Spring 1999, The 46th Joint Lecture Meeting on Applied Physics, Proceedings No. 1, p. 46).
9, 29a-ZB-5, Aihara et al.), Which is advantageous for gettering by the formation and growth of BMD, but the problem of this epi layer defect has been increasing.

In order to avoid this epi-layer defect, CW →
A process order of PW → EP → HT can be considered, but by performing a heat treatment after the EP process, surface haze (a surface state that looks whitish when the wafer surface is irradiated with a condensing lamp) or LPD (Light Point Defec) is obtained.
(t, collective term for defects by light scattering method) In some cases, this step has not been positively adopted because the level may be deteriorated.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of such problems as haze of an epi layer, LPD, etc. before being put into a low-temperature and short-time device process. It is a primary object of the present invention to provide a silicon epitaxial wafer having a reduced defect level and controlled oxygen precipitation.

[0008]

In order to solve the above-mentioned problems, a method of manufacturing a silicon epitaxial wafer according to the present invention is directed to a method of forming an epitaxial layer on a surface of a silicon wafer obtained by slicing a silicon single crystal. In the manufacturing method, epitaxial growth is performed after removing a processing strain layer generated at least when slicing a silicon single crystal ingot,
Next, an oxygen precipitation heat treatment is performed, and thereafter, the surface of the epitaxial layer is mirror-polished (claim 1).

If an epitaxial wafer is manufactured in accordance with such a process sequence, oxygen epitaxy heat treatment is performed after an epitaxial layer is grown on the wafer surface, so that defects in the substrate induced by the heat treatment do not occur in the epi layer. That is, even if a defect occurs in the silicon wafer as the substrate due to the heat treatment, the defect does not propagate to the device active layer or the epilayer surface. Therefore, an epi wafer having few epi layer defects can be obtained. In addition, when a high-resistance substrate is mainly used, it is necessary to perform an oxygen donor killer heat treatment on the substrate in order to achieve a substrate resistivity as designed, but this can be included in the oxygen precipitation heat treatment. Thus, productivity can be improved and costs can be reduced. Of course E
Needless to say, a donor killer heat treatment may be performed before the P step. Further, as a final step, P
Haze deteriorated by oxygen precipitation heat treatment to perform W process,
Since the LPD level is improved to the same level as the mirror-polished wafer, there is no need to worry about haze after heat treatment for oxygen precipitation and deterioration of LPD. Therefore, the haze of the epi layer, LPD
And other defects can be reduced, and a high-quality silicon epitaxial wafer with controlled oxygen precipitation can be manufactured.

In this case, it is preferable to remove the work strain layer by chemical etching. Since the PW process is performed as the final process, the substrate on which the EP process is performed only needs to remove the work-strained layer.

Further, in this case, the silicon single crystal to be sliced can be a nitrogen-doped silicon single crystal. If the oxygen precipitation heat treatment is performed after the EP process according to the above-described process sequence using the silicon single crystal doped with nitrogen as the substrate, no defect occurs in the epi layer because the surface is already an epi layer. That is, even if a defect occurs in the substrate, this does not propagate to the device active layer or the epi layer surface, and as a result, an epi wafer having extremely few epi layer defects and a sufficient BMD density can be obtained. .

According to the present invention, there is provided a high-quality silicon epitaxial wafer in which defects such as haze and LPD of an epitaxial layer manufactured by the above-described manufacturing method are reduced and oxygen deposition is controlled. 4).

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto. FIG. 1 is a flowchart showing an outline of one embodiment of a method for manufacturing a silicon epitaxial wafer according to the present invention. In FIG. 1, first, a pulled silicon single crystal ingot is sliced (a), and at least a processing strain layer generated at the time of slicing is removed by chemical etching (b), and then epitaxial growth (c) is performed. In this step, a heat treatment (d) is performed, and then the surface of the epitaxial layer is mirror-polished (e).

Hereinafter, the above steps will be described in more detail. First, a silicon single crystal is pulled up, a single crystal ingot is sliced, and lapping, chamfering around a wafer, etching, and the like are performed to remove processing strain generated at this time. Any of these methods may be according to the prior art,
For example, for pulling a single crystal, CZ method, MCZ method, ECZ method,
Any method such as the EMCZ method and the FZ method may be used.

The addition of impurities such as phosphorus, boron, arsenic, nitrogen and carbon to the single crystal is not particularly limited. When adding these dopants, the doping concentration may be set according to the user's specifications.However, when using a high-resistance substrate as described above, the essential donor killer heat treatment may be performed together with the oxygen precipitation heat treatment. Accordingly, productivity can be improved and cost can be reduced by omitting the donor killer heat treatment step. For this reason, it is even more effective if the present invention is applied to the manufacture of an epi-wafer using a high-resistance substrate.

Although the diameter of the substrate to be used is also arbitrary,
In the case of using a wafer having a large diameter of 12 mm (12 mm) or more, the device process is performed at a low temperature and in a short time in order to increase the degree of integration of semiconductor elements and to suppress the occurrence of slip dislocation due to the weight of the wafer. For this reason, the gettering effect due to the formation and growth of the BMD during the conventional device process cannot be expected, so that the effect of the present invention is remarkably obtained.

The slice (a) of the silicon single crystal ingot may be sliced by any known method using an inner peripheral blade, an outer peripheral blade, a wire saw, or the like. The chamfering may be a conventional chamfering process using a diamond grindstone, or may be a mirror chamfering process suitable for reducing dust generation from the chamfered portion. For lapping, a conventional technique of grinding by flowing a lap liquid between parallel platens is applied, or a surface grinder may be used.

The purpose of the etching (b) is to remove a work-strained layer generated when a machining process such as slicing, lapping, or chamfering is performed, and can be completely removed by chemical etching. As this etching solution, an acid etching solution obtained by diluting a mixed acid composed of hydrofluoric acid, nitric acid, and acetic acid with water is used. Further, the etching may be performed by alkali etching using NaOH, KOH, or the like, or may be used in combination with acid etching.

Next, an epitaxial layer is deposited and grown (c). The EP process may be performed by a conventional method, and is not limited to the presence or absence of hydrogen baking or HCl etching performed before epitaxial growth. Further, the epitaxial growth is not limited to normal pressure, reduced pressure growth, or the like, and the epi reactor is not limited to a batch type, a single wafer type, or the like. The source gas is also SiCl ₄ , SiHCl ₃ , SiH ₂ Cl ₂ , Si
All commonly used materials such as H ₄ can be used. Note that the thickness of the epi layer needs to be “user specification + thickness polished in the PW process”.

Thereafter, an oxygen precipitation heat treatment (d) is performed. This oxygen precipitation heat treatment is a heat treatment for controlling oxygen precipitation,
For example, it is common to use a two-step heat treatment such as a heat treatment for forming oxygen precipitate nuclei at 450 to 800 ° C. and a heat treatment for growing oxygen precipitates at 800 ° C. or higher.
It is not limited to this. The oxygen precipitation heat treatment may include a donor killer heat treatment. Then, in the case of a high resistance substrate, it is not necessary to perform the donor killer heat treatment before the EP process. Further, the oxygen precipitation heat treatment conditions may be set to be suitable for them in consideration of the BMD size and density required by the user. As the heat treatment apparatus, a conventional apparatus may be used. A batch type furnace using resistance heating, a single-wafer type rapid heating / rapid cooling apparatus: R
TA (Rapid Thermal Anneale)
r) and the like are common, but not limited to these.

If the oxygen precipitation heat treatment is performed after the EP process, as described above, regardless of the presence or absence of nitrogen doping,
Since the surface is already an epi layer, no defect occurs in the epi layer. That is, even if a defect occurs in the substrate, it does not propagate to the device active layer or the epi layer surface. After the HT process, mirror polishing (e) of the epitaxial layer surface is performed. This can also be done according to the conventional method,
As described above, since the mirror polishing process of the epi layer surface is performed after the EP process, the surface quality such as flatness, microroughness, and haze is equal to that of the mirror wafer,
The surface quality of the epi wafer is further improved. Also,
There is also an effect that the LPD level and the crown (those in which silicon has abnormally grown around the wafer in the EP process) can be simultaneously improved by polishing the epilayer surface.

[0022]

EXAMPLES Hereinafter, the present invention will be described specifically with reference to Examples and Comparative Examples of the present invention, but the present invention is not limited to these. (Example 1) Diameter 200 mm (8 inches), boron added, resistivity 0.01 Ω · cm, initial oxygen concentration 16 ppm
a [JEIDA (Japan Electronicic
Industry Development and
Association: using the conversion factor of the Japan Electronics Industry Promotion Association)], the crystal was pulled up by the CZ method, sliced with a wire saw, wrapped, mirror-polished, and chemically etched with a mixed acid solution of hydrofluoric acid, nitric acid and acetic acid. . Thereafter, an epilayer (boron addition, resistivity 10 Ω · cm) is formed on the chemically etched surface at 1130 ° C. to a thickness of 22 μm.
Deposited. Then, 800 ° C./4Hr+1000° C./1
After an oxygen precipitation heat treatment of 6 hr, a mirror polishing step of the epi layer surface was performed.

In order to determine the polishing allowance at this time, a dummy wafer with boron addition and a resistivity of 10 Ω · cm was prepared.
The same polishing as above was performed. Capacitance type non-contact thickness gauge C
From the difference in wafer thickness before and after polishing measured by L-250 (manufactured by Ono Sokki Co., Ltd.), the polishing allowance this time was estimated to be 12 μm. Also, the epi-layer thickness on a wafer having a resistivity of 0.01 Ω · cm was determined by measuring the epi-layer thickness by FT-IR (Fourier transform infrared spectroscopy) (measuring device: OS-300, manufactured by Accent Optical Technologies). The thickness was 10 μm, and it was confirmed that the epi layer was sufficiently left.

Light scattering type particle counter: SP-
In the measurement of the surface of the epilayer using No. 1 (manufactured by KLA Tencor), the number of LPDs (size 0.09 μm or more) was 0 / wafer. The haze due to SP-1 was 0.07 on average.
6 ppm (Narrow mode), which is the same level as a normal mirror-surface wafer. In addition, a capacitance type flatness measuring device: Ultrascan 9650 (ADE)
The flatness is measured with the
When the average of 0 wafers, SFQR (Site
Front least sQares <site>
(Range) was 0.20 μm (20 mm × 20 mm site), which was equivalent to that of a normal mirror-polished wafer.

(Example 2) 300 mm (12 inches) in diameter, boron added, resistivity 10 Ω · cm, initial oxygen concentration 16 ppma-JEIDA, nitrogen concentration 4 × 10 ¹³ / cm
Crystal ³ was pulled up by the MCZ method, sliced with a wire saw, wrapped, chamfered, and chemically etched with an aqueous sodium hydroxide solution. afterwards,
On the chemically etched surface, an epilayer (boron addition, resistivity: 10 Ω · cm) was deposited at 22 ° C. at 1130 ° C. Next, after performing a heat treatment of 800 ° C./4Hr+1000° C./16Hr (also serving as a donor killer heat treatment by rapid cooling), double-side polishing / flattening polishing and mirror-surface chamfering were performed. From the polishing allowance in each of the double-side polishing and the flattening polishing, the polishing allowance on the front side was estimated to be 12 μm. From the difference between the wafer thickness before the EP step measured by the non-contact thickness gauge CL-250 and the wafer thickness after the epi layer mirror polishing step, the thickness of the epi layer deposited on the substrate was 10 μm.
Since it was estimated to be m, it was confirmed that the epi layer remained.

In the measurement with the particle counter: SP-1, the number of LPDs (size 0.09 μm or more) was 0 / wafer. The haze due to SP-1 was 0.1 on average.
049 ppm (Narrow mode), which is the same level as a normal mirror-polished wafer. In addition, a capacitance type flatness measuring device: AFS (Advanced)
Flatness System) -3220 (AD
E), the flatness was measured.
(Site Front least sQares <
The average value within the wafer plane (site> Division) was 0.036 μm (26 mm × 32 mm site), which was equivalent to that of a normal mirror-polished wafer.

(Comparative Example 1) A crystal having a diameter of 200 mm (8 inches), boron added, a resistivity of 0.01 Ω · cm, an initial oxygen concentration of 16 ppma-JEIDA was pulled up by the CZ method, sliced with a wire saw, wrapped, and mirror-polished. Was performed, and chemical etching was performed using a mixed acid solution. Thereafter, a heat treatment of 800 ° C./4Hr+1000° C./16Hr is performed, mirror polishing is performed, and 1130 ° C.
To make the epi layer (boron addition, resistivity 10Ω · cm) 10μ
Thus, an epitaxial wafer was obtained.

When this epi-wafer was measured with a particle counter: SP-1, 62 LPDs / wafer (size 0.09 μm or more) were detected, and the haze was 0.324 ppm on average (Narrow mode).
Met. The flatness by Ultrascan 9650 was 0.24 μm in SFQR. All of these quality characteristics were clearly deteriorated as compared with Example 1.

(Comparative Example 2) A crystal having a diameter of 200 mm (8 inches), boron added, resistivity of 0.01 Ω · cm, initial oxygen concentration of 16 ppm-JEIDA was pulled up by the CZ method, sliced with a wire saw, wrapped, and mirror-polished. After performing chemical etching with a mixed acid solution, mirror finishing was performed. Thereafter, an epilayer (boron addition, resistivity 10 Ω · cm) of 10 μm was deposited at 1130 ° C. Then, 800 ° C./4Hr+1000° C./16Hr
Was subjected to an oxygen precipitation heat treatment.

When this epiwafer was measured with a particle counter: SP-1, 124 LPDs / wafer (size 0.09 μm or more) were detected, and the haze was 0.238 ppm (Narrow mode) on average. The flatness by Ultrascan 9650 was 0.22 μm in SFQR. All of these quality characteristics were clearly deteriorated as compared with Example 1.

Comparative Example 3 Diameter: 300 mm (12 inches), boron added, resistivity: 10 Ω · cm, initial oxygen concentration: 16 ppm-JEIDA, nitrogen concentration: 4 × 10 ¹³ / cm ³
Was pulled up by the MCZ method, sliced with a wire saw, wrapped and chamfered, and alkali-etched with an aqueous sodium hydroxide solution. afterwards,
After a heat treatment of 800 ° C./4Hr+1000° C./16Hr (also serving as a donor killer heat treatment by rapid cooling), double-side polishing, flattening polishing, and mirror chamfering were performed.
Then, at 1130 ° C., an epi layer (boron added, resistivity 10
Ω · cm) was deposited at 10 μm.

In the measurement using the particle counter SP-1 of the epi-wafer, 141 particles / L of the wafer were measured.
PD (size 0.09 μm or more) was detected, and the haze was 0.303 ppm (Narrow mode) on average. When the flatness was measured with a flatness measuring device ASF-3220, the SFQD was 0.045 μm.
m. All of these quality characteristics were clearly deteriorated as compared with Example 2.

(Comparative Example 4) Diameter 300 mm (12 inches), boron added, resistivity 10 Ω · cm, initial oxygen concentration 16 ppm-JEIDA, nitrogen concentration 4 × 10 ¹³ / cm ³
Was pulled up by the MCZ method, sliced with a wire saw, wrapped and chamfered, and alkali-etched with an aqueous sodium hydroxide solution. afterwards,
After performing double-side polishing, flattening polishing and mirror chamfering,
Epilayer at 130 ° C (boron added, resistivity 10Ω · cm)
Was deposited in a thickness of 10 μm. Then, at 800 ° C./4Hr+10
A heat treatment of 00 ° C./16 hr (also serving as a donor killer heat treatment by rapid cooling) was performed.

In the measurement using the particle counter SP-1 of the epi-wafer, 337 particles / L of the wafer were measured.
PD (size 0.09 μm or more) was detected, and the haze was 0.183 ppm (Narrow mode) on average. When the flatness was measured with a flatness measuring device: ASF-3220, the SFQD was 0.042.
μm. All of these quality characteristics were clearly deteriorated as compared with Example 2.

The present invention is not limited to the above embodiment. The above embodiment is an exemplification, and has substantially the same configuration as the technical idea described in the scope of the claims of the present invention. It is included in the technical scope of the invention.

For example, in the above embodiment, the diameter 2
00mm (8 inches) and 300mm (12 inches)
The case where an epitaxial wafer is produced from a silicon single crystal wafer described above has been described by way of example, but the present invention is not limited to this, and the diameter is 100 to 400 mm (4 to 1 mm).
6 inch) or larger silicon single crystals.

[0037]

As described above in detail, according to the present invention, the defect level such as haze and LPD is reduced in the epi layer before the device is put into a low-temperature, short-time device process. A silicon epitaxial wafer with controlled oxygen deposition can be provided.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an example of a manufacturing process of an epitaxial wafer of the present invention.

FIG. 2 is a flowchart showing an example of a conventional epitaxial wafer manufacturing process.

Claims (4)

[Claims] 1. A method for manufacturing a silicon epitaxial wafer in which an epitaxial layer is formed on the surface of a silicon wafer obtained by slicing a silicon single crystal, wherein at least a processing strain layer generated when slicing the silicon single crystal ingot is removed. A method for manufacturing a silicon epitaxial wafer, comprising performing epitaxial growth, then performing an oxygen precipitation heat treatment, and then mirror-polishing the surface of the epitaxial layer. 2. The method for manufacturing a silicon epitaxial wafer according to claim 1, wherein the removal of the processing strain layer is performed by chemical etching. 3. The method for producing a silicon epitaxial wafer according to claim 1, wherein the silicon single crystal to be sliced is a nitrogen-doped silicon single crystal. 4. A silicon epitaxial wafer manufactured by the manufacturing method according to claim 1.