JP2002241192A - Semiconductor crystal manufacturing method and semiconductor light emitting device - Google Patents
Semiconductor crystal manufacturing method and semiconductor light emitting deviceInfo
- Publication number
- JP2002241192A JP2002241192A JP2001036604A JP2001036604A JP2002241192A JP 2002241192 A JP2002241192 A JP 2002241192A JP 2001036604 A JP2001036604 A JP 2001036604A JP 2001036604 A JP2001036604 A JP 2001036604A JP 2002241192 A JP2002241192 A JP 2002241192A
- Authority
- JP
- Japan
- Prior art keywords
- crystal growth
- crystal
- semiconductor crystal
- substrate
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000013078 crystal Substances 0.000 title claims abstract description 153
- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 239000000758 substrate Substances 0.000 claims abstract description 175
- -1 nitride compound Chemical class 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 25
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 238000002109 crystal growth method Methods 0.000 claims description 12
- 238000000926 separation method Methods 0.000 claims description 11
- 150000001875 compounds Chemical class 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 239000002994 raw material Substances 0.000 claims description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 230000009471 action Effects 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 238000012993 chemical processing Methods 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 claims description 2
- 238000010894 electron beam technology Methods 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 230000002542 deteriorative effect Effects 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 230000035882 stress Effects 0.000 abstract description 41
- 239000012141 concentrate Substances 0.000 abstract description 4
- 230000006355 external stress Effects 0.000 abstract description 2
- 229910002601 GaN Inorganic materials 0.000 description 15
- 230000000694 effects Effects 0.000 description 12
- 229910002704 AlGaN Inorganic materials 0.000 description 8
- 239000007789 gas Substances 0.000 description 6
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000011575 calcium Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012634 fragment Substances 0.000 description 2
- AMWRITDGCCNYAT-UHFFFAOYSA-L hydroxy(oxo)manganese;manganese Chemical compound [Mn].O[Mn]=O.O[Mn]=O AMWRITDGCCNYAT-UHFFFAOYSA-L 0.000 description 2
- 230000031700 light absorption Effects 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000010008 shearing Methods 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910020068 MgAl Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 150000002902 organometallic compounds Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Led Devices (AREA)
Abstract
(57)【要約】
【課題】 転位の少ない高品質の半導体結晶を得る。
【解決手段】 多数の突起部を有する下地基板上に III
族窒化物系化合物より成る基板層(所望の半導体結晶)
を成長させた場合、突起部の大きさや配置間隔や結晶成
長諸条件等によっては、各突起部間に半導体結晶が積層
されていない空洞が形成される。このため、突起部の高
さに比して基板層の厚さを十分に大きくすれば、内部応
力または外部応力がこの突起部に集中的に作用し易くな
る。その結果、特にこれらの応力は、突起部に対する剪
断応力等として作用し、この応力が大きくなった時に、
突起部が破断する。従って、この応力を利用すれば、容
易に下地基板と基板層とを分離することが可能となり、
下地基板から独立した半導体結晶を得ることができる。
空洞が大きく形成される程、突起部に上記の応力が集中
し易くなり、下地基板と基板層とをより確実に分離する
ことができる。
(57) [Summary] [PROBLEMS] To obtain a high-quality semiconductor crystal with few dislocations. SOLUTION: On a base substrate having a large number of protrusions, III
Substrate layer made of group nitride compound (desired semiconductor crystal)
Is grown, a cavity in which no semiconductor crystal is stacked is formed between the projections depending on the size, arrangement interval, crystal growth conditions, and the like of the projections. For this reason, if the thickness of the substrate layer is made sufficiently large compared to the height of the projection, the internal stress or the external stress tends to concentrate on the projection. As a result, in particular, these stresses act as a shear stress or the like on the protrusion, and when this stress increases,
The protrusion breaks. Therefore, if this stress is utilized, it is possible to easily separate the base substrate and the substrate layer,
A semiconductor crystal independent from the base substrate can be obtained.
The larger the cavity is, the more the above-mentioned stress is likely to be concentrated on the protrusion, and the base substrate and the substrate layer can be more reliably separated.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、横方向結晶成長作
用を利用して、下地基板上に III族窒化物系化合物半導
体から成る基板層を形成することにより結晶成長基板を
得る、半導体結晶の製造方法に関する。BACKGROUND OF THE INVENTION The present invention relates to a semiconductor crystal for producing a crystal growth substrate by forming a substrate layer made of a group III nitride compound semiconductor on an underlying substrate by utilizing a lateral crystal growth effect. It relates to a manufacturing method.
【0002】[0002]
【従来の技術】図5に例示する様に、例えばシリコン
(Si)等から成る下地基板上に窒化ガリウム(Ga
N)等の窒化物半導体を結晶成長させ、その後常温まで
冷却すると、窒化物半導体層に転位やクラックが多数入
ることが一般に知られている。2. Description of the Related Art As illustrated in FIG. 5, gallium nitride (Ga) is formed on an underlying substrate made of, for example, silicon (Si).
It is generally known that when a nitride semiconductor such as N) is crystal-grown and then cooled to room temperature, a large number of dislocations and cracks enter the nitride semiconductor layer.
【0003】[0003]
【発明が解決しようとする課題】この様に、成長層(窒
化物半導体層)に転位やクラックが多数入ると、その上
にデバイスを作製した場合に、デバイス中に格子欠陥や
転位、変形、クラック等が多数生じる結果となり、デバ
イス特性の劣化を引き起こす原因となる。また、例えば
シリコン(Si)等から成る下地基板を除去し、成長層
のみを残して、独立した基板(結晶)を得ようとする場
合、上記の転位やクラック等の作用により、大面積(1
cm2 以上)のものが得られない。As described above, when a large number of dislocations and cracks enter the growth layer (nitride semiconductor layer), when a device is fabricated thereon, lattice defects, dislocations, deformation, As a result, many cracks and the like are generated, which causes deterioration of device characteristics. Further, when an independent substrate (crystal) is to be obtained by removing the underlying substrate made of, for example, silicon (Si) and leaving only the growth layer, a large area (1
cm 2 or more) cannot be obtained.
【0004】本発明は、上記の課題を解決するために成
されたものであり、その目的は、クラックが無く、転位
の密度が低い高品質の半導体結晶(結晶成長基板)を得
ることである。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a high-quality semiconductor crystal (crystal growth substrate) having no cracks and low dislocation density. .
【0005】[0005]
【課題を解決するための手段、並びに、作用及び発明の
効果】上記の課題を解決するためには、以下の手段が有
効である。即ち、第1の手段は、横方向結晶成長作用を
利用して下地基板上に III族窒化物系化合物半導体から
成る基板層を形成することにより下地基板から独立した
半導体結晶を得る製造工程において、下地基板上に多数
の突起部を形成する突起部形成工程と、この突起部の表
面の少なくとも一部を基板層が結晶成長を開始する最初
の成長面としてこの成長面が各々互いに連結されて少な
くとも一連の略平面に成長するまで基板層を結晶成長さ
せる結晶成長工程と、突起部を破断することにより基板
層と下地基板とを分離する分離工程とを設けることであ
る。Means for Solving the Problems, Functions and Effects of the Invention In order to solve the above-mentioned problems, the following means are effective. That is, the first means is a manufacturing step of obtaining a semiconductor crystal independent of the underlying substrate by forming a substrate layer made of a group III nitride compound semiconductor on the underlying substrate by utilizing a lateral crystal growth effect, A projecting portion forming step of forming a large number of projecting portions on the base substrate, and at least a part of the surface of the projecting portion is at least partially connected to each other as an initial growth surface on which the substrate layer starts crystal growth. A crystal growth step of growing the substrate layer until a series of substantially flat surfaces is formed, and a separation step of separating the substrate layer and the base substrate by breaking the projections are provided.
【0006】ただし、ここで言う「 III族窒化物系化合
物半導体」一般には、2元、3元、又は4元の「Alx
Gay In(1-x-y) N(0≦x≦1,0≦y≦1,0≦
x+y≦1)」成る一般式で表される任意の混晶比の半
導体が含まれ、更に、p型或いはn型の不純物が添加さ
れた半導体も、本明細書の「 III族窒化物系化合物半導
体」の範疇とする。また、上記の III族元素(Al,G
a,In)の内の一部をボロン(B)やタリウム(T
l)等で置換したり、或いは、窒素(N)の一部をリン
(P)、砒素(As)、アンチモン(Sb)、ビスマス
(Bi)等で置換したりした半導体等もまた、本明細書
の「 III族窒化物系化合物半導体」の範疇とする。ま
た、上記のp型の不純物としては、例えば、マグネシウ
ム(Mg)や、或いはカルシウム(Ca)等を添加する
ことができる。また、上記のn型の不純物としては、例
えば、シリコン(Si)や、硫黄(S)、セレン(S
e)、テルル(Te)、或いはゲルマニウム(Ge)等
を添加することができる。また、これらの不純物は、同
時に2元素以上を添加しても良いし、同時に両型(p型
とn型)を添加しても良い。However, the term "III-nitride compound semiconductor" as used herein generally refers to binary, ternary or quaternary "Al x
Ga y In (1-xy) N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦
x + y ≦ 1) ”, and a semiconductor to which a p-type or n-type impurity is added, and a semiconductor of any mixed crystal ratio represented by the general formula: Semiconductor ”. In addition, the above group III elements (Al, G
a, In) is partially converted to boron (B) or thallium (T).
1) or a semiconductor in which part of nitrogen (N) is replaced by phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), or the like. "Group III nitride-based compound semiconductor" in the book. As the p-type impurity, for example, magnesium (Mg) or calcium (Ca) can be added. Examples of the n-type impurities include silicon (Si), sulfur (S), and selenium (S
e), tellurium (Te), germanium (Ge), or the like can be added. In addition, two or more of these impurities may be added at the same time, or both types (p-type and n-type) may be added at the same time.
【0007】例えば、図1に例示する様に、多数の突起
部を有する下地基板上に III族窒化物系化合物より成る
基板層(半導体結晶)を成長させる場合、突起部の大き
さや配置間隔や結晶成長諸条件等を調整することによ
り、各突起部間(突起部の側方)に、半導体結晶が積層
されていない「空洞」が形成可能となる。このため、突
起部の高さに比して基板層の厚さを十分に大きくすれ
ば、内部応力または外部応力がこの突起部に集中的に作
用し易くなる。その結果、特にこれらの応力は、突起部
に対する剪断応力等として作用し、この応力が大きくな
った時に、突起部が破断する。従って、この応力を利用
すれば、容易に下地基板と基板層とを分離(剥離)する
ことが可能となる。この手段により、下地基板から独立
した結晶(基板層)を得ることができる。また、上記の
「空洞」が大きく形成される程、突起部に応力(剪断応
力)が集中し易くなる。For example, as shown in FIG. 1, when a substrate layer (semiconductor crystal) made of a group III nitride compound is grown on a base substrate having a large number of projections, the size of the projections, the spacing between the projections, By adjusting various conditions for crystal growth and the like, it is possible to form a “cavity” in which no semiconductor crystal is stacked between each projection (side of the projection). For this reason, if the thickness of the substrate layer is made sufficiently large compared to the height of the projection, the internal stress or the external stress tends to concentrate on the projection. As a result, particularly, these stresses act as a shear stress or the like on the projection, and when the stress increases, the projection is broken. Therefore, if this stress is utilized, it is possible to easily separate (peel) the base substrate and the substrate layer. By this means, a crystal (substrate layer) independent of the underlying substrate can be obtained. Also, as the above-mentioned “cavity” becomes larger, stress (shear stress) tends to concentrate on the protrusion.
【0008】また、例えば、図1からも分かる様に、上
記の様な突起部を形成することにより、下地基板と基板
層(又は、所望の半導体結晶層)との接触部位が狭く限
定されるため、両者の格子定数差に基づく歪が生じ難く
なり、「下地基板と基板層の間の格子定数差に基づく応
力」が緩和される。このため、基板層(所望の半導体結
晶)が結晶成長する際に、成長中の基板層に働く不要な
応力が抑制されて転位やクラックの発生密度が低減され
る。Further, as can be seen from FIG. 1, for example, by forming the above-mentioned projections, the contact portion between the base substrate and the substrate layer (or a desired semiconductor crystal layer) is narrowed and limited. Therefore, distortion based on the difference between the two lattice constants is less likely to occur, and "stress based on the difference between the lattice constants of the underlying substrate and the substrate layer" is reduced. Therefore, when the substrate layer (desired semiconductor crystal) grows, unnecessary stress acting on the growing substrate layer is suppressed, and the density of dislocations and cracks is reduced.
【0009】尚、下地基板と基板層とを分離(剥離)す
る際に、下地基板側に基板層の一部が残っても良いし、
或いは、基板層側に下地基板の一部(例:突起部の破断
残骸)が残っても良い。即ち、上記の分離工程は、これ
らの材料の一部の残骸を皆無とする様な各材料の完全な
分離を前提(必要条件)とするものではない。When the base substrate and the substrate layer are separated (peeled), a part of the substrate layer may remain on the base substrate side,
Alternatively, a part of the underlying substrate (eg, broken debris of the protrusion) may remain on the substrate layer side. That is, the above-mentioned separation step does not assume (completely require) complete separation of each material such that some of the debris of these materials is eliminated.
【0010】また、上記の課題を解決する第2の手段
は、これらの第1の手段において、基板層と下地基板と
を冷却または加熱することにより、基板層と下地基板と
の熱膨張係数差に基づく応力を発生させ、この応力を利
用して上記の突起部の破断を実施することである。この
手段によれば、上記の応力を容易に生成することが可能
となる。A second means for solving the above-mentioned problem is that in the first means, the substrate layer and the underlying substrate are cooled or heated to thereby obtain a difference in thermal expansion coefficient between the substrate layer and the underlying substrate. Is to generate a stress based on the above, and to use the stress to break the projection. According to this means, the above-mentioned stress can be easily generated.
【0011】また、第3の手段は、横方向結晶成長作用
を利用して下地基板上に III族窒化物系化合物半導体か
ら成る基板層を形成することにより半導体結晶を得る製
造工程において、下地基板上に多数の突起部を形成する
突起部形成工程と、この突起部の表面の少なくとも一部
を基板層が結晶成長を開始する最初の成長面としてこの
成長面が各々互いに連結されて少なくとも一連の略平面
に成長するまで基板層を結晶成長させる結晶成長工程と
を設け、この結晶成長工程において III族窒化物系化合
物半導体の原料供給量qを調整することにより、下地基
板の突起部間の谷部の少なくとも一部の露出領域におけ
る III族窒化物系化合物半導体の結晶成長速度aと、突
起部の頭頂部における結晶成長速度bとの差分(b−
a)を略最大値に制御することである。A third means is that, in a manufacturing process for obtaining a semiconductor crystal by forming a substrate layer made of a group III nitride compound semiconductor on an underlying substrate by utilizing a lateral crystal growth effect, A projecting portion forming step of forming a large number of projecting portions thereon, and at least a part of the surface of the projecting portion is connected to each other as an initial growth surface where the substrate layer starts crystal growth, and at least a series of Providing a crystal growth step of growing the substrate layer until the substrate layer grows to a substantially flat surface. In this crystal growth step, by adjusting the raw material supply amount q of the group III nitride-based compound semiconductor, the valley between the protrusions of the base substrate is adjusted. Difference between the crystal growth rate a of the group III nitride compound semiconductor in at least a part of the exposed area of the portion and the crystal growth rate b at the top of the protrusion (b−
a) is controlled to a substantially maximum value.
【0012】この手段によれば、突起部の頭頂部付近の
結晶成長速度が相対的に大きくなり、上記の露出領域付
近の結晶成長は比較的抑制されて、頭頂部付近からの結
晶成長が支配的となる。この結果、突起部の頭頂部付近
から開始される基板層の横方向成長(ELO)が顕著と
なり、基板層の結晶成長時に基板層に働く「下地基板と
基板層の間の格子定数差に基づく応力」が緩和される。
従って、基板層の結晶構造が安定し、基板層に転位やク
ラックが発生し難くなる。また、基板層の横方向成長
(ELO)が顕著となれば、例えば、突起部の側方(各
突起部間)に比較的大きな空洞ができる場合もある。According to this means, the crystal growth rate in the vicinity of the top of the projection becomes relatively high, and the crystal growth in the vicinity of the above-mentioned exposed region is relatively suppressed, and the crystal growth from the vicinity of the top is dominant. Become a target. As a result, the lateral growth (ELO) of the substrate layer starting from near the top of the protrusion becomes remarkable, and acts on the substrate layer during the crystal growth of the substrate layer based on “difference in lattice constant between the underlying substrate and the substrate layer”. Stress ”is relieved.
Therefore, the crystal structure of the substrate layer is stabilized, and dislocations and cracks are less likely to occur in the substrate layer. If the lateral growth (ELO) of the substrate layer becomes remarkable, for example, a relatively large cavity may be formed on the side of the projection (between the projections).
【0013】例えば、図1に例示する様に、適当な大き
さ、間隔、或いは周期で下地基板の表面上に凹凸を形成
した場合、一般に、下地基板の外周側壁付近の周辺部分
以外では、凸部(突起部)の上面付近に比べて、凹部
(谷部)の方が結晶材料の単位時間・単位面積当たりの
供給量は少なくなり易い。この傾向は、結晶材料のガス
流の流量、温度、方向等にも依存するが、これらの諸条
件を最適、或いは好適に制御することにより、上記の差
分(b−a)を略最大値に制御することが可能となる。For example, as shown in FIG. 1, when irregularities are formed on the surface of an undersubstrate at an appropriate size, interval, or period, in general, the projections are formed on the surface of the undersubstrate except for the peripheral portion near the outer peripheral side wall. The supply amount of the crystal material per unit time / unit area tends to be smaller in the concave portion (valley portion) than in the vicinity of the upper surface of the portion (projection portion). This tendency also depends on the flow rate, temperature, direction, etc. of the gas flow of the crystal material, but by controlling these conditions optimally or suitably, the above-mentioned difference (ba) becomes substantially the maximum value. It becomes possible to control.
【0014】また、第4の手段は、上記の第1または第
2の手段の結晶成長工程において、III族窒化物系化合
物半導体の原料供給量qを調整することにより、下地基
板の突起部間の谷部の少なくとも一部の露出領域におけ
る III族窒化物系化合物半導体の結晶成長速度aと、突
起部の頭頂部における結晶成長速度bとの差分(b−
a)を略最大値に制御することである。[0014] A fourth means is that, in the crystal growth step of the first or second means, the raw material supply amount q of the group III nitride-based compound semiconductor is adjusted so that the distance between the protruding portions of the base substrate is reduced. Difference between the crystal growth rate a of the group III nitride compound semiconductor in at least a part of the exposed region of the valley portion and the crystal growth rate b at the top of the protrusion (b−
a) is controlled to a substantially maximum value.
【0015】この場合にも、上記の手段と同様に、基板
層の結晶成長時に基板層に働く「下地基板と基板層の間
の格子定数差に基づく応力」が緩和され、基板層の結晶
構造が安定し、基板層に転位やクラックが発生し難くな
る。この作用・効果は、各突起部間(突起部の側方)に
空洞ができる程に横方向成長が顕著な場合に、比較的顕
著となる。また、突起部の側方(各突起部間)に空洞が
形成されれば、突起部に剪断応力が集中し易くなり、上
記の分離工程において下地基板と基板層とを剪断応力に
より分離し易くなる。この作用・効果は、各突起部間
(突起部の側方)の空洞が大きくなる程、顕著となる。In this case as well, the "stress based on the lattice constant difference between the underlying substrate and the substrate layer" acting on the substrate layer during the crystal growth of the substrate layer is relaxed, and the crystal structure of the substrate layer is reduced. And dislocations and cracks are less likely to occur in the substrate layer. This action and effect becomes relatively remarkable when the lateral growth is remarkable such that a cavity is formed between the projections (side of the projections). Further, if cavities are formed on the sides of the projections (between the projections), the shear stress is easily concentrated on the projections, and the base substrate and the substrate layer are easily separated by the shearing stress in the above separation step. Become. This action and effect becomes more remarkable as the cavity between the projections (side of the projection) becomes larger.
【0016】また、第5の手段は、上記の第3または第
4の手段において、上記の原料供給量qを1μmol /mi
n 以上、100μmol /min 以下とすることである。The fifth means is the same as the third or fourth means, wherein the raw material supply amount q is 1 μmol / mi.
n or more and 100 μmol / min or less.
【0017】より望ましくは、上記の原料供給量qは、
5μmol /min 以上、90μmol /min 以下が良い。更
に望ましい値としては、形成される突起部の大きさや
形、配置間隔等の下地基板の仕様や、供給原料の種類や
供給流方向、結晶成長法等の諸条件にも依るが、概ね1
0〜80μmol /min 程度が理想的である。この値は、
大き過ぎると上記の差分(b−a)を略最大値に制御す
ることが難しくなるので、各突起部間(突起部の側方)
に大きな空洞を形成することが難しくなる。従って、こ
の様な場合には、格子定数差に基づく結晶内の応力が比
較的緩和され難く、転位が発生する等、基板層の単結晶
の結晶性が劣化し易くなってしまい望ましくない。More preferably, the raw material supply amount q is:
The range is preferably from 5 μmol / min to 90 μmol / min. A more desirable value depends on the specifications of the underlying substrate, such as the size and shape of the projections to be formed, the arrangement interval, and the like, the type of the raw material, the direction of the supply flow, and various conditions such as the crystal growth method.
The ideal range is about 0 to 80 μmol / min. This value is
If the difference is too large, it is difficult to control the difference (ba) to a substantially maximum value.
It is difficult to form large cavities in the area. Therefore, in such a case, the stress in the crystal based on the lattice constant difference is relatively hard to be relaxed, and the crystallinity of the single crystal of the substrate layer tends to deteriorate, such as generation of dislocation, which is not desirable.
【0018】また、応力(剪断応力)により、下地基板
と基板層とを分離する際にも、突起部側方の空洞が無い
か或いはこの空洞が小さいと、突起部に応力が集中し難
くなり、突起部の破断が起り難くなってしまい望ましく
ない。一方、原料供給量qが小さ過ぎると、結晶成長時
間が掛かり過ぎて生産性の面で不利となり、望ましくな
い。Further, even when the base substrate and the substrate layer are separated due to stress (shear stress), if there is no cavity on the side of the projection or this cavity is small, stress is less likely to concentrate on the projection. In addition, it is difficult to break the projection, which is not desirable. On the other hand, if the raw material supply amount q is too small, it takes too much crystal growth time, which is disadvantageous in terms of productivity and is not desirable.
【0019】また、第6の手段は、上記の第1乃至第5
の何れか1つの手段において、下地基板の材料として、
シリコン(Si)または炭化シリコン(SiC)を用い
ることである。また、その他の下地基板の材料として
は、例えば、GaN,AlN,GaAs,InP,Ga
P,MgO,ZnO,MgAl2 O4 等が有用で、ま
た、サファイア、スピネル、酸化マンガン、酸化ガリウ
ムリチウム(LiGaO2 )、硫化モリブデン(Mo
S)等も使用可能である。ただし、熱膨張係数差に基づ
く剪断応力を用いて下地基板と基板層とを分離する場合
には、両材料間の熱膨張係数差が小さくならない組み合
わせを選択することが望ましく、また、下地基板側に
は、破断が起り易い材料を選択することが望ましい。Further, the sixth means includes the first to fifth means.
In any one of the means,
Using silicon (Si) or silicon carbide (SiC). Other materials for the underlying substrate include, for example, GaN, AlN, GaAs, InP, Ga
P, MgO, ZnO, MgAl 2 O 4 and the like are useful, and sapphire, spinel, manganese oxide, lithium gallium oxide (LiGaO 2 ), molybdenum sulfide (Mo)
S) can also be used. However, when separating the base substrate and the substrate layer using shear stress based on the difference in thermal expansion coefficient, it is desirable to select a combination that does not reduce the difference in thermal expansion coefficient between both materials. It is desirable to select a material that easily breaks.
【0020】また、第7の手段は、上記の第1乃至第6
の何れか1つの手段において、下地基板の材料としてS
i(111)を用い、突起部形成工程において下地基板
の突起部間の谷部の露出領域にSi(111)面が露出
しない様に突起部を形成することである。本手段によれ
ば、上記の谷部の露出面の結晶成長速度aを小さく抑制
できるため、上記の差分(b−a)を、結晶性を維持し
たまま安定的に略最大化することが可能となる。Further, the seventh means includes the first through sixth means.
In any one of the means, the material of the underlying substrate may be S
i (111) is used to form a projection so that the Si (111) surface is not exposed in the exposed region of the valley between the projections of the base substrate in the projection formation step. According to this means, since the crystal growth rate a on the exposed surface of the valley can be suppressed to a small value, it is possible to stably substantially maximize the difference (ba) while maintaining the crystallinity. Becomes
【0021】また、第8の手段は、上記の第1乃至第7
の何れか1つの手段の突起部形成工程後に、少なくとも
突起部の表面に「Alx Ga1-x N(0<x≦1)」よ
り成るバッファ層を形成する工程を設けることである。Further, the eighth means includes the first to seventh means.
After the protrusion forming step of any one of the means, a step of forming a buffer layer made of “Al x Ga 1 -xN (0 <x ≦ 1)” at least on the surface of the protrusion is provided.
【0022】ただし、上記のバッファ層とは別に、更
に、上記のバッファ層と略同組成(例:AlNや、Al
GaN)の中間層を周期的に、又は他の層と交互に、或
いは、多層構造が構成される様に、積層しても良い。However, apart from the above-mentioned buffer layer, a composition substantially the same as that of the above-mentioned buffer layer (eg, AlN, Al
GaN) intermediate layers may be stacked periodically, alternately with other layers, or in a multilayer configuration.
【0023】この様なバッファ層(或いは、中間層)の
積層により、格子定数差に起因する基板層(成長層)に
働く応力を緩和できる等の従来と同様の作用原理によ
り、結晶性を向上させることが可能となる。By stacking such a buffer layer (or an intermediate layer), the crystallinity can be improved by the same operation principle as that of the related art such that the stress acting on the substrate layer (growth layer) caused by the lattice constant difference can be reduced. It is possible to do.
【0024】また、第9の手段は、上記の第8の手段に
おいて、バッファ層の膜厚を突起部の縦方向の高さ以下
に成膜することである。また、絶対的な目安としては、
バッファ層の膜厚は、およそ0.01μm以上、1μm以
下が望ましい。この手段により、バッファ層の上に形成
される所望の結晶層(例:GaN層)のみを良質に横方
向に成長させることができる。即ち、この手段により、
バッファ層の上に形成される結晶層に結晶成長時に掛か
る「格子定数差に基づく応力」が軽減され、転位密度が
効果的に低減できる。A ninth means is that, in the above-mentioned eighth means, the thickness of the buffer layer is formed to be equal to or less than the vertical height of the projection. Also, as an absolute guide,
The thickness of the buffer layer is desirably about 0.01 μm or more and 1 μm or less. By this means, only a desired crystal layer (eg, a GaN layer) formed on the buffer layer can be grown in the lateral direction with good quality. That is, by this means,
“Stress based on lattice constant difference” applied to the crystal layer formed on the buffer layer during crystal growth is reduced, and the dislocation density can be effectively reduced.
【0025】バッファ層等を形成するAlNやAlGa
N等は、下地基板の露出した表面の略全面に成膜され易
く、また、元来、所望の結晶の成長層等を形成するGa
Nの方が、AlNやAlGaN等よりも横方向成長し易
い傾向に有る様だが、上記の手段によれば、より確実に
大きな「空洞」を突起部の側方に形成することができ
る。AlN or AlGa for forming a buffer layer or the like
N and the like are easily formed on substantially the entire exposed surface of the base substrate, and Ga is originally formed to form a desired crystal growth layer and the like.
Although N tends to grow in the lateral direction more easily than AlN, AlGaN, or the like, according to the above-described means, a large “cavity” can be formed more reliably on the side of the protrusion.
【0026】また、この手段により、基板層を下地基板
から分離した際に、基板層の裏面(下地基板が有った側
の面)にも、結晶層(バッファ層の上に形成される所望
の層)が直に広範囲に露出する。従って、基板層の裏面
に電極を形成する際に、電気抵抗を抑制することが容易
となる。By this means, when the substrate layer is separated from the underlying substrate, the crystal layer (the desired layer formed on the buffer layer) is also formed on the back surface of the substrate layer (the surface on the side with the underlying substrate). Is exposed directly and widely. Therefore, when forming an electrode on the back surface of the substrate layer, it becomes easy to suppress the electric resistance.
【0027】尚、バッファ層の膜厚は、上記の通りおよ
そ0.01μm〜1μm程度が概ね妥当な範囲であるが、
より望ましくは、0.1μm以上、0.5μm以下が良い。
この膜厚が厚過ぎると、空洞が小さくなり易くなり望ま
しくない。また、この膜厚を薄くし過ぎると、略均一に
バッファ層を成膜することが困難となる。特に、突起部
の上部付近においてバッファ層の成膜ムラ(十分に成膜
されない部位)が生じると、結晶性にもムラが生じ易く
なり、望ましくない。Although the thickness of the buffer layer is generally about 0.01 μm to 1 μm as described above, it is generally reasonable.
More preferably, the thickness is 0.1 μm or more and 0.5 μm or less.
If the thickness is too large, the cavity tends to be small, which is not desirable. If the thickness is too small, it is difficult to form the buffer layer substantially uniformly. In particular, if unevenness in film formation of the buffer layer (a portion where the film is not sufficiently formed) occurs near the upper portion of the protrusion, unevenness tends to occur in crystallinity, which is not desirable.
【0028】また、第10の手段は、上記の第1乃至第
9の何れか1つの手段の結晶成長工程において、基板層
の膜厚を50μm以上とすることである。A tenth means is that in the crystal growth step of any one of the first to ninth means, the thickness of the substrate layer is 50 μm or more.
【0029】結晶成長させる基板層( III族窒化物系化
合物半導体)の厚さは、約50μm以上が望ましく、こ
の厚さが厚い程、基板層に対する引っ張り応力が緩和さ
れて、基板層の転位やクラックの発生密度を減少でき
る。また、更には、同時に基板層を強固にでき、上記の
剪断応力を上記の突起部に集中させ易くなる。The thickness of the substrate layer (group III nitride compound semiconductor) on which the crystal is grown is desirably about 50 μm or more. As this thickness increases, the tensile stress on the substrate layer is alleviated, and dislocation or dislocation of the substrate layer is reduced. Crack generation density can be reduced. Further, at the same time, the substrate layer can be strengthened, and the above-mentioned shear stress can be easily concentrated on the above-mentioned projections.
【0030】また、第11の手段は、上記の第1乃至第
10の何れか1つの手段の結晶成長工程において、結晶
成長速度の遅い結晶成長法から、結晶成長速度の速い結
晶成長法に、途中で結晶成長法を変更することである。In the eleventh means, in the crystal growth step of any one of the first to tenth means, a crystal growth method having a low crystal growth rate is changed to a crystal growth method having a high crystal growth rate. It is to change the crystal growth method on the way.
【0031】例えば、結晶成長面が一連の略平面状に成
るまでは、上記の差分(b−a)を略最大にし易い結晶
成長法(例:MOVPE法)を採用し、その後は、膜厚
を効率よく50μm以上にすることが容易な結晶成長法
(例:HVPE法)を採用すれば、短時間に結晶性の良
質な半導体結晶を得ることが可能となる。For example, until the crystal growth surface becomes a series of substantially planar shapes, a crystal growth method (eg, MOVPE method) that easily makes the above difference (ba) substantially maximum is adopted. If a crystal growth method (e.g., HVPE method) is used, which can easily make the thickness more than 50 μm efficiently, a semiconductor crystal having good crystallinity can be obtained in a short time.
【0032】また、第12の手段は、上記の第1乃至第
11の何れか1つの手段の突起部形成工程において、突
起部が略等間隔又は略一定周期で配置される様に上記の
突起部を形成することである。In a twelfth aspect, in the projection forming step of any one of the first to eleventh means, the projections are arranged such that the projections are arranged at substantially equal intervals or at a substantially constant period. Forming a part.
【0033】これにより、横方向成長の成長条件が全体
的に略均等となり、結晶性の良否にムラが生じ難くな
る。また、突起部間の谷部の上方が、基板層によって完
全に覆われるまでの時間に、局所的なバラツキが生じ難
くなるため、例えば、結晶成長速度の遅い結晶成長法か
ら、結晶成長速度の速い結晶成長法に、途中で結晶成長
法を変更する場合に、その時期を的確に、早期に、或い
は一意に決定することが容易となる。また、本手段によ
り、上記の空洞が各々略均等な大きさとなり、上記の剪
断応力を各突起部に略均等に分配することが可能となる
ため、全突起部の破断がムラなく生じ、下地基板と基板
層との分離が確実に実施できる様になる。As a result, the growth conditions for the lateral growth become substantially uniform as a whole, and the crystal quality is less likely to be uneven. In addition, since local variation is unlikely to occur during the time until the upper part of the valley between the protrusions is completely covered by the substrate layer, for example, a crystal growth method with a low crystal growth rate is used. When the crystal growth method is changed to a fast crystal growth method in the middle, it is easy to determine the timing accurately, early, or uniquely. Further, according to this means, the above-mentioned cavities each have a substantially uniform size, and the above-mentioned shear stress can be distributed substantially evenly to each of the protrusions. Separation of the substrate and the substrate layer can be reliably performed.
【0034】また、第13の手段は、上記の第12の手
段の突起部形成工程において、1辺が0.1μm以上の略
正三角形を基調とする2次元三角格子の格子点上に突起
部を形成することである。この手段により、上記の第1
2の手段をより具体的に正確、確実に実施でき、よっ
て、転位の数を確実に低減することができる。In a thirteenth aspect, in the projection forming step of the twelfth aspect, the projection is formed on a lattice point of a two-dimensional triangular lattice based on a substantially equilateral triangle having one side of 0.1 μm or more. Is to form By this means, the first
The second means can be more accurately and reliably implemented, and thus the number of dislocations can be reliably reduced.
【0035】また、第14の手段は、上記の第1乃至第
13の何れか1つの手段の突起部形成工程において、突
起部の水平断面形状を、略正三角形、略正六角形、略円
形、又は四角形に形成することである。この手段によ
り、 III族窒化物系化合物半導体より形成される結晶の
結晶軸の方向が各部で揃い易くなるため、或いは、任意
の水平方向に対して突起部の水平方向の長さ(太さ)を
略一様に制限できるため、転位の数を抑制することがで
きる。特に、正六角形や正三角形は、半導体結晶の結晶
構造と合致し易いのでより望ましい。また、円形や四角
形は製造技術の面で形成し易いと言う、現行一般の加工
技術水準の現状に照らしたメリットが有る。In a fourteenth aspect, in the protrusion forming step of any one of the first to thirteenth means, the horizontal cross-sectional shape of the protrusion is substantially regular triangle, substantially regular hexagon, substantially circular, Or it is formed in a quadrangle. By this means, the direction of the crystal axis of the crystal formed from the group III nitride-based compound semiconductor can be easily aligned at each part, or the horizontal length (thickness) of the protrusion relative to an arbitrary horizontal direction Can be substantially uniformly restricted, so that the number of dislocations can be suppressed. In particular, regular hexagons and regular triangles are more preferable because they easily match the crystal structure of the semiconductor crystal. In addition, there is an advantage in the light of the current state of the general processing technology that a circle or a square is easy to form in terms of manufacturing technology.
【0036】また、第15の手段は、上記の第1乃至第
14の何れか1つの手段の突起部形成工程において、突
起部の配置間隔(配置周期)を0.1μm以上、10μm
以下とすることである。より望ましくは、結晶成長の実
施条件にも依存するが、突起部の配置間隔は、0.5〜8
μm程度が良い。ただし、この配置間隔とは、互いに接
近する各突起部の中心点間の距離のことを言う。In a fifteenth aspect, in the projection forming step of any one of the first to fourteenth aspects, the arrangement interval (arrangement cycle) of the projections is 0.1 μm or more and 10 μm or more.
It is as follows. More preferably, the distance between the projections is 0.5 to 8 although it depends on the crystal growth conditions.
About μm is good. However, this arrangement interval refers to the distance between the center points of the respective protruding portions approaching each other.
【0037】この手段により、突起部の谷部の上方を基
板層で覆うことが可能となると同時に、突起部間に空洞
を形成することが可能となる。この値が小さ過ぎると、
ELOの作用が殆ど得られなくなり、結晶性が劣化す
る。また、形成される空洞が小さくなり過ぎて、基板層
の膜厚を必要以上に大きくしない限り、突起部を破断す
ることが容易でなくなる。By this means, it becomes possible to cover the upper part of the valley of the projection with the substrate layer, and at the same time, it is possible to form a cavity between the projections. If this value is too small,
The effect of ELO is hardly obtained, and the crystallinity deteriorates. In addition, the cavity formed is too small, and unless the thickness of the substrate layer is increased more than necessary, it is not easy to break the protrusion.
【0038】また、この値が大きくなり過ぎると、確実
に突起部の谷部の上方を基板層で覆うことができなくな
り、結晶性が均質かつ良質の結晶(基板層)が得られな
くなる。或いは、この値が更に大き過ぎると、谷部の露
出面が広大となり過ぎて、ELOの作用が殆ど得られな
くなり、また、空洞が全く形成されなくなるため、結晶
性が劣化し、また、基板層の膜厚を必要以上に大きくし
ない限り、突起部を破断することが容易でなくなる。On the other hand, if this value is too large, it is impossible to reliably cover the upper part of the valley of the projection with the substrate layer, and it becomes impossible to obtain a crystal (substrate layer) having uniform crystallinity and good quality. Alternatively, if this value is too large, the exposed surface of the valley becomes too large, so that the effect of ELO is hardly obtained, and no cavities are formed at all. Unless the film thickness is excessively large, it is not easy to break the projection.
【0039】また、第16の手段は、上記の第1乃至第
15の何れか1つの手段の突起部形成工程において、突
起部の縦方向の高さを0.5μm以上、20μm以下とす
ることである。より望ましくは、結晶成長の実施条件に
も依存するが、突起部の縦方向の高さは、0.8〜5μm
程度が良い。この高さが短過ぎると、突起部が無い場合
と同様に、ELOの作用が殆ど得られなくなり、結晶性
が劣化する。また、この高さが短過ぎると、上記の空洞
が形成されなくなる。また、この高さが高過ぎると、突
起部の形成自身が困難となったり、突起部の形成に必要
以上に時間がかかったり、下地基板の材料が必要以上に
消費されたりして望ましくない。また、この高さが高過
ぎると、剪断応力が突起部の縦方向に分散されてしま
い、突起部を確実に破断させることが難しくなる。According to a sixteenth aspect, in the projection forming step of any one of the first to fifteenth aspects, the height of the projection in the vertical direction is 0.5 μm or more and 20 μm or less. It is. More preferably, the vertical height of the projection is 0.8 to 5 μm, although it depends on the crystal growth conditions.
Good degree. If the height is too short, the effect of ELO is hardly obtained as in the case where there is no protrusion, and the crystallinity is deteriorated. If the height is too short, the above-mentioned cavity will not be formed. On the other hand, if the height is too high, the formation of the projection itself becomes difficult, it takes more time than necessary to form the projection, and the material of the underlying substrate is unnecessarily consumed, which is not desirable. If the height is too high, the shear stress is dispersed in the longitudinal direction of the projection, and it is difficult to reliably break the projection.
【0040】また、第17の手段は、上記の第1乃至第
16の何れか1つの手段の突起部形成工程において、突
起部の横方向の太さ、幅、又は直径を0.1μm以上、1
0μm以下とすることである。より望ましくは、結晶成
長の実施条件にも依存するが、突起部の横方向の太さ、
幅、又は直径は、0.5〜5μm程度が良い。この太さが
太過ぎると、格子定数差に基づいて基板層(成長層)に
働く応力の影響が大きくなり、基板層の転位数が増加し
易くなる。また、細過ぎると、突起部自身の形成が困難
となるか、或いは、突起部の頭頂部の結晶成長速度bが
遅くなり、望ましくない。In a seventeenth aspect, in the projection forming step of any one of the first to sixteenth aspects, the thickness, width, or diameter of the projection in the lateral direction is 0.1 μm or more. 1
0 μm or less. More preferably, depending on the crystal growth conditions, the lateral thickness of the protrusion,
The width or diameter is preferably about 0.5 to 5 μm. If the thickness is too large, the influence of stress acting on the substrate layer (growth layer) based on the lattice constant difference increases, and the number of dislocations in the substrate layer tends to increase. On the other hand, if the thickness is too small, it becomes difficult to form the projection itself, or the crystal growth rate b at the top of the projection becomes slow, which is not desirable.
【0041】また、応力(剪断応力等)により突起部を
破断させる際にも、突起部の横方向の太さ、幅、又は直
径が大き過ぎると、確実に破断されない部分が生じ易く
なり、望ましくない。また、格子定数差に基づいて基板
層(成長層)に働く応力の影響の大小は、突起部の横方
向の太さ(長さ)だけに依るものではなく、突起部の配
置間隔等にも依存する。そして、これらの設定範囲が不
適切であれば、上記の様に格子定数差に基づく応力の影
響が大きくなり、基板層の転位数が増加し易くなり、望
ましくない。Also, when the projection is broken by stress (such as shearing stress), if the projection is too large in width, width, or diameter, a portion that is not easily broken is likely to be formed, which is desirable. Absent. Further, the magnitude of the effect of the stress acting on the substrate layer (growth layer) based on the lattice constant difference does not depend only on the width (length) of the protrusions in the lateral direction, but also on the arrangement interval of the protrusions. Dependent. If these setting ranges are inappropriate, the influence of the stress based on the lattice constant difference increases as described above, and the number of dislocations in the substrate layer tends to increase, which is not desirable.
【0042】また、突起部の頭頂部付近の横方向の太
さ、幅、又は直径には、上記の様に最適値又は適正範囲
があるため、突起部の上面、底面、又は水平断面の形状
は、少なくとも局所的に閉じた形状(島状)、更には、
外側に向かって凸状に閉じた形状が良く、より望ましく
は、この上面、底面、又は水平断面の形状は、略円形や
略正多角形等が良い。この様な設定により、任意の水平
方向に対して確実に、上記の最適値又は適正範囲を実現
することが容易となる。Also, since the lateral thickness, width, or diameter near the top of the projection has an optimum value or an appropriate range as described above, the shape of the top, bottom, or horizontal cross section of the projection is Is at least a locally closed shape (island shape),
It is preferable that the shape is closed in a convex shape toward the outside, and more preferably, the shape of the upper surface, the bottom surface, or the horizontal cross section is a substantially circular shape or a substantially regular polygon. With such a setting, it is easy to reliably realize the optimum value or the appropriate range in any horizontal direction.
【0043】また、第18の手段は、上記の第1乃至第
17の何れか1つの手段において、結晶成長工程よりも
前に、各種エッチング、電子線照射処理、レーザ等の光
学的処理、化学的処理、或いは切削や研磨等の物理的処
理により、下地基板の突起部間の谷部の少なくとも一部
の露出領域の結晶性又は分子構造を劣化又は変化させる
ことにより、この露出領域における III族窒化物系化合
物半導体の結晶成長速度aを低下させることである。こ
の手段により、前記の結晶成長速度の差分(b−a)を
より大きくすることができる。従って、この手段によれ
ば、突起部の頭頂部付近の結晶成長速度が相対的に大き
くなるため、前記と同様の作用により、基板層の結晶成
長時に基板層に働く「下地基板と基板層の間の格子定数
差に基づく応力」が緩和され、基板層に転位やクラック
が発生し難くなる。In an eighteenth aspect, in any one of the first to seventeenth aspects, prior to the crystal growth step, various types of etching, electron beam irradiation, optical processing such as laser, chemical processing, and the like are performed. By degrading or changing the crystallinity or molecular structure of at least a part of the exposed region of the valley between the protrusions of the underlying substrate by physical treatment or physical treatment such as cutting or polishing, the group III in this exposed region The purpose is to reduce the crystal growth rate a of the nitride-based compound semiconductor. By this means, the difference (ba) between the crystal growth rates can be further increased. Therefore, according to this means, the crystal growth rate near the top of the protrusion becomes relatively large, and the same effect as described above acts on the substrate layer during the crystal growth of the substrate layer. The stress caused by the lattice constant difference between the layers is relaxed, and dislocations and cracks are less likely to occur in the substrate layer.
【0044】また、第19の手段は、上記の何れか1つ
の分離工程において、下地基板と基板層とから成る基板
を成長装置の反応室に残し、略一定流量のアンモニア
(NH3)ガスを反応室に流したままの状態で、基板を概ね
「−100℃/min〜−0.5℃/min」程度の冷却
速度で略常温まで冷却することである。例えば、この様
な手段により、基板層の結晶性を良質に維持したまま、
前記の分離工程を実施することができる。A nineteenth means is that, in any one of the above-mentioned separation steps, a substrate composed of a base substrate and a substrate layer is left in a reaction chamber of a growth apparatus, and a substantially constant flow rate of ammonia (NH 3 ) gas is supplied. In this state, the substrate is cooled to approximately room temperature at a cooling rate of about “-100 ° C./min to −0.5 ° C./min” while being kept flowing in the reaction chamber. For example, by such means, while maintaining the crystallinity of the substrate layer at a high quality,
The above separation step can be performed.
【0045】また、第20の手段は、少なくとも、上記
の何れか1つの分離工程よりも後に、基板層の裏面に残
った突起部の破断残骸をエッチング等の、化学的或いは
物理的な加工処理により除去する残骸除去工程を設ける
ことである。この手段によれば、基板層の裏面(下地基
板を剥離させた側の面)に、半導体発光素子等の電極を
形成した際に、電極と基板層との界面付近に生じる電流
ムラや電気抵抗を抑制でき、よって駆動電圧の低減や、
或いは発光強度の向上等を図ることができる。In the twentieth means, at least after any one of the above-mentioned separation steps, a chemical or physical processing such as etching is performed on the broken debris of the protrusion remaining on the back surface of the substrate layer. Is to provide a debris removal step for removing the debris. According to this means, when an electrode such as a semiconductor light emitting element is formed on the back surface of the substrate layer (the surface on the side from which the underlying substrate has been peeled off), current unevenness and electric resistance generated near the interface between the electrode and the substrate layer are formed. Can be suppressed, thereby reducing the drive voltage and
Alternatively, the emission intensity can be improved.
【0046】更に、突起部の破断残骸を除去することに
より、電極を半導体発光素子等の反射鏡としても利用す
る際には、鏡面付近での光の吸収や散乱が低減されて反
射率が向上するので、発光強度が向上する。また、例え
ば、研磨等の物理的な加工処理によりこの残骸除去工程
を実施した場合等には、基板層の裏面のバッファ層まで
をも取り除いたり、或いは、基板層の裏面の平坦度を向
上したりすることもできるので、電流ムラや電気抵抗の
抑制、或いは、鏡面付近での光の吸収や散乱の低減等
の、上記の作用効果を更に補強することができる。Further, by removing the broken debris of the projection, when the electrode is also used as a reflecting mirror of a semiconductor light emitting device or the like, light absorption and scattering near the mirror surface are reduced, and the reflectance is improved. Therefore, the emission intensity is improved. Further, for example, when the debris removal step is performed by a physical processing such as polishing, the buffer layer on the back surface of the substrate layer is also removed, or the flatness of the back surface of the substrate layer is improved. Therefore, the above-mentioned effects such as suppression of current unevenness and electric resistance or reduction of light absorption and scattering near the mirror surface can be further reinforced.
【0047】また、第21の手段は、 III族窒化物系化
合物半導体発光素子において、上記の第1乃至第20の
何れか1つの手段に依る半導体結晶の製造方法を用いて
製造された半導体結晶を結晶成長基板として備えること
である。この手段によれば、結晶性が良質で、内部応力
の少ない半導体より、 III族窒化物系化合物半導体発光
素子を製造することが可能又は容易となる。A twenty-first means is a group III nitride compound semiconductor light emitting device, wherein the semiconductor crystal is manufactured by using the semiconductor crystal manufacturing method according to any one of the first to twentieth means. As a crystal growth substrate. According to this means, it becomes possible or easy to manufacture a group III nitride compound semiconductor light emitting device from a semiconductor having good crystallinity and low internal stress.
【0048】また、第22の手段は、上記の第1乃至第
20の何れか1つの手段に依る半導体結晶の製造方法を
用いて製造された半導体結晶を結晶成長基板とした結晶
成長により、 III族窒化物系化合物半導体発光素子を製
造することである。この手段によれば、結晶性が良質
で、内部応力の少ない半導体より、 III族窒化物系化合
物半導体発光素子を製造することが可能又は容易とな
る。以上の手段により、前記の課題を解決することがで
きる。The twenty-second means may be formed by crystal growth using a semiconductor crystal manufactured by the method for manufacturing a semiconductor crystal according to any one of the first to twentieth means as a crystal growth substrate. It is to manufacture a group III nitride compound semiconductor light emitting device. According to this means, it becomes possible or easy to manufacture a group III nitride compound semiconductor light emitting device from a semiconductor having good crystallinity and low internal stress. With the above means, the above-mentioned problem can be solved.
【0049】[0049]
【発明の実施の形態】以下、本発明を具体的な実施例に
基づいて説明する。ただし、本発明は以下に示す実施例
に限定されるものではない。以下、本発明の実施例にお
ける半導体結晶(結晶成長基板)の製造手順の概要を例
示する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on specific embodiments. However, the present invention is not limited to the embodiments described below. Hereinafter, an outline of a manufacturing procedure of a semiconductor crystal (crystal growth substrate) in an embodiment of the present invention will be exemplified.
【0050】〔1〕突起部形成工程 図2に示す様に、シリコンより成る単結晶の下地基板1
01のSi(111)面上に、フォトリソグラフィーを
利用したドライエッチングにより、直径約1μm、高さ
約1μmの略円柱形状の突起部101aを約2μmの配
置間隔で形成した。配列形態としては、一辺が約2μm
の略正三角形を基調とする2次元三角格子の各格子点上
に突起部101aの円柱底面の中心が配置される様に、
突起部101aを形成した。ただし、下地基板101の
厚さは約200μmとした。[1] Projection Forming Step As shown in FIG. 2, a single crystal base substrate 1 made of silicon
On the Si (111) surface of No. 01, approximately columnar protrusions 101a having a diameter of about 1 μm and a height of about 1 μm were formed at an interval of about 2 μm by dry etching using photolithography. As an array form, one side is about 2 μm
So that the center of the cylindrical bottom surface of the projection 101a is arranged on each lattice point of the two-dimensional triangular lattice based on the substantially equilateral triangle of
The protrusion 101a was formed. However, the thickness of the base substrate 101 was about 200 μm.
【0051】〔2〕結晶成長工程 本結晶成長工程では、図4に示す様に、結晶の成長面
が、突起部101aの上面(初期状態)から各々互いに
連結されて一連の略平面状に成長するまでの成長工程を
有機金属化合物気相成長法(MOVPE法)に従って実
施し、その後、この基板層(結晶層)が200μm程度
の厚膜に成長するまでの成長工程をハイドライド気相成
長法(HVPE法)に従って実施した。尚、本結晶成長
工程では、アンモニア(NH3) ガス、キャリアガス(H2,
N2) 、トリメチルガリウム(Ga(CH3)3)ガス(以下「TMG
」と記す)、及びトリメチルアルミニウム(Al(C
H3)3 )ガス(以下「TMA 」と記す)を用いた。[2] Crystal Growth Step In this crystal growth step, as shown in FIG. 4, the crystal growth surfaces are connected to each other from the upper surface (initial state) of the protrusion 101a and grow in a series of substantially planar shapes. Is performed according to the metalorganic compound vapor phase epitaxy (MOVPE) method. Thereafter, the growth step until the substrate layer (crystal layer) is grown to a thickness of about 200 μm is performed by the hydride vapor phase epitaxy (MOVPE) method. HVPE method). In this crystal growth step, ammonia (NH 3 ) gas and carrier gas (H 2 ,
N 2 ), trimethylgallium (Ga (CH 3 ) 3 ) gas (hereinafter referred to as “TMG
]) And trimethylaluminum (Al (C
H 3) 3) using a gas (hereinafter referred to as "TMA").
【0052】(a)まず、上記の突起部101aが設け
られた下地基板101(図2)を有機洗浄及び酸処理に
より洗浄し、結晶成長装置の反応室に載置されたサセプ
タに装着し、常圧でH2を反応室に流しながら温度1100℃
で下地基板101をベーキングした。(A) First, the base substrate 101 (FIG. 2) provided with the above-mentioned projections 101a is washed by organic washing and acid treatment, and is mounted on a susceptor placed in a reaction chamber of a crystal growth apparatus. Temperature 1100 ° C while flowing H 2 into the reaction chamber at normal pressure
The base substrate 101 was baked.
【0053】(b)次に、上記の下地基板101の上
に、MOVPE法に従って、H2 ,NH3,TMG,TM
Aを供給して、AlGaNバッファ層(基板層第1層)
102aを成膜した。このAlGaNバッファ層102
aの結晶成長温度は、約1100℃、膜厚は約0.3μm
であった。(図3) (c)このAlGaNバッファ層(基板層第1層)10
2aの上に、基板層第2層の一部、即ち、膜厚約5μm
のGaN層102bを、H2、NH3 及びTMGを供給し
て、成長温度1075℃で結晶成長させた。この工程に
より、図4に示す様に、基板層第2層(GaN層102
b)の一部が横方向成長し、谷部即ち突起部101aの
側方に大きな空洞ができた。尚、この時のTMG供給速
度は、概ね40μmol /min 程度であり、基板層第2層
(GaN層102b)の結晶成長速度は、約1μm/H
r程度であった。[0053] (b) Next, on the underlying substrate 101, according to the MOVPE method, H 2, NH 3, TMG , TM
A to supply the AlGaN buffer layer (substrate layer first layer)
102a was formed. This AlGaN buffer layer 102
The crystal growth temperature of a is about 1100 ° C. and the film thickness is about 0.3 μm
Met. (FIG. 3) (c) This AlGaN buffer layer (substrate layer first layer) 10
2a, a part of the substrate layer second layer, that is, a film thickness of about 5 μm
The GaN layer 102b was grown at a growth temperature of 1075 ° C. by supplying H 2 , NH 3 and TMG. By this step, as shown in FIG. 4, the second substrate layer (GaN layer 102) is formed.
Part b) grew in the lateral direction, and a large cavity was formed on the side of the valley, that is, the protrusion 101a. The TMG supply rate at this time is about 40 μmol / min, and the crystal growth rate of the second substrate layer (GaN layer 102 b) is about 1 μm / H.
r.
【0054】(d)その後、ハイドライド気相成長法
(HVPE法)に従って、上記のGaN層(基板層第2
層)102bを、更に、200μmまで結晶成長させ
た。このHVPE法におけるGaN層102bの結晶成
長速度は、約45μm/Hr程度であった。(D) Thereafter, the GaN layer (substrate layer second layer) is formed according to the hydride vapor phase epitaxy (HVPE).
The layer 102b was further grown to 200 μm. The crystal growth rate of the GaN layer 102b in this HVPE method was about 45 μm / Hr.
【0055】〔3〕分離工程 (a)上記の結晶成長工程の後、アンモニア(NH3)ガス
を結晶成長装置の反応室に流したまま、下地基板101
と、(AlGaNバッファ層102aとGaN層102
bとから成る)基板層102を略常温まで冷却した。こ
の時の冷却速度は、概ね「−50℃/min〜−5℃/
min」程度であった。[3] Separation Step (a) After the above-described crystal growth step, the base substrate 101 is kept while flowing ammonia (NH 3 ) gas into the reaction chamber of the crystal growth apparatus.
(AlGaN buffer layer 102a and GaN layer 102
b) was cooled to approximately room temperature. The cooling rate at this time is generally “−50 ° C./min to −5 ° C./min.
min ”.
【0056】(b)その後、これらを結晶成長装置の反
応室から取り出すと、下地基板101から剥離したGa
N結晶が得られた。ただし、この結晶は、GaN層10
2bの裏面に、AlGaNバッファ層102aの小さな
一部分の残骸と突起部101aの破断残骸とが残留した
ままのものであった。(B) Thereafter, when these are taken out of the reaction chamber of the crystal growth apparatus, Ga separated from the underlying substrate 101 is removed.
N crystals were obtained. However, this crystal has a GaN layer 10
On the back surface of 2b, a small portion of the debris of the AlGaN buffer layer 102a and a broken debris of the protrusion 101a remained.
【0057】〔4〕破断残骸除去工程 上記の分離工程の後、フッ酸に硝酸を加えた混合液を用
いたエッチング処理により、GaN結晶の裏面に残った
Siより成る突起部101aの破断残骸を除去した。[4] Step of removing broken debris After the above separation step, the broken debris of the protrusion 101a made of Si remaining on the back surface of the GaN crystal is removed by etching using a mixture of hydrofluoric acid and nitric acid. Removed.
【0058】以上の製造方法により、膜厚約200μm
の結晶性の非常に優れた良質のGaN結晶(GaN層1
02b)、即ち、下地基板101から独立した所望の半
導体基板を得ることができた。By the above manufacturing method, the film thickness is about 200 μm
Quality GaN crystal (GaN layer 1)
02b), that is, a desired semiconductor substrate independent of the base substrate 101 could be obtained.
【0059】尚、上記の実施例では、図2に例示した様
に、下地基板の突起部や谷部は鉛直面と水平面により構
成されているが、これらは任意の斜面や曲面等から形成
しても良い。従って、図2(c)に例示した下地基板上
に形成される谷部の断面形状は、略矩形の凹字型以外に
も、例えば、略U字型や略V字型等の形に形成しても良
く、一般にこれらの形状、大きさ、間隔、配置、配向等
は任意である。In the above embodiment, as shown in FIG. 2, the projections and valleys of the base substrate are formed by a vertical plane and a horizontal plane. May be. Accordingly, the cross-sectional shape of the valley formed on the base substrate illustrated in FIG. 2C is not limited to a substantially rectangular concave shape, but may be, for example, a substantially U-shaped or substantially V-shaped shape. In general, these shapes, sizes, intervals, arrangements, orientations, and the like are arbitrary.
【図1】本発明の作用を説明する、突起部を有する下地
基板と、その上に成長した半導体結晶の、部分的な断片
の模式的な斜視図。FIG. 1 is a schematic perspective view of a base substrate having a projection and a partial fragment of a semiconductor crystal grown thereon illustrating the operation of the present invention.
【図2】本発明の実施例に係わる、下地基板(Si基
板)101の部分的な断片の模式的な斜視図(a)、平
面図(b)、及び断面図(c)。FIG. 2 is a schematic perspective view (a), a plan view (b), and a cross-sectional view (c) of a partial fragment of a base substrate (Si substrate) 101 according to an embodiment of the present invention.
【図3】基板層第1層(AlGaNバッファ層)102
aが成膜された下地基板101の模式的な斜視図
(a)、平面図(b)、及び断面図(c)。FIG. 3 is a substrate layer first layer (AlGaN buffer layer) 102;
5A is a schematic perspective view, FIG. 5B is a plan view, and FIG. 5C is a cross-sectional view of the base substrate 101 on which a is formed.
【図4】基板層102(層102a及び層102b)が
積層された下地基板101の模式的な斜視図(a)、平
面図(b)、及び断面図(c)。FIG. 4 is a schematic perspective view (a), a plan view (b), and a cross-sectional view (c) of an underlying substrate 101 on which a substrate layer 102 (layer 102a and layer 102b) is stacked.
【図5】従来の下地基板上の半導体結晶の模式的な断面
図。FIG. 5 is a schematic cross-sectional view of a conventional semiconductor crystal on a base substrate.
101 … 下地基板(Si基板) 101a … 突起部 102 … 基板層(窒化物半導体層) 102a … 基板層第1層(AlGaNバッファ層) 102b … 基板層第2層(GaN単結晶層) 101: Undersubstrate (Si substrate) 101a: Protrusion 102: Substrate layer (nitride semiconductor layer) 102a: First substrate layer (AlGaN buffer layer) 102b: Second substrate layer (GaN single crystal layer)
フロントページの続き (72)発明者 冨田 一義 愛知県愛知郡長久手町大字長湫字横道41番 地の1 株式会社豊田中央研究所内 Fターム(参考) 4G077 AA03 BE11 BE13 BE15 DB01 ED04 ED05 ED06 EE01 EE02 EF03 FJ03 TK01 TK04 TK06 TK10 TK11 5F041 AA40 CA33 CA40 CA67 CA77 5F045 AA04 AB09 AB14 AC08 AC12 AC15 AD14 AE29 AF02 AF03 BB01 BB02 BB11 BB12 BB13 CA09 CB02 DA53 EE12 HA01 HA02 HA08 HA09 HA11 HA12Continuation of the front page (72) Inventor Kazuyoshi Tomita 41-cho, Yokomichi, Nagakute-cho, Aichi-gun, Aichi Prefecture F-term in Toyota Central Research Laboratory Co., Ltd. 4G077 AA03 BE11 BE13 BE15 DB01 ED04 ED05 ED06 EE01 EE02 EF03 FJ03 TK01 TK04 TK06 TK10 TK11 5F041 AA40 CA33 CA40 CA67 CA77 5F045 AA04 AB09 AB14 AC08 AC12 AC15 AD14 AE29 AF02 AF03 BB01 BB02 BB11 BB12 BB13 CA09 CB02 DA53 EE12 HA01 HA02 HA08 HA09 HA11 HA12
Claims (22)
板上に III族窒化物系化合物半導体から成る基板層を形
成することにより、前記下地基板から独立した半導体結
晶を得る方法であって、 前記下地基板上に多数の突起部を形成する突起部形成工
程と、 前記突起部の表面の少なくとも一部を前記基板層が結晶
成長を開始する最初の成長面として、この成長面が各々
互いに連結されて少なくとも一連の略平面に成長するま
で、前記基板層を結晶成長させる結晶成長工程と、 前記突起部を破断することにより、前記基板層と前記下
地基板とを分離する分離工程とを有することを特徴とす
る半導体結晶の製造方法。1. A method for obtaining a semiconductor crystal independent of an undersubstrate by forming a substrate layer made of a group III nitride compound semiconductor on an undersubstrate by utilizing a lateral crystal growth action. A projecting portion forming step of forming a large number of projecting portions on the base substrate; and at least a part of the surface of the projecting portion is a first growing surface on which the substrate layer starts crystal growth. A crystal growth step of crystal-growing the substrate layer until it is connected and grown to at least a series of substantially flat surfaces; and a separation step of separating the substrate layer and the base substrate by breaking the projections. A method for manufacturing a semiconductor crystal, comprising:
は加熱することにより、前記基板層と前記下地基板との
熱膨張係数差に基づく応力を発生させ、この応力を利用
して前記突起部を破断することを特徴とする請求項1に
記載の半導体結晶の製造方法。2. A method of cooling or heating the substrate layer and the underlying substrate to generate a stress based on a difference in thermal expansion coefficient between the substrate layer and the underlying substrate, and utilizing the stress to generate the protrusion. The method for producing a semiconductor crystal according to claim 1, wherein the semiconductor crystal is broken.
板上に III族窒化物系化合物半導体から成る基板層を形
成することにより、半導体結晶を得る方法であって、 前記下地基板上に多数の突起部を形成する突起部形成工
程と、 前記突起部の表面の少なくとも一部を前記基板層が結晶
成長を開始する最初の成長面として、この成長面が各々
互いに連結されて少なくとも一連の略平面に成長するま
で、前記基板層を結晶成長させる結晶成長工程とを有
し、 前記結晶成長工程において、前記 III族窒化物系化合物
半導体の原料供給量qを調整することにより、 前記下地基板の前記突起部間の谷部の少なくとも一部の
露出領域における前記III族窒化物系化合物半導体の結
晶成長速度aと、前記突起部の頭頂部における結晶成長
速度bとの差分(b−a)を略最大値に制御することを
特徴とする半導体結晶の製造方法。3. A method for obtaining a semiconductor crystal by forming a substrate layer made of a group III nitride-based compound semiconductor on an undersubstrate by utilizing a lateral crystal growth action, comprising: A projecting portion forming step of forming a large number of projecting portions, at least a part of the surface of the projecting portion is used as an initial growth surface on which the substrate layer starts crystal growth, and the growth surfaces are connected to each other to form at least a series of A crystal growth step of growing the substrate layer until it grows into a substantially flat surface. In the crystal growth step, the raw material supply amount q of the group III nitride compound semiconductor is adjusted, The difference (ba) between the crystal growth rate a of the group III nitride compound semiconductor in at least a part of the exposed region of the valley between the protrusions and the crystal growth rate b at the top of the protrusion. ) Is controlled to a substantially maximum value.
窒化物系化合物半導体の原料供給量qを調整することに
より、 前記下地基板の前記突起部間の谷部の少なくとも一部の
露出領域における前記III族窒化物系化合物半導体の結
晶成長速度aと、前記突起部の頭頂部における結晶成長
速度bとの差分(b−a)を略最大値に制御することを
特徴とする請求項1、または請求項2に記載の半導体結
晶の製造方法。4. In the crystal growth step, a raw material supply amount q of the group III nitride-based compound semiconductor is adjusted so that at least a part of a valley between the protrusions of the base substrate is exposed in the exposed region. 2. The method according to claim 1, wherein a difference (ba) between a crystal growth rate a of the group III nitride-based compound semiconductor and a crystal growth rate b at the top of the protrusion is controlled to a substantially maximum value. A method for manufacturing a semiconductor crystal according to claim 2.
上、100μmol /min 以下としたことを特徴とする請
求項3、または請求項4に記載の半導体結晶の製造方
法。5. The method for producing a semiconductor crystal according to claim 3, wherein the raw material supply amount q is set to 1 μmol / min or more and 100 μmol / min or less.
ることを特徴とする請求項1乃至請求項5の何れか1項
に記載の半導体結晶の製造方法。6. The method of manufacturing a semiconductor crystal according to claim 1, wherein silicon (Si) or silicon carbide (SiC) is used as a material of the base substrate.
1)を用い、 前記突起部形成工程において、前記下地基板の前記突起
部間の谷部の露出領域に、Si(111)面が露出しな
い様に前記突起部を形成することを特徴とする請求項1
乃至請求項6の何れか1項に記載の半導体結晶の製造方
法。7. The method according to claim 1, wherein the base substrate is made of Si (11).
The method according to claim 1, wherein in the step of forming the protrusion, the protrusion is formed in an exposed region of a valley between the protrusions of the base substrate so that the Si (111) surface is not exposed. Item 1
A method for manufacturing a semiconductor crystal according to claim 6.
<x≦1)」より成るバッファ層を形成する工程を有す
ることを特徴とする請求項1乃至請求項7の何れか1項
に記載の半導体結晶の製造方法。8. After the step of forming the protrusion, at least the surface of the protrusion has “Al x Ga 1 -xN (0
8. The method of manufacturing a semiconductor crystal according to claim 1, further comprising a step of forming a buffer layer composed of <x ≦ 1).
方向の高さ以下に成膜することを特徴とする請求項8に
記載の半導体結晶の製造方法。9. The method according to claim 8, wherein the buffer layer is formed to have a thickness equal to or less than a height of the protrusion in a vertical direction.
る請求項1乃至請求項9の何れか1項に記載の半導体結
晶の製造方法。10. The method according to claim 1, wherein the thickness of the substrate layer is set to 50 μm or more in the crystal growth step.
い結晶成長法に、途中で結晶成長法を変更することを特
徴とする請求項1乃至請求項10の何れか1項に記載の
半導体結晶の製造方法。11. The method according to claim 1, wherein in the crystal growth step, the crystal growth method is changed halfway from a crystal growth method with a low crystal growth rate to a crystal growth method with a high crystal growth rate. 11. The method for manufacturing a semiconductor crystal according to any one of items 10 to 10.
に前記突起部を形成することを特徴とする請求項1乃至
請求項11の何れか1項に記載の半導体結晶の製造方
法。12. The method according to claim 1, wherein in the step of forming the protrusions, the protrusions are formed such that the protrusions are arranged at substantially equal intervals or at a substantially constant period. 2. The method for producing a semiconductor crystal according to claim 1.
角格子の格子点上に前記突起部を形成することを特徴と
する請求項12に記載の半導体結晶の製造方法。13. The projection forming step, wherein the projection is formed on a lattice point of a two-dimensional triangular lattice based on a substantially equilateral triangle having one side of 0.1 μm or more. 3. The method for producing a semiconductor crystal according to item 1.
起部の水平断面形状を、略正三角形、略正六角形、略円
形、又は四角形に形成したことを特徴とする請求項1乃
至請求項13の何れか1項に記載の半導体結晶の製造方
法。14. The projection according to claim 1, wherein in the projection forming step, a horizontal cross-sectional shape of the projection is formed into a substantially regular triangle, a substantially regular hexagon, a substantially circle, or a quadrangle. The method for producing a semiconductor crystal according to claim 1.
起部の配置間隔を0.1μm以上、10μm以下とするこ
とを特徴とする請求項1乃至請求項14の何れか1項に
記載の半導体結晶の製造方法。15. The semiconductor crystal according to claim 1, wherein, in the protrusion forming step, an interval between the protrusions is set to 0.1 μm or more and 10 μm or less. Manufacturing method.
起部の縦方向の高さを0.5μm以上、20μm以下とす
ることを特徴とする請求項1乃至請求項15の何れか1
項に記載の半導体結晶の製造方法。16. The method according to claim 1, wherein the height of the protrusion in the vertical direction is 0.5 μm or more and 20 μm or less in the step of forming the protrusion.
13. The method for producing a semiconductor crystal according to the above item.
起部の横方向の太さ、幅、又は直径を0.1μm以上、1
0μm以下とすることを特徴とする請求項1乃至請求項
16の何れか1項に記載の半導体結晶の製造方法。17. In the projecting portion forming step, the lateral thickness, width or diameter of the projecting portion is 0.1 μm or more,
17. The method of manufacturing a semiconductor crystal according to claim 1, wherein the thickness is set to 0 μm or less.
理、化学的処理、或いは切削や研磨等の物理的処理によ
り、 前記下地基板の前記突起部間の谷部の少なくとも一部の
露出領域の結晶性又は分子構造を劣化又は変化させるこ
とにより、前記露出領域における前記 III族窒化物系化
合物半導体の結晶成長速度aを低下させることを特徴と
する請求項1乃至請求項17の何れか1項に記載の半導
体結晶の製造方法。18. The projections of the undersubstrate by various etching, electron beam irradiation, optical processing such as laser, chemical processing, or physical processing such as cutting or polishing before the crystal growth step. By deteriorating or changing the crystallinity or molecular structure of at least a part of the exposed region of the valley between the parts, the crystal growth rate a of the group III nitride-based compound semiconductor in the exposed region is reduced. The method of manufacturing a semiconductor crystal according to claim 1, wherein
反応室に残し、略一定流量のアンモニア(NH3)ガスを前
記反応室に流したままの状態で、 前記基板を概ね「−100℃/min〜−0.5℃/mi
n」程度の冷却速度で略常温まで冷却することを特徴と
する請求項1又は請求項2、或いは、請求項4乃至請求
項18の何れか1項に記載の半導体結晶の製造方法。19. In the separating step, a substrate comprising the base substrate and the substrate layer is left in a reaction chamber of a growth apparatus, and a substantially constant flow rate of ammonia (NH 3 ) gas is allowed to flow into the reaction chamber. Then, the substrate is generally moved from -100 ° C / min to -0.5 ° C / mi.
19. The method for manufacturing a semiconductor crystal according to claim 1, wherein the semiconductor crystal is cooled to substantially normal temperature at a cooling rate of about "n".
チング等の、化学的或いは物理的な加工処理により除去
する残骸除去工程を有することを特徴とする請求項1又
は請求項2、或いは、請求項4乃至請求項19の何れか
1項に記載の半導体結晶の製造方法。20. A debris removing step of removing a broken debris of the protrusion remaining on the back surface of the substrate layer by a chemical or physical processing such as etching at least after the separating step. 20. The method for manufacturing a semiconductor crystal according to claim 1, wherein the semiconductor crystal is a semiconductor crystal.
に記載の半導体結晶の製造方法を用いて製造された、前
記半導体結晶を結晶成長基板として有することを特徴と
する III族窒化物系化合物半導体発光素子。21. A group III nitride comprising the semiconductor crystal as a crystal growth substrate manufactured by using the method of manufacturing a semiconductor crystal according to claim 1. Based compound semiconductor light emitting device.
に記載の半導体結晶の製造方法を用いて製造された、前
記半導体結晶を結晶成長基板とした結晶成長により製造
されたことを特徴とする III族窒化物系化合物半導体発
光素子。22. A semiconductor crystal produced by the method for producing a semiconductor crystal according to claim 1, wherein said semiconductor crystal is produced by crystal growth using said semiconductor crystal as a crystal growth substrate. A group III nitride compound semiconductor light emitting device.
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| DE60233386T DE60233386D1 (en) | 2001-02-14 | 2002-02-12 | METHOD FOR PRODUCING SEMICONDUCTOR CRYSTALS AND SEMICONDUCTOR LIGHT ELEMENTS |
| EP02711474A EP1367150B1 (en) | 2001-02-14 | 2002-02-12 | Production method for semiconductor crystal and semiconductor luminous element |
| PCT/JP2002/001159 WO2002064864A1 (en) | 2001-02-14 | 2002-02-12 | Production method for semiconductor crystal and semiconductor luminous element |
| KR10-2003-7010636A KR20030074824A (en) | 2001-02-14 | 2002-02-12 | Production method for semiconductor crystal and semiconductor luminous element |
| US10/467,566 US7052979B2 (en) | 2001-02-14 | 2002-02-12 | Production method for semiconductor crystal and semiconductor luminous element |
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| US5919305A (en) * | 1997-07-03 | 1999-07-06 | Cbl Technologies, Inc. | Elimination of thermal mismatch defects in epitaxially deposited films through the separation of the substrate from the film at the growth temperature |
| JP3525061B2 (en) * | 1998-09-25 | 2004-05-10 | 株式会社東芝 | Method for manufacturing semiconductor light emitting device |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW575908B (en) | 2004-02-11 |
| CN1863944A (en) | 2006-11-15 |
| JP4084541B2 (en) | 2008-04-30 |
| CN100414005C (en) | 2008-08-27 |
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