CN100414005C - Production method for semiconductor crystal and semiconductor luminous element - Google Patents
Production method for semiconductor crystal and semiconductor luminous element Download PDFInfo
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- CN100414005C CN100414005C CNB028046919A CN02804691A CN100414005C CN 100414005 C CN100414005 C CN 100414005C CN B028046919 A CNB028046919 A CN B028046919A CN 02804691 A CN02804691 A CN 02804691A CN 100414005 C CN100414005 C CN 100414005C
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- 230000012010 growth Effects 0.000 claims abstract description 223
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Abstract
A production method for a semiconductor crystal, which grows a semiconductor crystal consisting of a III nitride compound semiconductor on a base substrate by using a lateral crystal growth action to obtain a quality semiconductor crystal independent of the base substrate; and a semiconductor luminous element. The production method for a semiconductor crystal comprises the step of forming many protrusions on the base substrate, the step of crystal-growing the substrate layer, with at least part of the surfaces of the protrusions used as initial growth surfaces with which the substrate layer starts a crystal growth, until the growth surfaces are linked to one another to grow to at least a set of almost planes, and the step of separating the substrate layer from the base substrate by breaking the protrusions. Whereby, it is possible to obtain a high-quality semiconductor crystal free from cracks and low in dislocation density.
Description
Technical field
The present invention relates to by horizontal crystal growth effect, on bottom substrate, form the substrate layer that constitutes by III group-III nitride based compound semiconductor, obtain the manufacture method of the semiconductor crystal of crystal growth substrate.
The present invention relates to make the crystal growth that constitutes by III group-III nitride based compound semiconductor, obtain the method for semiconducter substrate by on the bottom substrate that forms by silicon (Si).The invention still further relates to the III group-III nitride based compound semiconductor element that this semiconducter substrate is made as the crystal growth substrate.
The present invention relates on bottom substrate, the semiconductor crystal that is made of III group-III nitride based compound semiconductor is grown up, obtain the independently method of high-quality semiconductor crystal from bottom substrate.
It is the manufacturing etc. of the various semiconductor element crystal growth substrates of representative that the present invention is suitable for LED etc.
Background technology
Generally know that, as illustrated in Figure 10, for example on bottom substrate, make gan nitride such as (GaN) carry out semiconductor crystal and grow up when being cooled to normal temperature then, a lot of transpositions and crackle are arranged on nitride semiconductor layer by silicon formations such as (Si).
Figure 11 illustration go up the mode sectional drawing of the existing semiconductor crystal of crystal growth at Si substrate (bottom substrate).In this crystal growth operation, adopted mocvd method.Shown in Figure 11 as this, go up generation " reactive site " and transposition, crackle etc. by the semiconductor crystal (GaN crystal etc.) that prior art goes up the high temperature growth at Si substrate (bottom substrate).
As on bottom substrate, the semiconductor crystal that is made of III group-III nitride based compound semiconductor is grown up, obtain the independently prior art of semiconductor crystal from this bottom substrate, for example generally know that the wet etching described in the publication communique " spy opens the manufacture method of flat 7-202265:III group-III nitride semiconductor " and/or on Sapphire Substrate by the HVPE method etc., the method that the GaN (purpose semiconductor crystal) of thick film is grown up, Sapphire Substrate is removed with laser radiation and grinding etc.
Disclosure of an invention
Like this, when on the layer (nitride semiconductor layer) of growing up a lot of transpositions and crackle being arranged, and when making device thereon, the result produces a lot of lattice imperfections and transposition, distortion, crackle etc. in device, become the reason that causes that device property worsens.
In addition, for example remove the bottom substrate that constitutes by silicon (Si) etc., only stay the layer of growing up, when expecting independently substrate (crystal), because of the effect of described transposition and crackle etc. can not get big area (1cm
2More than) product.
Transposition and crackle are that the result of the stress that produces according to the coefficient of thermal expansion differences of storeroom of the same race not and lattice parameter difference produces, and when making various semiconducter device with this crystal growth substrate, then cause the deterioration of device property.
In addition, near 1000 ℃～1150 ℃ of the crystal growth temperature of purpose semiconducter substrate (semiconductor crystal A), silicon (Si) and gan (GaN) reaction form polycrystal GaN (" reactive site " among the figure).Therefore, produce process high temperature crystal developmental process and be not easy to obtain problems such as monocrystalline GaN substrate.
In these prior aries, the problem that exists is: by bottom substrate (for example have, sapphire, silicon etc.) and III group-III nitride based compound semiconductor between thermal expansion rate variance and lattice parameter difference cause, when after the crystal growth operation is finished, lowering the temperature etc., at the purpose monocrystalline (for example: GaN etc.) go up stress application, on the purpose monocrystalline, produce a lot of transpositions and crackle.
For example, when using described such prior art, on the bottom substrate that forms by sapphire and/or silicon (Si) etc., make gan nitride semiconductor crystals such as (GaN) grow up, when being cooled to normal temperature then, stress by coefficient of thermal expansion differences and/or lattice parameter difference etc. causes produces a lot of transpositions and crackle on nitride semiconductor layer.
Like this, when going up at the layer (nitride semiconductor layer) of growing up when producing a lot of transpositions and crackle, when making device thereon, the result produces a lot of lattice imperfections and transposition, distortion, crackle etc. on device, become the reason that causes that device property worsens.
In addition, remove bottom substrate, only stay the layer of growing up, when expecting independently substrate (crystal), because of the effect of described transposition and crackle etc. can not get large-area product.When thick film is grown up, be linked to be and all crack on the purpose monocrystalline in long, so, be very easy to produce the part small pieces and problem such as peel off.
The present invention develops for solving described problem, and its purpose is to obtain there is not crackle, the low density high-quality semiconductor crystal of transposition (crystal growth substrate).
Another object of the present invention is to comparatively cheap silicon (Si) is made the high-quality semiconductor crystal that is used for obtaining not having crackle and polycrystalline piece (reactive site) as bottom substrate.Still a further object of the present invention is by the described semiconductor crystal of high quality manufacturing is made high-quality semiconducter device as the crystal growth substrate.
Another purpose of the present invention also is to obtain independently fine semiconductor crystal from bottom substrate.
For solving described problem, following method is effective.
Promptly, first method is by utilizing horizontal crystal growth effect, on bottom substrate, form the substrate layer that constitutes by III group-III nitride based compound semiconductor, obtain the manufacturing process of semiconductor crystal independently from bottom substrate, be provided with: jut forms operation, forms a plurality of juts on bottom substrate; The crystal growth operation, the initial growth face that at least a portion on this jut surface begins crystal growth as substrate layer, this growth face makes the substrate layer crystal growth, grows to each jut and is interconnected to the general plane that links to each other at least; Separation circuit, by broken protrusion portion, substrate layer is separated with bottom substrate, in described crystal growth operation, by adjusting the raw material supplying amount q of described III group-III nitride based compound semiconductor, the difference (b-a) of at least a portion of the paddy portion between the described jut of described bottom substrate being exposed the rate of crystal growth b of the rate of crystal growth a of described III group-III nitride based compound semiconductor in zone and described jut head is controlled to be maximum value.
But said here " III group-III nitride based compound semiconductor " generally comprises binary, ternary or quaternary general formula " Al
xGa
yIn
(1-x-y)N (0≤x≤1,0≤y≤1,0≤x+y≤1) " semi-conductor of any mixed crystal ratio of expression, and also the semi-conductor that has added p type or n type impurity also is decided to be the category of this specification sheets " III group-III nitride based compound semiconductor ".
In addition, the described III element (Al of family, Ga, In) part in is with boron (B) and thallium displacements such as (Tl), or the part of nitrogen (N) yet is decided to be the category of this specification sheets " III group-III nitride based compound semiconductor " with phosphorus (P), arsenic (As), antimony (Sb), bismuth metathetical such as (Bi) semi-conductor etc.
As described p type impurity, for example can add magnesium (Mg) and/or calcium (Ca) etc.
As described n type impurity, for example can add silicon (Si) and sulphur (S), selenium (Se), tellurium (Te) or germanium (Ge) etc.
These impurity both can add two kinds more than the element simultaneously, also can add amphitypy (P type and n type) simultaneously.
For example, as shown in Figure 1, have on the bottom substrate of a plurality of juts, when the substrate layer (semiconductor crystal) that is made of III group-III nitride based compound is grown up, by adjusting size and the configuration space and all conditions of crystal growth etc. of jut, can between each jut, (side of jut) form semiconductor crystal not by " cavity " of lamination.Therefore, compare with the height of jut, when making the thickness of substrate layer fully greatly, internal stress or external stress are concentrated easily and are acted on this jut.Consequently, particularly these stress are as to effect such as the shear-stress of jut and this stress when becoming big, and jut ruptures.Therefore, as long as utilize this stress just can separate (peeling off) to bottom substrate with substrate layer easily.Can obtain independently crystal (substrate layer) from bottom substrate by this method.
Described " cavity " forms greatly more, and stress (shear-stress) is easy more concentrated at jut.
For example, as also knowing from Fig. 1, by forming described the sort of jut, make the contact site of bottom substrate and substrate layer (or the crystal semiconductor layer of wishing) be defined narrowly, so, distortion according to both lattice parameter differences is difficult to produce, and " according to the stress of the lattice parameter difference between bottom substrate and substrate layer " is relaxed.Therefore, substrate layer (semiconductor crystal of hope) is when carrying out crystal growth, and the unwanted stress that the substrate layer in growing up is worked is suppressed, and the generation density of transposition and crackle is lowered.
When bottom substrate was separated (peeling off) with substrate layer, the part of substrate layer both can remain in bottom substrate on one side, or the part of bottom substrate (for example: the fracture remains of jut) also can remain in substrate layer on one side.That is, described separation circuit is not that these materials part remains are not all had, and each material separates as prerequisite (prerequisite) fully.
In the crystal growth operation of described first or second method, by adjusting the raw material supplying amount q of III group-III nitride based compound semiconductor, paddy portion at least a portion between the bottom substrate jut is exposed the field, and the difference (b-a) of the rate of crystal growth b at the rate of crystal growth a of III group-III nitride based compound semiconductor and jut top is controlled at roughly maximum value.
At this moment the same with aforesaid method, " according to the stress of the lattice parameter difference between bottom substrate and substrate layer " that during the substrate layer crystal growth substrate layer worked is relaxed, and the crystal structure of substrate layer is stable, is difficult to take place transposition and crackle on substrate layer.This effect and effect in the cavity between each jut (side of jut) laterally grow up when obvious more, it is more remarkable to become more.
If form the cavity, then shear-stress concentrates on jut easily, in described separation circuit, utilizes shear-stress easily bottom substrate to be separated with substrate layer in the side of jut (between each jut).This effect and effect are that the cavity of (side of jut) between each jut is big more remarkable more.
Second method that solves described problem is, in these first methods, by substrate layer and bottom substrate cooling or heating, makes the stress of generation according to substrate layer and bottom substrate coefficient of thermal expansion differences, utilizes this stress to implement the fracture of described jut.
Can generate described stress easily according to this method.
Third party's method is, utilizing horizontal crystal growth effect, on bottom substrate, forming the substrate layer that constitutes by III group-III nitride based compound semiconductor, obtaining in the manufacturing process of semiconductor crystal, be provided with: jut forms operation, forms a plurality of juts on bottom substrate; The crystal growth operation, the initial growth face that at least a portion on this jut surface begins crystal growth as substrate layer, this growth face makes the substrate layer crystal growth, grow to each jut is interconnected to the general plane that is connected at least.In this crystal growth operation, by adjusting the raw material supplying amount q of III group-III nitride based compound semiconductor, paddy portion at least a portion is exposed the field between the bottom substrate jut, and the difference (b-a) of the rate of crystal growth b at the rate of crystal growth a of III group-III nitride based compound semiconductor and jut top is controlled at roughly maximum value.
According to this method, near the rate of crystal growth the jut head relatively becomes greatly, describedly exposes near the crystal growth in zone and comparatively is suppressed, and becomes main flow near the crystal growth the top.Consequently, near horizontal growth (ELO) apparition of the substrate layer that begins the jut top, " according to the stress of the lattice parameter difference between bottom substrate and substrate layer " that works at substrate layer during the substrate layer crystal growth is relaxed.Therefore, the crystal structure of substrate layer is stable, is difficult to take place transposition and crackle on substrate layer.
During as horizontal growth (ELO) apparition of substrate layer, for example produce relatively macroscopic void sometimes in the side of jut (between each jut).
For example, as shown in Figure 1, on the surface of bottom substrate, form when concavo-convex with suitable size, interval or cycle, general beyond near the peripheral part the bottom substrate outer peripheral sidewall, with compare near protuberance (jut) top, the feed rate of the crystalline material time per unit unit surface of recess (paddy portion) tails off easily.Though this tendency also depends on the air flow rate, temperature, direction of crystalline material etc.,, can be controlled at roughly maximum value to described difference (b-a) by or control rightly optimum these all conditions.
Cubic method is, described first or third party's method in, described raw material supplying amount q fix on 1 μ mol/min above～below the 100 μ mol/min.
Better is, described raw material supplying amount q more than the 5 μ mol/min～below the 90 μ mol/min for well.As ideal value especially be, though it also depends on all conditions such as the kind of the specification of bottom substrate such as the size of jut of formation and shape, configuration space and base feed and supply flow direction, crystal growth method, is ideal about 10～80 μ mol/min probably.This is worth when excessive, then is difficult to described difference (b-a) is controlled at roughly maximum value, so, be difficult to that (side of jut) forms big cavity between each jut.Therefore, during this situation, be difficult to be relaxed, produce transposition etc. according to the intracrystalline stress ratio of lattice parameter difference, the crystallinity of substrate layer monocrystalline worsens easily, and this is unfavorable.
Utilize stress (shear-stress) bottom substrate with when substrate layer separates, if the side of jut does not have cavity or should the cavity hour, stress also is difficult to concentrate on jut, the fracture of jut is difficult to take place, and is unfavorable.
On the other hand, when raw material supplying amount q was too small, then crystal growth too expends time in, and was unfavorable aspect productivity, is unfavorable.
The 5th method is, described first or third party's method in, use silicon (Si) or silicon carbide (SiC) as the material of bottom substrate.
As the material of other bottom substrate, for example GaN, AlN, GaAs, InP, GaP, MgO, ZnO, MgAl
2O
4Deng being useful, and sapphire, spinel, manganese oxide, gallium oxide lithium (LiGaO
2), moly-sulfide (MoS) etc. also can use.
But when using shear-stress according to coefficient of thermal expansion differences that bottom substrate is separated with substrate layer, preferably select the big combination of coefficient of thermal expansion differences of two storerooms, and preferably be chosen in bottom substrate the material that ruptures takes place on one side easily.
The 6th method is, described first or third party's method in, use Si (111) as the material of bottom substrate, form in the operation at jut, the field of exposing of paddy portion makes Si (111) face unexposedly form jut between the bottom substrate jut.
According to present method, can suppress little to the rate of crystal growth a that face exposes in described paddy portion, so, can described difference (b-a) stable fixedly keeping the crystalline while as before reach roughly maximization.
The 7th method is, described first or after the jut of third party's method forms operation, is provided with by " Al on the surface of jut at least
xGa
(1-x)N (0＜x≤1) " form the operation of buffer layer.
But and described buffer layer, also can be additionally again with described buffer layer by the middle layer of roughly the same composition the (for example AlN and AlGaN) periodically, or with other layers alternately, or constitute in addition lamination of multi-ply construction ground.
By the lamination in sort buffer layer (or middle layer), can relax the stress that substrate layer (grow up layer) is worked that causes because of the lattice parameter difference etc., by improving crystallinity with existing same action principle.
The all directions method is, in described the 7th method, the vertical height following film forming of the thickness of buffer layer at jut.As absolute object, that the thickness of buffer layer is preferably in about 0.01 μ m is above～below the 1 μ m.
By this method, the crystal layer that only makes formed hope on the buffer layer (for example: the GaN layer) grow up in horizontal high-quality.That is, by this method, " according to the stress of lattice parameter difference " that the crystal layer that forms on buffer layer runs into when carrying out crystal growth is alleviated, and can effectively reduce transposition density.
The AlN of formation buffer layer etc. and AlGaN etc., the easy film forming on roughly whole on the surface that bottom substrate is exposed, and, originally, form the GaN of desirable crystal growth layer, have the tendency of laterally growing up easily, but, can form more reliably in the side of jut in big " cavity " according to described method than AlN and AlGaN etc.
By this method substrate layer when bottom substrate is separated, crystal layer (the desirable layer that forms on buffer layer) also directly exposes at the back side (side that bottom substrate has) of substrate layer on a large scale.Therefore, when forming electrode, suppress resistance and become easy at the back side of substrate layer.
The thickness of buffer layer as described, is roughly appropriate scope about about 0.01 μ m～1 μ m, but more preferably 0.1 μ m above～0.5 μ m is following for well.When this thickness was blocked up, the cavity diminished easily, was unfavorable.This thickness is crossed when approaching, and roughly the film forming change is difficult equably for buffer layer.Particularly, when producing buffer layer film forming irregular (not having abundant film forming part) near jut top, also being easy to generate irregularly on the crystallinity, is unfavorable.
The 9th method is, described first or the crystal growth operation of third party's method in, the thickness of substrate layer is fixed on more than the 50 μ m.
Make more than the preferably about 50 μ m of thickness of substrate layer (III group-III nitride based compound semiconductor) of crystal growth, this thickness is thick more, and the tensile stress of substrate layer is relaxed more, and the generation density of substrate layer transposition and crackle is more little.And, can make substrate layer firm simultaneously, described shear-stress concentrates on described jut easily.
The tenth method is, described first or the crystal growth operation of third party's method in, change the crystal growth method halfway, be altered to the fast crystal growth method of rate of crystal growth from the slow crystal growth method of rate of crystal growth.
For example, before crystal growth face becomes continuous general plane shape, as adopt easily make as described in difference (b-a) (for example: the MOVPE method) reach roughly maximum crystal growth method, then, adopt easily thickness efficiently reach more than the 50 μ m the crystal growth method (for example: the HVPE method), can obtain the semiconductor crystal of excellent in crystallinity at short notice.
The 11 method is, described first or the jut of third party's method form in the operation, jut by roughly uniformly-spaced or roughly some cycles ground dispose, form described jut like this.
Whereby, the growth condition that makes horizontal growth is approximate equality on the whole, is difficult to produce irregular on the crystallinity quality.The top of paddy portion between jut, be difficult to produce partial deviation in time before covering fully with substrate layer, so, for example, from the slow crystal growth method of rate of crystal growth to the fast crystal growth method of rate of crystal growth, when changing the crystal growth method halfway, its time is decision accurately, in early days or uniquely easily.
Use present method, described cavity becomes the size of each approximate equality, can distribute described shear-stress on each jut approximate equality ground, so the fracture of whole jut evenly produces, the separation energy of bottom substrate and substrate layer is reliably implemented.
The 12 method is, forms in the operation at the jut of described the 11 method, Yi Bian be being that summary equilateral triangle more than the 0.1 μ m is to form jut on the lattice point of plane trigonometry lattice of benchmark.
Can implement described the 12 method more specifically, accurately and reliably by this method, therefore, can reduce the transposition number reliably.
The 13 method is, described first or the jut of third party's method form in the operation, the horizontal section shape of jut is formed roughly equilateral triangle, roughly orthohexagonal, circular or square.
By this method, the crystal that forms by III group-III nitride based compound semiconductor, consistent easily at the crystalline axis direction each several part, or can be constrained to the cross-directional length of jut (thickness) in horizontal direction arbitrarily much the same, so, can suppress the transposition number.Particularly, orthohexagonal is consistent with the crystalline structure of semiconductor crystal easily with equilateral triangle, so be better.Circle and square we can say that forming it aspect manufacturing technology easily has the advantage that adopts existing general processing technology level to make.
The tenth cubic method is, described first or the jut of third party's method form in the operation, the configuration space of jut (configuration cycle) fix on 0.1 μ m above～below the 10 μ m.Better is, though also depend on the implementation condition of crystal growth, the configuration space of jut about 0.5～8 μ m for well.But this configuration space is meant the distance between each approaching mutually jut central point.
Can cover the paddy portion of jut top with substrate layer by this method, between jut, can form the cavity simultaneously.
When this is worth when too small, almost can not get the effect of ELO, crystallinity worsens.And what form is empty too small, and only otherwise the thickness of substrate layer is made size more than the needs, the fracture of jut just is not easy.
When this is worth when excessive, can not cover the paddy portion of jut top reliably with substrate layer, can not obtain crystallinity evenly and fine crystal (substrate layer).
Perhaps, when this be worth further when excessive, paddy portion expose face excessive, almost can not get the effect of ELO, and can not form the cavity fully, so crystallinity worsens, only otherwise the thickness of substrate layer is made size more than needing, the fracture of jut just is not easy.
The 15 method is, described first or the jut of third party's method form in the operation, vertically highly being decided to be more than the 0.5 μ m of jut～below the 20 μ m.Better is, though also depend on the implementation condition of crystal growth, vertical height of jut about 0.8～5 μ m for well.
When this was highly too short, the same when not having jut, the effect, the crystallinity that almost can not get ELO worsened.In addition, when this is highly too short, can not form described cavity.
When this excessive height, form jut self and become difficulty, to expend the necessary above time for forming jut, or the necessary above bottom substrate material of consumption, be unfavorable.In addition, during this excessive height, shear-stress is distributed to the vertical of jut, is difficult to make jut to rupture reliably.
The 16 method is, described first or the jut of third party's method form in the operation, horizontal thickness, width or the diameter of jut are decided to be more than the 0.1 μ m～below the 10 μ m.Better is, though also depend on the implementation condition of crystal growth, horizontal thickness, width or the diameter of jut about 0.5～5 μ m for well.
When this thickness is crossed when thick, become big according to the lattice parameter difference in the stress influence that substrate layer (layer of growing up) works, increase the transposition number of substrate layer easily.If when meticulous, then form jut self and become difficulty, or the rate of crystal growth b of jut head be slack-off, is unfavorable.
When making the jut fracture by stress (shear-stress etc.), if horizontal thickness, width or the diameter of jut are excessive, the part that easy generation can not reliably be ruptured is unfavorable.
The size of the stress influence that substrate layer (grow up layer) is worked according to the lattice parameter difference not only depends on the horizontal thickness of jut (length), and depends on the configuration space etc. of jut.If these setting ranges are inappropriate words, then as described, become the transposition number that increases substrate layer greatly, easily according to the stress influence of lattice parameter difference, are unfavorable.
Because thickness, width or diameter horizontal near the jut head are just like described optimum value or OK range, so, top, the bottom surface of jut or the shape of horizontal section, at least be the shape (island) of partial closure, and be to seal into being shaped as of convex laterally, better is, above this, the shape of bottom surface or horizontal section, be circular or roughly regular polygon etc. for well.By this setting, reliable easily described optimum value or the OK range that realizes any horizontal direction.
The 17 method is, described first or third party's method in, before the crystal growth operation, by photoprocess, chemical treatment or physical treatments such as cutting and grinding such as various etchings, electron beam radiation treatment, laser, make the paddy portion at least a portion between the bottom substrate jut expose regional crystallinity or molecular structure generation deterioration or variation, this rate of crystal growth a that exposes III group-III nitride based compound semiconductor in the zone is reduced.
By this method, the difference (b-a) of described rate of crystal growth is increased more.Therefore, according to this method, near the jut head rate of crystal growth relatively becomes big, so, by with above-mentioned same effect, during the substrate layer crystal growth, " according to the stress of the lattice parameter difference between bottom substrate and substrate layer " that substrate layer is worked is relaxed, on substrate layer, be difficult to take place transposition and crackle.
The tenth from all directions method be in described arbitrary separation circuit,, to remain in the reaction chamber of growth apparatuses, so that the ammonia (NH of certain flow roughly by the substrate that bottom substrate and substrate layer constitute
3) gas flows under the intact state in the reaction chamber, and substrate is cooled to roughly normal temperature with the about speed of cooling about " 100 ℃/min～-0.5 ℃/min ".
For example, by this method, can remain on the crystallographic former state of substrate layer and implement described separation circuit under the high-quality state.
The 19 method is, is provided with remains at least after described arbitrary separation circuit and removes operation, and the fracture remains remaining in substrate layer back side jut carry out processing treatment with method chemistry such as etching or physics and remove.
According to this method, when (having peeled off the side of bottom substrate) at the substrate layer back side and formed electrode such as semiconductor light-emitting elements, can be suppressed at the not even resistance of electric current of the near interface generation of electrode and substrate layer, therefore, can seek to reduce driving voltage and/or improve luminous intensity etc.
In addition, by removing the fracture remains of jut, when electrode is also utilized as the speculum of semiconductor light-emitting elements etc., make that the absorption and the scattering of light reduces near the minute surface, improved reflectivity, so, luminous intensity improved.
For example, when handling by Physical Processing such as grindings, implementing these remains and remove operation etc., buffer layer up to the substrate layer back side also can be removed, or the Flatness at the raising substrate layer back side, so, more can strengthen electric current not even resistance inhibition or reduce near the absorption of the light minute surface and the described action effect of scattering etc.
The 20 method is, utilize horizontal crystal growth effect, on the bottom substrate that forms by silicon (Si), in the semiconducter substrate manufacturing process that the semiconductor crystal A that is made of III group-III nitride based compound semiconductor grows up, comprise: prevent reaction process, on the bottom substrate prevent the responding layer film forming by high crystalline material B constitutes on fusing point or thermotolerance than semiconductor crystal A; Jut forms operation, by etching method chemistry or physics, is preventing responding layer on the single face of film forming one side, do not make bottom substrate expose from preventing that responding layer from forming a plurality of juts; The crystal growth operation as the initial growth face that semiconductor crystal A begins crystal growth, makes at least a portion on this jut surface semiconductor crystal A carry out crystal growth, and each is interconnected to and is at least continuous general plane to grow to this growth face.
But by the described semiconducter substrate that described semiconductor crystal A constitutes, both can be single layer structure, also can be multilayer structure (multilayered structure).
Here said " III group-III nitride based compound semiconductor " generally comprises binary, ternary or quaternary general formula " Al
xGa
yIn
(1-x-y)N (0≤x≤1,0≤y≤1,0≤x+y≤1) " semi-conductor of any mixed crystal ratio of expression, and also the semi-conductor that has added p type or n type impurity also is decided to be the category of this specification sheets " III group-III nitride based compound semiconductor ".
In addition, the described III element (Al of family, Ga, In) part in is with boron (B) and thallium displacements such as (Tl), or the part of nitrogen (N) yet is decided to be the category of this specification sheets " III group-III nitride based compound semiconductor " with phosphorus (P), arsenic (As), antimony (Sb), bismuth metathetical such as (Bi) semi-conductor etc.
As described p type impurity, for example can add magnesium (Mg) and/or calcium (Ca) etc.
As described n type impurity, for example can add silicon (Si) or sulphur (S), selenium (Se), tellurium (Te) or germanium (Ge) etc.
These impurity both can add two kinds more than the element simultaneously, also can add amphitypy (P type and n type) simultaneously.
Fig. 5 is the mode sectional drawing that illustrates the semiconductor crystal manufacturing process of key concept of the present invention.This prevents that responding layer is used to prevent Si and gallium nitride based semi-conductor reaction, like this, by on bottom substrate (Si substrate), by higher than gallium nitride based semi-conductor (semiconductor crystal A) fusing point or thermotolerance, for example formation such as SiC and AlN prevents responding layer (crystalline material B) film forming, even when carrying out long-time crystal growth, near silicon interface, do not form described " reacting part " at gallium nitride based semi-conductor (semiconductor crystal A) yet.
By forming a plurality of juts, gallium nitride based semi-conductor (semiconductor crystal A) is that starting point is also in horizontal growth with the flat top portion of jut.Like this, be difficult to produce according to the stress that prevents lattice parameter difference between responding layer and gallium nitride based semiconductor crystal A, stress is relaxed significantly.
Relaxed by forming a plurality of juts, act on the stress that prevents responding layer, these stress are difficult to work on the responding layer preventing, form longitudinal crack, thereby, preventing to be difficult on the responding layer produce to connect crackle longitudinally.Therefore,, can interdict bottom substrate (Si substrate) and gallium nitride based semi-conductor (semiconductor crystal A) fully with the responding layer that prevents that does not connect longitudinal crack, so, the generation of described the sort of " reacting part " can be prevented more reliably.
For example, by forming described the sort of jut, preventing responding layer and semiconducter substrate (promptly, the crystal semiconductor layer A that wishes) contact site limits narrowly, so, distortion according to both lattice parameter differences is difficult to become big, and " according to the stress of lattice parameter difference between bottom substrate and semiconducter substrate " is relaxed.Therefore, when semiconducter substrate (the semiconductor crystal A of hope) crystal growth, the unwanted stress that the semiconducter substrate in growing up is worked is suppressed, and has reduced the generation density of transposition and crackle.
That is,, on gallium nitride based semi-conductor (semiconductor crystal A), be difficult to take place transposition, and the generation density of crackle is cut down especially also by above stress mitigate effects.
By the above effect and the effect that multiplies each other, do not have described " reacting part " and, the high-quality semiconductor substrate that crackle, transposition density are fully suppressed (semiconductor crystal A) may obtain or become obtaining easily.
Buffer layer C among this figure, the form of adopt inserting as required also can, implementing in the present invention, the sort buffer layer is uncertain to be necessary integrant.That is,, also can obtain certain above effect of the present invention and effect even in the occasion of not establishing buffer layer.
The 21 method is that in described the 20 method, described semiconductor crystal A is by satisfying composition formula " Al
xGa
yIn
(1-x-y)N (0≤x＜1,0＜y≤1,0＜x+y≤1) " III group-III nitride based compound semiconductor constitute.
The 22 method is, in described the 20 method, prevents from the crystalline material B of responding layer to use silicon carbide (SiC), aluminium nitride (AlN) or spinel (MgAl as formation
2O
4).
The 23 method is, in described the 20 method, prevents from the crystalline material B of responding layer to use the aluminium ratio of components at least at the AlGaN more than 0.30, AlInN or AlGaInN as formation.And, as crystalline material B, preferably select lattice parameter less than the high stable material of the more firm thermotolerance of the interatomic bond force rate of 3.18A (fusing point).
The 20 cubic method is, in arbitrary method of described the 20,21,22, laterally grows up by making growth face, and each is interconnected, and forms the cavity that semiconductor crystal A does not have lamination between jut.
If this cavity is big more unreasonablely to be thought, but when excessive, then is difficult to obtain the growth face of general plane shape sometimes after connection, so will note.If when too small, the stress mitigate effects that produces of then laterally growing up also diminishes, so will note.
The 25 method is, in arbitrary method of described the 20,21,22, that the paddy portion thickness that prevents responding layer between jut forms 0.1 μ m is above～and below the 2 μ m.
This thickness is crossed when thin, then thickness with irregular or form the described crystalline material B that prevents responding layer neither very stable material, so, can not interdict gallium (Ga) or gan (GaN) and silicon (Si) fully.Therefore, the formation effect that prevents " reacting part (polycrystalline GaN) " according to these reactions can not fully obtain.
When the thickness that prevents responding layer paddy portion is blocked up, then be easy to generate crackle in the paddy portion that prevents responding layer, can not interdict gallium (Ga) or gan (GaN) and silicon (Si) fully.Therefore, the effect that " reacting part " forms that prevents according to these reactions can not fully obtain.
When the thickness that prevents responding layer paddy portion was blocked up, then only this a bit prevented that the lamination time of responding layer and lamination material are just especially important, and also undesirable at aspects such as production costs.
The 26 method is, form in the operation at the jut of described arbitrary method of the 20,21,22, jut vertically highly form 0.5 μ m above～below the 20 μ m.Better is jut vertically height more than the 1 μ m～below the 5 μ m for well.
Cross when low when this jut, described cavity diminishes, and the horizontal growth of semiconductor crystal A is insufficient, and the stress mitigate effects is insufficient, is unfavorable.When this jut was too high, then only this a bit prevented that the lamination time of responding layer and etching period or lamination material etc. are just especially important, and also undesirable at aspects such as production costs.
The 27 method is, forms in the operation at the jut of described arbitrary method of the 20,21,22, horizontal thickness, width or the diameter of jut are formed more than the 0.1 μ m～below the 10 μ m.Better is, though also depend on the implementation condition of crystal growth, horizontal thickness, width or the diameter of jut about 0.5～5 μ m for well.
When this thickness is crossed when thick, become the transposition number that increases semiconducter substrate greatly, easily in the stress influence that semiconducter substrate (layer of growing up) works according to the lattice parameter difference.If when meticulous, then the formation of jut self becomes difficulty, or the rate of crystal growth b of jut head is slack-off, is unfavorable.
The 20 all directions method is, in arbitrary method of described the 20,21,22, be provided with separation circuit, by semiconductor crystal A and bottom substrate being cooled off or being heated, produce stress, the jut fracture is separated semiconductor crystal A with bottom substrate by utilizing this stress according to semiconductor crystal A and bottom substrate coefficient of thermal expansion differences.
For example, as shown in Figure 5, have on the bottom substrate of a plurality of juts, when the semiconducter substrate (semiconductor crystal A) that is made of III group-III nitride based compound is grown up, by adjusting size and the configuration space and all conditions of crystal growth etc. of jut, can between each jut, (side of jut) form semiconductor crystal A not by " cavity " of lamination.Therefore, compare with the height of jut, abundant when thick as semiconducter substrate (semiconductor crystal A) is made, internal stress or external stress are concentrated easily and are acted on this jut.Consequently, particularly, these stress work to jut as shear-stress etc., and this stress is when becoming big, and jut ruptures.
Therefore, as long as utilize this stress just can easily separate (peeling off) to bottom substrate with semiconducter substrate.
In addition, described " cavity " forms greatly more, the easy more jut that concentrates on of stress (shear-stress).
That is, owing to just can generate described stress easily according to described hentriaconta-method, so semiconductor crystal A can easily separate with bottom substrate.
When bottom substrate was separated (peeling off) with semiconducter substrate, the part that the part of semiconducter substrate both can remain in bottom substrate one side or bottom substrate (for example: the fracture remains of jut) also can remain in semiconducter substrate one side.That is, described separation circuit is not that these materials part remains are not separated each material as prerequisite (prerequisite) with all having fully.
Removing of this fracture remains etc. also can use well-known method such as grinding and etching to implement as required.
The 29 method is, in the crystal growth operation of described arbitrary method of the 20,21,22, more than semiconductor crystal A lamination 50 μ m.
When this thickness is thick more, the tensile stress of semiconducter substrate (semiconductor crystal A) is relaxed more, the generation density of semiconducter substrate transposition and crackle reduces, and semiconducter substrate is firm simultaneously, so, make described stress concentration at described jut easily.
The thickness of bottom substrate (Si substrate) is preferably in below the 300 μ m.When this thickness is thin more, the tensile stress of semiconducter substrate (semiconductor crystal A) is relaxed more, the generation density of semiconducter substrate transposition and crackle reduces.But the thickness of bottom substrate is during less than 50 μ m, and the absolute strength of bottom substrate self has problems, and is difficult to keep high productivity.Therefore, in order to ensure the quality and the productivity of the crystal growth substrate of making, that the thickness of bottom substrate is preferably in 50 μ m is above～below the 300 μ m.
Comparatively speaking, make the thickness of the thickness of semiconducter substrate (semiconductor crystal A) of crystal growth and bottom substrate (Si substrate) much the same or be preferred more than it.By this setting, the tensile stress of semiconducter substrate is relaxed easily, the generation of semiconducter substrate transposition and crackle is than significantly being suppressed in the past.Comparatively speaking, thick more this effect of semiconducter substrate is big more.
The 30 method is, in the crystal growth operation of described the 20 method, by adjusting the raw material supplying amount q of III group-III nitride based compound semiconductor, the difference (b-a) that paddy portion at least a portion between the bottom substrate jut is etched the rate of crystal growth b at the rate of crystal growth a of III group-III nitride based compound semiconductor in zone and jut top is controlled at roughly maximum value.
According to this method, near the rate of crystal growth the jut top relatively becomes greatly, describedly is etched near the crystal growth in zone and comparatively is suppressed, and near crystal growth from the head becomes main flow.Consequently, horizontal growth apparition near begin the jut head semiconducter substrate (semiconductor crystal A), when semiconductor substrate crystal was grown up, " according to the stress that prevents the lattice parameter difference between responding layer and semiconducter substrate " that semiconducter substrate is worked was relaxed.Therefore, the crystal structure of semiconducter substrate is stable, is difficult to take place transposition and crackle on semiconducter substrate.
During horizontal growth (ELO) apparition of semiconducter substrate, for example, be easy to generate bigger cavity in the side of jut (between each jut).
On the surface of bottom substrate, form when concavo-convex with suitable size, interval or cycle, generally except that near the peripheral part the bottom substrate outer peripheral sidewall, with compare near protuberance (jut) top, recess (paddy portion) tails off on the feed rate of crystalline material time per unit unit surface easily.Though this tendency also depends on the air flow rate, temperature, direction of crystalline material etc.,, can be controlled at roughly maximum value to described difference (b-a) by or control rightly optimum these all conditions.
The hentriaconta-method is, the described raw material supplying amount q in described the 30 method be set in 1 μ mol/min above～below the 100 μ mol/min.
Better is, described raw material supplying amount q more than the 5 μ mol/min～below the 90 μ mol/min for well.As better value, though it also depends on the kind of the specification of bottom substrate such as the size of jut of formation and shape, configuration space and base feed and supply flow to all conditions such as, crystal growth methods, is ideal about about 10～80 μ mol/min.When this is worth when excessive, then be difficult to described difference (b-a) is controlled at roughly maximum value, so, be difficult to that (side of jut) forms big cavity between each jut.Therefore, in this case, produced transposition etc. according to the crystal internal stress of lattice parameter difference is difficult to relax, semiconducter substrate monocrystalline crystallinity worsens easily, is unfavorable.
Utilize stress (shear-stress) bottom substrate with when semiconducter substrate is separated, if the side of jut does not have cavity or should the cavity hour, stress also is difficult to concentrate on jut, the fracture of jut is difficult to take place, and is unfavorable.
On the other hand, when raw material supplying amount q was too small, then crystal growth too expends time in, and was unfavorable aspect productivity, is unfavorable.
The 32 method is in described the 20 method, after jut forms operation, to be provided with one and to form by " Al on the surface of jut at least
xGa
(1-x)N (0＜x≤1) " operation of the buffer layer C that constitutes.
But, described buffer layer C is semiconductor layers such as near grow up 400 ℃～1100 ℃ AlN and AlGaN, this buffer layer C also can be additionally again with described buffer layer C by the middle layer (following only say sometimes " buffer layer ") of roughly the same composition the (for example AlN and AlGaN) periodically, or with other layers alternately, or constitute multilayered structure ground lamination in semiconducter substrate (semiconductor crystal A).
By the lamination in these buffer layers (or middle layer), can relax the stress that semiconducter substrate (grow up layer) is worked that causes by the lattice parameter difference etc., by with existing same action principle, can improve crystallinity.
In addition, this effect and effect are remarkable especially when formation prevents that the crystalline material B of responding layer from being silicon carbide (SiC) etc.
The 33 method is, in described the 32 method, the thickness of buffer layer C is formed more than the 0.01 μ m～below the 1 μ m.
Can only make the desirable semiconductor crystal A that on buffer layer, forms (for example: the GaN layer) grow up by this method in horizontal high-quality.
The thickness of buffer layer as mentioned above, is general appropriate scope about about 0.01 μ m～1 μ m, but more preferably 0.1 μ m above～0.5 μ m is following for well.When this thickness was blocked up, the cavity diminished easily, was unfavorable.When this thickness is crossed when thin, buffer layer roughly equably film forming become difficulty.Particularly, when producing buffer layer film forming irregular (not having abundant film forming part) near jut top, also being easy to generate irregularly on the crystallinity, is unfavorable.
The 30 cubic method is, form in the operation at the jut of described the 20 method, jut by roughly uniformly-spaced or roughly some cycles ground dispose, form described jut like this.
Whereby, the growth condition of so horizontal growth is approximate equality on the whole, is difficult to produce irregular on the crystallinity quality.
Use present method, described cavity becomes the size of each approximate equality, can described shear-stress approximate equality be distributed in each jut, so the fracture of whole jut evenly produces, the separation energy of bottom substrate and semiconducter substrate is implemented reliably.
Paddy portion top between jut, in time before covering fully with semiconducter substrate, be difficult to produce partial deviation, so, for example, to the fast crystal growth method of rate of crystal growth, when changing the crystal growth method halfway, its period is decision accurately, in early days or uniquely easily from the slow crystal growth method of rate of crystal growth.
The 35 method is, forms in the operation at the jut of described the 30 cubic method, Yi Bian being that roughly equilateral triangle more than the 0.1 μ m is to form jut on the lattice point of plane trigonometry lattice of benchmark.
By this method, can described the 15 method more specifically, correctly implement reliably therefore, can reduce the transposition number reliably.
The 36 method is, form in the operation at the jut of described the 20,21,22 methods, the horizontal section shape of jut becomes roughly equilateral triangle, roughly orthohexagonal, circular, essentially rectangular, almost diamond or almost parallel tetragon.
By this method, the crystal that forms by III group-III nitride based compound semiconductor, consistent easily at the crystalline axis direction each several part, or can be constrained to the cross-directional length of jut (thickness) to any horizontal direction much the same, so, can suppress the transposition number.Particularly, orthohexagonal and equilateral triangle and parallelogram etc., consistent with the crystalline structure of semiconductor crystal easily, so be better.Circle and rectangle are seen easy formation from the manufacturing technology aspect, have the advantage of making according to the present situation of existing general processing technology level.
The 37 method is, forms in the operation at the jut of described the 20,21,22 methods, make the configuration space of jut become 0.1 μ m above～below the 10 μ m.Better is, though also depend on the implementation condition of crystal growth, the configuration space of jut about 0.5～8 μ m for well.But this configuration space is meant the distance between each approaching mutually jut central point.
By this method, can the paddy portion of jut top be covered with purpose semiconducter substrate (semiconductor crystal A), can between jut, (the paddy portion of jut) form the cavity simultaneously.
When this is worth when too small, almost can not get the effect of ELO, can not obtain sufficient stress mitigate effects, crystallinity worsens.In addition, formation empty too small, making only otherwise the thickness of semiconducter substrate needs above size, and the fracture of jut just is not easy.
When this is worth when excessive, can not the paddy portion of jut top be covered reliably with semiconducter substrate, can not obtain crystallinity evenly and fine semiconducter substrate (semiconductor crystal A).
Perhaps, when this be worth further when excessive, paddy portion expose face excessive, almost can not get the effect of ELO, and can not form the cavity fully
The 30 all directions method is, preventing in the reaction process of described the 20,21,22 methods, preventing the both sides film forming of responding layer on bottom substrate.
Can prevent or relax the warpage (bending) of the bottom substrate (Si substrate) that after preventing reaction process, produces like this.
The 39 method is, the semiconductor crystal that III group-III nitride based compound semiconductor is constituted is grown up on bottom substrate, make the manufacturing process of fine semiconductor crystal A independently from this bottom substrate, be provided with: crystal seed lamination operation, the crystal seed layer lamination on bottom substrate that constitutes by single or multiple lift III group-III nitride based compound semiconductor; Corrode remains portion and form operation,, carry out the erosion of chemistry or physics and handle, crystal seed layer partly or is dispersedly remained on the bottom substrate the film forming lateral part of bottom substrate crystal seed layer; The crystal growth operation, expose the face initial crystal growth face that crystal growth begins as semiconductor crystal A to what crystal seed layer corroded remains portion, this crystal growth face makes semiconductor crystal A crystal growth be each interconnective general plane that becomes to link to each other at least by crystal growth; Separation circuit corrodes remains portion by fracture semiconductor crystal A is separated with bottom substrate.
But said here " III group-III nitride based compound semiconductor " generally comprises binary, ternary or quaternary general formula " Al
1-x-yGa
yIn
xN; 0≤x≤1,0≤y≤1,0≤1-x-y≤1 " semi-conductor of any mixed crystal ratio of expression, and also the semi-conductor that has added p type or n type impurity is also included within the category of this specification sheets " III group-III nitride based compound semiconductor ".
In addition, the described III element (Al of family, Ga, In) at least a portion in is with boron (B) and thallium displacements such as (Tl), or at least a portion of nitrogen (N) is also included within the category of this specification sheets " III group-III nitride based compound semiconductor " with phosphorus (P), arsenic (As), antimony (Sb), bismuth metathetical such as (Bi) semi-conductor etc.
As described p type impurity, for example can add magnesium (Mg) and/or calcium (Ca) etc.
As described n type impurity, for example can add silicon (Si) or sulphur (S), selenium (Se), tellurium (Te) or germanium (Ge) etc.
These impurity both can add two kinds more than the element simultaneously, also can add amphitypy (P type and n type) simultaneously.
As the material of described bottom substrate, can use sapphire, spinel, manganese oxide, gallium oxide lithium (LiGaO
2), moly-sulfide (MoS), silicon (Si), silicon carbide (SiC), AlN, GaAs, InP, GaP, MgO, ZnO or MgAl
2O
4Deng.That is, these are as the material of bottom substrate, can use useful, well-known in the crystal growth of III group-III nitride based compound semiconductor or crystal growth substrate arbitrarily.
The material of bottom substrate, from the reaction of GaN, coefficient of thermal expansion differences and the viewpoint of stability at high temperature, it is better selecting sapphire.
On the bottom substrate with a plurality of erosion remains portion, when the purpose semiconductor crystal A that III group-III nitride based compound is constituted grew up, bottom substrate only was connected with erosion remains portion with semiconductor crystal A.Therefore, when doing the thickness of semiconductor crystal A fully greatly, internal stress or external stress are just concentrated this erosion remains portion that acts on easily.Consequently, particularly these stress corrode the fracture of remains portion to corroding remains portion as shear stress, when this stress becomes big.
That is, as according to as described in method of the present invention, utilize its stress, just can easily separate (peeling off) to bottom substrate with semiconductor crystal A.Utilize this method, can obtain independently monocrystalline (semiconductor crystal A) from bottom substrate.
By forming described the sort of erosion remains portion, the contact site of bottom substrate and semiconductor crystal A is defined narrow, so, be difficult to produce according to the distortion of both lattice parameter differences, " according to the stress of lattice parameter difference between bottom substrate and semiconductor crystal A " is relaxed.Therefore, when desirable semiconductor crystal A carried out crystal growth, the unwanted stress that the semiconductor crystal A in growing up is worked was suppressed, and the generation density of transposition and crackle is lowered.
And, so-called " a plurality of erosion remains portion ", as long as at least for example Fig. 9 see from vertical section like that be " a plurality of " just can, even as its planeform be linked to be one also not serious.Therefore, for example,, also can obtain effect of the present invention and effect even on square waveform of linearity and rapid sinusoidal waveform or spirrillum etc., form the planeform of striped (corroding remains portion).
Be not limited to shape of stripes, though circular, substantially elliptical, roughly polygon or roughly regular polygon etc. form the planeform of described erosion remains portion arbitrarily on the island shape etc., also can obtain effect of the present invention and effect certainly.
When bottom substrate was separated (peeling off) with semiconductor crystal A, the part of semiconductor crystal A also can remain in a side of bottom substrate, or the part of bottom substrate (for example: the fracture remains that corrode remains portion) also can remain in semiconductor crystal A one side.That is, described separation circuit is not that these materials part remains are not all had ground, each material fully discretely as prerequisite (prerequisite).
The 40 method is in the crystal growth operation of described the 39 method, the thickness of semiconductor crystal A to be fixed on more than the 50 μ m.Make more than the preferably about 50 μ m of thickness of purpose semiconductor crystal A of crystal growth, this thickness is thick more, and semiconductor crystal A is firm more, and, easily described shear-stress is concentrated on described erosion remains portion.
By these effects, poor according to lattice parameter, even under the medium condition of high temperature of crystal growth, also can produce and peel off phenomenon, so, after it is peeled off, the stress that is caused by coefficient of thermal expansion differences works hardly to semiconductor crystal A, therefore, transposition and crackle, high-quality semiconductor crystal A (for example GaN monocrystalline) can not taken place.
The 41 method is, in described the 39 method, by semiconductor crystal A and bottom substrate being cooled off or being heated, makes it produce stress according to semiconductor crystal A and bottom substrate coefficient of thermal expansion differences, utilizes this stress cracking erosion remains portion.
That is, described fracture (peeling off) also can be produced by the stress (shear-stress) according to semiconductor crystal A and bottom substrate coefficient of thermal expansion differences.
According to this method, particularly the thickness of semiconductor crystal A is formed on 50 μ m when above, when the crystallinity of keeping semiconductor crystal A is high, semiconductor crystal A and bottom substrate is ruptured.
The 42 method is in described the 39 method, the superiors of crystal seed layer or crystal seed layer to be formed by gan (GaN).As the concrete composition of semiconductor crystal A, to optimum and very useful gan (GaN) such as semi-conductive crystal growth substrates, it is the highest to be considered to now on the industry utility value.Therefore, at this moment, can implement the crystal growth of purpose semiconductor crystal A (GaN monocrystalline) best by the superiors of crystal seed layer or crystal seed layer are formed by gan (GaN).
But the utility values on industry such as AlGaN and/or AlGaInN are also big certainly, so, also can select these as the more specifically composition of crystal semiconductor layer A.At this moment, preferably by forming the superiors of crystal seed layer or crystal seed layer by more close semi-conductor of forming (III group-III nitride based compound semiconductor) or the roughly the same semi-conductor of forming with purpose monocrystalline (crystal semiconductor layer A).
The 43 method is that in described the 39 method, the orlop of crystal seed layer or crystal seed layer is formed by aluminium nitride (AlN).
Like this, owing to form so-called buffer layer by aluminium nitride (AlN), so, can obtain well-known effect according to this buffer layer (AlN) lamination.That is,, the crystalline raising of purpose crystal semiconductor layer A is become may or become easy by relaxing the well-known action principles such as stress that purpose crystal semiconductor layer A is worked that cause by the lattice parameter difference.
According to this method, can the stress between AlN buffer layer and bottom substrate be increased more, so, can the easier separation of carrying out bottom substrate.
For fully obtaining described action effect, for example, crystal seed layer is formed by two-layer, and its lower floor is AlN buffer layer (a crystal seed layer the first layer), and its upper strata is that the layer structure etc. of the multilayer crystal seed layer of GaN layer (the crystal seed layer second layer) is very effective.According to this combination, can obtain simultaneously the described the 4th and the effect and the effect of the 5th method well.
The 40 cubic method is, the erosion remains portion in arbitrary method of the described the 39 to the 43 forms operation, the configuration space that corrodes remains portion is fixed on more than the 1 μ m～below the 50 μ m.Better is, though also depend on the implementation condition of crystal growth, the configuration space that corrodes remains portion about 5～30 μ m for well.But this configuration space is meant the distance between the approaching mutually remains portion that respectively corrodes central point.
By this method, can cover the paddy portion top of corroding remains portion with semiconductor crystal A.
When this is worth when excessive, then can not cover the paddy portion top of corroding remains portion with semiconductor crystal A reliably, can not obtain crystallinity evenly and fine crystal (semiconductor crystal A).
Perhaps, when this is worth further when excessive, then the skew apparition of crystal orientation is unfavorable.
Be decided to be S, described configuration space (configuration cycle) when being decided to be L corroding horizontal thickness, width or the diameter of remains size portion, then the value of S/L is about 1/4 to be ideal.By this setting, the horizontal growth (ELO) of desirable semiconductor crystal A fully promoted, so, can obtain high-quality monocrystalline.
Below, the distance between mutually relative erosion remains portion sidewall be decided to be W (=L-S), the zone between this sidewall (that is the recess that, is etched and its upper area) is called the side.In addition, below described width S is called the crystal seed width.Therefore, the ratio S/W of side is reached about 1/3 is ideal to the crystal seed width.
Corrode remains portion by roughly uniformly-spaced or roughly the configuration of some cycles ground to implement described erosion processing be preferred.
Like this, horizontal growth condition of growing up is approximate equality on the whole, is difficult to produce irregular on crystallinity quality and growth thickness.Corrode the paddy portion top between the remains portion, be difficult to produce partial deviation in time before covering fully with semiconductor crystal A, so, for example from the slow crystal growth method of rate of crystal growth to the fast crystal growth method of rate of crystal growth, when changing the crystal growth method halfway, its period is decision accurately, in early days or uniquely easily.
Use this method, can corrode remains portion approximate equality ground to described shear-stress and distribute, so the fracture of whole erosion remains portion evenly produces, the separation energy of bottom substrate and semiconductor crystal A is implemented reliably at each.
Therefore, for example, make and corrode the platform shape that remains portion forms striated, it wait direction, uniformly-spaced configuration also can.The formation of this erosion remains portion has the advantage that can implement easily with reference to the present situation of existing general etching and processing technical level.At this moment, the direction of platform shape (corroding remains portion) is semiconductor crystal＜1-100〉or＜11-20〉just can.
On one side be that roughly equilateral triangle more than the 0.1 μ m is that it also is effective forming the method that corrodes remains portion on the lattice point of plane trigonometry lattice of benchmark.According to this method, owing to reduce contact area with bottom substrate more, so, according to above-mentioned effect, can reduce the transposition number reliably, can easily carry out the separation of bottom substrate simultaneously.
The horizontal section shape that corrodes remains portion, be made for roughly equilateral triangle, roughly orthohexagonal, circular or tetragonal method also are effective.
By this method, form the crystalline crystalline axis direction at III group-III nitride based compound semiconductor, each one is consistent easily, perhaps, can be constrained to the cross-directional length (thickness) that corrodes remains portion to any horizontal direction much the same, so, can suppress the transposition number.Particularly orthohexagonal and equilateral triangle are consistent with the crystalline structure of semiconductor crystal easily, so, be ideal.From manufacturing technology, circular and square forms easily, has the advantage made from reference to the present situation of existing general etching and processing technical level.
The 45 method of the present invention is described bottom substrate to be corroded handle more than the 0.01 μ m.Handle (etching and processing etc.) as long as corrode the part of bottom substrate by described erosion, then in the crystal growth operation afterwards, make the more planarization of surface (crystal growth face) of purpose semiconductor crystal A easily, and, form " cavity " easily in the side of corroding remains portion.Should " cavity " form greatly more, the easy more stress (shear-stress) that makes concentrates on erosion remains portion.
The 46 method is, forms in the operation in the erosion remains portion of described the 39 to the 43 arbitrary method, the horizontal thickness, width or the diameter that corrode remains portion are decided to be more than the 0.1 μ m～below the 20 μ m.Better is, though also depend on the implementation condition of crystal growth, horizontal thickness, width or the diameter that corrodes remains portion about 0.5～10 μ m for well.When this thickness is crossed when thick, the stress influence that works at semiconductor crystal A according to the lattice parameter difference becomes big, increases the transposition number of semiconductor crystal A easily.If when meticulous, it is slack-off then to form the rate of crystal growth b that corrodes remains portion self change difficulty or corrode remains size portion, is unfavorable.
When making the fracture of erosion remains portion by stress (shear-stress etc.), if it is excessive to corrode horizontal thickness, width or the diameter of remains portion, then the contact area with bottom substrate becomes greatly, so, also be easy to generate the part that is not reliably ruptured, be unfavorable.
The size of the stress influence that semiconductor crystal A is worked according to the lattice parameter difference not only depends on and corrodes the horizontal thickness (length) of remains portion, and, also depend on the configuration space that corrodes remains portion etc.These setting ranges increase the transposition number of semiconductor crystal A easily if inappropriate words are big according to the stress influence change of lattice parameter difference then as above-mentioned, are unfavorable.
For near erosion remains size portion, horizontal thickness, width or diameter have optimum value or OK range as described, corroding top, the bottom surface of remains portion or the shape of horizontal section is the shape (island) of partial closure at least, and be being shaped as of convex sealing laterally, better is, above this, the shape of bottom surface or horizontal section be circular and roughly regular polygon etc. for well.By this setting, reliable easily described optimum value or the OK range that realizes any horizontal direction.
The 47 method is, in the crystal growth operation of described the 39 to the 43 arbitrary method, to the fast crystal growth method of rate of crystal growth, changes the crystal growth method from the slow crystal growth method of rate of crystal growth halfway.
For example, by from the fast crystal growth method of horizontal growth to the fast crystal growth method of vertical growth, change the crystal growth method halfway, can obtain the semiconductor crystal A of excellent in crystallinity the short period of time.
The 40 all directions method is, in arbitrary method of the described the 39 to the 43, at least be provided with remains and remove operation after separation circuit, the fracture remains the erosion remains portion that remains in the semiconductor crystal A back side carry out processing treatment with method chemistry such as etching or physics and remove.
According to this method, when the semiconductor crystal A back side (side that bottom substrate is stripped from) forms the electrode of semiconductor light-emitting elements etc., can be suppressed at the not even resistance of electric current of the near interface generation of electrode and semiconductor crystal A, thereby can seek to reduce driving voltage and/or improve luminous intensity etc.
In addition, by removing the fracture remains that corrode remains portion, when the speculum that electrode also can be used as semiconductor light-emitting elements etc. utilized, the absorption and the scattering of light were lowered near the minute surface, and reflectivity improves, so, improved luminous intensity.
For example, when handling by Physical Processing such as grindings, implementing these remains and remove operation etc., also can remove buffer layer up to the semiconductor crystal A back side, or the Flatness at the raising semiconductor crystal A back side, so, more can strengthen the not inhibition of even resistance of electric current, or the above-mentioned action effect of near the absorption of the light of reduction minute surface and scattering etc.
Described processing treatment also available heat is handled.When the sublimation temperature of wanting the part of removing is lower than the sublimation temperature of purpose semiconductor crystal A, also can remove unwanted part by hyperthermic treatment and laser radiation etc.
When crystal seed layer is made multilayer, preferably " Al
xGa
(1-x)N (0≤x＜1) " the buffer layer film forming that constitutes, as the semiconductor layer of initial lamination.
But this buffer layer also can be additionally, again with described buffer layer by the middle layer of roughly the same composition the (for example AlN and AlGaN) periodically, or with other layers alternately, or constitute in addition lamination of multilayered structure ground.
By the lamination in sort buffer layer (or middle layer), can relax the stress that semiconductor crystal A is worked that causes by the lattice parameter difference etc., by improving crystallinity with existing same action principle.
In described separation circuit, bottom substrate and semiconductor crystal A cooling the time, they remain in the reaction chamber of growth apparatuses, with the ammonia (NH of certain flow roughly
3) gas flows under the intact state in reaction chamber, being cooled to roughly with the about speed of cooling about " 100 ℃/min～-0.5 ℃/min ", the method for normal temperature is an ideal.For example, can maintain the crystallinity of semiconductor crystal A stable by this method and the high-quality state under intactly implement described separation circuit reliably.
By above method of the present invention, can be effectively or reasonably solve described problem.
Description of drawings
Fig. 1 is explanation effect of the present invention, has the bottom substrate of jut and the pattern stereographic map of the semiconductor die body portion part of growth thereon;
Fig. 2 is pattern stereographic map (a), orthographic plan (b) and the sectional view (c) of the part part of the bottom substrate (Si substrate) 101 that relates to of first embodiment of the invention;
Fig. 3 is the pattern stereographic map (a) of the film forming bottom substrate 101 of substrate layer the first layer (AlGaN buffer layer) 102a, orthographic plan (b) and sectional view (c);
Pattern stereographic map (a), orthographic plan (b) and the sectional view (c) of the bottom substrate 101 of Fig. 4 is lamination substrate layer 102 (layer 102 a and a layer 102b);
Fig. 5 is the mode sectional drawing that illustrates the semiconductor crystal manufacturing process of key concept of the present invention;
Fig. 6 is pattern stereographic map (a), orthographic plan (b) and the sectional view (c) of the part part of the bottom substrate (Si substrate) that relates to of second embodiment of the invention;
Fig. 7 is the pattern stereographic map (a) of the film forming bottom substrate of buffer layer C (AlGaN layer), orthographic plan (b) and sectional view (c);
Pattern stereographic map (a), orthographic plan (b) and the sectional view (c) of the bottom substrate that Fig. 8 is a lamination semiconducter substrate (semiconductor crystal A);
Fig. 9 is the mode sectional drawing of the semiconductor crystal of the semiconductor crystal manufacturing process that relates to of third embodiment of the invention;
Figure 10 is existing bottom substrate semiconductor-on-insulator crystalline mode sectional drawing;
Figure 11 is the mode sectional drawing of enumerating that carries out the existing semiconductor crystal of crystal growth on Si substrate (bottom substrate).
Be used to implement preferred plan of the present invention
Below according to specific embodiment explanation the present invention.But, the present invention be not limited to below shown in embodiment.Described item also is to be used to implement preferred plan of the present invention in the disclosure of an invention hurdle.
Enumerate the summary of semiconductor crystal (crystal growth substrate) manufacturing sequence in the first embodiment of the invention below.First embodiment is corresponding with described first method～the 22 method (technical scheme 1～19) in the open hurdle of the present invention.
(first embodiment)
[1] jut forms operation
As shown in Figure 2, on the Si (111) of the monocrystalline bottom substrate 101 that constitutes by silicon face,, form the jut 101a of the substantial cylindrical shape of the about 1 μ m of diameter, highly about 1 μ m with the configuration space of about 2 μ m by utilizing the dry etching of photoetching method.As the assortment mode, be that the cylinder bottom center of configuration jut 101a forms jut 101a on each lattice point of plane trigonometry lattice that is benchmark with the roughly equilateral triangle of about 2 μ m on one side.But the thickness of bottom substrate 101 is decided to be about 200 μ m.
[2] crystal growth operation
In this crystal growth operation, as shown in Figure 4, adopt organometallic compound chemical vapour deposition (MOVPE method) to be implemented as farm labourer's preface, (A-stage) grows to each and interconnects and become continuous general plane shape above jut 101a, then, adopt hydride chemical vapour deposition (HVPE method) to be implemented as farm labourer's preface, grow to thickness about about 200 μ m up to its substrate layer (crystal layer).
In this crystal growth operation, use ammonia (NH
3) gas, carrier gas (H
2, N
2), trimethyl-gallium (Ga (CH
3)
3) gas (following note is made " TMG ") and trimethyl aluminium (Al (CH
3)
3) gas (following note is made " TMA ").
(a) at first, the bottom substrate 101 (Fig. 2) that is provided with described jut 101a, clean with organic solvent washing and acid treatment, be contained on the pedestal of the indoor setting of crystal growth device reaction, the limit makes H with normal pressure
2Flow into the reaction chamber inner edge and bottom substrate 101 is carried out roasting with 1100 ℃ of temperature.
(b) then, adopt on the described bottom substrate 101 of MOVPE normal direction and supply with H
2, NH
3, TMG, TMA, AlGaN buffer layer (substrate layer the first layer) 102a film forming.The crystal growth temperature of this AlGaN buffer layer 102a is about 1100 ℃, and thickness is about 0.3 μ m (Fig. 3).
(c) to the last supply of this AlGaN buffer layer (substrate layer the first layer) 102a H
2, NH
3, TMG, with 1075 ℃ of parts that make the substrate layer second layer of growth temperature, i.e. the GaN layer 102b crystal growth of the about 5 μ m of thickness.As shown in Figure 4, by this operation, the part of the substrate layer second layer (GaN layer 102b) is laterally grown up, and in paddy portion, promptly the side of jut 101a forms big cavity.
At this moment TMG feed speed is about about 40 μ mol/min, and the rate of crystal growth of the substrate layer second layer (GaN layer 102b) is about about 1 μ m/Hr.
(d) then, according to hydride chemical vapour deposition (HVPE method), make the further crystal growth of described GaN layer (the substrate layer second layer) 102b to 200 μ m.In this HVPE method, GaN layer 102b rate of crystal growth is about about 45 μ m/Hr.
[3] separation circuit
(a) after described crystal growth operation, make ammonia (NH
3) to flow into the crystal growth device reaction indoor for gas, intactly bottom substrate 101 and (being made of AlGaN buffer layer 102a and GaN layer 102b) substrate layer 102 is cooled to roughly normal temperature.At this moment speed of cooling is approximately about " 50 ℃/min～-5 ℃/min ".
(b) then, when they are taken out from crystal growth device reaction chamber, can obtain the GaN crystal of peeling off from bottom substrate 101.But, the sub-fraction remains of this crystal also untouched fixedly residual AlGaN buffer layer 102a and the fracture remains of jut 101a at the back side of GaN layer 102b.
[4] the fracture remains are removed operation
After above-mentioned separation circuit, carry out etch processes by using the mixed solution that has added nitric acid in the hydrofluoric acid, the fracture remains of the jut 101a that is made of Si that remains in the GaN crystal back side are removed.
By above manufacture method, can obtain the very good high-quality GaN crystal (GaN layer 102b) of the about 200 μ m crystallinity of thickness, that is, obtain independently desirable semiconducter substrate from bottom substrate 101.
As shown in Figure 2, in above-mentioned first embodiment, the jut of bottom substrate and paddy portion are made of vertical surface and horizontal plane, but they also can be by inclined-plane and curved surface etc. form arbitrarily.Therefore, the section shape of the paddy portion that forms on the cited bottom substrate of Fig. 2 (c) except that the concave character type of essentially rectangular, also can form for example roughly U font and roughly V-shape, generally their shape, size, at interval, configuration, orientation etc. be arbitrarily.
The following describes second embodiment of the present invention.The second embodiment scheme is corresponding with described the 23 method～the 43 method (technical scheme 20～38) in the open hurdle of the present invention.
When enforcement is of the present invention, also can among following, select various creating conditions respectively arbitrarily.In addition, these various creating conditions also can at random be made up.
At first, initial, as the method that forms III group-III nitride based compound semiconductor layer, organometallic compound chemical vapour deposition (MOCVD or MOVPE) is an ideal.Yet, also can use molecular beam chemical vapour deposition (MBE), halogenide chemical vapour deposition (HalideVPE), liquid phase flop-in method (LPE) etc., also can form each layer with different growing methods respectively.
To buffer layer, consider that from correcting reasons such as lattice off resonance forming is ideal in the crystal growth substrate or on the bottom substrate etc.
Particularly, in semiconducter substrate (semiconductor crystal A), during lamination buffer layer (above-mentioned middle layer),, can use the III group-III nitride based compound semiconductor Al that forms under the low temperature as these buffer layers
xGa
yIn
(1-x-y)N (0≤x≤1,0≤y≤1,0≤x+y≤1), the better Al that is to use
xGa
(1-x)N (0≤x≤1).This buffer layer both can be an individual layer, also can be different multiple layers such as composition.The formation method of buffer layer both can form with 380～420 ℃ low temperature, on the contrary, also can form with mocvd method 1000～1180 ℃ scope.Use the DC magnetic controlled tube sputtering apparatus, as raw material, also can form the buffer layer that constitutes by AlN by reactive sputtering with high purity metal aluminium and nitrogen.
Similarly, can form with general formula Al
xGa
yIn
(1-x-y)The buffer layer of N (0≤x≤1,0≤y≤1,0≤x+y≤1, ratio of components is any) expression.Also can use vapour deposition method, ion plating method, laser to remove method, ECR method.The buffer layer of physical vapor deposition preferably carries out under 200～600 ℃.More preferably 300～600 ℃, especially preferred is 350～450 ℃.When using physical vapor depositions such as these sputtering methods, the thickness of buffer layer preferably 100～3000
More preferably 100～400
Most preferably 100～300
As multiple layer, for example, by Al
xGa
(1-x)The alternately formation of layer that N (0≤x≤1) constitutes and GaN layer, its method are for example alternately to change formation below 600 ℃ and more than 1000 ℃ forming the temperature of forming identical layer.Certainly, also be made up these so long, but the also III group-III nitride based compound semiconductor Al of lamination more than three kinds of multiple layer
xGa
yIn
(1-x-y)N (0≤x≤1,0≤y≤1,0≤x+y≤1).Usually buffer layer is noncrystal, and the middle layer is a single crystal.As one-period, also can form a plurality of cycles to buffer layer and middle layer, any period also can repeatedly.Many more repeatedly crystallinity are good more.
The III group-III nitride based compound semiconductor on buffer layer and upper strata, even the part that III family is elementary composition is replaced with boron (B), thallium (Tl), or, in fact also can be applicable to the present invention part phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) displacement that nitrogen (N) is formed.In addition, these elements are mixed with unconspicuous amount in composition also can.For example, the III group-III nitride based compound semiconductor Al that also can in forming, not have indium (In), arsenic (As)
xGa
(1-x)Among the N (0≤x≤1), by being mixed than the big indium (In) of aluminium (Al), gallium (Ga) atomic radius or the arsenic (As) bigger than nitrogen (N) atomic radius, because the crystal dilatating and deformable that nitrogen-atoms comes off and causes is proofreaied and correct with compression set, crystallinity improves.
At this moment, acceptor impurity enters the position of III family atom easily, so, also can obtain the P N-type waferN with ア ズ ゲ ロ one Application.Like this, by crystallinity is improved, connect displacement and also can drop to about 100 to 1/1000th and conform to the present invention.Buffer layer and III group-III nitride based compound semiconductor layer are for two cycles during the above stratum basale that forms, and the element that doping is bigger than main composition element atomic radius in each III group-III nitride based compound semiconductor layer is better.When constituting, preferably use the two component system or the three component system of original III group-III nitride based compound semiconductor as luminous element.
When forming n type III group-III nitride based compound semiconductor layer,, can add IV family element or VI family elements such as Si, Ge, Se, Te, C as n type impurity.As p type impurity, can add II family element or IV family elements such as Zn, Mg, Be, Ca, Sr, Ba.Also can be in these elements a plurality of, or n type impurity and p type impurity mix in one deck.
The use horizontal extension is grown up, and the transposition that reduces III group-III nitride based compound semiconductor layer also is arbitrarily.Any means of at this moment, can adopt mask method, step being buried by etching.
Etching mask can adopt poly semiconductor, silicon oxide (SiO such as polysilicon, polycrystalline nitride-based semiconductor
X), silicon nitride (SiN
X), titanium oxide (TiO
X), zirconium white (ZrO
X) oxide compound, the nitride that wait, titanium (Ti), tungsten refractory metal, their multilayer films such as (W).Their film is arbitrarily except chemical vapour depositions such as evaporation, sputter, CVD.
When carrying out etching, reactive ion beam etching (RIBE) is preferred, but can use engraving method arbitrarily.As the method that on substrate surface, does not form step with vertical side, also adopt by anisotropic etching, for example form in the bottom of step do not have the bottom surface, section is the method for V word shape.
On III group-III nitride based compound semiconductor, can form semiconductor elements such as FET, luminous element.When being luminous element, its luminescent layer can be considered homostyructure, heterojunction structure, dual heterojunction structure except multiple quantum trap structure (MQW), single quantum well structure (SQW), but also can be by formation such as pin knot or pn knots.
Below according to specific embodiment explanation the present invention.But the embodiment shown in below the present invention is not limited to again.
(second embodiment)
Enumerate the summary of semiconductor crystal (crystal growth substrate) manufacturing sequence in the embodiment of the invention below.
[1] prevents reaction process
Originally prevent that reaction process from being to go up the manufacturing process that lamination prevents responding layer in bottom substrate (Si substrate).
Originally preventing in the reaction process, at first on Si (111) substrate, preventing the in addition about 1.5 μ m of film forming of responding layer to what constitute by silicon carbide (SiC) by chemical vapour deposition (CVD).For preventing the single-chip warpage, also can carry out the film forming of SiC film on table back of the body two sides.The formation of silicon carbide (SiC) also can be undertaken by Metal Organic Vapor Phase Epitaxy (MOCVD).
[2] jut forms operation
Prevent on the responding layer that described dry etching by utilizing photoetching method forms the jut B1 (Fig. 6) of the substantial cylindrical shape of the about 1 μ m of diameter, highly about 1 μ m with the configuration space of about 2 μ m.As the assortment mode, be that configuration jut B1 cylinder bottom center forms jut B1 on each lattice point of plane trigonometry lattice that is benchmark with the roughly equilateral triangle of about 2 μ m on one side.But the thickness of bottom substrate is decided to be about 200 μ m.
[3] crystal growth operation
As shown in Figure 8, in this crystal growth operation, be to adopt organometallic compound chemical vapour deposition (MOVPE method) to be implemented as farm labourer's preface, up to crystalline growth face above jut B1 (A-stage) each interconnect the general plane shape of growing up to linking to each other, then, adopt hydride chemical vapour deposition (HVPE method) to be implemented as farm labourer's preface, grow to thickness about about 200 μ m up to this semiconducter substrate (crystal layer).
In this crystal growth operation, use ammonia (NH
3) gas, carrier gas (H
2, N
2), trimethyl-gallium (Ga (CH
3)
3) gas (following note is made " TMG ") and trimethyl aluminium (Al (CH
3)
3) gas (following note is made " TMA ").
(a) at first, the bottom substrate that is provided with described jut B1 (Fig. 2) with organic solvent washing and acid treatment washing, is contained on the pedestal of the indoor setting of crystal growth device reaction, the limit makes H with normal pressure
2Flow into the reaction chamber inner edge and bottom substrate is carried out roasting with 1100 ℃ of temperature.
(b) then, adopt the MOVPE method, on described bottom substrate, supply with H
2, NH
3, TMG, TMA, make AlGaN buffer layer (buffer layer C) film forming.The crystal growth temperature of this AlGaN buffer layer C is about 1100 ℃, and thickness is about 0.2 μ m.(Fig. 3)
(c) go up supply H to this AlGaN buffer layer (buffer layer C)
2, NH
3, TMG, with 1075 ℃ of parts that make semiconducter substrate of growth temperature, i.e. the GaN layer A crystal growth of the about 5 μ m of thickness.As shown in Figure 8, by this operation, the part of semiconducter substrate (GaN layer A) is laterally grown up, and in paddy portion, promptly the side of jut B1 forms big cavity.
At this moment TMG feed speed is about about 40 μ mol/min, and the rate of crystal growth of GaN layer (semiconductor crystal A) is about about 1 μ m/Hr.
(d) then, adopt hydride chemical vapour deposition (HVPE method), make the further crystal growth of described GaN layer (semiconductor crystal A) to 200 μ m.The GaN layer crystal body growth rate of this HVPE method is about about 45 μ m/Hr.
[4] separation circuit
(a) after described crystal growth operation, make ammonia (NH
3) to flow into the crystal growth device reaction arbitrarily indoor for gas, and the wafer with bottom substrate (Si substrate) is cooled to roughly normal temperature.At this moment speed of cooling is so long as just can about " 50 ℃/min～-5 ℃/min " approximately.
(b) then, they are taken out from crystal growth device reaction chamber, can obtain the GaN crystal of peeling off from bottom substrate (Si substrate) (semiconductor crystal A).But this crystal is also residual at the back side of GaN layer (semiconducter substrate) the sub-fraction remains of AlGaN buffer layer C and the fracture remains of jut B1 are arranged.
[5] the fracture remains are removed operation
After described separation circuit,, the fracture remains of the jut B1 that is made of Si that remains in the GaN crystal back side are removed by milled processed.
But this fracture remains are removed operation and also can be implemented by using the mixed solution that added nitric acid in the hydrofluoric acid etc. to carry out etch processes.
Adopt above manufacture method can obtain the very good high-quality GaN crystal (GaN layer) of the about 200 μ m crystallinity of thickness, promptly can obtain independently desirable semiconducter substrate (semiconductor crystal A) from bottom substrate.
Prevent the crystalline material B of responding layer as formation, adopt AlN, Al
xGa
(1-x)N (0.30≤x≤1) etc. also can obtain effect and the effect roughly same with described embodiment.Be more typically, as formation prevent the crystalline material B of responding layer can use silicon carbide (SiC, 3C-SiC), aluminium nitride (AlN), spinel (MgAl
2O
4), or the aluminium ratio of components is at least at the AlCaN more than 0.30, AlInN or AlGaInN.
Form the semiconductor crystal A of purpose semiconducter substrate, be not limited to gan (GaN), can select described general " III group-III nitride based compound semiconductor " arbitrarily.
Purpose semiconducter substrate (semiconductor crystal A) also can have multilayered structure.
As shown in Figure 6, the jut of bottom substrate and paddy portion are made of vertical surface and horizontal plane among the described embodiment, but they also can be by inclined-plane and curved surface etc. form arbitrarily.Therefore, the section shape of the shown paddy portion that forms on bottom substrate of Fig. 2 (c) except that the concave character type of essentially rectangular, also can form for example roughly U font and roughly V-shape, their general shape, size, at interval, configuration, orientation etc. be arbitrarily.
The following describes the 3rd embodiment.The 3rd embodiment is corresponding with the described the 40 cubic method～the 55 method (technical scheme 39～48) in open hurdle of the present invention.
Below according to specific embodiment explanation the present invention.But the embodiment shown in below the present invention is not limited to again.
(the 3rd embodiment)
1, crystal seed lamination operation
In the present embodiment the crystal seed layer (III group-III nitride based compound semiconductor) that constitutes by the crystal seed layer the first layer (AlN buffer layer 102) and the crystal seed layer second layer (GaN layer 103), by film forming with the vapor deposition of organometallic compound chemical vapour deposition (following table is shown " MOVPE ").Here used gas is ammonia (NH
3) gas and carrier gas (H
2, N
2) and trimethyl-gallium (Ga (CH
3)
3, following note makes " TMG ") and trimethyl aluminium (Al (CH
3)
3, following note makes " TMA ").
Fig. 9 illustrates the mode sectional drawing of the semiconductor crystal of present embodiment semiconductor crystal manufacturing process.
At first, Sapphire Substrate 101 (bottom substrate) square an inch, the about 250 μ m of thickness is cleaned by organic solvent washing and thermal treatment (roasting).Then, a face of the bottom substrate 101 of this single crystal as crystal growth face, H
2With 10 liters/minute, NH
3Divide with 20 μ mol/ with 5 liters/minute, TMA and to supply with, make the thickness of AlN buffer layer 102 (crystal seed layer the first layer) crystal growth to 200nm.At this moment crystal growth temperature is about 400 ℃.
Again the temperature of Sapphire Substrate 101 is warmed up to 1000 ℃, H
2With 20 liters/minute, NH
3Divide with 300 μ mol/ with 10 liters/minute, TMG to import, make GaN layer 103 (the crystal seed layer second layer) film forming to the about 1.5 μ m of thickness (Fig. 9 (a)).
2, corrode remains portion and form operation
Then, use strong baking to burn the protection mask,, form configuration cycle by using the selection dry etching of reactive ion etching (RIE)
Striated corrode remains portions (Fig. 9 (b)).
That is, become width of fringe by etching
Lateral width
The striated of the about 0.1 μ m of substrate, section shape form the erosion remains portion of essentially rectangular.Described protection mask makes the sidewall of the erosion remains portion of residual one-tenth striated form { the 11-20} face of GaN layer 103 (the crystal seed layer second layer).By this etching, the striated erosion remains portion approximate period ground that has in flat top portion by GaN layer 103 (the crystal seed layer second layer) and AlN buffer layer 102 (crystal seed layer the first layer) formation crystal seed layer is formed, in lateral paddy portion, the part of Sapphire Substrate 101 is exposed.
3, crystal growth operation
Then, the residual erosion remains portion of striated expose face as initial crystal growth face, form the purpose semiconductor crystal A that constitutes by the GaN monocrystalline with the HVPE method.
At last, make purpose semiconductor crystal A crystal growth to about the 250 μ m.At this moment, in early days of growth, GaN is in horizontal and vertical growth, in case each one connect, become the smooth general plane shape that links to each other after, the GaN crystal is then in vertical growth.
In this HVPE method, use horizontal HVPE device.That V family raw material uses is ammonia (NH
3) and III family raw material uses is that Ga reacts with HCl and the GaCl that obtains.
Like this, mainly grow up by horizontal extension, the side of crystal seed layer is buried, and then, by vertical growth, obtains the semiconductor crystal A (GaN monocrystalline) (Fig. 9 (c)) of purpose thickness.Symbol R among the figure represents " cavity ".
4, separation circuit
Described semiconductor crystal A with 1.5 ℃/minute speed of cooling from 1100 ℃ of cool to room temperature lentamente.Whereby, near AlN buffer layer 102 (crystal seed layer the first layer), produce and peel off, obtain independently the semiconductor crystal A of purpose thickness (GaN monocrystalline) (Fig. 9 (d)) from bottom substrate 101.
Except described buffer layer, also can with described buffer layer by the middle layer of roughly the same composition the (for example AlN and AlGaN) periodically, or with other layers alternately, or constitute multi-ply construction ground and carry out lamination.
By the lamination in sort buffer layer (or middle layer), can be stress mitigation that semiconductor crystal A is worked that causes by the lattice parameter difference etc., by with existing same action principle, can improve crystallinity.
In described separation circuit, bottom substrate and semiconductor crystal A cooling the time, they remain in the reaction chamber of growth apparatuses, make the roughly ammonia (NH of certain flow
3) under the state of gas with any inflow reaction chamber, be cooled to roughly the method for normal temperature with the speed of cooling about " 100 ℃/min～-0.5 ℃/min " approximately and also can use.When this speed of cooling was too fast, semiconductor crystal A might break, and cracks.
Separation circuit, according to the stress of bottom substrate and semiconductor crystal A lattice parameter difference, the crystal growth operation carry out midway also passable.
When expression is of the present invention, adopted the foregoing description as the most practical appropriate example, but the present invention not only is defined in described embodiment, within the scope of the present invention other variation and application examples include interior.
Claims (48)
1. the manufacture method of a semiconductor crystal, this method is by utilizing horizontal crystal growth effect, on bottom substrate, form the substrate layer that constitutes by III group-III nitride based compound semiconductor, obtain the independently method of semiconductor crystal from described bottom substrate, it is characterized in that, this method comprises: jut forms operation, forms a plurality of juts on described bottom substrate; The crystal growth operation as the initial growth face that described substrate layer begins crystal growth, makes described substrate layer crystal growth at least a portion on described jut surface, is interconnected to form the plane that links to each other at least separately until this growth face; Separation circuit, by the described jut that ruptures, described substrate layer is separated with described bottom substrate, in described crystal growth operation, by adjusting the raw material supplying amount q of described III group-III nitride based compound semiconductor, the difference (b-a) of at least a portion of the paddy portion between the described jut of described bottom substrate being exposed the rate of crystal growth b of the rate of crystal growth a of described III group-III nitride based compound semiconductor in zone and described jut head is controlled to be maximum value.
2. the manufacture method of semiconductor crystal as claimed in claim 1, it is characterized in that, by described substrate layer and described bottom substrate being cooled off or being heated, produce the stress that causes by described substrate layer and described bottom substrate coefficient of thermal expansion differences, utilize this stress to make described jut fracture.
3. the manufacture method of a semiconductor crystal, this method is by utilizing horizontal crystal growth effect, on bottom substrate, form the substrate layer that constitutes by III group-III nitride based compound semiconductor and obtain the method for semiconductor crystal, it is characterized in that, this method comprises: jut forms operation, forms a plurality of juts on described bottom substrate; The crystal growth operation, the at least a portion on described jut surface is begun the initial growth face of crystal growth as described substrate layer, make described substrate layer crystal growth, be interconnected to form the plane that links to each other at least separately until this growth face, described crystal growth operation is by adjusting the raw material supplying amount q of described III group-III nitride based compound semiconductor, and the difference (b-a) of the paddy portion at least a portion between the described jut of described bottom substrate being exposed the rate of crystal growth b of the rate of crystal growth a of regional described III group-III nitride based compound semiconductor and described jut head is controlled to be maximum value.
4. as the manufacture method of claim 1 or the described semiconductor crystal of claim 3, it is characterized in that, described raw material supplying amount q fix on 1 μ mol/min above～below the 100 μ mol/min.
5. as the manufacture method of each described semiconductor crystal of claim 1 or claim 3, it is characterized in that, use silicon (Si) or silicon carbide (SiC) as the material of described bottom substrate.
6. as the manufacture method of each described semiconductor crystal of claim 1 or claim 3, it is characterized in that, material as described bottom substrate uses Si (111), form in the operation at described jut, the zone is exposed by paddy portion between the described jut of described bottom substrate, makes Si (111) face unexposedly form described jut.
7. as the manufacture method of each described semiconductor crystal of claim 1 or claim 3, it is characterized in that after described jut forms operation, having at least and on the surface of described jut, form by Al
xGa
(1-x)The operation of the buffer layer that N constitutes, wherein, 0＜x≤1.
8. the manufacture method of semiconductor crystal as claimed in claim 7 is characterized in that, makes the thickness of described buffer layer carry out film forming below vertical height of described jut.
9. as the manufacture method of claim 1 or the described semiconductor crystal of claim 3, it is characterized in that, in described crystal growth operation, the thickness of described substrate layer is fixed on more than the 50 μ m.
10. as the manufacture method of claim 1 or the described semiconductor crystal of claim 3, it is characterized in that, in described crystal growth operation, change the crystal growth method halfway, be altered to the fast crystal growth method of rate of crystal growth from the slow crystal growth method of rate of crystal growth.
11. the manufacture method as claim 1 or the described semiconductor crystal of claim 3 is characterized in that, forms in the operation at described jut, described jut is pressed uniformly-spaced or the configuration of some cycles ground, forms described jut like this.
12. the manufacture method of semiconductor crystal as claimed in claim 11 is characterized in that, forms in the operation at described jut, and be that equilateral triangle more than the 0.1 μ m is the described jut of formation on the lattice point of plane trigonometry lattice of benchmark on one side.
13. the manufacture method as claim 1 or the described semiconductor crystal of claim 3 is characterized in that, forms in the operation at described jut, makes the horizontal section shape of described jut form equilateral triangle, orthohexagonal, circle or square.
14. the manufacture method as claim 1 or the described semiconductor crystal of claim 3 is characterized in that, forms in the operation at described jut, the configuration space of described jut is decided to be more than the 0.1 μ m～below the 10 μ m.
15. the manufacture method as claim 1 or the described semiconductor crystal of claim 3 is characterized in that, forms in the operation at described jut, vertically highly being decided to be more than the 0.5 μ m of described jut～below the 20 μ m.
16. the manufacture method as claim 1 or the described semiconductor crystal of claim 3 is characterized in that, forms in the operation at described jut, horizontal thickness, width or the diameter of described jut are decided to be more than the 0.1 μ m～below the 10 μ m.
17. manufacture method as claim 1 or the described semiconductor crystal of claim 3, it is characterized in that, before described crystal growth operation, by photoprocess, chemical treatment or physical treatments such as cutting and grinding such as various etchings, electron beam radiation treatment, laser, the crystallinity or the molecular structure that make at least a portion of the paddy portion between the described jut of described bottom substrate expose the zone worsen or change, and reduce the described rate of crystal growth a that exposes the described III group-III nitride based compound semiconductor in zone whereby.
18. the manufacture method of semiconductor crystal as claimed in claim 1 is characterized in that, in described separation circuit, the substrate that is made of described bottom substrate and described substrate layer is stayed in the reaction chamber of growth apparatuses, at the ammonia (NH with certain flow
3) gas flows under the state in the described reaction chamber, and the speed of cooling about described substrate usefulness-100 ℃/min～-0.5 ℃/min is cooled to normal temperature.
19. the manufacture method of semiconductor crystal as claimed in claim 1, it is characterized in that, at least after described separation circuit, remains are set and remove operation,, handle with chemistry such as etching or Physical Processing and to remove the described jut fracture remains that remain in the described substrate layer back side.
20. the manufacture method of a semiconductor crystal, this method is by utilizing horizontal crystal growth effect, on the bottom substrate that forms by silicon (Si), the semiconductor crystal A that is made of III group-III nitride based compound semiconductor is grown up and obtain the method for semiconducter substrate, it is characterized in that, this method comprises: prevent reaction process, on described bottom substrate, preventing the responding layer film forming by what constitute than described semiconductor crystal A fusing point or the high crystalline material B of thermotolerance; Jut forms operation, on the single face of film forming one side, does not make described bottom substrate form a plurality of juts from the described responding layer that prevents in the described responding layer that prevents by chemistry or physical etch with exposing; The crystal growth operation as the initial growth face that described semiconductor crystal A begins crystal growth, makes at least a portion on described jut surface described semiconductor crystal A carry out crystal growth, is interconnected to form the plane that links to each other at least separately until this growth face.
21. the manufacture method of semiconductor crystal as claimed in claim 20 is characterized in that, described semiconductor crystal A is by satisfying composition formula Al
xGa
yIn
(1-x-y)The III group-III nitride based compound semiconductor of N constitutes, wherein, and 0≤x＜1,0＜y≤1,0＜x+y≤1.
22. the manufacture method of semiconductor crystal as claimed in claim 20 is characterized in that, forms the described described crystalline material B that prevents responding layer, is made of silicon carbide, aluminium nitride or spinel.
23. the manufacture method of semiconductor crystal as claimed in claim 20 is characterized in that, forms the described described crystalline material B that prevents responding layer, is made of at the AlGaN more than 0.30, AlInN or AlGaInN at least the aluminium ratio of components.
24. the manufacture method as claim 20,21, each described semiconductor crystal of 22 is characterized in that, laterally grows up by making described growth face, and interconnects separately, forms the not cavity of the described semiconductor crystal A of lamination between described jut.
25. the manufacture method as claim 20,21, each described semiconductor crystal of 22 is characterized in that, described between described jut prevent the thickness of the paddy portion of responding layer form 0.1 μ m above～below the 2 μ m.
26. the manufacture method as claim 20,21, each described semiconductor crystal of 22 is characterized in that, forms in the operation at described jut, vertically highly the forming more than the 0.5 μ m of described jut～below the 20 μ m.
27. the manufacture method as claim 20,21, each described semiconductor crystal of 22 is characterized in that, forms in the operation at described jut, horizontal thickness, width or the diameter of described jut are formed more than the 0.1 μ m～below the 10 μ m.
28. manufacture method as claim 20,21, each described semiconductor crystal of 22, it is characterized in that, be provided with separation circuit, by described semiconductor crystal A and described bottom substrate being cooled off or being heated, the stress that generation is caused by described semiconductor crystal A and described bottom substrate coefficient of thermal expansion differences, by utilizing this stress to make described jut fracture, described semiconductor crystal A is separated with described bottom substrate.
29. the manufacture method as claim 20,21, each described semiconductor crystal of 22 is characterized in that, in described crystal growth operation, described semiconductor crystal A lamination is reached more than the 50 μ m.
30. the manufacture method of semiconductor crystal as claimed in claim 20, it is characterized in that, in described crystal growth operation, by adjusting the raw material supplying amount q of described III group-III nitride based compound semiconductor, the difference (b-a) of the rate of crystal growth b at rate of crystal growth a that is etched the described III group-III nitride based compound semiconductor in the zone of the paddy portion at least a portion between the described jut of described bottom substrate and described jut top is controlled to be maximum value.
31. the manufacture method of semiconductor crystal as claimed in claim 30 is characterized in that, described raw material supplying amount q be set in 1 μ mol/min above～below the 100 μ mol/min.
32. the manufacture method of semiconductor crystal as claimed in claim 20 is characterized in that, after described jut formed operation, setting formed by Al on the surface of described jut at least
xGa
(1-x)The operation of the buffer layer C that N constitutes, wherein, 0＜x≤1.
33. the manufacture method of semiconductor crystal as claimed in claim 32 is characterized in that, the thickness of described buffer layer C form 0.01 μ m above～below the 1 μ m.
34. the manufacture method of semiconductor crystal as claimed in claim 20 is characterized in that, forms in the operation at described jut, described jut is pressed uniformly-spaced or the configuration of some cycles ground, forms described jut.
35. the manufacture method of semiconductor crystal as claimed in claim 34 is characterized in that, Yi Bian being that equilateral triangle more than the 0.1 μ m is to form described jut on the lattice point of plane trigonometry lattice of benchmark.
36. manufacture method as claim 20,21, each described semiconductor crystal of 22, it is characterized in that, form in the operation at described jut, the horizontal section shape of described jut is equilateral triangle, orthohexagonal, circle, rectangle, rhombus or parallelogram.
37. the manufacture method as claim 20,21, each described semiconductor crystal of 22 is characterized in that, forms in the operation at described jut, the configuration space of described jut is formed more than the 0.1 μ m～below the 10 μ m.
38. the manufacture method as claim 20,21, each described semiconductor crystal of 22 is characterized in that, prevents in the reaction process described, the described both sides film forming of responding layer on described bottom substrate that prevent.
39. the manufacture method of a semiconductor crystal, this method is to make the semiconductor crystal that is made of III group-III nitride based compound semiconductor, on bottom substrate, grow up, obtain the independently method of high-quality semiconductor crystal A from described bottom substrate, it is characterized in that, this method is provided with: crystal seed lamination operation, the crystal seed layer lamination on described bottom substrate that constitutes by single or multiple lift III group-III nitride based compound semiconductor; Corrode remains portion and form operation, the film forming lateral part of the described crystal seed layer of described bottom substrate is carried out chemistry or physical erosion processing, make described crystal seed layer partly or dispersedly remain on the described bottom substrate; The crystal growth operation, the face that exposes of the erosion remains portion of described crystal seed layer, begin the initial crystal growth face of crystal growth as described semiconductor crystal A, make described semiconductor crystal A carry out crystal growth, make this crystal growth face interconnect, form the plane that links to each other at least separately by crystal growth; Separation circuit by the described erosion remains portion of rupturing, separates described semiconductor crystal A with described bottom substrate.
40. the manufacture method of semiconductor crystal as claimed in claim 39 is characterized in that, in described crystal growth operation, the thickness of described semiconductor crystal A is decided to be more than the 50 μ m.
41. the manufacture method of semiconductor crystal as claimed in claim 39, it is characterized in that, by described semiconductor crystal A and described bottom substrate being cooled off or being heated, make the stress of its generation, utilize the described erosion remains of this stress cracking portion based on described semiconductor crystal A and described bottom substrate coefficient of thermal expansion differences.
42. the manufacture method of semiconductor crystal as claimed in claim 39 is characterized in that, the superiors of described crystal seed layer or described crystal seed layer are formed by gan (GaN).
43. the manufacture method of semiconductor crystal as claimed in claim 39 is characterized in that, the orlop of described crystal seed layer or described crystal seed layer is formed by aluminium nitride (AlN).
44., it is characterized in that as the manufacture method of claim 39 to each described semiconductor crystal of claim 43, form in the operation in described erosion remains portion, the configuration space of described erosion remains portion is decided to be more than the 1 μ m～below the 50 μ m.
45., it is characterized in that as the manufacture method of claim 39 to each described semiconductor crystal of claim 43, form in the operation in described erosion remains portion, described bottom substrate is corroded more than the processing 0.01 μ m.
46. as the manufacture method of claim 39 to each described semiconductor crystal of claim 43, it is characterized in that, form in the operation in described erosion remains portion, horizontal thickness, width or the diameter of described erosion remains portion are decided to be more than the 0.1 μ m～below the 20 μ m.
47. as the manufacture method of claim 39 to each described semiconductor crystal of claim 43, it is characterized in that, in described crystal growth operation,, change the crystal growth method halfway from the slow fast crystal growth method of crystal growth normal direction rate of crystal growth of rate of crystal growth.
48. as the manufacture method of claim 39 to each described semiconductor crystal of claim 43, it is characterized in that, at least after described separation circuit, remains are set and remove operation, the described erosion remains portion fracture remains that remain in the described semiconductor crystal A back side, carry out processing treatment with chemistry such as etching or physics method and remove.
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Also Published As
| Publication number | Publication date |
|---|---|
| CN1863944A (en) | 2006-11-15 |
| JP4084541B2 (en) | 2008-04-30 |
| JP2002241192A (en) | 2002-08-28 |
| TW575908B (en) | 2004-02-11 |
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