JP2002237605A - Semiconductor element - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a semiconductor element having a high surge withstand capability. SOLUTION: An N type silicon region 12 is formed on an N ^{+ type} silicon layer 11. P on the surface of the N-type silicon region 12
^A plurality of ^{+ type} silicon regions 16 are formed at equal intervals. Further, around the ^{P +} form silicon region 16, to form a ^{P +} form of the guard ring region 17. At this time, the specific resistance of the N-type silicon region 12, the distance between the P ⁺ -type silicon region 16 and the guard ring region 17, the diffusion depth, and the like, are such that the P ⁺ -type silicon region 16 and the guard ring region 17 When the breakdown voltage is applied, a substantially integrated depletion layer is formed, and when the breakdown voltage is applied, the depletion layer is formed between the N ^{+ type} silicon layer 11 and the N ^{+ type} silicon layer 11.
It is configured to reach the interface with the silicon region 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a rectifying function, and more particularly to a semiconductor device in which a rectifying portion having a Schottky barrier and a rectifying portion having a PN junction are adjacent to each other.

[0002]

2. Description of the Related Art A semiconductor device used for a rectifier or the like, for example, a switching device is required to have high switching speed and forward and reverse characteristics. As such a semiconductor rectifier, a PN junction diode using a PN junction and a Schottky diode using a Schottky junction are widely used.

A PN junction diode has high reverse characteristics, such as low leakage current and high withstand voltage when a reverse voltage is applied. However, a PN junction diode has a low switching speed and is not suitable for use in a high-speed circuit. As a means for improving the switching speed, there is a method of diffusing a heavy metal such as gold or platinum. However, while the switching speed is improved, the reverse leakage current increases and the forward voltage drop increases.

[0004] Schottky diodes have high switching characteristics such as high switching speed. However, the Schottky diode has low reverse characteristics, and has a problem particularly when used in a high-voltage, large-current circuit. For example, the resistance to the overvoltage in the reverse direction (surge resistance) is low, and when a reverse voltage near the breakdown voltage is applied, the leakage current flowing over the Schottky barrier sharply increases.

As a semiconductor element having both the characteristics of the PN junction diode and the Schottky diode described above, there is known a semiconductor element disclosed in Japanese Patent Publication No. 59-35183. The semiconductor device disclosed in the above publication has a configuration in which a rectifying portion of a Schottky barrier and a rectifying portion of a PN junction are arranged adjacent to each other.

The semiconductor device has a structure in which, when viewed in cross section, a rectifying portion of a Schottky barrier and a rectifying portion of a PN junction are alternately arranged adjacent to an interface between an electrode (Schottky metal) and a semiconductor layer. Having. According to the above configuration, at the time of forward operation, a current flows through the Schottky barrier, so that a high switching characteristic similar to that of a Schottky diode can be obtained. In the reverse operation, the Schottky junction region is filled with the depletion layer formed by the PN junction, and the leakage current from the Schottky junction region can be suppressed. Therefore, a good reverse voltage characteristic (surge resistance) can be obtained. can get.

However, in the above-described semiconductor device, when a reverse voltage is applied, a region where a rectifying portion formed by a Schottky junction and a junction portion formed by a PN junction are arranged adjacent to each other (hereinafter, referred to as a “rectifying composite region”). The leakage current is likely to flow at the peripheral edge of ()).

As a means for preventing a leakage current, there is known a method of forming an annular guard ring region so as to be adjacent to and surround the outer periphery of a rectifying composite region. The guard ring region is formed as a PN junction region and provided in contact with the electrode. That is, the outer periphery of the rectification composite region is
The junction is terminated, and a boundary portion between the insulating film and the electrode is formed on the surface of the diffusion region constituting the PN junction at the termination. The guard ring region surrounding the rectifying composite region effectively prevents leakage current from the peripheral edge by a depletion layer extending around the guard ring region when a reverse voltage is applied.

[0009]

However, in the semiconductor device having the guard ring region formed on the outer periphery of the rectifying composite region, when a breakdown voltage in the opposite direction is applied, surge current concentrates on the guard ring region. And flow. As described above, the conventional semiconductor rectifier having the guard ring structure has a problem that the surge resistance is low.

In view of the above circumstances, an object of the present invention is to provide a highly reliable semiconductor device. Another object of the present invention is to provide a semiconductor device having a high surge withstand capability.

[0011]

In order to achieve the above object, a semiconductor device according to the present invention is formed on a semiconductor substrate of a first conductivity type and a surface region of the semiconductor substrate. A first semiconductor region of a different first conductivity type and a surface region of the first semiconductor region are formed so as to be exposed in a substantially ring shape to the surface region of the first semiconductor region.
A second semiconductor region of a second conductivity type forming an N-junction; and a surface region of the first semiconductor region inside the second semiconductor region, the surface of which is exposed in an island shape;
A third semiconductor region of a second conductivity type forming a PN junction with the semiconductor region; surfaces of the first semiconductor region and the third semiconductor region exposed inside the second semiconductor region; A semiconductor element provided so as to be in contact with a part of the surface and forming a Schottky junction with the first semiconductor region, wherein the second semiconductor region and the third semiconductor region; A PN junction formed by the first semiconductor region and the first semiconductor region forms a substantially integrated depletion layer when a reverse voltage is applied.
When a reverse breakdown voltage is applied, the voltage reaches the interface between the semiconductor substrate and the first semiconductor region.

In the above structure, for example, the specific resistance of the first semiconductor region is in a range of 0.5 Ωcm to 5 Ωcm, and the semiconductor substrate and the first semiconductor region are arranged from the bottom of the second semiconductor region and the third semiconductor region. The distance to the interface with the region is, for example, in the range of 1.5 μm to 14.5 μm.

According to the above configuration, when a reverse breakdown voltage is applied to the semiconductor element, the surge current flows through a relatively large cross section at the interface between the first semiconductor region and the semiconductor base. It is possible to prevent the flow from being concentrated on the second semiconductor region formed on the periphery of the contact region between the first semiconductor region and the metal layer, and to prevent local destruction of the semiconductor element. As described above, according to the above embodiment, a highly reliable semiconductor device having a high surge withstand capability can be obtained.

In the above structure, the third semiconductor region may be formed at substantially the same depth as the second semiconductor region, or may be formed deeper than the second semiconductor region. This makes it possible to make the breakdown voltage of the third semiconductor region equal to or lower than the breakdown voltage of the second semiconductor region, so that the surge current does not concentrate on the second semiconductor region. be able to.

In the above configuration, for example, a plurality of the third semiconductor regions are formed, and the plurality of the third semiconductor regions are
They are arranged at equal intervals from each other. Further, for example, the plurality of third semiconductor regions are formed at an interval of 0.5 μm to 10 μm from each other.

According to the above configuration, the Schottky junction and the PN junction can be formed uniformly in the first semiconductor region, and when the reverse voltage is applied, the plurality of third semiconductor regions are continuously integrated. A depletion layer is formed.
Therefore, high rectification characteristics (low forward voltage drop, low leakage current, high surge resistance, etc.) of the semiconductor element can be obtained.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. Figure 1
Shows a cross-sectional view of the semiconductor device according to the present embodiment,
FIG. 2 shows a plan view of the semiconductor device of FIG. The semiconductor element described below functions as a diode having a Schottky junction and a PN junction.

As shown in FIG. 1, a semiconductor device 1 according to the present embodiment has an N ^{+ type} silicon layer 11 and an N type silicon region 12 formed on a silicon substrate 10 made of single crystal silicon. It comprises an anode electrode 13 and a cathode electrode 14 provided on the front and back surfaces.

The N ^{+ type} silicon layer 11 is formed on the silicon substrate 1
0 is formed on one surface. The impurity concentration of the N ^{+ type} silicon layer 11 is, for example, about 1.5 × 10 ¹⁹ cm ⁻³ . The N-type silicon region 12 includes the N ⁺ -type silicon layer 11.
It is formed thereon by epitaxial growth. N-type silicon region 12 is, for example, 1.2 × ¹⁰ 16 cm ^{- 3}
Degree (in case of <100> plane) or 9.2 × 10
^It has an impurity concentration of about ¹⁵ cm ⁻³ (in the case of the <111> plane). The thickness L1 is about 2 μm to 15 μm, for example, about 2.1 μm (<100> plane) or about 2.5 μm (<111> plane). At this time, the specific resistance of the N-type silicon region 12 is 0.5 Ωcm to 5 Ωcm.
It is about Ωcm.

On the surface of the N-type silicon region 12, a P ⁺ -type silicon region 16 and a P ^{+ -type} guard ring region 17 are formed.

P⁺The silicon region 16 remains on its surface.
And surrounded by the N-type silicon region 12,
A plurality of islands are formed at equal intervals in the surface region of the region 12.
You. P ⁺The impurity concentration of the silicon region 16 is, for example,
Peak concentration 4.0 × 10¹⁷cm^-3Degree and surface concentration
6.0 × 10¹⁶cm^-3Degree (<100> plane), or
Is the peak concentration of 1.2 × 10¹⁸cm^-3Degree and surface
Concentration 2.0 × 10¹⁶cm^-3Degree (<111> plane)
is there. Also, P⁺Depth L2 of the silicon region 16
Is, for example, about 0.5 μm to 10 μm.
For example, about 1.0 μm (<100> plane) or 1.2
μm (<111> plane). Therefore, P ⁺Shape
N from the bottom of the⁺Silicon layer 11 and N-type silicon
The distance L3 to the interface with the recon region 12 is 1.5 μm
１４14.5 μm.

When the cross section shown in FIG. 1 is viewed, the guard ring region 17
It is provided on both sides of the ^{+ type} silicon region 16. The impurity concentration of the guard ring region 17 is, for example, 4.5 × 10
¹⁸ cm ^-3 (<100> surface) or 6.5 ×
It is about 10 ¹⁸ cm ⁻³ (<111> plane). Also,
The diffusion depth L4 of the guard ring region 17 is, for example, 0.
5 μm to 10 μm, for example, about 1.2 μm (<100> plane) or about 0.9 μm (<111
> Plane). Therefore, the distance L5 from the bottom of the guard ring region 17 to the interface between the N ^{+ type} silicon layer 11 and the N type silicon region 12 is about 1.5 μm to 14.5 μm.

FIG. 2 is a plan view of the semiconductor device 1 shown in FIG. Here, the anode electrode 13 and the insulating film 15 are not shown in FIG.
Are indicated by dotted lines.

As shown in FIG. 2, in this embodiment, a plurality of square P ⁺ -type silicon regions 16 are exposed on the surface of the silicon substrate 10. Around the P ⁺ form silicon region 16, so as to surround the P ⁺ form silicon region 16, a ring-shaped guard ring region 17 is exposed on the surface of the silicon substrate 10. Thus, the surface of the silicon substrate 10 has a configuration in which the N-type silicon region 12 is exposed in a mesh between the P ⁺ -type silicon region 16 and the guard ring region 17.

Returning to FIG. 1, an insulating film 15 is disposed on the upper surface of the silicon substrate 10. The insulating film 15 is composed of a silicon oxide film or the like, and has an opening 15a at the center thereof. When viewed from above as shown in FIG. 2, the openings 15a of the insulating film 15 are formed by a plurality of P ⁺ -type silicon regions 1.
6 and along the guard ring region 17. That is, the guard ring region 17 is N
It is provided on the periphery of a region corresponding to the opening 15 a of the silicon region 12, and is in contact with the anode electrode 13 and the insulating film 15.

Referring back to FIG. 1, an anode electrode 13 is formed on the upper surface of the insulating film 15. The anode electrode 13 is
Silicon substrate 1 through opening 15a of silicon substrate 10
It is in contact with 0. That is, the anode electrode 13 is in contact with the island-shaped exposed N-type silicon region 12 inside the guard ring region 17 formed along the opening 15a.

The anode electrode 13 is made of a metal such as palladium and functions as an anode electrode of the semiconductor element 1 as a diode. The anode electrode 13 in contact with the N-type silicon region 12 at the opening 15a forms a Schottky junction with the N-type silicon region 12. As a result, a rectifying portion by a Schottky junction is formed between the anode electrode 13 and the N-type silicon region 12, and the semiconductor element 1 has a function as a Schottky diode.

The P ⁺ -type silicon region 16 formed inside the guard ring region 17 makes low resistance contact with the anode electrode 13 and has a P-type silicon region with the N-type silicon region 12.
An N junction is formed. Thereby, the P ^{+ type} silicon region 1
A rectifying portion formed by a PN junction is formed between 6 and the N-type silicon region 12, and the semiconductor element 1 has a function as a PN junction diode.

Accordingly, the anode electrode 13 and the N-type silicon region 12 are provided on the anode-side main surface of the silicon substrate 10.
And a P ^{+ -type} silicon region 16 to form a rectifying composite region formed by combining a Schottky junction and a PN junction formed by the P ^{+ -type} silicon region 16. In the rectification composite region, the rectification portion by the PN junction and the rectification portion by the Schottky junction are alternately adjacent to each other. With the above configuration, the characteristics of the Schottky diode and the PN junction diode, that is, low forward voltage drop and reverse breakdown voltage can be obtained.

Here, the guard ring region 17 is composed of a P ^{+ type} diffusion region. The guard ring region 17 surrounding the rectifying composite region is formed with the N-type silicon region 12 and the PN region.
By forming the junction, a reverse current passing through the peripheral portion of the Schottky junction surface of the anode electrode 13 when a reverse voltage is applied is prevented, and a low leakage current and a high surge withstand capability of the semiconductor element 1 can be obtained.

[0031] Here, the ^{P +} silicon region 16 spacing between L6, and the interval L7 between the ^{P +} silicon region 16 and the guard ring region 17 is about 0.5 to 3 m, for example, at about 0.7μm It is formed. At this time, when a reverse voltage is applied to the semiconductor element 1, a plurality of P ⁺
Silicon region 16 and P ^{+ -type} guard ring region 17
And the depletion layer formed by the PN junction between the N-type silicon region 12 and the N-type silicon region 12 are connected to each other, and are in a so-called pinch-off state. Thereby, the electric field applied to the Schottky barrier formed between the N-type silicon region 12 and the anode electrode 13 is reduced. This makes it possible to reduce the leakage current when the reverse voltage is applied.

The specific resistance, impurity concentration, spacing, etc. of the N-type silicon region 12, the P ⁺ -type silicon region 16 and the guard ring region 17 have the above-mentioned numerical configuration. 0.5Ωcm ~ 5Ωcm,
The distances L3 and L5 from the bottoms of the P ^{+ type} silicon region 16 and the guard ring region 17 to the interface between the N ^{+ type} silicon layer 11 and the N type silicon region 12 are each 1.5 μm or more.
It is about 14.5 μm.

In the above structure, the integrated depletion layer 18 formed by the PN junction when the reverse breakdown voltage is applied
Reaches the interface between the N ⁺ -type silicon layer 11 and the N-type silicon region 12, as shown in FIG. 3, and enters a so-called reach-through state. Here, the semiconductor device 1 of the present embodiment
In this case, the Schottky junction does not yield before reaching the reach-through state. Therefore, when a reverse breakdown voltage is applied to the semiconductor element 1, a surge current flows through a relatively large cross section between the N ^{+ type} silicon layer 11 and the N type silicon region 12, so that the surge current flows in the guard ring region. 17 is prevented from flowing intensively, and local destruction of the semiconductor element 1 is prevented.

A cathode electrode 14 is provided on the lower surface of the silicon substrate 10 and is in low resistance contact with the N ^{+ type} silicon layer 11. The cathode electrode 14 is made of, for example, aluminum. Here, the N ^{+ type} silicon layer 11 and N
The silicon region 12 functions as a cathode region of the diode.

As described above, the semiconductor device 1 of the above embodiment has a Schottky junction and an adjacent PN junction, and has characteristics of both a Schottky diode and a PN junction diode, that is, low forward voltage drop, low Has leakage current, high surge resistance, etc. Also, the semiconductor element 1
When a reverse voltage is applied, a depletion layer formed by adjacent PN junctions is integrated and continuous with each other to prevent leakage current from a Schottky junction.

Further, the semiconductor element 1 has the P ^{+ type} silicon region 16 and the guard ring region 1 when a high reverse voltage is applied.
7 and the N-type silicon region 12 are integrated, and the N ⁺ -type silicon region 12 and the N-type silicon layer 1 are integrated.
1 is reached. For this reason,
When a high reverse voltage is applied to the semiconductor element 1, a surge current flows through the PN junction and the Schottky junction through a relatively large cross section between the N ^{+ type} silicon layer 11 and the N type silicon region 12. Is the guard ring area 1
7, and local destruction of the semiconductor element 1 is prevented. Thus, according to the above embodiment, a highly reliable semiconductor rectifier having a high surge withstand capability can be obtained.

The present invention is not limited to the above embodiment, and various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the above embodiment, the N-type silicon region 1
The anode electrode 13 that forms a Schottky junction with the anode 2 is made of palladium, but is not limited thereto.
If it functions as a Schottky metal, such as chromium, titanium, molybdenum, tungsten, and aluminum,
Any metal is possible.

In the above embodiment, P⁺Silicon area
A structure in which 16 are scattered in an N-type silicon region 12 in an island shape;
did. However, as shown in FIG.⁺Silicon area
16 is formed in the N-type silicon region 12 in a stripe shape.
Configurations are also possible. At this time, P⁺Silicon region 16
May be, for example, about 1.7 μm. Also, P ⁺
-Shaped silicon region 16 is meshed with N-type silicon region 12
A formed configuration is also possible. Furthermore, P⁺Shaped silico
The plane shape of the connection area 16 is not a square, but a circle or polygon.
And so on.

In the above configuration, the distance between the P ^{+ type} silicon region 16 and the guard ring region 17 is the same.
The distance between the P ^{+ -type} silicon regions 16 and the like may be reduced.

Further, the thickness and impurity concentration of the N-type silicon region 12, the ^{P +} silicon regions 16 and the diffusion depth and the impurity concentration of the guard ring region 17, the ^{P +} silicon regions 16 and between the ^{P +} silicon region 16 The interval between the guard ring region 17 and the like is not limited to the numerical values shown in the above embodiment. Therefore, when a reverse breakdown voltage is applied, the depletion layer formed by the PN junction before the breakdown of the PN junction reaches the interface between the N-type silicon region 12 and the N ⁺ -type silicon layer 11 (reach-through). Any numerical configuration may be used.

In the above embodiment, the N ^{+ type} silicon layer 1
1, a P-type diffusion region is formed. But,
However, the configuration is not limited to this, and an N-type diffusion region may be formed on the P-type silicon layer.

[0043]

As described above, according to the present invention,
A highly reliable semiconductor element is provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a cross section of the semiconductor device when a breakdown voltage is applied.

FIG. 4 is a plan view of a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor element 10 Silicon substrate 11 N ^{+ type} silicon layer 12 N type silicon region 13 Anode electrode 14 Cathode electrode 15 Insulating film 15a Opening 16 P ^{+ type} silicon region 17 Guard ring region 18 Depletion layer

Claims (5)

[Claims] A semiconductor substrate of a first conductivity type, a first semiconductor region of a first conductivity type formed in a surface region of the semiconductor substrate and having an impurity concentration different from that of the semiconductor substrate; A second semiconductor region of a second conductivity type, the surface of which is formed to be substantially ring-shaped exposed on the surface region, and a PN junction with the first semiconductor region; and the first semiconductor region inside the second semiconductor region. Is formed on the surface region of the first semiconductor region so that the surface is exposed in an island shape.
A third semiconductor region of a second conductivity type forming a junction; surfaces of the first semiconductor region and the third semiconductor region exposed inside the second semiconductor region; and a part of a surface of the second semiconductor region And a metal layer provided to be in contact with the first semiconductor region and forming a Schottky junction with the first semiconductor region, wherein the second semiconductor region, the third semiconductor region, and the first semiconductor region are provided. And a PN junction formed by the first and second regions form a substantially integrated depletion layer when a reverse voltage is applied, and the depletion layer forms the semiconductor substrate and the first semiconductor region when a reverse breakdown voltage is applied. A semiconductor element reaching an interface with the semiconductor element. 2. The semiconductor device according to claim 1, wherein the first semiconductor region has a specific resistance of 0.5Ωc.
m to 5 Ωcm, and the semiconductor substrate and the first semiconductor region are located at the bottom of the second semiconductor region and the third semiconductor region.
The distance to the interface with the semiconductor region is 1.5 μm to 14.5.
The semiconductor device according to claim 1, wherein the semiconductor device is in a range of μm. 3. The semiconductor device according to claim 1, wherein the third semiconductor region is formed at substantially the same depth as the second semiconductor region or deeper than the second semiconductor region.
Or the semiconductor element according to 2. 4. The semiconductor device according to claim 1, wherein a plurality of said third semiconductor regions are formed, and said plurality of third semiconductor regions are arranged at equal intervals from each other. Semiconductor element. 5. The semiconductor device according to claim 1, wherein the plurality of third semiconductor regions are at a distance of 0.1 mm from each other.
5. The semiconductor device according to claim 4, wherein the semiconductor device is formed at an interval of 5 μm to 10 μm.