JP2002237470A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a homogeneous silicide layer that less produces a defect such as a junction leak. SOLUTION: A method for manufacturing a semiconductor device includes a preheating step of heating the surface of a silicon layer during formation of a metal film, when the metal film is formed on the silicon layer and then the silicon layer is heated to make the metal film react with the silicon layer and to form the silicide layer on the silicon layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which at least a surface layer of a silicon layer is silicided.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, miniaturization of device sizes has been promoted. This means that as the miniaturization progresses, the number of devices that can be obtained from one substrate increases,
This is because when the semiconductor device includes a transistor, the characteristics of the transistor are improved. However, with the progress of miniaturization, the resistance of the wiring portion, not the transistor itself, has influenced the operation speed of the transistor. Therefore, in the manufacture of a semiconductor device, a salicide technique for reducing the resistance of a gate line, a diffusion region, or the like is indispensable.

In manufacturing a semiconductor device using the salicide technique, first, a normal transistor is formed on a silicon substrate. That is, formation of an element isolation region, a well, a gate, and an N + / P + diffusion layer. Next, after performing a surface treatment on the silicon substrate after the transistor formation step using a hydrofluoric acid aqueous solution or the like to expose the silicon surface, a metal film is formed on the silicon surface.

Next, a protective film for preventing oxidation of the metal film is provided on the metal film, and the substrate is heated by RTA (Rapid Thermal Annealing) or the like (annealing for forming silicide). Forming a silicide layer on the substrate by reacting silicon of the substrate with the metal film. On the surface of the silicon substrate on which the silicide layer is formed, there is a portion that does not cause a silicide reaction, such as an element isolation region or a sidewall formed by an oxide film.

[0005] Since these portions are portions for electrical isolation, there is a problem if unreacted metal remains on these portions. Therefore, a chemical treatment for removing the unreacted metal film on the element isolation region and the sidewall is performed. This process includes
Dissolving the metal film formed on the surface of the silicon substrate,
A chemical solution that does not dissolve silicide is used.

Finally, annealing for phase change of the silicide is performed at a temperature higher than the heating temperature in the annealing for forming the silicide to change the silicide layer into a structure having a lower resistance. The reason for dividing the annealing process into two is that if the temperature is too high in the annealing for forming silicide, silicon of the substrate diffuses violently into the element isolation region and the metal film on the sidewall, and the silicide is separated into the element isolation region and This is because it is also formed on the sidewall. By using such a salicide technique, a low-resistance conductive region can be formed only on the silicon surface by utilizing the selectivity of the reaction without using a conventional photolithography technique.

However, a disadvantage of the above-mentioned method using the salicide technique is that silicon of the substrate is consumed in forming the silicide. As the thickness of the N + / P + diffusion layer becomes thinner with the progress of miniaturization, and when silicon in this region is consumed for forming the silicide layer, the lower surface of the formed silicide layer and N + The distance from the junction below the / P + diffusion layer is further reduced, and junction leakage is likely to occur. In this case, if the silicide layer is thinned, consumption of silicon during silicide formation can be suppressed, and the distance between the junction and the bottom surface of the silicide layer can be increased to reduce junction leakage. And the sheet resistance of the diffusion region is increased.

Usually, as a countermeasure for suppressing a junction leak and an increase in sheet resistance, a method of forming silicide flat is used. It is known that the flatness of silicide greatly changes during the above-described reaction between metal and silicon based on the state of the silicon surface of the substrate. This is because even if the oxide film is removed from the silicon surface of the substrate by a pretreatment or the like, the silicon surface is exposed to the air and an oxide film is formed again before the metal film is formed.

If the oxide film formed between the metal film and the silicon substrate is extremely thin, silicide is formed.
This is usually the metal used to form the silicide,
This is because the silicon oxide film has a reducing property. However, since the oxide film formed on the surface of the silicon substrate is generally non-uniform, a portion where silicide is easily generated and a portion where silicide is not easily generated are formed, and as a result, a non-uniform silicide layer is formed on the silicon substrate. The silicide layer formed on the non-uniform oxide film is liable to cause a junction leak because the distance between the bottom surface of the silicide layer and the junction under the N + / P + diffusion layer is short in a thick portion, Further, since the average thickness of the silicide layer itself is small, the sheet resistance is large.

Further, depending on the device, carbon, fluorine and the like may be mixed into the silicon surface during the manufacturing process. These are likely to occur mainly in steps such as gate etching and etch-back when forming sidewalls. It is considered that the incorporation of such an element increases the non-uniformity of the silicon surface, and causes a junction leak by the same effect as the non-uniformity of the oxide film.

As a method of improving such non-uniformity of silicide and preventing junction leakage, for example, Japanese Patent Application Laid-Open
There is a method of manufacturing a semiconductor device described in JP-A-9-251967. The manufacturing method described in the above publication will be described in the order of steps with reference to FIG. It is to be noted that, since this diagram is a schematic diagram in which the scale is partially enlarged for explanation, its shape or size is not necessarily the same as that of an actual device.

FIG. 2A shows a state in which the silicon surface is made amorphous after the formation of the transistor is completed. 101 is a gate, 102 is a sidewall, 103
Is a shallow diffusion layer, 104 is an element isolation region, 105 is an amorphous region formed by ion implantation, 107 is a deep diffusion layer, and 106 is silicon (silicon wafer) as a substrate. To simplify the description, gate oxide films, wells, and the like are omitted in the figure.

FIG. 2B shows a state in which the formation of the metal film 108 and the oxidation preventing film 109 has been completed. Cobalt is often used for the metal film 108, and cobalt is
Reacts with 6 to produce silicide. Antioxidant film 10
Titanium nitride 9 is often used and functions as a film for preventing oxidation of the metal film 108.

FIG. 2C shows a state after annealing for forming silicide is performed in the state of FIG. 2B. The silicide layer 110 is formed so as to fit in the amorphous region 105 provided in the above (a). Since silicon in the amorphous region 105 that has been uniformly amorphousized reacts with cobalt in the metal film 109, the formed silicide layer 110 has high flatness. Fig. 2 (d)
This is a state after annealing for phase change of silicide is performed in the state of (c). Annealing for the phase change of silicide is performed at a higher temperature than annealing for forming silicide. By this annealing, the silicide layer 110 generated in (c) further reacts with the silicon 106 of the substrate to form a silicide layer 111 having an increased thickness. Since a uniform silicide layer 110 is formed in (c), the PN junction and the silicide layer 1
Even at a portion where the distance of 10 is the closest, a distance that does not cause junction leakage is maintained.

[0015]

As described above, in order to make the silicon surface amorphous by implanting ions, ions of arsenic or the like having a relatively large mass are usually used. However, it is known that such ions easily form an amorphous layer, but easily cause defects in a region deeper than the region into which the ions are implanted. When such a defect occurs, a level which causes a junction leak of silicon is easily generated. The increase in the leakage current increases the current consumption during standby of the device, which is a serious problem particularly in an LSI for a portable device operated by a battery or the like.

The present invention has been made in view of the above problems, and has as its object to form a silicide layer which is more uniform and hardly causes defects such as junction leaks in a semiconductor device.

[0017]

According to the present invention, a first heating is performed on a surface of a silicon layer, a metal film is laminated in that state, and then a second heating is performed to at least form the silicon layer. There is provided a method for manufacturing a semiconductor device, wherein a surface layer is silicided.

That is, in the present invention, the thermal energy of the heated silicon layer surface is used to form an oxide film and a metal film formed on the surface of the silicon layer. By reacting with the supplied metal atoms, the oxide film is reduced. As a result, the oxide film disappears or becomes thinner, so that a uniform and flat silicide layer can be formed on the surface of the silicon layer.

The silicon layer in the present invention may be a silicon substrate itself on which a circuit portion of a semiconductor element such as a capacitor or a transistor is formed, or a silicon layer functioning as a conductive layer or a wiring layer of these elements. .

The first heating temperature is preferably from 300 to 400.degree. If the first heating temperature is lower than 300 ° C., irregularities are likely to occur at the interface between the silicon and the silicide layer. If the first heating temperature is higher than 400 ° C., the breakdown voltage of the gate oxide film or the like tends to deteriorate due to plasma damage during the sputtering of the metal film.

The material of the metal film in the present invention includes:
Examples thereof include high melting point metals such as cobalt and titanium, but are not particularly limited as long as they react with silicon to form silicide. As a method of forming a metal film, a vapor deposition method,
Conventional thin film forming techniques such as CVD and sputtering can be used.

The second heating means in the present invention includes furnace annealing, annealing by RTA and the like. The second heating temperature is preferably from 500 to 900C.

According to the present invention, after the metal film is formed, an antioxidant film is formed on the surface of the metal film while the temperature of the surface of the silicon layer is once lowered from the first heating temperature. The step of performing the second heating is included. That is, when the silicon layer forming the transistor is silicided by using the manufacturing method including the first heating step of the present invention, the breakdown voltage of the gate oxide film may be deteriorated. Since the amount of current flowing through the oxide film during the film formation can be reduced, the above-described deterioration of the breakdown voltage is prevented. The temperature of the silicon layer during the formation of the antioxidant film is
It is sufficient that the temperature falls to 200 ° C. or lower, and the lower limit is not particularly defined. The material of the antioxidant film in the present invention includes titanium nitride, but is not particularly limited as long as it is a material of the conventional antioxidant film. As a method of forming the antioxidant film, a vapor deposition method, CV
Conventional thin film forming techniques such as method D and sputtering can be used. According to the present invention, since the antioxidant film can be continuously formed by the film forming apparatus used for forming the metal film, the oxidation of the metal film can be prevented.

If it is desired to further improve the junction leakage using the above method, a part or all of a region from the surface of the silicon layer to a depth of 12 nm from the surface of the silicon layer is subjected to the first heating. It is preferable to make it amorphous.
That is, if the surface of the silicon layer is contaminated with carbon, fluorine, or the like, and the temperature of the silicon layer is increased to form a metal film, the resulting silicide is not uniform. By making the outermost surface of the layer amorphous, the bond between carbon and fluorine and silicon is broken, and the reaction with the metal is promoted. As a result, the reaction between the metal and silicon proceeds uniformly, silicide is formed uniformly, and junction leakage is suppressed. It is preferable that the above-mentioned amorphization is usually performed so that the ionic species diffuse only into a shallow portion in the upper layer portion of the silicon layer and the ionic species do not enter into the deep portion of the silicon layer.

The penetration depth of the ion species mainly depends on the implantation energy. Examples of ion species used for the above shallow ion implantation include boron, phosphorus, arsenic, nitrogen, and silicon. Among them, relatively heavy arsenic is preferable.
The ion implantation amount in the present invention is 1E14 to 8E14 / c.
The ion implantation energy is on the order of m ² , and the ion implantation energy is 5 to 15 keV.

As described above, since the ion implantation energy in the present invention is smaller than that of the prior art, even if a region where a defect occurs due to the implanted ion species occurs in the silicon layer, the depth is not so large. Therefore, it does not affect the joining region.

According to the present invention, ion implantation is performed in a state where the surface of the silicon layer is not exposed (for example, in a state where an oxide film or the like existing on the silicon surface is not removed or in a state where a protective film is laminated). As a result, the invasion of the ion species into the deep portion of the silicon layer can be stopped, and the ion species can be implanted only into the shallow portion of the upper portion of the silicon layer. Therefore, shallow ion implantation becomes possible irrespective of the capability of the ion implantation apparatus.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings, but the present invention is not limited by these embodiments. Figure 1
1 shows an outline of a manufacturing process of a MOS transistor according to the present invention. Note that FIG. 1 is not necessarily the same as the actual device shape because the scale is partially enlarged for the sake of explanation. For simplicity, gate oxide films, wells, and the like are omitted from the figure.

Embodiment An embodiment of the present invention will be described with reference to FIG. Figure 1
(A) shows a state where the silicon surface is made amorphous after the formation of the MOS transistor is completed. 1 is a gate electrode, 2 is a sidewall, 3 is a shallow diffusion layer, 4 is an element isolation region, 5 is an amorphous layer, 7 is a deep diffusion layer, 6
Is a silicon substrate (silicon wafer).

The formation of the amorphous layer is performed when the surface of the silicon substrate 6 to be silicided is contaminated with carbon, fluorine or the like. The depth of the shallow diffusion layer 3 is 120 n.
m, the depth of the deep diffusion layer 7 is 160 nm. Each of the diffusion layers 3 and 7 is manufactured by implanting BF ₂ and As.

The sidewall 2 can be formed by a method of etching back to the surface of the silicon substrate 6 or a method of leaving an oxide film of about 10 nm on the surface of the silicon 6. According to the latter method, it is possible to reduce contamination of carbon and fluorine due to the influence of etching generated on the surface of the silicon substrate 6. However, when a plurality of devices are manufactured in the same process, the film thickness to be etched back is reduced. It may be different depending on the part, and it may be difficult to leave an oxide film on the surface of silicon 6.

The formation of the amorphous layer 5 was performed by arsenic ion implantation. Normally, when arsenic ions are implanted into the silicon substrate 6, an amorphous region is generated on the surface side of the silicon substrate 6 beyond the average projection range. Further, at the part deeper than the average projection range, it was knocked out by implanted As
This produces a region into which Si atoms have entered. Such a region is likely to have a defect, and dislocation is generated by a heating process. These cause junction leakage.

However, in the present invention, since arsenic ions are implanted into a very shallow region on the surface of the silicon substrate 6, the implantation energy is 10 keV and the amount of implanted ions (doping amount) is 3E14 / cm2). As described above, since the implantation energy is small, even if a region into which the silicon atoms knocked out by the implanted arsenic ions enter as described above is formed, the depth is not so deep. Has no effect.

FIG. 1B shows a state in which the formation of the metal film 8 has been completed after the first heating. The metal film 8 is formed on the silicon substrate 6
This is a metal film for generating silicide by reacting with cobalt. In this example, cobalt was used. The metal film 8 was formed by sputtering. Set the power of the sputtering device to 50
0 W and the pressure in the apparatus was about 5 mT. The temperature (first heating temperature) of the silicon substrate 6 during sputtering is 350 ° C.
And Note that when the first heating temperature is 300 ° C. or lower, unevenness is generated at the interface between silicide and silicon, and a junction leak is likely to occur. If the metal film 8 is made thin while leaving the unevenness in order to reduce the junction leak, the sheet resistance will increase. When the first heating temperature is 400 ° C. or higher, the gate oxide film is deteriorated in breakdown voltage due to plasma damage during sputtering.

FIG. 1C shows a state in which after the formation of the metal film 8, the temperature of the silicon substrate 6 is temporarily lowered, and the antioxidant film 9 is formed in this state. The antioxidant film 9 was formed by sputtering using titanium nitride in this example. The power of the sputtering equipment is 2 kW and the pressure inside the equipment is 10
It was about mT. The sputtering of the metal film 8 and the sputtering of the antioxidant film 9 were continuously performed in the same sputtering apparatus while maintaining a vacuum. This is to prevent oxidation of cobalt in the metal film 8. The temperature of the silicon substrate 6 at the start of the sputtering was 70 ° C.

If the temperature of the silicon substrate 6 exceeds 200 ° C. during the sputtering of the antioxidant film 9, the breakdown voltage of the gate insulating film may be deteriorated due to plasma damage at the time of sputtering the antioxidant film 9. The degree of deterioration of the breakdown voltage differs depending on the device. If it is confirmed that the breakdown voltage of the gate insulating film has deteriorated, the temperature of the silicon substrate 6 is raised to 200 while holding the silicon substrate 6 while maintaining a vacuum of the order of 10E-8 in the same apparatus after the sputtering of the metal film 8.
℃. However, since the substrate temperature is lowered to 200 ° C., the processing time becomes longer, and the throughput is reduced.

FIG. 1D shows a state after the formation of the oxidation preventing film 9 is completed and a second heat treatment is performed. A silicide layer 10 is formed in each of the diffusion layers 3 and 7.
The second heating temperature was 570 ° C. FIG. 1 (e) shows a state in which a heat treatment at a higher temperature than the state of the above (d) has been performed. By the high-temperature heat treatment, the silicide layer 10 generated in the above (d) further reacted with the silicon substrate 6 to form a silicide layer 11 having an increased film thickness.

[Comparative Example] As was added to the N ⁺ diffusion layer region of the device as a sample under the conditions of 50 keV, 3E15 / cm ² , and P ⁺
After injecting BF ² into the diffusion layer region under the conditions of 30 keV and 2E15 cm ² , RTA annealing was performed at 1000 ° C. for 10 seconds. afterwards,
As was implanted into the surface of the silicon substrate under the conditions of ²⁰ keV and 3E14 / cm ² . This step is a method according to the prior art for amorphizing Si.

Thereafter, the natural oxide film on the surface of the silicon substrate was removed with an aqueous HF solution. Co with a film thickness of 80Å, then Ti
N 2 was deposited at a film thickness of 200 ° in this order by continuous sputtering in vacuum, and annealing at 570 ° C. for 60 seconds using RTA was performed in a nitrogen atmosphere. Then, unreacted Co and TiN were removed with a 4: 1 solution of sulfuric acid: hydrogen peroxide. At this time, the thickness of the silicide was about 150 mm. afterwards,
Annealing at 750 ° C. for 30 seconds was performed in a nitrogen atmosphere using RTA. The final thickness of the silicide layer was about 300 mm.

The sample on which the silicide layer was formed by the conventional method had an average junction leakage current of 1.8 V and 1.8E-8Å / cm ^2.
(N ⁺ diffusion layer side) and 3.4E-7Å / cm ² (P ⁺ diffusion layer side)
Met. On the other hand, the sample in which silicide was formed by applying the method of manufacturing a semiconductor device of the present invention shown in the above embodiment had an average junction leakage current of 1.8 V and 1.8E-8Å / cm ^2.
(N ⁺ diffusion layer side) and 2.5E-8Å / cm ² (P ⁺ diffusion layer side)
Met. In the sample device in which the silicide layer was formed by the conventional method, the junction with the junction under the N + / P + diffusion layer was not broken, but the leakage current increased by one to two digits.

[0041]

According to the present invention, in order to form an oxide film and a metal film formed on the surface of the silicon layer by utilizing the thermal energy of the surface of the silicon layer which has been heated, the surface of the silicon layer is formed. By reacting with the supplied metal atoms, the oxide film is reduced. As a result, the oxide film disappears or becomes thinner, so that a uniform and flat silicide layer can be formed on the surface of the silicon layer. Therefore, junction leakage in the semiconductor device is less likely to occur.
Further, by forming the antioxidant film while the temperature of the silicon layer is once lowered after forming the metal film, deterioration of the breakdown voltage in the semiconductor device formed on the silicon layer is prevented.

By making the surface of the silicon layer amorphous, the bond between carbon and fluorine and silicon is broken, and the reaction between metal atoms forming the metal film and silicon is promoted. As a result, the reaction between the metal film and silicon proceeds uniformly, silicide is formed uniformly, and junction leakage is suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic process diagram illustrating an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic process diagram illustrating an embodiment of a method for manufacturing a semiconductor device according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate electrode 2 Side wall 3 Shallow diffusion layer 4 Element isolation region 5 Amorphous layer 6 Silicon substrate (silicon layer) 7 Deep diffusion layer 8 Metal film 9 Oxidation prevention film 10 Silicide layer 11 Low resistance silicide layer

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yasuhiko Sueyoshi 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka F-term (reference) 4M104 AA01 BB20 CC01 DD22 DD26 DD37 DD79 DD82 DD84 GG09 GG10 GG14 HH04 5F048 AA07 AB03 AC01 BA01 BF06 BF16 BG14 5F140 AA10 AA24 AB01 AB03 BG08 BJ01 BJ08 BK22 BK29 BK34 BK38 BK39

Claims (6)

[Claims] 1. A first heating is performed on a surface of a silicon layer, a metal film is laminated in that state, and then a second heating is performed to silicide at least a surface layer of the silicon layer. Semiconductor device manufacturing method. 2. The method according to claim 1, wherein the first heating temperature is 300 to 400 ° C. 3. The method according to claim 1, wherein the second heating temperature is 500 to 900 ° C. 4. After the metal film is formed, the temperature of the surface of the silicon layer is temporarily lowered from the first heating temperature.
4. The method of manufacturing a semiconductor device according to claim 1, wherein an antioxidant film is formed on a surface of the metal film, and then the second heating is performed. 5. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the oxidation prevention film is formed on the surface of the metal film while the temperature of the surface of the silicon layer is temporarily lowered to 200 ° C. or less from the first heating temperature. Method. 6. The method according to claim 1, further comprising a step of amorphizing a part or all of a region from the surface of the silicon layer to a depth of 12 nm before performing the first heating. A method for manufacturing a semiconductor device.