JPH09298297A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress a short channel effect and also suppress fluctuations in characteristics caused by variations in a sidewall width. SOLUTION: The semiconductor device includes a low-concentration source/ drain region 6 having impurities implanted therein with use of a first sidewall insulating film 4 contacted with a gate electrode 3 of polysilicon as a mask, and also includes a high-concentration source/drain region 8 having impurities of the same conduction type as the above impurities implanted therein with use of a second sidewall insulating film 7 positioned outside the first sidewall insulating film 4 as a mask, the concentration of the region 8 being higher than that of the region 6. The first sidewall insulating film 4 oxidizes the gate electrode 3, a substrate oxidizing film 5' is positioned under the second sidewall insulating film 7, and the film 5' is formed by making thin the original substrate oxidizing film 5 formed at the time of obtaining the first sidewall insulating film 4.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an LDD (Light).
The present invention relates to a semiconductor device having a tly doped drain structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, in order to manufacture a semiconductor device having an LDD structure, sidewalls are formed on both sides of a gate electrode.

For example, Japanese Patent Laid-Open No. 3-171740 discloses a method of forming the sidewall by oxidizing a polysilicon gate electrode. According to this method, an oxide film is formed on the surface of the semiconductor substrate at the same time as the sidewall. However, when the impurities are implanted using the sidewall as a mask, the oxide film on the surface of the semiconductor substrate is usually not removed. Have been to. This is because the oxide film formed on the polysilicon gate electrode has a film thickness of 20 nm to 40 nm, while the oxide film on the surface of the semiconductor substrate has a small film thickness of about 10 nm. This is because injection can be performed.

On the other hand, in Japanese Patent Laid-Open No. 3-214737 or Japanese Patent Laid-Open No. 4-180235, an LDD structure is adopted in which the sidewalls have a multilayer film structure and impurities are sequentially injected using the sidewalls made of each film as a mask. However, since this method is a method in which an insulating film is deposited by a CVD method or the like and anisotropically etching is performed to form the sidewalls, insulation on the surface of the semiconductor substrate other than the sidewalls is disclosed. The film is completely removed.

[0005]

By the way, in recent years,
A transistor compatible with a low power supply voltage of about 2 V has been developed, but in such a transistor, it is necessary to set the substrate impurity concentration low because it is necessary to lower the threshold voltage. Further, in order to increase the drain current, it is necessary to increase the impurity concentration of the low concentration source / drain layer. Therefore, if the transistor has the same structure as the conventional transistor for a power supply voltage of 3.3 V, the short channel effect is likely to occur.

Here, as described above, when the side wall is formed by oxidizing the gate electrode, impurities are usually ion-implanted while leaving the oxide film on the surface of the semiconductor substrate. It must be strengthened by the presence of the oxide film. For this reason,
The source / drain layer tends to enter under the gate electrode, making it difficult to suppress the short channel effect in a transistor compatible with a low power supply voltage. Therefore, JP-A-3-1717
As disclosed in Japanese Patent Laid-Open No. 40-40, the ion implantation using the sidewalls obtained by oxidizing the gate electrode as a mask is used only in forming the high-concentration diffusion layer and determines the effective channel length. In the formation of, the ion implantation using the side wall obtained by oxidizing the gate electrode as a mask is not performed. Furthermore, since it is not possible to independently set the film thickness (sidewall width) of the sidewall obtained by oxidizing the gate electrode and the film thickness of the oxide film on the surface of the semiconductor substrate, it is attempted to increase the film thickness of the sidewall. Then, the film thickness of the oxide film on the surface of the semiconductor substrate is also increased. Therefore, when the thickness of the side wall is increased, the implantation strength of the ion implantation must be further increased, which causes the low concentration source / drain layer to enter under the gate electrode. However, this method has an advantage that variation in the film thickness of the sidewall is small.

On the other hand, in the technique disclosed in Japanese Patent Laid-Open No. 3-214737 or Japanese Patent Laid-Open No. 4-180235, the insulating film is formed by film deposition such as the CVD method as described above. The thickness tends to vary,
Furthermore, in anisotropic etching, the amount of overetching must be increased in consideration of the variation in the thickness of the oxide film, and the variation in the sidewall width becomes even greater. Further, due to the miniaturization of the semiconductor device structure, it becomes difficult to more strictly control the sidewall width and the junction profile of the source / drain layers, so that the transistor characteristics vary. Further, the increase in the amount of over-etching causes defects due to etching damage in the low-concentration source / drain layers, so that problems such as increase in leak current and deterioration of hot carrier characteristics occur.

Further, any of the above-mentioned conventional techniques includes a step of performing ion implantation using only the gate electrode as a mask. In this step, the source / drain layer easily enters under the gate electrode, so that a transistor compatible with a low power supply voltage is provided. Sufficient suppression of the short channel effect at.

In view of the above situation, the present invention can suppress the short channel effect, suppress the characteristic fluctuation due to the variation of the sidewall width, and further prevent the characteristic deterioration due to the etching damage and the manufacturing thereof. The purpose is to provide a method.

[0010]

According to the present invention, there is provided a semiconductor device comprising:
A low-concentration diffusion layer formed by implanting impurities using the first sidewall insulating film in contact with the gate electrode made of polysilicon or polycide as a mask, and a second sidewall insulating film located outside the first sidewall insulating film. A high-concentration diffusion layer formed by injecting an impurity of the same conductivity type as that of the impurity with a concentration higher than that of the low-concentration diffusion layer using the mask as a mask. The substrate oxide film is formed by oxidation, and the substrate oxide film is located below the second sidewall insulating film, and the substrate oxide film is a substrate oxide film that was initially formed when the first sidewall insulating film was obtained. It is characterized by being made thin.

With this structure, since the first side wall insulating film is formed by oxidizing the gate electrode, there is little variation in the film thickness, and the first side wall insulating film is used as a mask to form a low film. The accuracy of the formation position of the concentration diffusion layer is high, and it is possible to reduce variations in transistor characteristics between elements. Further, this low-concentration diffusion layer is formed by using the first sidewall insulating film as a mask, and the low-concentration diffusion layer penetrates under the gate electrode as compared with the one formed by using only the gate electrode as a mask. Is less likely to occur, it is easy to suppress the short channel effect. Further, since the substrate oxide film is formed by thinning the substrate oxide film at the beginning of formation, the ion implantation energy at the time of forming the low concentration diffusion layer can be reduced, which also contributes to the formation of the low concentration diffusion layer below the gate electrode. Less likely to get in. Furthermore, the presence of the thin substrate oxide film described above can reduce damage to the substrate during etching of the substrate oxide film, and suppress generation of interface states under the sidewall due to leak current and hot carriers. be able to.

The thickness of the first side wall insulating film is 40 nm.
It is preferably 100 nm or more and 100 nm or less. When the thickness of the first sidewall insulating film is 40 nm or more, it is difficult for the low concentration diffusion layer formed using the first sidewall insulating film as a mask to enter under the gate electrode. Since the thickness of the first sidewall insulating film is 100 nm or less, even if the low-concentration diffusion layer is formed by low-energy ion implantation, the offset amount of the low-concentration diffusion layer with respect to the gate electrode can be reduced, The fluctuation of the drain current can be reduced.

It is desirable that the film thickness of the substrate oxide film is 10 nm or less. With this structure, the low-concentration diffusion layer can be formed by low-energy ion implantation. Therefore, the gate electrode of the low-concentration diffusion layer is formed. It is less likely to get into the bottom.

It is desirable that the end of the low-concentration diffusion layer is located at the end of the channel region under the gate electrode. With this structure, the short channel effect is suppressed and an offset structure is formed. Can be prevented.

The gate electrode is a multilayer structure in which a polysilicon layer, a first silicide layer having a low metal content, a second silicide layer having a high metal content, and a silicon oxide film are laminated in this order from the bottom. It may have a film structure.
Here, "the content of the metal is small" is an amount determined from the viewpoint of preventing the polysilicon layer and the silicide layer from being separated from each other, and preferably, the atomic percentage of the metal is more than 20% and 30% or less. It Also,
The "high metal content" is an amount determined from the viewpoint of reducing the resistance of the gate electrode, and preferably the atomic percentage of the metal is more than 30% and 50% or less. Further, as the metal, for example, a metal having a high melting point (melting point of 1400 ° C. or higher) is used.

According to the above construction, the presence of the first silicide layer in the formation of the first side wall insulating film can prevent the polysilicon layer and the silicide film from peeling off. By the presence of the silicide layer, the resistance of the gate electrode can be reduced.

Further, in the method for manufacturing a semiconductor device of the present invention, the first step of oxidizing the substrate on which the gate electrode is formed and the oxide film formed on the surface of the substrate in the first step are all removed or A second step of thinning and a third step of forming a low-concentration diffusion layer by implanting ions with the first sidewall insulating film formed at the side end portion of the gate electrode in the first step as a mask And a fourth step of forming a second sidewall insulating film located outside the first sidewall insulating film, and ion implantation in the third step using the second sidewall insulating film as a mask. And a fifth step of implanting ions at a high concentration to form a high-concentration diffusion layer. As a result, the semiconductor device described above can be manufactured.

In the above manufacturing method, the second sidewall insulating film is formed of a material different from that of the first sidewall insulating film, which is an oxide film, and then formed on the upper surface of the gate electrode in the first step. The oxide film may be removed. This reduces variation in the film thickness (width) of the second sidewall insulating film due to the etching for removing the oxide film, and reduces variations in characteristics.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a cross-sectional view showing a manufacturing process of an NMOS transistor of this embodiment. First, as shown in FIG. 1A, after forming an oxide film to be a gate insulating film 2 and polysilicon to be a gate electrode 3 on a p-type silicon substrate (or p well) 1,
The gate electrode 3 is formed by lithography and etching.

Next, as shown in FIG.
The first side wall insulating film 4 having a thickness of about 60 nm is obtained by placing the substrate in an oxygen atmosphere at 950 ° C. and thermally oxidizing the surface of the gate electrode 3. At this time, a substrate oxide film 5 having a film thickness of about 20 nm (hereinafter, this substrate oxide film is referred to as a substrate oxide film at the beginning of formation) 5 is also formed on the surface of the silicon substrate 1.

Next, as shown in FIG. 3C, the initial formation substrate oxide film 5 having a film thickness of about 20 nm is etched by anisotropic etching to reduce the film thickness to about 5 nm. A substrate oxide film 5'is obtained. Then, phosphorus (P) is implanted with an energy of 10 keV and a dose of 4E1.
Implantation is performed under the condition of 3 / cm ² to form the n-type low-concentration source / drain layer 6.

Next, as shown in FIG. 3D, a silicon nitride film to be the second sidewall insulating film 7 is formed to 70 n by the CVD method.
Then, the second side wall insulating film 7 is formed by anisotropic etching. In this anisotropic etching,
The silicon nitride film deposited on the silicon substrate 1 is completely removed. This is because the silicon nitride film formed by the CVD method is not uniform in film thickness as compared with the above-described thermal oxide film which becomes the first sidewall insulating film 4, so that the uniformity of ion implantation is not deteriorated. This is because
It should be noted that FIG. 6D shows a state in which the substrate oxide film 5'is also removed by this etching. After that, arsenic (A
s), implantation energy 30 keV, dose 4E15
/ Cm ² to implant the n-type high-concentration source / drain layer 8. As described above, the second side wall insulating film 7 is formed by the CVD method, so that the film thickness (width) of the second side wall insulating film 7 varies.
The high-concentration source / drain layer 8 is formed by ion implantation using the mask as a mask, and strictness in the formation position accuracy is not required unlike the low-concentration source / drain layer 4, so the film of the second sidewall insulating film 7 is formed. Thickness (width) variations are not a concern here.

Next, the substrate is exposed to a nitrogen atmosphere at about 800 ° C. for about 60 minutes to perform heat treatment for activating impurities. As a result, as shown in FIG.
8 will spread somewhat laterally.

Here, in the steps shown in FIGS. 1B and 1C, if the impurity is ion-implanted in the state where the substrate oxide film 5 is initially formed (film thickness is 20 nm), the implantation strength is increased. However, this increases the junction depth of the low-concentration source / drain layer 6 formed by this ion implantation and the penetration into the inside of the channel, thereby suppressing the short channel effect. Is insufficient. On the other hand, when the implantation strength is set to a value lower than 30 keV (for example, 10 keV to 20 keV), the peak concentration position of the impurity and the oxide film / silicon substrate interface are substantially the same, and thus the substrate oxide film 5 at the initial formation is formed. Even a slight variation causes a concentration variation in the low-concentration source / drain layer, which deteriorates the transistor characteristics.

In the method of manufacturing the NMOS transistor of this embodiment, the substrate oxide film 5 initially formed on the silicon substrate 1 is changed to the substrate oxide film 5'having a thickness of about 5 nm, and then phosphorus (P) is added.
Since the implantation strength of is suppressed to a low value of about 10 keV, the above-mentioned problem does not occur.

Further, the initial-formation substrate oxide film 5 on the silicon substrate 1 formed in the step of FIG. 1B has good film thickness uniformity, and the variation is suppressed to about ± 3%. Further, since the substrate oxide film 5 is initially formed by thermal oxidation, it is thinner than the first sidewall insulating film 4. Therefore, it takes only a short time to thin the substrate oxide film 5 by etching at the initial formation, and the film thickness of the substrate oxide film 5'obtained by this etching can be suppressed to about ± 5%. That is, the substrate oxide film 5
Since the film thickness uniformity is excellent, the variation of the impurity implantation concentration is reduced, and the variation of the drain current between the elements is reduced. Although the substrate oxide film 5 at the beginning of formation may be completely removed, it is preferable that the substrate oxide film 5'being left at the beginning not be completely removed as in this embodiment. By leaving the substrate oxide film 5 ', damage to the silicon substrate 1 at the time of etching the substrate oxide film can be reduced, and generation of an interface state under the sidewall due to leak current or hot carriers can be suppressed. Because.

Further, since the first side wall insulating film 4 is formed by thermal oxidation, the drawbacks of obtaining the first side wall insulating film by the CVD method can be solved. That is, when the sidewall insulating film is deposited by the CVD method, the thickness of the deposited film on the silicon substrate is approximately the same as the thickness of the sidewall insulating film. It cannot be left to the extent of etching. Therefore, there is no choice but to completely remove the deposited film on the silicon substrate, and if over-etching is performed in this removal, the low-concentration source / drain layer on the silicon substrate will be damaged, and the problems described in the conventional example will be solved. Occurs. Further, the over-etching increases the variation in the thickness of the sidewall insulating film (about ± 10%). According to the method of this embodiment, since the first side wall insulating film 4 is formed by thermal oxidation, the variation in the film thickness of the first side wall insulating film 4 can be suppressed to about ± 5%. And like this,
Since the variation in the film thickness of the first sidewall insulating film 4 can be suppressed low, the variation in the positional relationship between the gate electrode 3 and the end of the low concentration source / drain layer 6 can be reduced, and the variation in the transistor characteristics can be reduced.

Further, in the step of FIG. 1D, CV
The silicon nitride film to be the second sidewall insulating film 7 is formed by the D method.
Since it is deposited to a film thickness of 0 nm, the high concentration source / drain layer 8 does not reach below the first sidewall insulating film 4. Therefore, the low concentration source / drain layer 6 n ⁻
The length of the layer in the channel direction (see symbol B in the figure) is about 0.1.
.mu.m, an NMOS transistor having excellent resistance to hot carrier deterioration and an excellent drain current driving force is formed.

Further, in the step of FIG. 1 (d), about 800 ° C.
The substrate is exposed to the nitrogen atmosphere for about 60 minutes to perform a heat treatment for activating the impurities, and the low concentration source / drain layer 6 tries to spread into the channel region by diffusion by this heat treatment. However, if the first sidewall insulating film 4 is about 60n
Since it is formed to be thicker than m, the end of the low-concentration source / drain layer 6 does not enter below the gate electrode 3 and can substantially coincide with the end of the gate electrode 3. As a result, the short channel effect is improved by about 0.12 μm, and the impurity concentration of the low-concentration source / drain layer 6 is increased to increase the drain current, as compared with the method of implanting impurities using only the gate electrode as a mask. It becomes possible.

Here, the thickness of the first side wall insulating film 4 depends on the ion implantation conditions for forming the low concentration source / drain layers 6 and the heat treatment conditions for activating the impurities, but is 40 n.
It is desirable that the thickness is in the range of m to 100 nm. 40
Below nm, the short channel effect becomes significant, and
This is because, above 00 nm, the end of the low-concentration source / drain layer 6 has an offset structure formed outside the end of the gate electrode 3, so that the drain current is significantly reduced.

(Embodiment 2) Next, based on FIG.
A method of manufacturing a semiconductor device having a polycide structure will be described. For convenience of explanation, the same parts as those in FIG. 1 are designated by the same reference numerals. First, as shown in FIG. 2A, an oxide film serving as the gate insulating film 2 and polysilicon 13a (having a film thickness of 100 nm) serving as the gate electrode 13 and Ti, are formed on the p-type silicon substrate (or p well) 1. The refractory metal silicide layer 13b (film thickness 100 nm) of W or the like is formed in this order, and the refractory metal silicide layer 13b is formed.
A silicon oxide film 14 (having a film thickness of 50 nm) for preventing the upper surface of the refractory metal silicide layer 13b from being oxidized is formed thereon. Then, the gate electrode 3 is formed by lithography and etching.

Next, as shown in FIG.
The first side wall insulating film 4 having a film thickness of about 60 nm is obtained by placing the substrate in an oxygen atmosphere at 950 ° C. and thermally oxidizing the surface of the gate electrode 13. At this time, the initially formed substrate oxide film 5 having a film thickness of about 20 nm is also formed on the surface of the silicon substrate 1.

Next, as shown in FIG. 3C, the initial formation substrate oxide film 5 having a film thickness of about 20 nm is etched by anisotropic etching to reduce the film thickness to about 5 nm. A substrate oxide film 5'is obtained. Then, phosphorus (P) is implanted with an energy of 10 keV and a dose of 4E1.
Implantation is performed under the condition of 3 / cm ² to form the n-type low-concentration source / drain layer 6.

Next, as shown in FIG. 3D, a silicon nitride film to be the second sidewall insulating film 7 is formed to 70 n by the CVD method.
Then, the second side wall insulating film 7 is formed by anisotropic etching. In this anisotropic etching,
The silicon nitride film deposited on the silicon substrate 1 is completely removed. After that, arsenic (As) is implanted under the conditions of an implantation energy of 30 keV and a dose amount of 4E15 / cm ² to form an n-type high concentration source / drain layer 8.

Next, the substrate is exposed to a nitrogen atmosphere at about 800 ° C. for about 60 minutes to perform heat treatment for activating impurities. As a result, as shown in FIG.
8 will spread somewhat laterally.

In the method of manufacturing a semiconductor device having this polycide structure, the refractory metal silicide layer 13b is a birefringent refractory metal silicide layer.
The lower layer side is, for example, a WSi ₃ layer (film thickness 50 nm) having a low refractory metal content, and the upper layer side has a higher refractory metal content, for example, a WSi ₂ layer (film thickness 50 n).
m). According to this, in the formation of the first sidewall insulating film 4, since the WSi ₃ layer containing a small amount of the refractory metal is present, the polysilicon layer 13a and the silicide layer 13b can be prevented from peeling off. In addition, the presence of WSi ₂ having a high content of the refractory metal allows the resistance of the gate electrode 13 to be reduced. The atomic percentage of WSi ₃ is 25%, and the atomic percentage of WSi ₂ is 33%.

(Embodiment 3) Next, based on FIG.
A method of manufacturing a semiconductor device having a salicide structure will be described. For convenience of explanation, the same parts as those in FIG. 1 are designated by the same reference numerals. FIG. 3A shows a state in which the high-concentration source / drain layer 8 is formed using the second sidewall insulating film 7 made of a silicon nitride film as a mask. In this figure, a silicon oxide film 24 is formed on the upper surface of the gate electrode 23 made of polysilicon.

Next, as shown in FIG. 6B, only the oxide film on the upper surface side of the gate electrode 23 is removed. Where the second
When the side wall insulating film 7 is made of a silicon oxide film, it is difficult to remove only the oxide film on the upper surface side of the gate electrode 23, but the second side wall insulating film 7 is a silicon nitride film (that is, the second side wall insulating film 7). Since it is a material different from the oxide film which is the material of the first side wall insulating film), it is possible to remove only the oxide film on the upper surface side of the gate electrode 23 without causing the width variation of the second side wall insulating film 7. it can.

Next, as shown in FIG. 6C, a titanium (Ti) film 25 is formed on the surface of the substrate by using a general salicide structure forming method.

Then, as shown in FIG. 3D, heat treatment for silicidation and removal of unreacted titanium are performed. As a result, the silicide layer 26 is formed on the upper surface of the gate electrode 23 and the high-concentration source / drain layer 8.

According to the method described above, the gate electrode 2
Since the oxide film on the upper surface side of 3 can be removed without changing the width of the second sidewall insulating film 7, it is possible to reduce variations in transistor characteristics between elements. Further, since the oxide film on the upper surface side of the gate electrode 23 is removed, the upper surface (exposed surface) of the gate electrode 23 is located lower than the second sidewall insulating film 7, so that the silicide layer on the gate electrode 23 is formed. 26 and the silicide layer 26 on the high-concentration source / drain layer 8 are easily separated from each other.

[0043]

As described above, since the first side wall insulating film is formed by oxidizing the gate electrode, there is little variation in the film thickness, and the first side wall insulating film is used as a mask. Further, the accuracy of the formation position of the low-concentration diffusion layer is high, and it is possible to reduce variations in transistor characteristics between elements. Further, this low-concentration diffusion layer is formed by using the first sidewall insulating film as a mask, and the low-concentration diffusion layer penetrates under the gate electrode as compared with the one formed by using only the gate electrode as a mask. Is less likely to occur, it is easy to suppress the short channel effect. In addition, since the substrate oxide film is formed by thinning the substrate oxide film at the beginning of formation, it is possible to reduce the ion implantation energy when forming the low-concentration diffusion layer,
This also makes it difficult for the low-concentration diffusion layer to enter below the gate electrode. Furthermore, the presence of the thin substrate oxide film described above can reduce damage to the substrate during etching of the substrate oxide film, and suppress the generation of interface states under the sidewall due to leak current and hot carriers. be able to.

The thickness of the first sidewall insulating film is 40 nm or more 1
When the thickness is set to 00 nm or less, it is difficult for the low-concentration diffusion layer formed using the first sidewall insulating film as a mask to enter under the gate electrode, and the low-concentration diffusion layer is formed by low-energy ion implantation. Also, the offset amount of the low-concentration diffusion layer with respect to the gate electrode can be reduced, and the fluctuation of the drain current can be reduced.

When the film thickness of the substrate oxide film is 10 nm or less, the low-concentration diffusion layer can be formed by low-energy ion implantation, so that the low-concentration diffusion layer is less likely to enter below the gate electrode. Become.

When the end portion of the low concentration diffusion layer is located at the end of the channel region under the gate electrode, the short channel effect can be suppressed and the offset structure can be prevented.

The gate electrode is a polysilicon layer, a first silicide layer containing a refractory metal, and a second refractory metal content higher than that of the first silicide layer.
In the case of the multilayer film structure in which the silicide layer and the silicon oxide film are sequentially stacked, the presence of the first silicide layer in the formation of the first sidewall insulating film results in the polysilicon. The layer can be prevented from peeling off from the silicide film, and the presence of the second silicide layer can reduce the resistance of the gate electrode.

The semiconductor device having the above structure can be manufactured by the method for manufacturing a semiconductor device according to the present invention.

In the above manufacturing method, after forming the second side wall insulating film with a material different from that of the first side wall insulating film which is the oxide film, the second side wall insulating film is formed on the upper surface of the gate electrode in the first step. When the formed oxide film is removed, the film thickness (width) of the second sidewall insulating film is reduced from being changed by the etching for removing the oxide film, and variations in characteristics are reduced. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is an element sectional view showing each step of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an element cross-sectional view showing each step of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is an element sectional view showing each step of manufacturing a semiconductor device according to a third embodiment of the invention.

[Explanation of symbols]

 1 p-type silicon substrate 2 gate insulating film 3 gate electrode 4 first sidewall insulating film 5 initial substrate oxide film 5'substrate oxide film 6 low concentration source / drain layer 7 second sidewall insulating film 8 high concentration source / drain Layer 13 Gate electrode 23 Gate electrode

Claims (7)

[Claims] 1. A low-concentration diffusion layer formed by implanting impurities using a first sidewall insulating film in contact with a gate electrode made of polysilicon or polycide as a mask, and a first impurity layer located outside the first sidewall insulating film. 2. A semiconductor device having a high-concentration diffusion layer formed by implanting an impurity of the same conductivity type as the impurity at a higher concentration than the low-concentration diffusion layer using the second sidewall insulation film as a mask. Is formed by oxidizing the gate electrode, a substrate oxide film is located below the second sidewall insulating film, and the substrate oxide film is the first oxide film.
The semiconductor device is characterized in that it is formed by thinning the substrate oxide film at the initial formation, which is formed when the side wall insulating film is obtained. 2. The film thickness of the first sidewall insulating film is 40 nm.
The semiconductor device according to claim 1, wherein the thickness is 100 nm or less. 3. The semiconductor device according to claim 1, wherein the film thickness of the substrate oxide film is 10 nm or less. 4. The semiconductor device according to claim 1, wherein an end of the low-concentration diffusion layer is located at an end of a channel region below the gate electrode. 5. The gate electrode is formed by sequentially stacking a polysilicon layer, a first silicide layer having a low metal content, a second silicide layer having a high metal content, and a silicon oxide film in this order from the bottom. 5. The semiconductor device according to claim 1, wherein the semiconductor device has a multilayer film structure. 6. A first step of oxidizing a substrate having a gate electrode formed thereon, and a second step of removing or thinning all the oxide film formed on the surface of the substrate in the first step,
A third step of forming a low-concentration diffusion layer by implanting ions using the first sidewall insulating film formed on the side end portion of the gate electrode as a mask in the first step; and the first sidewall. A fourth step of forming a second sidewall insulating film located outside the insulating film; and the third step using the second sidewall insulating film as a mask
And a fifth step of forming a high-concentration diffusion layer by implanting ions at a higher concentration than the ion implantation in the step of. 7. The first sidewall insulating film is formed of a material different from that of the first sidewall insulating film, which is an oxide film, and then the first sidewall insulating film is formed.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the oxide film formed on the upper surface of the gate electrode is removed in the step of.