JP2002204433A - Video signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video signal processing circuit that can conduct detailed control by allowing a telecine detection circuit to detect a telecine signal in the unit of one pixel for a plurality of number of times. SOLUTION: In the video signal processing circuit that detects a motion from a current interlace video signal and a 2F delay signal, detects whether or not the video signal is a telecine signal depending on the presence of the motion, selects either the current video signal or the 2F delay signal depending on a telecine detection signal and synthesizes the selected signal with a 1F delay signal to provide an output of the result as a progressive signal, the telecine detection circuit 21 comprises a counter 27 that first counts one image pattern of pixels of a still picture with a small luminance frame difference in the unit of pixels, a counter 32 that counts number of coincident times on the basis of the coincidence between a pattern of a signal regarded to represent a coincident pattern when the counts is a setting value or over and an image pattern of a signal delayed from the signal above, and a comparator 34 that judges whether or not the video signal is a telecine signal depending on whether the pattern coincident count is greater than a setting value or not and provides an output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an I / P (interlace / progressive) conversion process for detecting whether an NTSC signal has been subjected to telecine conversion and performing an appropriate process on a movie material. The present invention relates to a video signal processing circuit that detects whether a signal is a telecine signal from a material and performs processing.

[0002]

2. Description of the Related Art As shown in FIG. 6 (a), a signal captured at a rate of 24 frames per second, such as a movie, is divided into two frames so that an odd frame has two fields and an even frame has three fields.
By performing a -3 pull-down process, as shown in (b), the signal is converted into an interlaced signal composed of 60 fields per second, broadcast, and packaged. Also,
The same applies to the case where 3-2 pull-down processing is performed on one frame so that odd frames have three fields and even frames have two fields. In (b), the subscript u is “up”
And b represents “down”.

An interlaced scanning NTSC signal is converted to a PD
When displaying on a progressive scan panel such as P (plasma display panel), a motion adaptive I / P (interlace / progressive) conversion process as shown in FIG. 5 is performed. In FIG. 5, the interlaced video signal input to the interlaced video signal input terminal 10 is composed of a signal without delay, a signal with 1F delay by the 1F delay circuit 11, and a 2F delay signal through the 1F delay circuit 12. Are sent to the motion detection circuit 13 to detect the motion of the video. When the presence or absence of a motion is detected by the motion detection circuit 13, the output of the inter-field interpolation circuit 15 as shown in FIG. The output of the field interpolation circuit 14 as shown is selected. Then, the signal selected by the motion adaptive interpolation circuit 16 and the 1F delay signal pass through the double-speed conversion circuit 17 and the double-speed conversion circuit 18, respectively, and the output is converted to the synthesis circuit 19.
And a progressive video signal is output from the progressive video signal output terminal 20.

That is, in such a conventional circuit, regardless of whether the signal input to the interlaced video signal input terminal 10 is a signal which has been subjected to telecine conversion, in a still image portion, two fields are interpolated from one field to another. One frame is formed, and in the moving image portion, one frame is formed from one field by field interpolation.
Therefore, in the telecine-converted signal, there are frames (hatched portions in FIG. 7) made of different frames, such as A and B, B and C, C and D,. Therefore, there is a problem that image quality is deteriorated.

In order to solve such a problem, as shown in FIG. 8, a telecine detecting circuit 21 is inserted after the motion detecting circuit 13 (Japanese Patent Laid-Open No. Hei 5-183888).
No. JP-A-8-237694). In FIG. 8,
It is assumed that a telecine signal as shown in FIG. 9A is input to the interlace video signal input terminal 10. This input signal is delayed by the 1F delay circuit 11 and the 1F delay circuit 12, and a signal as shown in FIG. 9B delayed by 2F is output. When the telecine detection circuit 21 detects a telecine, one of these (a) and (b), that is, a field made from the same frame is selected, and as shown in FIG. A signal is output. This signal,
The signal as shown in FIG. 9D delayed by one field is synthesized by the synthesizing circuit 19 through the double-speed conversion circuit 17 and the double-speed conversion circuit 18, respectively, and is formed from the same frame as shown in FIG. The output field signal is output.

[0006]

As described above, the conventional circuit shown in FIG. 8 solves the problem of image quality degradation due to the presence of frames made from different frames. However, in Japanese Unexamined Patent Publication No. Hei 5-183888, since one field is integrated and detected once every five times in a unit of one field, the influence of large noise, for example, white noise is large, and only rough control can be performed. There was a problem.

Further, in a telecine video signal formed by forming a video signal from a film, an image is often blurred due to mechanical factors such as uneven rotation of a motor and gears during frame advance of the film. Generally, the film is fed vertically, so that blurring occurs more in the vertical direction and less in the horizontal direction. Japanese Patent Application Laid-Open No. Hei 8-237694 discloses that a reference value of a vertical shake component is set to be larger than a reference value of a horizontal shake component, and the telecine video signal cannot be effectively detected due to mechanical factors by limiting the reference value to a value less than these reference values. The purpose of the present invention is to solve the problem, and is different from that of the present invention in which only a telecine signal is detected.

According to the present invention, in a telecine detecting circuit, 1
It is an object of the present invention to provide a circuit capable of performing finer control by detecting a plurality of times in units of pixels.

[0009]

According to the present invention, a motion is detected by a motion detecting circuit 13 from a current signal of an input interlaced video signal and a 2F delay signal, and a telecine detecting circuit 21 is detected based on the presence or absence of the motion detecting signal. A video signal processing circuit for detecting whether or not the signal is a telecine signal, selecting one of the current signal and the 2F delay signal with the telecine detection output, synthesizing the selected signal and the 1F delay signal, and outputting as a progressive signal In the telecine detection circuit 21,
A still pixel integration counter 27 for counting the number of still pixels for one screen, and a signal 5 that is regarded as a screen match when the count value from the still pixel integration counter 27 is equal to or greater than a set value.
A screen coincidence counter 32 for counting the number of coincidences upon seeing coincidence with an F-delayed screen, and a comparator 34 for outputting a telecine detection signal when the count value of the screen coincidence counter 32 exceeds a set value. Is a video signal processing circuit characterized by the following.

With such a configuration, a still image having a small luminance frame difference is first counted for one screen in pixel units, and it is determined whether or not the coincidence for one screen is greater than a set value. The number of screen matches between the count value and the one delayed by five fields is counted, and it is determined whether or not the screen is a telecine based on whether the number of matches on the screen is greater than a set value. Therefore,
Fine control can be performed, and deterioration of image quality can be suppressed as much as possible.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. 1, an interlaced video signal input terminal 10, a 1F delay circuit 11, a 1F delay circuit 12, a motion detection circuit 13, a field selection circuit 22, a double speed conversion circuit 17, a double speed conversion circuit 18, a synthesis circuit 19, and a progressive video signal The output terminal 20 is the same as in FIG.

The telecine detecting circuit 21 according to the present invention comprises:
The luminance frame difference signal input terminal 23 receives the current field from the motion detection circuit 13 and the current field and the 1F delay circuit 11 and the 1F delay circuit 12 in the luminance frame difference signal input terminal 23 in units of pixels. A luminance frame difference signal from a field delayed field is input. The comparator 25 compares the luminance frame difference signal input to the luminance frame difference signal input terminal 23 with the set value signal from the set value 1 input terminal 24, and when the luminance frame difference is large, determines that the pixel is a moving pixel. If it is smaller, it is determined to be a still pixel, and a signal for the still pixel is output. By increasing the set value signal from the set value 1 input terminal 24, stable telecine detection can be performed even in a noisy image.

The still pixel integration counter 27 counts the number of still pixels from the comparator 25 when an enable signal for one screen is input from the enable signal input terminal 26. In the case of a letterbox movie material, more accurate telecine detection can be performed by enabling the still pixel integration counter 27 except for the upper and lower bands in the enabled state. The comparator 29 compares the number of still pixels in one screen from the still pixel integration counter 27 with the set value from the set value 2 input terminal 28, and when the number of still pixels in one screen is larger than the set value, For the time being, the output is a coincidence in which the screen is regarded as a still image. When it is small, the output is inconsistent, in which the screen is regarded as a moving image. The set value from the set value 2 input terminal 28 is
By increasing the size, stable telecine detection can be performed even in a noisy image. In the OR circuit 31, the current screen and the 5F
The coincidence with the screen delayed by 5 fields by the delay circuit 30 is checked. The coincidence with the five-field delay is determined by the fact that the TV signal has almost no coincidence with the five-field delay except for a still image, but the telecine signal has a high possibility of coincidence with the five-field delay. by.

The screen match counter 32 counts how many times the screen matches. In the comparator 34, the number of screen matches in the screen match counter 32 and the set value 3 input terminal 3
3, and if the number of screen matches is greater than the set value, the signal is determined to be a telecine signal, and a telecine detection signal is output from the telecine detection signal output terminal 35. If it is smaller than the set value, no telecine detection signal appears. The telecine detection signal from the telecine detection signal output terminal 35 is sent to the field selection circuit 22. The following operation is the same as in the case of FIG. The set value 3 input terminal 3
By increasing the set value from 3, stable telecine detection can be performed even in a noisy image.

As described above, a still image with a small luminance frame difference is first counted for one screen in pixel units.
It is determined whether the match for the screen is greater than the set value, and the number of screen matches between this count value and the one delayed by 5 fields is counted. This is to determine whether it is telecine. Therefore, by using the pixel unit as described above, fine control can be performed, and deterioration of image quality can be suppressed as much as possible.

FIG. 2 shows a second embodiment of the present invention. The comparator 34 in the first embodiment shown in FIG. 1 determines that the signal is a telecine signal if it is larger than the set value of the set value 3 input terminal 33, and if it is smaller than the set value, it is a signal other than the telecine signal. Therefore, when the output of the screen coincidence counter 32 rises and falls near the set value of the set value 3 input terminal 33, the operation becomes unstable by repeatedly judging a telecine signal or a signal other than a telecine signal. . Therefore, in the second embodiment of the present invention shown in FIG. 2, a hysteresis characteristic circuit 41 is used instead of the comparator 34, and the set value 3 input terminal 33 has a range between the upper limit value and the lower limit value as the set value. It is something. With this configuration, the hysteresis characteristic circuit 41 determines that the signal is a telecine signal when the value exceeds the upper limit of the set value 3 input terminal 33. Judge as a signal, judge as a signal other than telecine signal when it becomes smaller than the lower limit, and judge as a signal other than telecine signal as it is even if it becomes larger than the lower limit after it becomes smaller than the lower limit,
When it becomes larger than the upper limit value, it is determined that the signal is a telecine signal. By giving the range to the set value, the operation is stabilized. By increasing the difference (hysteresis) between the upper and lower values and the lower limit, stable telecine detection can be performed even in a noisy image.

FIG. 3 shows a third embodiment of the present invention. In the embodiment shown in FIGS. 1 and 2, in a pause state of a VTR or the like, since a still screen is continuous, there is a possibility that this is determined as a telecine signal. In such a case, it is necessary to determine that the signal is not a telecine signal. FIG.
Is a modification of such a point. A comparator 37 is provided between the still pixel integration counter 27 and the screen coincidence counter 32.
A stationary counter 38 and a comparator 40 are inserted.
The comparator 37 compares the number of still pixels counted by the still pixel integration counter 27 with the set value of the set value 4 input terminal 36, and outputs when the number of still pixels is equal to or larger than the set value. Here, by setting the set value of the set value 4 input terminal 36 to be larger than the set value of the set value 2 input terminal 28 and to the number of pixels in a substantially complete still image, the static counter 38
In such a case, when the screens are completely matched continuously, such as in a pause state of a VTR or the like, the number of still screens is counted. The comparator 40 compares the number of still screens with the set value of the set value 5 input terminal 39, and when the number exceeds the set value, determines that the screen is stationary due to a temporary stop or the like and outputs it. Then, the screen coincidence counter 32 is set to 0 based on the output of the comparator 40, and it is assumed that the signal is not a telecine signal. With such a configuration, it is possible to prevent a still screen, which is a signal other than the telecine signal whose screens are continuously matched, from being erroneously determined as a telecine signal.

FIG. 4 shows a fourth embodiment of the present invention. In this embodiment, the comparator 37 in FIG. 3 is omitted, and the output of the comparator 29 is continuously output as in a temporary stop state of a VTR or the like. The still counter 38 counts the number of still screens whose screens completely match. That is, when the number of still pixels in one screen from the still pixel integration counter 27 is larger than the set value from the set value 2 input terminal 28 from the comparator 29, a coincidence output that regards the screen as a still image is provided, When the value is small, a non-coincidence output for temporarily considering the screen as a moving image is obtained. Therefore, the screen coincidence signal from the comparator 29 is counted by the stationary counter 38, and this count value is set by the set value 5 input terminal 39. The value is compared with a set value for detecting a pause state of a VTR or the like. If the set value is exceeded, it is determined that the screen is stationary due to a pause or the like, and is output from the comparator 40. The screen coincidence counter 32 is set to 0, and it is assumed that the signal is not a telecine signal.

[0019]

According to the first aspect of the present invention, in the video signal processing circuit, the telecine detection circuit 21 includes a still pixel integration counter 27 for counting the number of still pixels for one screen.
A screen match counter 32 for counting the number of matches by checking a match between a signal regarded as a screen match when the count value from the still pixel integration counter 27 is equal to or greater than a set value and a screen delayed by 5F; And a comparator 34 for outputting a telecine detection signal when the count value exceeds a set value. A still image having a small luminance frame difference is first counted for one screen in pixel units, and a match for one screen is set. It is determined whether the value is greater than the value, then the number of screen matches between this count value and the one delayed by 5 fields is counted, and whether or not this screen is a telecine is determined by whether the number of matches on this screen is greater than a set value. It is like that. Accordingly, fine control can be performed by using a pixel unit, and deterioration of image quality can be suppressed as much as possible.

According to the second aspect of the present invention, in the video signal processing circuit, the telecine detection circuit 21 compares the luminance frame difference signal input from the motion detection circuit 13 with the set value and converts the signal having a small difference into a static signal. A comparator 25 for determining a pixel, a still pixel integration counter 27 for counting the number of still pixels for one screen from the comparator 25, and a comparison and determination of a count value and a set value of the still pixels for one screen. , A comparator 29 for outputting a signal that is regarded as a screen match when the value is equal to or greater than a set value, an OR circuit 31 for checking the match between the count value of the comparator 29 and the count value of the screen delayed by 5F, A screen coincidence counter 32 for counting the number of screen coincidences is compared with a count value of the screen coincidence counter 32 and a set value. If the set value is exceeded, a telecine detection signal is output. Since then and a 34, the circuit configuration can be provided easily and inexpensively.

According to the third aspect of the present invention, the comparator 34 for outputting the telecine detection signal is replaced with the hysteresis characteristic circuit 41 having a range between the upper limit value and the lower limit value as the set value. Even if the output of the counter 32 fluctuates near the set value of the set value 3 input terminal 33, the operation is stabilized without judging that the signal is a telecine signal or a signal other than the telecine signal.

According to the fourth aspect of the present invention, the number of still pixels counted by the still pixel integration counter 27 is set between the still pixel integration counter 27 and the screen coincidence counter 32 to the number of pixels in the case of a substantially complete still image. When the number of still images exceeds the set value, a comparator 37 outputs when the number is equal to or more than the set value, a still counter 38 counts the number of still images when the screens are continuously matched, and the number of still images of the still counter 38 exceeds the set value. Since a comparator 40 that determines that the signal is not a telecine signal and sets the screen coincidence counter 32 to 0 is inserted, a still image with a signal other than the telecine signal such that the images match continuously is mistaken for a tenesine signal. Judgment can be prevented.

According to the fifth aspect of the present invention, the comparator 29
A screen match signal from a comparator 29 that outputs a signal that is regarded as a screen match when the number of still pixels in one screen from the still pixel integration counter 27 is larger than a set value is counted between the screen match counter 32 and the screen match counter 32. When the still counter 38 and the number of still screens of the still counter 38 exceed a set value,
Screen coincidence counter 3 judging that it is not a telecine signal
Since a comparator 40 for setting 2 to 0 is inserted, a simpler configuration prevents a still picture with a signal other than a telecine signal, such as a continuous picture coincidence, from being erroneously determined as a tenescine signal. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a video signal processing circuit according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of a telecine detection circuit 21 which is a main part of the video signal processing circuit according to the present invention.

FIG. 3 is a block diagram showing a third embodiment of a telecine detection circuit 21 which is a main part of the video signal processing circuit according to the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of a telecine detection circuit 21 which is a main part of a video signal processing circuit according to the present invention.

FIG. 5 is a block diagram of a conventional video signal processing circuit.

FIG. 6 shows a signal of a movie or the like shot at 24 frames per second,
FIG. 9 is an explanatory diagram of converting to an interlaced signal composed of 60 fields per second by performing 3 pull-down processing.

FIG. 7 is a diagram showing an example of a conventional video signal processing circuit shown in FIG.
FIG. 4 is an explanatory diagram of a / P (interlace / progressive) conversion process.

FIG. 8 is a block diagram of a conventional video signal processing circuit after improvement.

FIG. 9 is a diagram showing an example of I by the conventional video signal processing circuit shown in FIG.
FIG. 4 is an explanatory diagram of a / P (interlace / progressive) conversion process.

[Explanation of symbols]

Reference numeral 10: interlace video signal input terminal, 11: 1F delay circuit, 12: 1F delay circuit, 13: motion detection circuit, 14
... field interpolation circuit, 15 ... field interpolation circuit, 16 ... motion adaptive interpolation circuit, 17 ... double speed conversion circuit, 1
8 double speed conversion circuit, 19 synthesis circuit, 20 progressive video signal output terminal, 21 telecine detection circuit, 22
... Field selection circuit, 23 ... Luminance frame difference signal input terminal, 24 ... Set value 1 input terminal, 25 ... Comparator, 26
... enable signal input terminal, 27 ... still pixel integration counter, 28 ... set value 2 input terminal, 29 ... comparator, 30 ... 5
F delay circuit, 31 ... OR circuit, 32 ... Screen coincidence counter, 33 ... Set value 3 input terminal, 34 ... Comparator, 35 ... Telecine detection signal output terminal, 36 ... Set value 4 input terminal, 3
7 comparator, 38 stationary counter, 39 set value 5 input terminal, 40 comparator, 41 hysteresis characteristic circuit.

Continued on the front page (72) Inventor Junichi Onodera 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa Prefecture F-term in Fujitsu General Co., Ltd. 5C063 AA02 AC01 BA04 BA10 BA12 CA05 CA40

Claims (5)

[Claims] 1. A motion detection circuit 13 detects a motion from a current signal of an input interlaced video signal and a 2F delay signal, and a telecine detection circuit 2 detects the presence or absence of the motion detection signal.
1 to detect whether the signal is a telecine signal, and select one of a current signal and a 2F delay signal with this telecine detection output;
In the video signal processing circuit that combines the selected signal and the 1F delay signal and outputs the resultant signal as a progressive signal, the telecine detection circuit 21 includes a still pixel integration counter 27 that counts the number of still pixels for one screen, A screen match counter 32 that counts the number of matches by seeing a match between a signal regarded as a screen match when the count value from the integrating counter 27 is equal to or greater than a set value and a screen delayed by 5F;
A video signal processing circuit comprising: a comparator that outputs a telecine detection signal when the count value of the screen coincidence counter exceeds a set value. 2. A motion detection circuit 13 detects a motion from a current signal of an input interlaced video signal and a 2F delay signal, and determines whether or not the motion detection signal is present.
1 to detect whether the signal is a telecine signal, and select one of a current signal and a 2F delay signal with this telecine detection output;
In the video signal processing circuit that combines the selected signal and the 1F delay signal and outputs the resultant signal as a progressive signal, the telecine detection circuit 21 compares the luminance frame difference signal input from the motion detection circuit 13 with a set value to obtain a difference. , A still pixel integration counter 27 for counting the number of still pixels for one screen from the comparator 25, a count value and a set value of the still pixels for one screen And an OR circuit 31 for comparing the count value of the comparator 29 with the count value of the screen delayed by 5 frames, and outputs a signal that determines a screen match when the count value is equal to or more than the set value. A screen match counter 32 for counting the number of screen matches of the OR circuit 31;
A video signal processing circuit comprising: a comparator for comparing a count value of the screen coincidence counter with a set value and outputting a telecine detection signal when the count value exceeds the set value. 3. A comparator 34 for outputting a telecine detection signal.
3. The video signal processing circuit according to claim 2, wherein a hysteresis characteristic circuit 41 having a range between an upper limit value and a lower limit value as a set value is used. 4. When the number of still pixels counted by the still pixel integration counter 27 between the still pixel integration counter 27 and the screen coincidence counter 32 is equal to or larger than a set value set to the number of pixels in a substantially complete still image. A comparator 37 for outputting, a still counter 38 for counting the number of still screens when the screens continuously match, and when the number of still screens of the still counter 38 exceeds a set value, it is determined that the signal is not a telecine signal. 4. The video signal processing circuit according to claim 2, wherein a comparator for setting the screen coincidence counter to zero is inserted. 5. A comparator 29 which outputs a signal between a comparator 29 and a screen coincidence counter 32, which is regarded as a screen coincidence when the number of static pixels in one screen from the static pixel integration counter 27 is larger than a set value. And a comparator 40 for setting the screen coincidence counter 32 to 0 when the number of static screens of the stationary counter 38 exceeds a set value and determining that the signal is not a telecine signal.
4. The video signal processing circuit according to claim 2, wherein