JP2002202755A - Light-emitting device and its drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light-emitting device which is hard to generate a false outline and its drive method. SOLUTION: To prevent display disturbances, such as false outline from being viewed, longer subframe periods are divided in order and dispersed in a single frame period, so that the divided subframe periods will not appear successively. Data read out in the divided subframe period appearing for the 1st time among the divided subframe periods are held by memories in respective pixels, and the held data are read out in other divided subframe periods and displayed. This constitution can prevent the display disturbances, such as false outline, which is conspicuous in time-division drive by a binary coding method from being viewed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an EL panel in which an EL element formed on a substrate is sealed between the substrate and a cover material. In addition, E in which an IC is mounted on the EL panel
Regarding the L module. In this specification, the EL panel and the EL module are collectively referred to as a self-luminous device. The present invention further relates to an electronic device using the light emitting device.

[0002]

2. Description of the Related Art An EL element emits light by itself and thus has high visibility, is not necessary for a backlight required for a liquid crystal display (LCD), is optimal for thinning, and has no restriction on a viewing angle. Therefore, in recent years, self-luminous devices using EL elements have attracted attention as display devices replacing CRTs and LCDs.

An EL element has a layer containing an organic compound capable of obtaining luminescence (Electro Luminescence) generated by applying an electric field (hereinafter, referred to as an EL layer), an anode layer, and a cathode layer. Luminescence of an organic compound includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning from a triplet excited state to a ground state. Then, either light emission may be used.

[0004] In this specification, all layers provided between an anode and a cathode are defined as EL layers. Specifically, the EL layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer,
An electron transport layer and the like are included. Basically, the EL element has an anode /
It has a structure in which a light emitting layer / cathode is laminated in order. In addition to this structure, an anode / hole injection layer / light emitting layer / cathode or anode / hole injection layer / light emitting layer / electron transport layer / cathode Etc. in some cases.

[0005] In this specification, emission of an EL element is referred to as driving of the EL element. In this specification, an element formed of an anode, an EL layer, and a cathode is referred to as an EL element.
It is called an element.

[0006] By the way, methods of driving a self-luminous device having an EL element mainly include analog driving and digital driving. In particular, digital driving is promising because digital video signals having image information (digital video signals) can be used as they are without being converted to analog in order to display images in response to the digitization of broadcast radio waves. It is.

A driving method for performing gray scale display by using a binary voltage of a digital video signal includes an area division driving method,
And a time-division driving method.

The area division driving method is a driving method in which one pixel is divided into a plurality of sub-pixels, and each sub-pixel is independently driven based on a digital video signal to perform gradation display. In this area division driving method, one pixel must be divided into a plurality of sub-pixels, and further, in order to drive each sub-pixel independently, it is necessary to provide a pixel electrode corresponding to each sub-pixel. . For this reason, there is a disadvantage that the structure of the pixel becomes complicated.

On the other hand, the time division driving method is a driving method for performing gradation display by controlling the lighting length of a pixel.
Specifically, one frame period is divided into a plurality of subframe periods. Then, in each sub-frame period, whether or not each pixel is turned on is selected by the digital video signal. By summing the length of the sub-frame period during which the pixel is turned on, of all the sub-frame periods that appear during one frame period, the gray scale of the pixel is obtained.

In general, organic EL materials have a higher response speed than liquid crystal or the like, and thus EL elements are suitable for time-division driving.

[0011]

The case where an intermediate gray scale is displayed by time division driving based on a simple binary code method will be described below in detail with reference to FIG.

FIG. 27A shows a pixel portion of a general self-luminous device, and FIG. 27B shows the length of all subframe periods appearing in one frame period in the pixel portion. .

In FIG. 27, an image is displayed using a 6-bit digital video signal capable of displaying 1 to 64 gradations. The right half of the pixel portion displays 33 (32 + 1) gradations, and the left half displays 32 (31 + 1) gradations.

When a 6-bit digital video signal is used, generally, six sub-frame periods SF1 to SF6 appear during one frame period. The digital video signals of the first to sixth bits of the digital video signal correspond to the subframe periods SF1 to SF6, respectively.

The length ratio of the subframe periods SF1~SF6 is 2 ^0: 2 ^{1: 2} 2: 2 ^3: 2 ^4: 2 ^5. The length of the subframe period SF corresponding to the digital video signal of the most significant bit (6th bit in this case) is the longest, and the length of the subframe period corresponding to the digital video signal of the least significant bit (1st bit) Is the shortest.

When performing the display of 32 gradations, the pixels are turned on in the sub-frame periods SF2 to SF6, and the pixels are turned off in the sub-frame period SF1. In the case of performing the display of 33 gradations, the pixels are turned off in the sub-frame periods SF2 to SF6, and the pixels are turned on in the sub-frame period SF1.

When this driving is performed, 3
A false contour may be visually recognized at a boundary between a part displaying two gradations and a part displaying 33 gradations.

A false contour is an unnatural contour which is often visually recognized when performing a time grayscale display by a binary code method, and is mainly caused by fluctuations in perceived luminance caused by human visual characteristics. It has been. With reference to FIG. 28, the mechanism of the generation of the false contour will be described in detail.

FIG. 28A shows a pixel portion of a self-luminous device in which a false contour appears, and FIG. 28B shows the length of a sub-frame period appearing in one frame period in the pixel portion. Shows the ratio of

In FIG. 28, an image is displayed using a 6-bit digital video signal capable of displaying 1 to 64 gradations. The right half of the pixel section displays 33 gradations,
The left half displays 32 gradations.

In a portion of the pixel portion where a 32-gradation display is performed, the pixels are lit during a period of 31/63 of one frame period, and the pixels are not lit during a period of 32/63 of one frame period. It is a state of. The period in which the pixel is lit and the period in which the pixel is not lit appear alternately.

Further, in a portion of the pixel portion where a display of 33 gradations is performed, the pixels are lit during a period of 32/63 of one frame period, and 31/6 of one frame period.
In the period 3, the pixel is in a non-lighting state. The period in which the pixel is lit and the period in which the pixel is not lit appear alternately.

When displaying a moving image, for example, FIG.
It is assumed that the boundary between the portion displaying 32 gradations and the portion displaying 33 gradations moves in the direction of the dotted line. That is, in the vicinity of the boundary, the pixel switches from the display of 32 gradations to the display of 33 gradations. Then, in the pixel near the boundary, 3 immediately after the lighting period for displaying 32 gradations.
A lighting period for displaying three gradations is started. Therefore, to the human eye, the pixel appears to be continuously lit for one frame period. This is perceived as an unnatural bright line on the screen.

Conversely, for example, in FIG.
It is assumed that the boundary between the part displaying 32 gradations and the part displaying 33 gradations has moved in the direction of the solid line. That is, in the vicinity of the boundary, the pixel switches from the display of 33 gradations to the display of 32 gradations. Then, in the pixel near the boundary, 33
A lighting period for displaying 32 gradations starts immediately after the lighting period for displaying gradation. Therefore, to the human eye, the pixel appears to be in a non-lighting state continuously for one frame period. This is perceived as an unnatural dark line on the screen.

The unnatural bright lines and dark lines appearing on the screen as described above are display disturbances called false contours (moving picture false contours).

By the way, even in a still image, display disturbance may be visually recognized for the same reason that a false contour of a moving image occurs in a moving image. The display disturbance in a still image is such that the boundary of gradation appears to fluctuate. Hereinafter, the reason why such display disturbance is visually recognized in a still image will be briefly described.

[0027] Even though the human eye intends to gaze at one point, the viewpoint is moving delicately, and it is difficult to accurately look at a fixed point. For this reason, when the user stares at the boundary between the portion of the pixel portion displaying 32 gradations and the portion displaying 33 gradations, even if she intends to stare at the boundary, the viewpoint is actually changed. It moves slightly right, left, up and down.

For example, it is assumed that the viewpoint has moved from a portion displaying 32 gradations to a portion displaying 33 gradations. The pixel is in a non-lighting state when the viewpoint is placed in a portion displaying 32 gradations, and the pixel is in a non-lighting state when the viewpoint is placed in a portion displaying 33 gradations. In the human eye,
The pixel is visually recognized as if the pixel had not been turned on.

Conversely, for example, it is assumed that the viewpoint has moved from a portion displaying 33 tones to a portion displaying 32 tones. When the pixel is lit when the viewpoint is placed on a portion displaying 33 gradations, and when the pixel is lit when the viewpoint is placed on a portion displaying 32 gradations. , To the human eye throughout a frame period,
The pixel is visually recognized as if the pixel had been lit all the time.

Therefore, since the viewpoint slightly moves up, down, left, right, up and down, the human eyes see the pixel as if it were in a lighting state or a non-lighting state throughout one frame period, and as if the boundary was The display disturbance is visually recognized as if swinging.

[0031]

SUMMARY OF THE INVENTION The present inventors divided a subframe period having a long period in order to prevent a display disturbance such as a false contour from being visually recognized. Further, the divided sub-frame periods (divided sub-frame periods) are dispersed within one frame period so that they do not appear continuously.

The number of divided subframe periods may be one or more. However, it is preferable to divide the sub-frame period corresponding to the upper bit, that is, the sub-frame period having a longer length in order.

The number of divisions of the sub-frame period can be appropriately selected by a designer. The number of divisions is determined by the balance between the driving speed of the self-luminous device and the required image display quality. Is preferred.

It is preferable that the lengths of the divided sub-frame periods corresponding to the digital video signal of the same bit are the same, but the present invention is not limited to this. The lengths of the divided subframe periods need not always be the same.

The above driving method is realized by forming a memory in each pixel.

According to the above configuration, it is possible to prevent display disturbances such as false contours, which are remarkable in time division driving by the binary code method, from being visually recognized. The reason will be described below.

FIG. 1A shows a pixel portion of a self-luminous device.
FIG. 1B shows the ratio of the lengths of the sub-frame periods SF appearing in one frame period (F) in the pixel portion.

In FIG. 1, ⁿ is capable of displaying 1 to 2 ⁿ gradations.
Images are displayed using bit digital video signals. The right half of the pixel portion displays 2 ^{n -1} +1 gradations, and the left half displays 2 ^{n -1} gradations.

When an n-bit digital video signal is used, according to a simple binary code method, n sub-frame periods SF1 to SFn appear in one frame period. Then, the digital video signals of the first to n-th bits of the digital video signal are subframe periods SF1 to SFn respectively.
It corresponds to.

The length ratio of the subframe periods SF1~SFn ^{is, 2 0: 2 1: 2} 2: ...: 2 n-2: a 2 ^n-1. The length of the sub-frame period SFn corresponding to the digital video signal of the most significant bit (the n-th bit in this case) is the longest,
The length of the sub-frame period SF1 corresponding to the digital video signal of the least significant bit (first bit) is the shortest.

In the case of performing the display of 2 ^n-1 gradations, the pixels are turned on in the sub-frame periods SF1 to SF (n-1), and the pixels are turned off in the sub-frame period SFn. Also, when displaying 2 ^n-1 +1 gradations,
The pixels are turned off in the sub-frame periods SF1 to SF (n-1), and the pixels are turned on in the sub-frame period SFn.

The subframe period SFn, which is the longest subframe period, is divided into two. Note that, here, the subframe period SFn is divided into two divided subframe periods, but the present invention is not limited to this. The number of divisions of the subframe period may be any number as long as the operation speed of the driving circuit and the TFT of the pixel can catch up.

The divided sub-frame periods (divided sub-frame periods) do not appear successively, and a sub-frame period corresponding to a digital video signal of another bit always appears in between.

The lengths of the divided sub-frame periods need not be all the same. In addition, the arrangement order of the subframe periods is not necessarily limited. It is not always the case that the subframe periods corresponding to the lower bits are arranged in order from the subframe period corresponding to the upper bits.

FIG. 2A shows a pixel portion of a self-luminous device which performs display by the driving method of the present invention. FIG. 2B shows a sub-frame period and a sub-frame period appearing in one frame period in the pixel portion. The divided sub-frame period is divided into a period in which the pixel is lit and a period in which the pixel is not lit (non-lit), and the length of each period is shown.

In FIG. 2A, the right half of the pixel portion is 2 ^{n -1.}
+1 gradation display is performed, and the left half displays 2 ^n-1 gradations.

In the portion of the pixel portion where 2 ^{n -1} gradation is displayed, the pixels are lit during the period of (2 ⁿ -1 -1) / 2 ⁿ in one frame period. The pixel is in a non-lighting state during a period of 2 ⁿ⁻¹ / 2 ⁿ during the period.
The period in which the pixel is lit and the period in which the pixel is not lit appear alternately.

In the portion of the pixel portion where 2 ^{n -1} +1 gradation is displayed, the pixels are lit during the period of 2 ^{n -1} / 2 ⁿ in one frame period. The pixel is in a non-lighting state during the period of (2 ⁿ⁻¹ −1) / 2 ⁿ . The period in which the pixel is lit and the period in which the pixel is not lit appear alternately.

It is quite possible that the human viewpoint moves delicately left, right, up and down, and accidentally spans another subframe period or divided subframe period. In such a case, even if the human viewpoint continuously gazes only at non-lighted pixels, or conversely, continuously gazes only at lighted pixels, the lighting period during one frame period And the non-lighting period are divided and appear alternately, so that the length of the continuous lighting period or the non-lighting period is shorter than that of the conventional simple binary code method. can do.

For example, as shown by the broken line, if the viewpoint is 2
It is assumed that the display is moved from a portion displaying ^n-1 gradation to a portion displaying 2 ^{n -1} +1 gradation. According to the driving method of the present invention, when the viewpoint is placed on a portion displaying 2 ^{n -1} gradations, the pixel is in a non-lighting state, and the viewpoint is 2
^{Even if the} pixel is in the non-lighting state when moving to the portion displaying the ( ^n-1) +1 gradation, 2 appear continuously.
The sum of the two non-lighting periods becomes shorter than before. Therefore, it is possible to prevent the pixel from being visually recognized as if the pixel had been in a non-lighting state throughout one frame period.

Conversely, for example, as shown by a solid line, it is assumed that the viewpoint has moved from a portion displaying 2 ^{n -1} +1 gradation to a portion displaying 2 ^{n -1} gradation. According to the driving method of the present invention, when the viewpoint is placed on a portion displaying 2 ^n-1 +1 gradation, the pixel is in a lighting state, and the viewpoint displays 2 ^n-1 gradation. Even if the pixel is in the lighting state when moving to the portion where the light is present, the sum of two lighting periods that appear consecutively is shorter than in the related art. Therefore, it is possible to prevent the human eyes from visually recognizing the pixels as if they were in the lighting state throughout one frame period.

According to the above configuration, it is possible to prevent display disturbances such as false contours, which are remarkable in time division driving by the binary code method, from being visually recognized.

The configuration of the present invention will be described below.

According to the present invention, there is provided a self-luminous device having a plurality of pixels provided with an EL element, a memory, a first TFT, a second TFT, and a third TFT, wherein the first One of a source region and a drain region of the TFT receives a digital video signal, and the other is connected to a gate electrode of the third TFT.
One of a source region and a drain region of T is connected to the memory, the other is connected to the gate electrode of the third TFT, and the source region of the third TFT is connected to a first power supply. And a drain region is connected to the EL element.

According to the present invention, an EL element and an SRAM
A self-luminous device including a plurality of pixels provided with a first TFT, a second TFT, and a third TFT, wherein one of a source region and a drain region of the first TFT is A digital video signal is input, and the other is connected to the gate electrode of the third TFT, and the second TF
One of the source region and the drain region of the T
AM, the other is connected to the gate electrode of the third TFT, the source region of the third TFT is connected to the first power supply, and the drain region is connected to the EL element. A self-luminous device is provided.

According to the present invention, there is provided a method for driving a self-luminous device having a plurality of pixels provided with an EL element, a memory, a first TFT, a second TFT, and a third TFT. A p-th bit digital signal is input to the gate electrode of the third TFT via the first TFT, and the p-th digital signal is stored in the memory via the first TFT and the second TFT. A period during which a signal is written, and the third TFT through the first TFT.
There is a period during which the q-th digital signal is input to the gate electrode of the FT and the p-th digital signal written in the memory is held, and the p-th digital signal held in the memory is A period during which reading is performed and input to the gate electrode of the third TFT, wherein switching of the third TFT is controlled by the p-th digital signal and the q-th digital signal. This provides a driving method of the self-luminous device, wherein light emission of the EL element is controlled.

According to the present invention, there is provided a method for driving a self-luminous device having a plurality of pixels provided with an EL element, a memory, a first TFT, a second TFT, and a third TFT. The input of the digital video signal to the pixel is controlled by the first TFT, and some bits of the digital video signal input to the pixel are written to the memory by the second TFT. And reading from the memory is controlled, and switching of the third TFT is controlled by a digital video signal of some bits read from the memory or a digital video signal input to the pixel. And a method for driving a self-luminous device, wherein light emission of the EL element is controlled by the third TFT.

According to the present invention, there is provided a method for driving a self-luminous device having a plurality of pixels provided with an EL element and a memory, wherein a plurality of sub-frame periods are provided in one frame period. At least one of the frame periods includes a plurality of divided sub-frame periods, and in at least one of the plurality of divided sub-frame periods, a digital video signal is written to the memory. In a divided sub-frame period that appears after the divided sub-frame period in which the digital video signal is written, the digital video signal is read from the memory, and the EL element includes a digital video signal input to the pixel, Or that light emission is controlled by the read digital video signal The driving method of a self light emitting device is provided, wherein.

According to the present invention, an EL element and an SRAM
A driving method for a self-luminous device having a plurality of pixels provided with a first TFT, a second TFT, and a third TFT, wherein the third TFT is connected via the first TFT. A period during which the p-th digital signal is input to the gate electrode and the p-th digital signal is written to the SRAM via the first TFT and the second TFT; Through the TFT of the third T
A period during which the q-th digital signal is input to the gate electrode of the FT and the p-th digital signal written in the SRAM is held, and the p-th digital signal held in the SRAM is A period during which reading is performed and input to the gate electrode of the third TFT, wherein switching of the third TFT is controlled by the p-th digital signal and the q-th digital signal. This provides a driving method of the self-luminous device, wherein light emission of the EL element is controlled.

According to the present invention, an EL element and an SRAM
And a driving method for a self-luminous device having a plurality of pixels provided with a first TFT, a second TFT, and a third TFT, wherein the first TFT transmits a digital video signal to the pixel. Of the digital video signal input to the pixel, writing of the SRAM and reading from the SRAM are controlled by the second TFT, Switching of the third TFT is controlled by a digital video signal of some bits read from the SRAM or a digital video signal input to the pixel, and the EL element is controlled by the third TFT. A method for driving a self-luminous device, characterized in that light emission of the light-emitting device is controlled.

According to the present invention, there is provided a driving method of a self-luminous device having a plurality of pixels provided with an EL element and an SRAM, wherein a plurality of sub-frame periods are provided in one frame period. At least one of the frame periods includes a plurality of divided sub-frame periods, and in at least one of the plurality of divided sub-frame periods, a digital video signal is written to the SRAM, and In a divided sub-frame period that appears after the divided sub-frame period in which the digital video signal is written, the digital video signal is read from the SRAM, and the EL element includes a digital video signal input to the pixel, Or that light emission is controlled by the read digital video signal The driving method of a self light emitting device is provided, wherein.

The present invention may be characterized in that the memory has three n-channel TFTs and three p-channel TFTs.

The present invention relates to the above three n-channel TFTs.
Has a gate electrode connected to the gate electrode of the first TFT, and the three p-channel TFTs
One of the gate electrodes of the FT may be connected to the gate electrode of the second TFT included in a different pixel.

The present invention is characterized in that the memory is an n-channel TFT and a p-channel TFT whose gate electrodes are connected to each other.
It has two sets of FTs, the n-channel TFT and the p-type TFT.
The channel type TFT has a drain region connected to each other. The two sets of the n-channel type TFT and the p-channel type TFT have a gate electrode connected to another pair of drain regions. A pair of a drain region and a pair of a drain region and a drain region may be connected to a source region or a drain region of the second TFT.

The present invention may be characterized in that the SRAM has two n-channel TFTs and two p-channel TFTs.

According to the present invention, the SRAM comprises an n-channel TFT and a p-channel TFT each having a gate electrode connected to each other.
It has two sets of FTs, the n-channel TFT and the p-type TFT.
The channel type TFT has a drain region connected to each other. The two sets of the n-channel type TFT and the p-channel type TFT have a gate electrode connected to another pair of drain regions. A pair of a drain region and a pair of a drain region and a drain region may be connected to a source region or a drain region of the second TFT.

The present invention may be characterized in that the plurality of divided subframe periods do not appear continuously.

[0068]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described below.

(Embodiment 1)

FIG. 3 is a block diagram of a self-luminous device according to the present invention. 100 is a pixel portion, 101 is a source signal line drive circuit, 102 is an address gate signal line drive circuit, 103
Denotes a memory gate signal line drive circuit.

FIG. 4 shows a detailed configuration of the pixel section 100.
The pixel unit 100 includes source signal lines S1 to Sx, address gate signal lines Ga1 to Gay, memory gate signal lines Gm1 to Gmy, and high-voltage power supply lines HPS1 to HPS.
y, and low-voltage-side power supply lines LPS1 to LPSy.

Source signal lines, address gate signal lines,
The pixel 104 has a region having one memory gate signal line, one high-voltage power line, and one low-voltage power line. The pixel unit 100 includes a plurality of pixels 1 in a matrix.
04 is provided.

FIG. 5 shows a detailed configuration of the pixel 104. FIG. 5 shows an arbitrary one of the plurality of pixels 104, including a source signal line Sj (one of S1 to Sx) and an address gate signal line Gai (one of Ga1 to Gay). ), Memory gate signal lines Gmi (Gm1 to Gm
y), the high voltage side power supply line HPSi (HPS1
To HPSi) and the low voltage side power supply line LPSi
(One of LPS1 to LPSy).

The high-voltage power lines HPS1 to HPSy are connected to the high-voltage power source, and the low-voltage power lines LPS1 to LPSy are connected to the low-voltage power source.

The pixel 104 includes the address TFT 10.
5. TFT 106 for memory, TFT 10 for EL drive
7, an EL element 108 and a memory 109.

The gate electrode of the address TFT 105 is connected to the address gate signal line Gai. Also,
One of a source region and a drain region of the address TFT 105 is connected to the source signal line Sj, and the other is connected to the gate electrode of the EL driving TFT 107.

The gate electrode of the memory TFT 106 is connected to the memory gate signal line Gmi.
One of a source region and a drain region of the memory TFT 106 is connected to the gate electrode of the EL driving TFT 107, and the other is connected to the memory 109. That is, the side of the source region and the drain region of the address TFT 105 that is not connected to the source signal line Sj,
The source region and the drain region of the memory TFT 106 that are not connected to the memory 109 are connected.

The source region of the EL driving TFT 107 is connected to the pixel electrode side power supply 181, and the drain region is connected to the pixel electrode of the EL element 108. E
The L element 108 has a pixel electrode, a counter electrode, and an EL layer provided between the pixel electrode and the counter electrode. EL
The opposite electrode of the element 108 is connected to the opposite electrode power supply 182.

The pixel electrode side power supply 181 and the counter electrode side power supply 1
When the potential of the pixel electrode side power supply 181 is applied to the pixel electrode of the EL element 108,
Have a potential difference from each other to the extent that they emit light.

In FIG. 5, the EL driving TFT 107 has p
Although the case of a channel type TFT is described, this embodiment is not limited to this structure. EL drive TFT1
07 may be an n-channel TFT.

When the EL driving TFT 107 is a p-channel TFT, the pixel electrode side power supply 181 connected to the source region of the EL driving TFT 107 is shared with the high voltage side power supply and connected to the opposite electrode of the EL element 108. The opposing electrode side power supply 182 may be configured to be common to the low voltage side power supply.

The EL driving TFT 107 is an n-channel type TFT.
In the case of FT, the pixel electrode side power supply 181 connected to the source region of the EL driving TFT 107 is shared with the low voltage side power supply, and the counter electrode side power supply 182 connected to the counter electrode of the EL element 108 is connected with the high voltage side power supply. A common configuration may be used.

The pixel electrode and the counter electrode of the EL element are
One is the anode and the other is the cathode. EL drive TF
When T107 is a p-channel TFT, it is desirable to use an anode as a pixel electrode and a cathode as a counter electrode. Conversely, the EL driving TFT 107 is an n-channel type TF
In the case of T, it is desirable to use the cathode as a pixel electrode and the anode as a counter electrode.

Next, a detailed configuration of the memory 109 will be described. FIG. 6 shows a detailed configuration of the memory 109.

The memory 109 has three p-channel type TFs.
T110, 111, 112 and three n-channel type TFs
T113, 114, and 115.

The source region of the p-channel TFT 110 is connected to the high-voltage power supply line HPSi, and the drain region is connected to the source region of the p-channel TFT 111. And n
The source region of the channel type TFT 114 is on the low voltage side power supply line LPSi, and the drain region is an n-channel type TFT 113.
Connected to the source region.

The drain region of the p-channel TFT 111 and the drain region of the n-channel TFT 113 are connected at a connection point 116.

The source region of the p-channel TFT 112 is connected to the high-voltage power line HPSi, and the source region of the n-channel TFT 115 is connected to the low-voltage power line LSi.
Connected to PSi. And p-channel type TFT1
The drain region 12 and the drain region of the n-channel TFT 115 are connected at a connection point 117.

The gate electrode of the p-channel TFT 110 is connected to an address gate signal line Gai, and the gate electrode of the n-channel TFT 114 is connected to a memory gate signal line Gm (i-1).

The gate electrodes of the p-channel TFT 111 and the n-channel TFT 113 are connected to each other, and are also connected to a connection point 117, respectively. p-channel type T
The FT 112 and the gate electrode of the n-channel TFT 115 are connected, and are also connected to a connection point 116, respectively.

The connection point 116 is connected to the source region or the drain region of the memory TFT 106.

In this embodiment, the address T
The FT 105 and the memory TFT 106 need to have the same polarity. Also, address TFT
105 and the memory TFT 106 are the EL driving T
It is necessary to have the polarity opposite to that of FT107.

Further, among the TFTs included in the memory 109, the TFT whose gate electrode is connected to the address gate signal line Gai and the EL driving TFT 107 need to have the same polarity. Further, among the TFTs included in the memory 109, the TFT whose gate electrode is connected to the memory gate signal line Ga (i-1) included in an adjacent pixel has the same polarity as the address TFT 105 and the memory TFT 106. It is necessary to be.

Next, the driving of the self-luminous device of this embodiment will be described with reference to FIG.

In FIG. 7, an arbitrary sub-frame period SFt
In SFt + 2, the number of bits of the digital video signal input to the gate electrode of the EL driving TFT 107 and the connection point 116 are shown. Note that, of the subframe periods SFt to SFt + 2, the subframe period SFt
Represents two divided subframe periods (SFt_1, SFt_
It appears divided in 2).

Whether or not the EL element emits light in each sub-frame period is controlled by a digital video signal corresponding to each sub-frame period.

In the divided sub-frame period SFt in the divided sub-frame period SFt_1, the address selection signal output from the address gate signal line driving circuit 102 causes the address gate signal lines Ga1 to Gay to be output. Are sequentially selected.

In this specification, an address gate signal line is selected when all the address TFTs 105 whose gate electrodes are connected to the address gate signal line.
Is turned on.

At the same time, the memory gate signal lines Gm1 to Gmy are sequentially selected by the memory selection signal output from the memory gate signal line driving circuit 103.

In this specification, selecting a memory gate signal line means that all the memory TFTs 106 whose gate electrodes are connected to the memory gate signal line are turned on.

For example, in the case of the pixel on the i-th line, the address gate signal line Gai and the memory gate signal line Gmi are simultaneously selected in the divided sub-frame period SFt_1. Therefore, all the address TFTs 105 whose gate electrodes are connected to the address gate signal line Gai are turned on. At the same time, the memory gate signal line Gmi
All the memory TFTs 106 connected to the gate electrode are turned on.

Further, of the TFTs included in the memory 109, a TFT whose gate electrode is connected to the address gate signal line Gai (PTFT 110 in this embodiment)
Turns off.

When the memory gate signal line Gmi is selected, the memory gate signal line Gm
Since (i-1) is not selected, the TFT whose gate electrode is connected to the memory gate signal line Gm (i-1)
(NTFT 114 in the case of the present embodiment) is off.

Then, the t-th bit digital video signal is supplied from the source signal line driving circuit 101 to each source signal line S.
1 to Sx.

As a result, the t-th bit digital video signal is input to the gate electrode of the EL driving TFT 107 via the addressing TFT 105. At the same time, the digital video signal of the t-th bit is input to the connection point 116 via the memory TFT 106 and held in the memory 109.

When the digital video signal of the t-th bit is input to the gate electrode of the EL driving TFT 107 of each pixel, the switching of the EL driving TFT 107 is performed by the information of 1 or 0 included in the digital video signal of the t-bit. Controlled.

When the EL driving TFT 107 is turned on,
The potential of the pixel electrode side power supply 181 is applied to the pixel electrode of the EL element 108. Since the potential of the counter electrode side power supply 182 is applied to the counter electrode of the EL element 108,
A pixel electrode side power supply 181 and a counter electrode side power supply 182 are provided in the L layer.
EL drive voltage, which is the potential difference between
Emits light.

Conversely, when the EL driving TFT 107 is turned off, the potential of the pixel electrode side power supply 181 is not applied to the pixel electrode of the EL element 108. Therefore, since the pixel electrode of the EL element 108 is kept at the same potential as the counter electrode, the EL element 108 does not emit light.

The divided sub-frame period in which the address gate signal line and the memory gate signal line are simultaneously selected is referred to as a pixel and memory writing period.

When the selection of the address gate signal line Gai and the memory gate signal line Gmi is completed, both the address TFT 105 and the memory TFT 106 are turned off. Then, among the TFTs included in the memory 109, the TFT whose gate electrode is connected to the address gate signal line Gai is turned on.

When the above operation is repeated and all address gate signal lines and memory gate signal lines have been selected, the divided sub-frame period SFt_1 ends.

Next, the sub-frame period SFt + 1 is started, and the address gate signal lines Ga1 to Gay are sequentially selected by the address selection signal output from the address gate signal line drive circuit 102.

For example, in the case of the i-th pixel, when the address gate signal line Gai is selected, all the address TFTs 105 whose gate electrodes are connected to the address gate signal line Gai are turned on.

Further, of the TFTs included in the memory 109, the TFT whose gate electrode is connected to the address gate signal line Gai (PTFT 110 in this embodiment)
Turns off.

Since the memory gate signal line is not selected, all the memory TFTs 106 whose gate electrodes are connected to the memory gate signal line Gmi are turned off. Further, of the TFTs included in the memory 109, a TFT whose gate electrode is connected to the memory gate signal line Gm (i-1) (NTFT1 in this embodiment)
14) is off.

When each address gate signal line is selected, the digital video signal of the (t + 1) th bit is supplied from the source signal line drive circuit 101 to each source signal line S.
1 to Sx. As a result, the address TFT 1
05 to the gate electrode of the EL driving TFT 107,
The digital video signal of the (t + 1) th bit is input.

In the sub-frame period SFt + 1, the memory TFTs 106 are all off, so that the digital video signal of the t-th bit input to the memory 109 in the divided sub-frame period SFt_1 remains held.

When the digital video signal of the (t + 1) th bit is input to the gate electrode of the EL driving TFT 107 of each pixel, the EL video signal is generated by the (t + 1) th bit of the digital video signal as in the divided sub-frame period SFt_1.
Switching of the driving TFT 107 is controlled, and whether the EL element 108 emits light or not is selected.

The period in which only the address gate signal line is selected and the memory gate signal line is not selected is called a pixel writing period.

When the selection of the address gate signal line Gai is completed, the address TFT 105 is turned off, and among the TFTs included in the memory 109, the TFT whose gate electrode is connected to the address gate signal line Gai (this embodiment) In this case, PTFT 110 is turned on.

Then, the address gate signal line Ga (i
+1) selection is started.

When the above operation is repeated and all the address gate signal lines are selected, the sub-frame period SFt + 1 ends.

Next, the divided sub-frame period SFt_2 is started, and the memory gate signal lines Gm1 to Gmy are sequentially selected by the memory selection signal output from the memory gate signal line driving circuit 103. At this time, the periods during which the memory gate signal lines are selected (selection periods) overlap each other by half. For example, when the selection period of the memory gate signal line Gm (i-1) has passed half, the selection period of the memory gate signal line Gmi starts next. Then, the memory gate signal line G
When the selection period of m (i-1) ends, the selection period of the memory gate signal line Gm (i + 1) starts. Therefore, two memory gate signal lines are always selected except for the first one and the last one.

In the sub-frame period SFt_2, since the address gate signal line is not selected, the address TFT 105 is off. Further, among the TFTs included in the memory 109, a TFT whose gate electrode is connected to the address gate signal line (PTFT 110 in this embodiment) is turned on.

For example, in the case of the pixel on the i-th line, in the first half of the selection period of the memory gate signal line Gm (i-1), of the TFTs of the memory 109, the memory gate signal line Gm (i-1) The TFT to which the gate electrode is connected (NTFT 114 in this embodiment) is turned on.

In the first half of the selection period of the memory gate signal line Gmi, the memory gate signal line Gmi
All the memory TFTs 106 connected to the gate electrode are turned on. Then, the digital video signal of the t-th bit held in the memory 109 is output to the EL driving TFT.
Input to the gate electrode 107.

When the digital video signal of the t-th bit is input to the gate electrode of the EL driving TFT 107 of each pixel, as in the divided sub-frame period SFt_1,
The EL driving T by the digital video signal of the t-th bit
The switching of the FT 107 is controlled, and the EL element 108
Is selected to emit or not.

In the first half of the selection period of the memory gate signal line Gmi, the memory gate signal line Gm (i
Since -1) is selected, NTFT 114 remains on.

Next, in the latter half of the selection period of the memory gate signal line Gmi, the next memory gate signal line Gmi is selected.
The selection period of m (i-1) ends. Therefore, the NTFT 114 whose gate electrode is connected to the memory gate signal line Gm (i-1) is turned off. A memory TFT 1 having a gate electrode connected to a memory gate signal line Gmi
06 remains on.

The period during which only the memory gate signal line is selected and the address gate signal line is not selected is called a memory writing period.

When the above operation is repeated and all the memory gate signal lines have been selected, the divided sub-frame period SFt_2 ends.

Then, a divided subframe period SFt + 2_1 which is a pixel and memory writing period is started, and an address gate signal line and a memory gate signal line are sequentially selected.

As described above, in the driving method of the self-luminous device according to the present embodiment, the pixel and memory writing period, the pixel writing period, and the memory reading period are provided.

FIG. 8 is a simplified diagram showing a pixel connection structure in the above-described driving method.

FIG. 8A shows a pixel and memory writing period. A digital video signal input from a source signal line Sj is supplied to an EL driving TFT 1 via an ON address TFT 105 and a memory TFT 106.
07 and the memory 109.

FIG. 8B shows a case of a pixel writing period, in which a digital video signal input from the source signal line Sj is input to the gate electrode of the EL driving TFT 107 via the ON address TFT 105. . Since the memory TFT 106 is off, the memory 109 holds the previously input digital video signal.

FIG. 8C shows the case of the memory readout period. Since the addressing TFT 105 is off, the digital video signal from the source signal line Sj is supplied to the EL driving TF.
No signal is input to the gate electrode of T107. TF for memory
Since T106 is on, the digital video signal held in the memory 109 is input to the gate electrode of the EL driving TFT 107 via the memory TFT 106.

By repeating the above operation, the driving of the EL element is controlled in each sub-frame period.

The timing at which the sub-frame period and the divided sub-frame period start are different for each pixel of each line. FIG. 9 shows the timing at which the subframe period and the divided subframe period start in the pixels of each line. The vertical axis indicates the position of a pixel, and the horizontal axis indicates time.

The start timing of one frame period differs for each pixel of each line, but the length of one frame period is the same for all pixels.

The length of each subframe period is SF
1: SF2: ...: SFn = 2 0: 2 1: ...: meets the 2 ^n-1. When the sub-frame period is divided into a plurality of divided sub-frame periods, the sum of all divided sub-frame periods is regarded as the length of the sub-frame period. For example, if the sub-frame period SFt is composed of three divided sub-frame periods SFt_1, SFt_2, and SFt_3, SFt = SFt_1 + SFt_2
+ SFt_3.

In the driving method of the present embodiment, gradation is displayed by controlling light emission of the EL element in each sub-frame period including the divided frame period. The gradation of the pixel is
It is determined by the ratio of the sum of the light emitting sub-frame periods (lighting periods) in one frame period.

As described above, in the self-luminous device of the present embodiment, the lighting period and the non-lighting period are divided and appear alternately during one frame period. Therefore, even if the human viewpoint moves delicately left, right, up and down and stares only at non-illuminated pixels continuously, or conversely stares only at pixels that are illuminated continuously, the continuous lighting period Alternatively, since the length of the non-lighting period is shorter than that of the conventional driving by the simple binary code method, it is possible to prevent the false contour from being visually recognized.

According to the above configuration, it is possible to prevent display disturbances such as false contours, which are remarkable in time division driving by the binary code method, from being visually recognized.

In this embodiment mode, the address gate signal lines and the memory gate signal lines are controlled by different gate signal line driving circuits (address gate signal line driving circuit 102 and memory gate signal line driving circuit 103). However, the present embodiment is not limited to this. The address gate signal line and the memory gate signal line may be controlled by one gate signal line driving circuit.

Further, in this embodiment, an example has been described in which only one memory read period is provided for one pixel and memory write period, but the present embodiment is not limited to this. A plurality of memory reading periods may be provided with a pixel writing period interposed therebetween.

Further, in the present embodiment, the configuration has been described in which the divided subframe period that first appears among the plurality of divided subframe periods becomes the pixel and memory writing period. Not limited.
When the sub-frame period is divided into a plurality of divided sub-frame periods, the first divided sub-frame period that does not necessarily need to be the pixel and memory writing period. Also, any one of the divided sub-frame periods does not necessarily have to be a pixel and memory writing period, and all of the divided sub-frame periods may be pixel writing periods.

Furthermore, unless the divided sub-frame periods divided from the same sub-frame period appear continuously, the order in which the sub-frame periods and the divided sub-frame periods appear can be appropriately set by the designer. is there.

In the self-luminous device of the present embodiment, the digital video signal is stored in the memory provided in the pixel. Therefore, if a still image is written once, the digital video signal is input for each frame. , A still image can be displayed continuously. That is, when a still image is displayed, it is possible to stop the source signal line driving circuit after performing a signal processing operation for at least one frame, thereby greatly reducing power consumption. Becomes

(Embodiment 2) Next, a configuration of the pixel portion 100 shown in FIG. 3 which is different from that of Embodiment 1 will be described.

FIG. 10 shows a detailed configuration of the pixel portion 100 of this embodiment. The pixel portion 100 includes source signal lines S1 to S1.
Sx, address gate signal lines Ga1 to Gay, memory gate signal lines Gm1 to Gmy, high-voltage power lines HPS1 to HPSy, and low-voltage power lines LPS1 to LPS.
PSy, power supply lines Va1 to Vay on the pixel electrode side, and power supply lines Vb1 to Vby on the opposite electrode side.

Source signal lines, address gate signal lines,
The pixel 304 has a region having one memory gate signal line, one high voltage side power line, one low voltage side power line, one pixel electrode side power line, and one counter electrode side power line. Pixel section 1
In 00, a plurality of pixels 304 are provided in a matrix.

FIG. 11 shows a detailed configuration of the pixel 304.
FIG. 11 shows an arbitrary one of the plurality of pixels 304 and one of the source signal lines Sj (S1 to Sx).
), An address gate signal line Gai (Ga1 to Gay)
), A memory gate signal line Gmi (Gm
1 to Gmy), the high voltage side power supply line HPSi
(One of HPS1 to HPSy), low voltage side power supply line LPSi (one of LPS1 to LPSy), pixel electrode side power supply line Vai (one of Va1 to Vay), and counter electrode side power supply line Vbi (1 of Vb1 to Vby)
One).

The high-voltage power lines HPS1 to HPSy are connected to the high-voltage power supply, and the low-voltage power lines LPS1 to LPSy are connected to the low-voltage power supply. Also, the pixel electrode side power supply line V
a1 to Vay are the pixel electrode side power supply and the counter electrode side power supply line V
b1 to Vby are respectively connected to the counter electrode side power supply.

The pixel 304 includes the address TFT 30.
5. TFT 306 for memory, TFT 30 for EL driving
7, an EL element 308 and a memory 309.

The gate electrode of the address TFT 305 is connected to the address gate signal line Gai. Also,
One of a source region and a drain region of the address TFT 305 is connected to the source signal line Sj, and the other is connected to the gate electrode of the EL driving TFT 307.

The gate electrode of the memory TFT 306 is connected to the memory gate signal line Gmi.
One of a source region and a drain region of the memory TFT 306 is connected to the gate electrode of the EL driving TFT 307, and the other is connected to the memory 309. That is, the side of the source region and the drain region of the address TFT 305 that is not connected to the source signal line Sj,
The source region and the drain region of the memory TFT 306 that are not connected to the memory 309 are electrically connected to each other.

The source region of the EL driving TFT 307 is connected to the pixel electrode side power supply line Vai, and the drain region is connected to the pixel electrode of the EL element 308.
The EL element 308 has a pixel electrode, a counter electrode, and an EL layer provided between the pixel electrode and the counter electrode. E
The opposite electrode of the L element 308 is connected to the opposite electrode side power supply line Vbi.

The potential of the pixel electrode side power supply line Vai and the potential of the counter electrode side power supply line Vbi are equal to the potential of the pixel electrode side power supply line Vai.
When applied to the pixel electrode of the L element 308, there is a potential difference between them so that the EL element 308 emits light.

Although FIG. 11 shows a case where the EL driving TFT 307 is a p-channel TFT, the present embodiment is not limited to this structure. EL drive TFT
Reference numeral 307 may be an n-channel TFT.

The pixel electrode and the counter electrode of the EL element are
One is the anode and the other is the cathode. When the anode is used as a pixel electrode and the cathode is used as a counter electrode, the EL driving TFT 307 is preferably a p-channel TFT. Conversely, when the cathode is used as a pixel electrode and the anode is used as a counter electrode, the EL driving TFT 307 is preferably an n-channel TFT.

Next, the detailed configuration of the memory 309 will be described. FIG. 12 shows a detailed configuration of the memory 309.

The memory 309 has two p-channel type TFs.
T (PTFT) 311, 312 and two n-channel TFTs (NTFT) 313, 314.

The source regions of the p-channel TFTs 311 and 312 are connected to the high-voltage power supply line HPSi. The source regions of the n-channel TFTs 313 and 314 are connected to the low-voltage power supply line LPSi.

The drain region of the p-channel TFT 311 and the drain region of the n-channel TFT 313 are connected at a connection point 316. Also, a p-channel TFT
The drain region 312 and the drain region of the n-channel TFT 314 are connected at a connection point 317.

The gate electrodes of the p-channel TFT 311 and the n-channel TFT 313 are connected to a connection point 317. The gate electrodes of the p-channel TFT 312 and the n-channel TFT 314 are connected to a connection point 316.

The connection point 316 is connected to the source region or the drain region of the memory TFT 306.

The address TFT 305 and the memory TFT 306 have the same polarity.

Next, the driving of the self-luminous device of this embodiment will be described with reference to FIG.

In FIG. 13, an arbitrary subframe period SF
From t to SFt + 2, the address gate signal line Ga
(I + 1), the potential of the signal input to Gai, Ga (i-1), and the memory gate signal lines Gm (i + 1), G
mi and Gm (i−1) are shown. In each subframe period, E
A bit number of a digital video signal input to the gate electrode of the L driving TFT 307 and the connection point 316 is shown.

Note that subframe periods SFt to SFt + 2
Among them, the sub-frame period SFt appears divided into two divided sub-frame periods (SFt_1, SFt_2). The sub-frame period SFt + 2 also appears as being divided into a plurality of divided sub-frame periods.
Shows the first divided subframe period SFt + 2
Only _1 is shown.

Whether or not the EL element emits light in each subframe period and each divided subframe period is controlled by a digital video signal corresponding to each period.

In the divided sub-frame period SFt_1 that appears earlier in the divided sub-frame period SFt, the address selection signal output from the address gate signal line driving circuit 102 causes the address gate signal lines Ga1 to Gay to be applied. Are sequentially selected.

In this specification, “selecting an address gate signal line” means that all the address TFTs 305 whose gate electrodes are connected to the address gate signal line.
Is turned on.

At the same time, the memory gate signal lines Gm1 to Gmy are sequentially selected by the memory selection signal output from the memory gate signal line driving circuit 103.

In this specification, selecting a memory gate signal line means that all the memory TFTs 306 whose gate electrodes are connected to the memory gate signal line are turned on.

Further, the high voltage side power supply lines HPS1 to HPS
y and the low-voltage power supply lines LPS1 to LPSy are sequentially maintained at the intermediate potential. Note that the intermediate potential is a potential between the highest potential applied to the high-voltage power supply line and the lowest potential applied to the low-voltage power supply line.

For example, in the case of the pixel on the i-th line, the address gate signal line Gai and the memory gate signal line Gmi are simultaneously selected in the divided sub-frame period SFt_1. Therefore, all the addressing TFTs 305 whose gate electrodes are connected to the addressing gate signal line Gai are turned on. At the same time, the memory gate signal line Gmi
All the memory TFTs 306 connected to the gate electrode are turned on.

Further, the high voltage side power supply line HPSi and the low voltage side power supply line LPSi are sequentially maintained at the intermediate potential.

The t-th bit digital video signal is supplied from the source signal line driving circuit 101 to each source signal line S.
1 to Sx.

As a result, the t-th bit digital video signal is input to the gate electrode of the EL driving TFT 307 via the address TFT 305. At the same time, the digital video signal of the t-th bit is input to the connection point 316 via the memory TFT 306 and held in the memory 309.

When the digital video signal of the t-th bit is input to the gate electrode of the EL driving TFT 307 of each pixel, the switching of the EL driving TFT 307 is performed by the information of 1 or 0 included in the digital video signal of the t-bit. Controlled.

When the EL driving TFT 307 is turned on,
The potential of the pixel electrode side power supply line Vai is applied to the pixel electrode of the EL element 308. Since the potential of the power supply line Vbi on the counter electrode side is applied to the counter electrode of the EL element 308, the EL layer is supplied with the EL drive voltage which is the potential difference between the power supply line Vai on the pixel electrode side and the power supply line Vbi on the counter electrode side. , The EL element 308 emits light.

Conversely, when the EL driving TFT 307 is turned off, the potential of the pixel electrode side power supply line Vai is not applied to the pixel electrode of the EL element 308. Accordingly, the pixel electrode of the EL element 308 is kept at the same potential as the counter electrode power supply line Vbi, so that the EL element 308 does not emit light.

The divided sub-frame period in which the address gate signal line and the memory gate signal line are simultaneously selected is called a pixel and memory writing period.

When the selection of the address gate signal line Gai and the memory gate signal line Gmi is completed, both the address TFT 305 and the memory TFT 306 are turned off. Also, the high-voltage power line HPSi and the low-voltage power line L
The potential with PSi is kept at Vddh and Vss, respectively. Note that Vddh> Vss.

Next, the address gate signal line Ga
The selection of (i + 1) and the memory gate signal line Gm (i + 1) is started.

When the above operation is repeated and all the address gate signal lines and the memory gate signal lines are selected, the divided sub-frame period SFt_1 ends.

Next, the sub-frame period SFt + 1 is started, and the address gate signal lines Ga1 to Gay are sequentially selected by the address selection signal output from the address gate signal line drive circuit 102.

For example, in the case of the i-th pixel, when the address gate signal line Gai is selected, all the address TFTs 305 whose gate electrodes are connected to the address gate signal line Gai are turned on.

Since the memory gate signal line is not selected, all the memory TFTs 306 whose gate electrodes are connected to the memory gate signal line Gmi are turned off.

The high voltage side power supply lines HPS1 to HPSy
And the potentials of the low voltage side power supply lines LPS1 to LPSy are kept at Vddh and Vss, respectively.

When each address gate signal line is selected, the digital video signal of the (t + 1) th bit is supplied from the source signal line drive circuit 101 to each source signal line S.
1 to Sx. As a result, the address TFT 3
05 to the gate electrode of the EL driving TFT 307,
The digital video signal of the (t + 1) th bit is input.

In the subframe period SFt + 1, the memory TFTs 306 are all off, so that the t-th bit digital video signal input to the memory 309 in the divided subframe period SFt_1 remains held.

When the digital video signal of the (t + 1) th bit is input to the gate electrode of the EL driving TFT 307 of each pixel, the EL video signal is generated by the (t + 1) th bit of the digital video signal as in the divided subframe period SFt_1.
The switching of the driving TFT 307 is controlled, and whether or not the EL element 308 emits light is selected.

The period in which only the address gate signal line is selected and the memory gate signal line is not selected is called a pixel writing period.

When the selection of the address gate signal line Gai is completed, the address TFT 305 is turned off. Next, selection of the address gate signal line Ga (i + 1) is started.

When the above operation is repeated and all the address gate signal lines are selected, the sub-frame period SFt + 1 ends.

Next, the divided sub-frame period SFt_2 is started, and the memory gate signal lines Gm1 to Gmy are sequentially selected by the memory selection signal output from the memory gate signal line driving circuit 103.

In the subframe period SFt_2, the address gate signal line is not selected, so that the address TFT 305 is off.

The high voltage side power supply lines HPS1 to HPSy
And the potentials of the low voltage side power supply lines LPS1 to LPSy are kept at Vddh and Vss, respectively.

For example, in the case of the pixel on the i-th line, during the selection period of the memory gate signal line Gmi, all the memory TFTs 306 whose gate electrodes are connected to the memory gate signal line Gmi are turned on. Then, memory 3
The digital video signal of the t-th bit held by the pixel 09 is input to the gate electrode of the EL driving TFT 307.

When the digital video signal of the t-th bit is input to the gate electrode of the EL driving TFT 307 of each pixel, as in the divided sub-frame period SFt_1,
The EL driving T by the digital video signal of the t-th bit
The switching of the FT 307 is controlled, and the EL element 308
Is selected to emit or not.

The period in which only the memory gate signal line is selected and the address gate signal line is not selected is called a memory read period.

When the selection of the memory gate signal line Gmi is completed, the memory TFT 306 is turned off. Then, the selection of the memory gate signal line Gm (i + 1) is started.

When the above operation is repeated and all the memory gate signal lines are selected, the divided sub-frame period SFt_2 ends.

Then, a divided subframe period SFt + 2_1, which is a pixel and memory writing period, starts, and an address gate signal line and a memory gate signal line are sequentially selected.

As described above, in the driving method of the self-luminous device according to the present embodiment, the pixel and memory writing period, the pixel writing period, and the memory reading period are provided.

FIG. 14 shows a simplified connection structure of pixels in the above-described driving method.

FIG. 14A shows a pixel and memory writing period. A digital video signal input from a source signal line Sj is supplied to an EL driving TFT via an ON address TFT 305 and a memory TFT 306.
The signal is input to the gate electrode 307 and the memory 309.

FIG. 14B shows the case of the pixel writing period, in which the digital video signal input from the source signal line Sj is supplied to the EL via the ON address TFT 305.
The signal is input to the gate electrode of the driving TFT 307. Since the memory TFT 306 is off, the memory 309 holds the previously input digital video signal.

FIG. 14C shows the case of the memory readout period. Since the address TFT 305 is turned off, the digital video signal from the source signal line Sj is supplied to the EL drive TFT.
It is not input to the gate electrode of FT307. T for memory
Since the FT 306 is on, the digital video signal held in the memory 309 is input to the gate electrode of the EL driving TFT 307 via the memory TFT 306.

By repeating the above operation, the driving of the EL element is controlled in each sub-frame period.

The timings at which the sub-frame period and the divided sub-frame period start are different for each pixel of each line. The timing at which the sub-frame period and the divided sub-frame period start in the pixels of each line can be referred to FIG.

The start timing of one frame period differs for each pixel of each line, but the length of one frame period is the same for all pixels.

The length of each subframe period is SF
1: SF2: ...: SFn = 2 0: 2 1: ...: meets the 2 ^n-1. When the sub-frame period is divided into a plurality of divided sub-frame periods, the sum of all divided sub-frame periods is regarded as the length of the sub-frame period. For example, if the sub-frame period SFt is composed of three divided sub-frame periods SFt_1, SFt_2, and SFt_3, SFt = SFt_1 + SFt_2
+ SFt_3.

In the driving method of the present embodiment, gradation is displayed by controlling the light emission of the EL element in each sub-frame period including the divided frame period. The gradation of the pixel is
It is determined by the ratio of the sum of the light emitting sub-frame periods (lighting periods) in one frame period.

As described above, in the self-luminous device of this embodiment, the lighting period and the non-lighting period are divided and appear alternately during one frame period. Therefore, even if the human viewpoint moves delicately left, right, up and down and stares only at non-illuminated pixels continuously, or conversely stares only at pixels that are illuminated continuously, the continuous lighting period Alternatively, since the length of the non-lighting period is shorter than that of the conventional driving by the simple binary code method, it is possible to prevent the false contour from being visually recognized.

According to the above configuration, it is possible to prevent display disturbances such as false contours, which are remarkable in time division driving by the binary code method, from being visually recognized.

In this embodiment mode, the address gate signal line and the memory gate signal line are controlled by different gate signal line drive circuits (address gate signal line drive circuit 102 and memory gate signal line drive circuit 103). However, the present embodiment is not limited to this. The address gate signal line and the memory gate signal line may be controlled by the same gate signal line driving circuit.

Further, in this embodiment, an example has been described in which only one memory reading period is provided for one pixel and memory writing period, but this embodiment is not limited to this. A plurality of memory reading periods may be provided with a pixel writing period interposed therebetween.

Further, in the present embodiment, a configuration has been shown in which, among a plurality of divided sub-frame periods, a divided sub-frame period that appears first becomes a pixel and memory writing period. Not limited.
When the sub-frame period is divided into a plurality of divided sub-frame periods, the first divided sub-frame period that does not necessarily need to be the pixel and memory writing period. Also, any one of the divided sub-frame periods does not necessarily have to be a pixel and memory writing period, and all of the divided sub-frame periods may be pixel writing periods.

Furthermore, the order in which the sub-frame periods and the divided sub-frame periods appear can be appropriately set unless the divided sub-frame periods divided from the same sub-frame period appear continuously.

In the self-luminous device of this embodiment, the potentials of the high-voltage power supply line and the low-voltage power supply line are constant during periods other than the pixel and memory writing periods. Therefore, since the memory provided in the pixel functions as an SRAM, when a digital video signal is stored in the memory, the stored digital video signal is held until the digital video signal is input to the memory again. Therefore,
In the case of a still image using a 1-bit digital video signal,
Once writing is performed, a still image can be displayed continuously without inputting a digital video signal for each frame. That is, when displaying a still image, it is possible to stop the source signal line driving circuit after performing a signal processing operation for at least one frame, thereby reducing power consumption. Become.

[0225]

Embodiments of the present invention will be described below.

(Embodiment 1) In this embodiment, an example will be described in which the self-luminous device of the present invention having the configuration shown in FIGS. 4 to 6 is driven by using an 8-bit digital video signal.

FIG. 15 is a diagram simply showing the driving method of the present embodiment, in which the gate electrode of the EL driving TFT 107,
The bit numbers of the digital video signal input to the connection point 116 are shown. Note that the horizontal axis is time.

BK indicates a digital signal (non-display signal) that does not perform display in all pixels. Therefore, the non-display signal has no image information. When a non-display signal is input to the gate electrode of the EL driving TFT 107 instead of the digital video signal, the EL driving TFT is turned off, and the EL element does not emit light. In this specification,
A period in which all the pixels do not perform display by the non-display signal is referred to as a non-display period (BKF).

When one frame period starts, first, a non-display period BKF1 starts. The non-display period BKF1 is a pixel and memory writing period, and the source signal line Sj
The non-display signal BK input to the EL driving TFT 107
Is input to the gate electrode and the memory 109.

When a non-display signal BK is input to the gate electrode of the EL driving TFT 107, the EL driving TFT 107
Is turned off, and the EL element does not emit light.

Next, subframe period SF1 is started. The sub-frame period SF1 is a pixel writing period in which the digital video signal of the first bit is the EL driving TF.
Input to the gate electrode of T107. Then, whether or not the EL element emits light is selected by the digital video signal of the first bit.

In the sub-frame period SF1, the non-display signal BK is held in the memory 109.

Next, the non-display period BKF2 is started. The non-display period BKF2 is a memory reading period, in which the non-display signal BK held in the memory 109 is read and input to the gate electrode of the EL driving TFT 107. When the non-display signal BK is input to the gate electrode of the EL driving TFT 107, the EL driving TFT 1
07 is turned off, and the EL element does not emit light.

Next, subframe period SF2 is started. Since the sub-frame period SF2 is a pixel writing period, the digital video signal of the second bit is the EL driving T
Input to the gate electrode of FT107. Then, whether or not the EL element emits light is selected by the digital video signal of the second bit.

In the sub-frame period SF2, the non-display signal BK is held in the memory 109.

Next, the non-display period BKF3 is started. The non-display period BKF3 is a memory reading period, in which the non-display signal BK held in the memory 109 is read and input to the gate electrode of the EL driving TFT 107. When the non-display signal BK is input to the gate electrode of the EL driving TFT 107, the EL driving TFT 1
07 is turned off, and the EL element does not emit light.

Next, divided subframe period SF8_1 is started. The divided subframe period SF8_1 is a pixel and memory writing period, and the eighth bit digital video signal input to the source signal line Sj is input to the gate electrode of the EL driving TFT 107 and the memory 109. Then, by the 8th bit digital video signal,
Whether the EL element emits light or not is selected.

Next, subframe period SF5 is started. Since the sub-frame period SF5 is a pixel writing period, the digital video signal of the fifth bit is the EL driving T
Input to the gate electrode of FT107. Then, whether or not the EL element emits light is selected by the digital video signal of the fifth bit.

In the sub-frame period SF5, the digital video signal of the eighth bit is held in the memory 109.

Next, divided subframe period SF8_2 is started. The divided sub-frame period SF8_2 is a memory readout period, in which the digital video signal of the 8th bit held in the memory 109 is read out.
The signal is input to the gate electrode of the EL driving TFT 107. Then, whether or not the EL element emits light is selected by the digital video signal of the 8th bit.

Next, divided subframe period SF6_1 is started. Since the divided sub-frame period SF6_1 is a pixel writing period, a 6-bit digital video signal is input to the gate electrode of the EL driving TFT 107.
Then, whether or not the EL element emits light is selected based on the 6-bit digital video signal.

In the divided sub-frame period SF6_1, the digital video signal of the eighth bit is held in the memory 109.

Next, divided subframe period SF8_3 is started. The divided sub-frame period SF8_3 is a memory readout period, in which the digital video signal of the eighth bit held in the memory 109 is read out.
The signal is input to the gate electrode of the EL driving TFT 107. Then, whether or not the EL element emits light is selected by the digital video signal of the 8th bit.

Next, subframe period SF4 is started. Since the sub-frame period SF4 is a pixel writing period, the digital video signal of the fourth bit is the EL driving T
Input to the gate electrode of FT107. Then, whether or not the EL element emits light is selected by the fourth bit digital video signal.

In the sub-frame period SF4, the digital video signal of the eighth bit is held in the memory 109.

Next, divided subframe period SF8_4 is started. The divided sub-frame period SF8_4 is a memory readout period, in which the digital video signal of the eighth bit held in the memory 109 is read out.
The signal is input to the gate electrode of the EL driving TFT 107. Then, whether or not the EL element emits light is selected by the digital video signal of the 8th bit.

Next, a sub-frame period SF3 is started. Since the sub-frame period SF3 is a pixel writing period, the digital video signal of the third bit is the EL driving T
Input to the gate electrode of FT107. Then, whether or not the EL element emits light is selected by the digital video signal of the third bit.

In the sub-frame period SF3, the digital video signal of the eighth bit is held in the memory 109.

Next, divided subframe period SF8_5 is started. The divided sub-frame period SF8_5 is a memory reading period, in which the digital video signal of the eighth bit held in the memory 109 is read.
The signal is input to the gate electrode of the EL driving TFT 107. Then, whether or not the EL element emits light is selected by the digital video signal of the 8th bit.

Next, divided subframe period SF7_1 is started. The divided subframe period SF7_1 is a pixel and memory writing period, and the seventh bit digital video signal input to the source signal line Sj is input to the gate electrode of the EL driving TFT 107 and the memory 109. And by the 7-bit digital video signal,
Whether the EL element emits light or not is selected.

Next, divided subframe period SF6_2 is started. Since the divided sub-frame period SF6_2 is a pixel writing period, a 6-bit digital video signal is input to the gate electrode of the EL driving TFT 107.
Then, whether or not the EL element emits light is selected based on the 6-bit digital video signal.

In the divided sub-frame period SF6_2, the digital video signal of the seventh bit is held in the memory 109.

Next, divided subframe period SF7_2 is started. The divided sub-frame period SF7_2 is a memory readout period, in which the seventh bit digital video signal held in the memory 109 is read out.
The signal is input to the gate electrode of the EL driving TFT 107. Then, whether or not the EL element emits light is selected by the 7-bit digital video signal.

When the divided subframe period SF7_2 ends, one frame period ends. The gradation of each pixel is determined by the ratio of the sum of the lengths of the light emitting sub-frame periods in one frame period.

According to the above configuration, it is possible to prevent display disturbances such as false contours, which are remarkable in time division driving by the binary code method, from being visually recognized.

In this embodiment, the driving method of the self-luminous device having the structure shown in FIGS. 4 to 6 has been described.
The driving method described in this embodiment can also be used for the self-luminous device having the configuration shown in FIGS.

(Embodiment 2) In this embodiment, Embodiment 1
An example will be described in which the polarity of the TFT is different from that of the pixel shown in FIG.

FIG. 16 shows the structure of a pixel according to this embodiment. FIG. 16 shows an arbitrary one of the plurality of pixels 204, and includes a source signal line Sj (one of S1 to Sx),
Address gate signal lines Gai (one of Ga1 to Gay) and memory gate signal lines Gmi (Gm1 to Gm1)
my), high-voltage side power supply line HPSi (HPS
1 to HPSy) and the low voltage side power supply line LPS
i (one of LPS1 to LPSy).

The pixel 204 is provided with the address TFT 20.
5. TFT 206 for memory, TFT 20 for EL drive
7, an EL element 208 and a memory 209.

The gate electrode of the addressing TFT 205 is
It is connected to the address gate signal line Gai. One of a source region and a drain region of the address TFT 205 is connected to the source signal line Sj, and the other is connected to the gate electrode of the EL driving TFT 207.

The gate electrode of the memory TFT 206 is connected to the memory gate signal line Gmi.
One of a source region and a drain region of the memory TFT 206 is connected to the gate electrode of the EL driving TFT 207, and the other is connected to the memory 209. That is, the side of the source TFT and the drain region of the address TFT 205 that is not connected to the source signal line Sj,
The source region and the drain region of the memory TFT 206 that are not connected to the memory 209 are connected.

The source region of the EL driving TFT 207 is connected to the pixel electrode side power supply 281, and the drain region is connected to the pixel electrode of the EL element 208. E
The L element 208 has a pixel electrode, a counter electrode, and an EL layer provided between the pixel electrode and the counter electrode. EL
A counter electrode of the element 208 is connected to a counter electrode side power supply 282.

The pixel electrode side power supply 281 and the counter electrode side power supply 2
When the potential of the pixel electrode side power supply 281 is applied to the pixel electrode of the EL element 208, the potential of
Have a potential difference from each other to the extent that they emit light.

The pixel electrode and the counter electrode of the EL element 208
One is the anode and the other is the cathode. In this embodiment, E
Since the L driving TFT 207 is an n-channel TFT, the cathode is used as a pixel electrode and the anode is used as a counter electrode.

The pixel electrode side power supply 281 connected to the source region of the EL driving TFT 107 is shared with the low voltage side power supply, and the counter electrode side power supply 282 connected to the counter electrode of the EL element 208 is connected to the high voltage side power supply. A configuration may be used in common with.

Next, the detailed configuration of the memory 209 will be described. FIG. 17 shows a detailed configuration of the memory 209.

The memory 209 has three n-channel type TFs.
T210, 211, 212 and three p-channel type TFs
T213, 214, and 215.

The source region of the n-channel TFT 210 is connected to the low-voltage side power supply line LPSi, and the drain region is connected to the source region of the n-channel TFT 211. Also p
The source region of the channel type TFT 214 is on the high voltage side power supply line HPSi, and the drain region is a p-channel type TFT 213.
Connected to the source region.

The drain region of the n-channel TFT 211 and the drain region of the p-channel TFT 213 are connected at a connection point 216.

The source region of the n-channel TFT 212 is connected to the low-voltage power line LPSi, and the source region of the p-channel TFT 215 is connected to the high-voltage power line HSi.
Connected to PSi. And n-channel type TFT2
The drain region 12 and the drain region of the p-channel TFT 215 are connected at a connection point 217.

The gate electrode of the n-channel TFT 210 is connected to the address gate signal line Gai, and the gate electrode of the p-channel TFT 214 is connected to the memory gate signal line Gm (i-1).

The gate electrodes of the n-channel TFT 211 and the p-channel TFT 213 are connected, and are also connected to the connection point 217. n-channel type T
The FT 212 and the gate electrode of the p-channel TFT 215 are connected, and are also connected to a connection point 216, respectively.

The connection point 216 is connected to the source or drain region of the memory TFT 206.

In the present invention, the addressing TFT 2
05 and the memory TFT 206 need to have the same polarity. Also, the address TFT 205
And the memory TFT 206 are the EL driving TFT 2
It is necessary to have a polarity opposite to 07.

Further, among the TFTs included in the memory 209, the TFT whose gate electrode is connected to the address gate signal line Gai and the EL driving TFT 207 need to have the same polarity. Further, among the TFTs included in the memory 209, a TFT whose gate electrode is connected to the memory gate signal line Ga (i-1) included in an adjacent pixel has the same polarity as the address TFT 205 and the memory TFT 206. It is necessary to be.

This embodiment can be implemented by freely combining with Embodiment 1.

(Embodiment 3) In this embodiment, an example in which a capacitor is provided in the pixel shown in FIG. 5 will be described.

FIG. 18 shows the structure of a pixel according to this embodiment. Those shown in FIG. 5 are denoted by the same reference numerals. In the pixel shown in FIG. 18, the detailed connection of TFTs and EL elements other than the capacitor has already been described in the embodiment, and therefore, only the connection configuration of the capacitor will be described here.

The capacitor 131 is an EL driving TFT 1
07 and a high voltage power supply line HPSi. The capacitors 132 and 133 are respectively formed by a high-voltage power supply line HPSi and two sets of n-channel TFTs and p-channel TFTs whose drain regions are connected to each other.

By providing the capacitor, it is possible to prevent the charge held in the memory 109 from decreasing due to the off-state current of the addressing TFT 105 and the memory TFT 106 (the current flowing in the channel formation region when the TFT is off).

Note that the capacitors 131, 132, and 133 need not always be provided.

This embodiment can be implemented by freely combining with Embodiments 1 and 2.

(Embodiment 4) In this embodiment, an example in which the polarity of a TFT is different from that of the pixel shown in Embodiment Mode 2 will be described.

FIG. 19 shows a detailed configuration of the pixel 404.
FIG. 19 shows an arbitrary one of the plurality of pixels 404, and one of the source signal lines Sj (S1 to Sx).
), An address gate signal line Gai (Ga1 to Gay)
), A memory gate signal line Gmi (Gm
1 to Gmy), the high voltage side power supply line HPSi
(One of HPS1 to HPSy), low voltage side power supply line LPSi (one of LPS1 to LPSy), pixel electrode side power supply line Vai (one of Va1 to Vay), and counter electrode side power supply line Vbi (1 of Vb1 to Vby)
One).

The high-voltage power lines HPS1 to HPSy are connected to the high-voltage power supply, and the low-voltage power lines LPS1 to LPSy are connected to the low-voltage power supply. Also, the pixel electrode side power supply line V
a1 to Vay are the pixel electrode side power supply and the counter electrode side power supply line V
b1 to Vby are respectively connected to the counter electrode side power supply.

The pixel 404 includes the address TFT 40.
5. TFT 406 for memory, TFT 40 for EL driving
7, an EL element 408 and a memory 409.
In this embodiment, the address TFT 405 and the memory TFT 406 are p-channel TFTs, and the EL driving TFT 407 is an n-channel TFT.

The gate electrode of the address TFT 405 is connected to the address gate signal line Gai. Also,
One of a source region and a drain region of the address TFT 405 is connected to the source signal line Sj, and the other is connected to the gate electrode of the EL driving TFT 407.

The gate electrode of the memory TFT 406 is connected to the memory gate signal line Gmi.
One of a source region and a drain region of the memory TFT 406 is connected to the gate electrode of the EL driving TFT 407, and the other is connected to the memory 409. That is, the side of the source region and the drain region of the address TFT 405 that is not connected to the source signal line Sj,
The source region and the drain region of the memory TFT 406 which are not connected to the memory 409 are electrically connected to each other.

The source region of the EL driving TFT 407 is connected to the pixel electrode side power supply line Vai, and the drain region is connected to the pixel electrode of the EL element 408.
The EL element 408 has a pixel electrode, a counter electrode, and an EL layer provided between the pixel electrode and the counter electrode. E
The opposite electrode of the L element 408 is connected to the opposite electrode side power supply line Vbi.

The potential of the pixel electrode side power supply line Vai and the potential of the counter electrode side power supply line Vbi are E potential of the pixel electrode side power supply line Vai.
When applied to the pixel electrode of the L element 408, there is a potential difference between them so that the EL element 408 emits light.

The pixel electrode and the counter electrode of the EL element are
One is the anode and the other is the cathode. When the EL driving TFT 407 is an n-channel TFT as in this embodiment, it is preferable to use a cathode as a pixel electrode and an anode as a counter electrode.

Next, the detailed configuration of the memory 409 will be described. FIG. 20 shows a detailed configuration of the memory 409.

The memory 409 has two n-channel type TFs.
T (NTFT) 411 and 412 and two p-channel type TFT (PTFT) 413 and 414 are provided.

The source regions of the n-channel TFTs 411 and 412 are connected to the low-voltage side power supply line LPSi. The source regions of the p-channel TFTs 413 and 414 are respectively connected to the high-voltage power supply line HPSi.

[0295] The drain region of the n-channel TFT 411 and the drain region of the p-channel TFT 413 are connected at a connection point 416. Also, n-channel type TFT
The drain region 412 and the drain region of the p-channel TFT 414 are connected at a connection point 417.

The gate electrodes of the n-channel TFT 411 and the p-channel TFT 413 are connected to a connection point 417. The gate electrodes of the p-channel TFT 412 and the n-channel TFT 414 are connected to a connection point 416.

The connection point 416 is connected to the source or drain region of the memory TFT 406.

The address TFT 405 and the memory TFT 406 have the same polarity.

This embodiment can be implemented by freely combining with Embodiment 1.

(Embodiment 5) This embodiment describes an example in which a capacitor is provided in the pixel shown in FIG.

FIG. 21 shows a configuration of a pixel of this embodiment. Those shown in FIG. 11 are denoted by the same reference numerals. In the pixel shown in FIG. 21, the detailed connection of the TFT and the EL element other than the capacitor has already been described in the embodiment, and therefore, only the connection configuration of the capacitor will be described here.

The capacitor 331 is an EL driving TFT 3
07 and the pixel electrode side power supply line Vai. The capacitors 332 and 333 are respectively formed by the pixel electrode side power supply line Vai and the gate electrodes of the n-channel TFT and the p-channel TFT included in the memory 309 and having two drain regions connected to each other. I have.

By providing the capacitor, it is possible to prevent the charge held in the memory 309 from decreasing due to the off-state current of the addressing TFT 305 or the memory TFT 306 (current flowing in the channel formation region when the TFT is off).

The capacitors 331, 332, 333
Need not be provided separately when the parasitic capacitance is sufficient.

This embodiment can be implemented by freely combining with Embodiments 1 and 4.

(Embodiment 6) In this embodiment, a source signal line driving circuit, an address gate signal line driving circuit and a memory gate signal line driving circuit used for driving the pixel portion of the self light emitting device of the present invention. A detailed configuration will be described.

FIG. 22 is a block diagram of a driving circuit of the self-luminous device of this embodiment. FIG. 22A illustrates a source signal line driver circuit 601, which includes a shift register 602, a latch (A) 603, and a latch (B) 604.

In the source signal line driver circuit 601, a clock signal (CLK) and a start pulse (SP) are input to the shift register 602. Shift register 6
02 sequentially generates a timing signal based on the clock signal (CLK) and the start pulse (SP), and sequentially inputs the timing signal to a subsequent circuit through a buffer or the like (not shown).

The timing signal from the shift register 602 is buffer-amplified by a buffer or the like. The wiring to which the timing signal is input has a large load capacitance (parasitic capacitance) because many circuits or elements are connected.
This buffer is provided to prevent "dulling" of the rise or fall of the timing signal caused by the large load capacitance. It is not always necessary to provide a buffer.

[0310] The timing signal buffer-amplified by the buffer is input to the latch (A) 603. The latch (A) 603 has a plurality of stages of latches for processing an n-bit digital video signal. Latch (A)
When the timing signal is input, the 603 sequentially captures and holds an n-bit digital video signal input from outside the source signal line driving circuit 601.

[0311] When a digital video signal is taken into the latch (A) 603, the digital video signal may be sequentially input to the latches of a plurality of stages of the latch (A) 603. However, the present invention is not limited to this configuration. The latches of a plurality of stages included in the latch (A) 603 may be divided into several groups, and a so-called divided drive in which digital video signals are input simultaneously in parallel for each group may be performed. The number of groups at this time is called a division number. For example, when the latch is divided into groups for every four stages, it is referred to as divided drive in four divisions.

[0312] The time until the writing of the digital video signal to the latches of all the stages of the latch (A) 603 is completed is called a line period. Actually, the line period may include a period obtained by adding the horizontal retrace period to the line period.

When one line period ends, latch (B)
A latch signal (Latch Signal) is input to 604. At this moment, the digital video signal written and held in the latch (A) 603 is simultaneously sent to the latch (B) 604, and written and held in the latches of all the stages of the latch (B) 604.

The digital video signal is latched (B) 604
The digital video signal is sequentially written into the latch (A) 603 which has been transmitted to the latch 603 based on the timing signal from the shift register 602.

During the second line period, the digital video signal written and held in the latch (B) 603 is input to the source signal line.

FIG. 22B is a block diagram showing a configuration of an address gate signal line driving circuit.

Address gate signal line drive circuit 605
Have a shift register 606 and a buffer 607, respectively. In some cases, a level shift may be provided.

In the address gate signal line driving circuit 605, the timing signal from the shift register 606 is input to the buffer 607 and input to the corresponding address gate signal line. 1 for the address gate signal line
The gate electrodes of the address TFTs of the pixels for the lines are connected. Then, the address T for the pixels of one line
Since the FT must be turned on all at once, a buffer capable of flowing a large current is used.

Since the memory gate signal line drive circuit has the same structure as the address gate signal line drive circuit, FIG. 22B is referred to. However, in the case of the memory gate signal line driving circuit, the output from the buffer is input to the memory gate signal line. The gate electrode of the memory TFT of one line of pixels is connected to the memory gate signal line. Since the memory TFTs of the pixels for one line must be turned on all at once, a buffer capable of flowing a large current is used.

This embodiment can be implemented by freely combining with Embodiments 1 to 5.

(Embodiment 7) In this embodiment, the TFTs (N-channel TFT and P-channel TF) of the pixel portion and the driving circuit provided around the pixel portion are provided on the same substrate.
The method for simultaneously producing T) will be described in detail. In this embodiment, only the TFT for address and the TFT for EL driving are typically shown as TFTs in the pixel portion. However, a memory TFT for each pixel and a TFT included in the memory can be formed at the same time.

First, as shown in FIG. 23A, oxidation is performed on a substrate 5001 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass. A base film 5002 made of an insulating film such as a silicon film, a silicon nitride film, or a silicon oxynitride film is formed.
For example, a plasma CVD method SiH _4, NH _3, N ₂ silicon oxynitride film 5002a made from O 10 to 2
00 [nm] (preferably 50 to 100 [nm]) is formed, similarly SiH _4, N ₂ O hydrogenated silicon oxynitride film 5002b made from 50 to 200 [nm] (preferably 100
１５０150 [nm]). Although the base film 5002 has a two-layer structure in this embodiment, the base film 5002 may have a single-layer structure or a structure in which two or more insulating films are stacked.

Each of the island-shaped semiconductor layers 5003 to 5006 is formed of a crystalline semiconductor film formed by using a semiconductor film having an amorphous structure by a laser crystallization method or a known thermal crystallization method.
The thickness of the island-shaped semiconductor layers 5003 to 5006 is 25 to 8
It is formed with a thickness of 0 [nm] (preferably 30 to 60 [nm]). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to form a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser is used.
In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 300 [Hz], and the laser energy density is set to 100 to 400 [mJ / cm ² ] (typically, 200 to 300 [mJ / cm ² ]). When a YAG laser is used, its second harmonic is used, the pulse oscillation frequency is set to 30 to 300 [kHz], and the laser energy density is set to 300 to 600 [mJ / cm ² ] (typically 350 to 500 [mJ / cm ² ]).
[mJ / cm ² ]). And a width of 100 to 1000 [μ
m], for example, a laser beam condensed linearly at 400 [μm] is radiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is set to 50 to 90 [%]. Do.

Next, island-like semiconductor layers 5003 to 5006
Is formed to cover the gate insulating film 5007. The gate insulating film 5007 is formed by a plasma CVD method or a sputtering method.
It is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm]. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 [nm]. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicat
e) and O ₂ were mixed, the reaction pressure was 40 [Pa], and the substrate temperature was 30.
It can be formed by discharging at a high frequency (13.56 [MHz]) and a power density of 0.5 to 0.8 [W / cm ² ] at 0 to 400 [° C.]. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].

[0326] Then, a first conductive film 5008 and a second conductive film 5009 for forming a gate electrode are formed over the gate insulating film 5007. In this embodiment, the first conductive film 5008 is formed of Ta to a thickness of 50 to 100 [nm],
A second conductive film 5009 is formed with W to a thickness of 100 to 300 [nm].

The Ta film is formed by a sputtering method by sputtering a Ta target with Ar. in this case,
When an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film can be prevented from peeling. Also, α
The phase Ta film has a resistivity of about 20 [μΩcm] and can be used as a gate electrode, but the β-phase Ta film has a resistivity of about 180 [μΩcm] and is not suitable for a gate electrode. . In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to the Ta α-phase is formed on a Ta base with a thickness of about 10 to 50 [nm]. Can be easily obtained.

When a W film is formed, it is formed by a sputtering method using W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
[μΩcm] or less is desirable. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistance is increased. From this, in the case of the sputtering method, a W target having a purity of 99.9999 or 99.99 [%] is used, and a W film is formed with sufficient care so as not to mix impurities from the gas phase during film formation. By doing so, a resistivity of 9 to 20 [μΩcm] can be realized.

In this embodiment, the first conductive film 500
8 was Ta, and the second conductive film 5009 was W. However, there is no particular limitation, and any of Ta, W, Ti, Mo, Al, and Cu was used.
Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Another example of the combination other than the present embodiment is that the first conductive film is formed of tantalum nitride (T
aN), and the second conductive film is made of W,
Forming a first conductive film of tantalum nitride (TaN);
Preferably, the first conductive film is formed of tantalum nitride (TaN), and the second conductive film is formed of Cu.

Next, a mask 5010 made of a resist is formed, and a first etching process for forming electrodes and wirings is performed. In this embodiment, ICP (Inductively Coupled)
d Plasma: Inductively coupled plasma) etching method,
CF ₄ and Cl ₂ are mixed as an etching gas, and RF (13.56 [MH]) of 500 [W] is applied to the coil-type electrode at a pressure of 1 [Pa].
z]) Power is supplied to generate plasma. 100 [W] RF (13.56 [MH] also on the substrate side (sample stage)
z]) Apply power and apply a substantially negative self-bias voltage. When CF ₄ and Cl ₂ are mixed, the W film and Ta
The film is etched to the same extent.

[0331] Under the above-mentioned etching conditions, the shape of the resist mask is made appropriate, so that the edges of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. Become. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Since the selectivity of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 [nm] by over-etching. become. Thus, by the first etching process, the first conductive layer and the second conductive layer
Conductive layers 5011 to 5016 (first conductive layer 50
11a to 5016a and second conductive layers 5011b to 501
6b) is formed. At this time, in the gate insulating film 5007, a region which is not covered with the first shape conductive layers 5011 to 5016 is etched to a thickness of about 20 to 50 [nm] to form a thinned region. (FIG. 23 (A))

Then, a first doping process is performed to add an impurity element imparting N-type. (FIG. 23B) The doping method may be an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 ×
10 ^{13 to} 5 × 10 ¹⁴ [atoms / cm ² ] and acceleration voltage of 60
It is performed as 100 keV. An element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used as the impurity element imparting the N-type. Here, phosphorus (P) is used. In this case, the conductive layers 5011 to 5015 serve as a mask for the impurity element imparting N-type, and the first impurity regions 5017 to 5025 are formed in a self-aligned manner. First
1 × 10 ²⁰ to 1 ×
An impurity element imparting N-type is added in a concentration range of 10 ²¹ [atoms / cm ³ ].

Next, a second etching process is performed as shown in FIG. Similarly, using an ICP etching method, CF ₄ , Cl ₂ and O ₂ are mixed in an etching gas,
At a pressure of 1 [Pa], 500 [W] RF (1) is applied to the coil type electrode.
3.56 [MHz]) power is supplied to generate plasma. On the substrate side (sample stage), 50 [W] RF (13.
56 [MHz]), and a self-bias voltage lower than that in the first etching process is applied. Under such conditions, the W film is anisotropically etched, and Ta, which is the first conductive layer, is anisotropically etched at a lower etching rate to form the second shape conductive layers 5026 to 5031 (first Conductive layers 5026a to 5031a and second conductive layer 5026
b to 5031b). At this time, in the gate insulating film 5007, the second shape conductive layers 5026 to 5026-5
The area not covered by 031 is further etched by about 20 to 50 [nm] to form a thinned area.

The etching reaction of the W film or the Ta film by the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radicals or ionic species and the vapor pressure of the reaction product.
Comparing the vapor pressures of fluorides and chlorides of W and Ta, W
WF ₆ is extremely high and other WC
l ₅ , TaF ₅ and TaCl ₅ are comparable. Therefore, C
With the mixed gas of F ₄ and Cl ₂ , both the W film and the Ta film are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in Ta, the increase in the etching rate is relatively small even if F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ .
Since the oxide of Ta does not react with fluorine or chlorine,
The etching rate of the a film decreases. Therefore, the W film and Ta
It is possible to make a difference in the etching rate with the film, and it is possible to make the etching rate of the W film larger than that of the Ta film.

Then, as shown in FIG.
Perform doping processing. In this case, the first doping process
Lowering the dose than the
Doping with an impurity element for imparting a mold. For example,
Speed voltage is set to 70 to 120 [keV] and 1 × 10¹³[atoms / cm
^Two] At the dose amount of FIG.
A new impurity region is formed inside the formed first impurity region.
Form. Doping is performed in the second shape conductive layer 5026.
To 5030 as a mask for the impurity element,
The region under the second conductive layers 5026a to 5030a is also not
Doping is performed so that a pure element is added. Like this
The third conductive layer 5026a to 5030a.
Impurity regions 5032 to 5041 and a first impurity region
Second impurity region 5042 between the second impurity region and the third impurity region
To 5051. N-type impurity element
Is 1 × 10 2 in the second impurity region.¹⁷~ 1 × 10¹⁹[atoms
/cm^Three] In the third impurity region.
10¹⁶~ 1 × 10¹⁸[atoms / cm ^Three]
You.

Then, as shown in FIG. 24B, island-shaped semiconductor layers 5004 to 504 forming a P-channel TFT are formed.
In 06, fourth impurity regions 5052 to 5074 having a conductivity type opposite to the first conductivity type are formed. Second conductive layer 5027
Using b to 5030b as a mask for the impurity element, an impurity region is formed in a self-aligned manner. At this time, N
The entire surface of the island-shaped semiconductor layer 5003 and the wiring portion 5031 forming the channel type TFT is covered with a resist mask 5200. Phosphorus is added at a different concentration to each of the impurity regions 5052 to 5074, but diborane (B
₂ H ₆ ) and an impurity concentration of 2 × 10 ²⁰ to 2 × 10 ²¹ [a
toms / cm ³ ].

With the above steps, an impurity region is formed in each island-like semiconductor layer. Second overlapping with the island-shaped semiconductor layer
Conductive layers 5026 to 5030 function as gate electrodes. 5031 functions as an island-shaped source signal line.

[0338] In this way, FIG.
As shown in (C), a step of activating the impurity element added to each of the island-shaped semiconductor layers is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm.
The heat treatment is performed in a nitrogen atmosphere of not more than [ppm] at 400 to 700 [° C.], typically 500 to 600 [° C.] In this embodiment, the heat treatment is performed at 500 [° C.] for 4 hours. However, 50
When the wiring material used for 26 to 5031 is weak to heat,
Activation is preferably performed after an interlayer insulating film (mainly composed of silicon) is formed in order to protect wirings and the like.

Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-like semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, as shown in FIG.
Of the interlayer insulating film 5075 from the silicon oxynitride film to 100
It is formed with a thickness of about 200 [nm]. After a second interlayer insulating film 5076 made of an organic insulating material is formed thereon, a first interlayer insulating film 5075, a second interlayer insulating film 5076,
And a contact hole is formed in the gate insulating film 5007, and each wiring (including connection wiring and signal line) 5077 is formed.
After patterning and forming the patterns 5082 and 5084, the pixel electrode 5083 in contact with the connection wiring 5082 is formed by patterning.

As the second interlayer insulating film 5076, a film made of an organic resin is used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 5076 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, an acrylic film is formed with a thickness that can sufficiently flatten a step formed by a TFT. Preferably, it is 1 to 5 [μm] (more preferably, 2 to 4 [μm]).

The contact hole is formed by dry etching or wet etching to form N-type impurity regions 5017 and 5018 or P-type impurity regions 5052.
A contact hole reaching to 5074, a contact hole reaching the wiring 5031, a contact hole (not shown) reaching the current supply line, and a contact hole (not shown) reaching the gate electrode are formed.

The wiring (including the connection wiring and the signal line) 5
077 to 5082 and 5084, the Ti film is 100 [n
m], an aluminum film containing Ti is 300 [nm], and a Ti film 1
A laminate film having a three-layer structure in which 50 nm is continuously formed by a sputtering method and patterned into a desired shape is used. Of course,
Other conductive films may be used.

In the present embodiment, an ITO film having a thickness of 110 [nm] was formed as the pixel electrode 5083, and was patterned. A contact is made by arranging the pixel electrode 5083 so as to be in contact with and overlap with the connection wiring 5082. Alternatively, a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide may be used. This pixel electrode 5083 becomes an anode of the EL element. (FIG. 25
(A))

Next, as shown in FIG. 25B, an insulating film containing silicon (a silicon oxide film in this embodiment) is formed to a thickness of 500 [nm], and is formed at a position corresponding to the pixel electrode 5083. An opening is formed, and a third interlayer insulating film 5085 is formed. When the opening is formed, a tapered side wall can be easily formed by using a wet etching method. If the side wall of the opening is not sufficiently smooth, EL due to a step
Layer degradation becomes a significant problem.

Next, the EL layer 5086 and the cathode (MgA
g electrode) 5087 is continuously formed using a vacuum deposition method without opening to the atmosphere. Note that the thickness of the EL layer 5086 is 80
２００200 [nm] (typically 100-120 [nm]), and the thickness of the cathode 5087 is 180-300 [nm] (typically 20-200 [nm]).
0 to 250 [nm]).

In this step, an EL layer is sequentially formed for the pixel corresponding to red, the pixel corresponding to green, and the pixel corresponding to blue. However, since the EL layer has poor resistance to a solution, it must be formed individually for each color without using a photolithography technique. Therefore, a metal mask is used to hide portions other than the desired pixels, and only necessary portions are selectively removed.
Preferably, an L layer is formed.

That is, first, a mask for hiding all pixels other than the pixels corresponding to red is set, and an EL layer for emitting red light is selectively formed using the mask. Next, a mask for hiding all pixels other than pixels corresponding to green is set, and a green light-emitting EL layer is selectively formed using the mask. Next, a mask for covering all pixels other than the pixel corresponding to blue is similarly set, and an EL layer for emitting blue light is selectively formed using the mask. Note that all the masks are described herein as being different, but the same mask may be used again.

Next, a cathode 5087 is formed. Cathode 508
7 may be formed as a continuous film common to the EL layers of each color, or may be selectively formed for each color using a metal mask. Note that it is preferable to perform processing without breaking vacuum until an EL layer and a cathode are formed in all pixels.

Here, a method of forming three types of EL elements corresponding to RGB is used. However, a method of combining a white light emitting EL element and a color filter, a blue or blue-green light emitting EL element and a phosphor (fluorescent And a method in which an EL element corresponding to RGB is stacked on a cathode (a counter electrode) using a transparent electrode.

Note that a known material can be used for the EL layer 5086. As a known material, it is preferable to use an organic material in consideration of a driving voltage. For example, a four-layer structure including a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer may be used as the EL layer. In this embodiment, E
An example using a MgAg electrode as the cathode of the L element is shown,
Other known materials may be used.

Next, a protective electrode 5088 is formed to cover the EL layer and the cathode. As the protective electrode 5088, a conductive film mainly containing aluminum may be used. The protective electrode 5088 may be formed by a vacuum evaporation method using a mask different from that used when the EL layer and the cathode are formed. After the EL layer and the cathode are formed, they are preferably formed continuously without being released to the atmosphere.

Lastly, a passivation film 5089 made of a silicon nitride film is formed to a thickness of 300 [nm]. Although the protection electrode 5088 actually serves to protect the EL layer from moisture and the like, the reliability of the EL element can be further improved by forming the passivation film 5089.

Thus, an active matrix type self-luminous device having a structure as shown in FIG. 25B is completed. In addition,
In the manufacturing process of the active matrix type self-luminous device in this embodiment, due to the circuit configuration and process,
A source signal line is formed of Ta and W which are materials forming a gate electrode, and a gate signal line is formed of Al which is a wiring material forming source and drain electrodes. May be.

Incidentally, the active matrix substrate of this embodiment exhibits extremely high reliability and can improve the operating characteristics by arranging the TFT having the optimum structure not only in the pixel portion but also in the drive circuit portion. In the crystallization step, N
It is also possible to increase the crystallinity by adding a metal catalyst such as i. Thus, the driving frequency of the source signal line driving circuit can be increased to 10 MHz or more.

First, a TFT having a structure in which hot carrier injection is reduced so as not to reduce the operation speed as much as possible,
N-channel type TF of CMOS circuit forming drive circuit section
Used as T. In addition, as the drive circuit here,
It includes a shift register, a buffer, a level shifter, a latch in line-sequential driving, a transmission gate in point-sequential driving, and the like.

In the case of this embodiment, the active layer of the N-channel TFT is composed of a source region, a drain region, a GOLD region,
The GOLD region includes a DD region and a channel formation region, and overlaps with the gate electrode via a gate insulating film.

A P-channel type TFT of a CMOS circuit
Since there is almost no concern about deterioration due to hot carrier injection, it is not necessary to provide an LDD region. Needless to say, it is also possible to provide an LDD region similarly to the N-channel type TFT and take measures against hot carriers.

In addition, when a CMOS circuit in which a current flows bidirectionally in a channel formation region, that is, a CMOS circuit in which the roles of a source region and a drain region are switched is used in a driver circuit, an N-type CMOS circuit is formed. In the channel type TFT, it is preferable to form an LDD region on both sides of the channel formation region so as to sandwich the channel formation region. An example of such a transmission gate is a transmission gate used for dot-sequential driving. In the case where a CMOS circuit that requires an off-current value to be kept as low as possible is used in a driving circuit, a CMOS
The N-channel TFT forming a circuit preferably has a structure in which a part of an LDD region overlaps with a gate electrode through a gate insulating film. As such an example, a transmission gate used for dot-sequential driving is also mentioned.

When the structure shown in FIG. 25 (B) is actually completed, the protective film (laminate film, ultraviolet curable resin film, etc.) having high airtightness and low degassing or transparent film is provided so as not to be further exposed to the outside air. It is preferable to package (enclose) with an optical sealing material. At this time, the reliability of the EL element is improved by setting the inside of the sealing material to an inert atmosphere or disposing a hygroscopic material (for example, barium oxide) inside.

If the airtightness is improved by processing such as packaging, a connector (flexible printed circuit board: FPC) for connecting terminals routed from elements or circuits formed on the board to external signal terminals To complete the product. Such a state in which the product can be shipped is referred to as a self-luminous device in this specification.

According to the steps described in this embodiment, the number of photomasks required for manufacturing the active matrix substrate is five (the island-shaped semiconductor layer pattern, the first wiring pattern (the gate wiring, the island-shaped source wiring). , A capacitor wiring), a mask pattern of an n-channel region, a contact hole pattern, and a second wiring pattern (including a pixel electrode and a connection electrode). As a result, the process can be shortened, which can contribute to a reduction in manufacturing cost and an improvement in yield.

This embodiment can be implemented by freely combining with Embodiments 1 to 6.

(Embodiment 8) In the present invention, by using an EL material capable of utilizing phosphorescence from triplet excitons for light emission, external light emission quantum efficiency can be remarkably improved. As a result, the power consumption and the life of the EL element can be reduced,
And weight reduction becomes possible.

Here, a report is shown in which the triplet exciton is used to improve the external emission quantum efficiency. (T.Tsutsui, C.Adac
hi, S. Saito, Photochemical Processes in Organized
Molecular Systems, ed.K. Honda, (Elsevier Sci. Pub.,
Tokyo, 1991) p.437.)

The molecular formula of the EL material (coumarin dye) reported in the above article is shown below.

[0367]

Embedded image

(MABaldo, DFO'Brien, Y. You, A. Shou
stikov, S. Sibley, METhompson, SRForrest, Nature
395 (1998) p.151.)

The EL materials (P
The molecular formula of (t complex) is shown below.

[0370]

Embedded image

(MABaldo, S. Lamansky, PEBurrrows,
METhompson, SRForrest, Appl.Phys.Lett., 75 (199
9) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamu
ra, T.Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Ma
yaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.)

The EL materials (I
The molecular formula of (r complex) is shown below.

[0373]

Embedded image

As described above, if the phosphorescence emission from the triplet exciton can be used, the external emission quantum efficiency three to four times higher than the case of using the fluorescence emission from the singlet exciton can be realized in principle. .

[0375] The EL material which can use phosphorescence from triplet excitons for light emission used in the self-luminous device of the present invention is not limited to the above structure. Further, the EL material used for the self-luminous device of the present invention is not limited to an EL material capable of utilizing phosphorescence for light emission, and may be an EL material capable of utilizing fluorescence for light emission.

The structure of this embodiment can be implemented by freely combining with any of the structures of Embodiments 1 to 7.

(Embodiment 9) Since the self-luminous device is of a self-luminous type, it has better visibility in a bright place and a wider viewing angle than a liquid crystal display. Therefore, it can be used for display portions of various electronic devices.

As electronic equipment using the self-luminous device of the present invention, a video camera, digital camera, goggle type display (head mounted display), navigation system, sound reproducing device (car audio, audio component, etc.), notebook personal computer , Game devices, portable information terminals (mobile computers, mobile phones, portable game machines, electronic books, etc.), and image reproducing devices provided with recording media (specifically, DVD: Digital Versat)
(an apparatus provided with a display capable of reproducing a recording medium such as an ile disc) and displaying an image thereof. In particular, it is desirable to use a self-luminous device for a portable information terminal in which the screen is often viewed from an oblique direction, since the wide viewing angle is regarded as important. FIG. 26 shows specific examples of these electronic devices.
Shown in

[0379] FIG. 26A illustrates an EL display device, which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The self-luminous device of the present invention can be used for the display portion 2003. Since the self-luminous device is a self-luminous type, it does not require a backlight and can be a display portion thinner than a liquid crystal display. Note that the EL display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

FIG. 26B shows a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103,
An operation key 2104, an external connection port 2105, a shutter 2106, and the like are included. The light emitting device of the present invention is
02 can be used.

[0381] FIG. 26C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, and a display portion 2.
203, keyboard 2204, external connection port 220
5, including a pointing mouse 2206 and the like. The self-luminous device of the present invention can be used for the display portion 2203.

FIG. 26D shows a mobile computer, which includes a main body 2301, a display portion 2302, and a switch 230.
3, an operation key 2304, an infrared port 2305, and the like. The self light emitting device of the present invention can be used for the display portion 2302.

FIG. 26E shows a portable image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium, and includes a main body 2401, a housing 2402, a display portion A 2403, a display portion B 2404, a recording medium ( DVD, etc.) reading unit 240
5, operation keys 2406, a speaker unit 2407, and the like. The display portion A 2403 mainly displays image information, and the display portion B 2404 mainly displays character information. The light emitting device of the present invention employs these display portions A, B 2403, and 240.
4 can be used. Note that the image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 26 (F) shows a goggle type display (head mounted display).
1, including a display unit 2502 and an arm unit 2503. The self-luminous device of the present invention can be used for the display portion 2502.

[0385] FIG. 26G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, and an image receiving portion 260.
6, a battery 2607, a voice input unit 2608, operation keys 2609, and the like. The light emitting device of the present invention is
02 can be used.

[0386] Here, FIG. 26H illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, a voice input portion 2704, a voice output portion 2705, operation keys 2706,
An external connection port 2707, an antenna 2708, and the like are included.
The self-luminous device of the present invention can be used for the display portion 2703. Note that the display portion 2703 displays white characters on a black background, so that power consumption of the mobile phone can be suppressed.

If the emission luminance of the EL material becomes higher in the future, it becomes possible to enlarge and project the light containing the output image information with a lens or the like and use it for a front-type or rear-type projector.

[0388] Further, the above electronic equipment can be connected to the Internet or C
Information distributed through an electronic communication line such as an ATV (cable television) is often displayed, and in particular, opportunities to display moving image information are increasing. Since the response speed of the EL material is very high, the self-luminous device is preferable for displaying moving images.

In the self-luminous device, the light-emitting portion consumes power. Therefore, it is desirable to display information so that the light-emitting portion is reduced as much as possible. Therefore, portable information terminals,
In particular, when a self-light-emitting device is used for a display portion mainly including character information such as a mobile phone or a sound reproducing device, it is desirable to drive the non-light-emitting portion as a background so that character information is formed by a light-emitting portion.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be used for electronic devices in various fields. Further, the electronic apparatus of the present embodiment may use a self-luminous device having any of the configurations shown in Embodiments 1 to 8.

[0391]

According to the self-luminous device of the present invention, the lighting period and the non-lighting period are divided and appear alternately during one frame period. As a result, the human viewpoint moves slightly from side to side and up and down,
Even if only the non-lighted pixels are continuously stared at, or conversely, only the lighted pixels are continuously stared, the length of the continuous lighting period or non-lighting period is the conventional simple length. Since it is shorter than the drive by the binary code method, it is possible to prevent the false contour from being recognized.

Also, in the self-luminous device of the present invention shown in the first embodiment, a digital video signal is stored in a memory provided in a pixel. Still images can be displayed continuously without inputting digital video signals. That is, when a still image is displayed, it is possible to stop the source signal line driving circuit after performing a signal processing operation for at least one frame, thereby greatly reducing power consumption. Becomes

In the self-luminous device of the present invention shown in Embodiment Mode 2, the potentials of the high-voltage power supply line and the low-voltage power supply line are constant during periods other than the pixel and memory writing periods. Therefore, the memory provided in the pixel is SR
To function as an AM, when a digital video signal is stored in the memory, the stored digital video signal is held until the digital video signal is input to the memory again. Therefore, in the case of a still image, once writing is performed, the still image can be displayed continuously without inputting a digital video signal for each frame. That is, when a still image is displayed, it is possible to stop the source signal line driving circuit after performing a signal processing operation for at least one frame, thereby greatly reducing power consumption. Becomes

According to the above configuration, it is possible to prevent a display disturbance such as a false contour, which is remarkable in time division driving by the binary code method, from being visually recognized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a pixel portion of a self-luminous device using a driving method of the present invention and a ratio of the length of a display period to the length of a divided display period.

FIG. 2 is a diagram showing a pixel portion of a self-luminous device using the driving method of the present invention and a ratio of the length of a lighting period to the length of a non-lighting period.

FIG. 3 is a top block diagram of the self-luminous device of the present invention.

FIG. 4 illustrates a pixel portion of the self-luminous device of the present invention.

FIG. 5 is a pixel circuit diagram of the self-luminous device of the present invention.

FIG. 6 is a circuit diagram of a memory.

FIG. 7 is a diagram showing a method for driving a self-luminous device of the present invention.

FIG. 8 is a diagram showing a connection configuration of pixels during driving.

FIG. 9 is a diagram showing a method for driving a self-luminous device of the present invention.

FIG. 10 illustrates a pixel portion of a self-luminous device of the present invention.

FIG. 11 is a pixel circuit diagram of a self-luminous device of the present invention.

FIG. 12 is a circuit diagram of a memory.

FIG. 13 is a diagram showing a driving method of the self-luminous device of the present invention.

FIG. 14 is a diagram showing a connection configuration of pixels during driving.

FIG. 15 is a diagram showing a driving method of the self-luminous device of the present invention.

FIG. 16 is a pixel circuit diagram of a self-luminous device of the present invention.

FIG. 17 is a circuit diagram of a memory.

FIG. 18 is a pixel circuit diagram of a self-luminous device of the present invention.

FIG. 19 is a pixel circuit diagram of a self-luminous device of the present invention.

FIG. 20 is a circuit diagram of a memory.

FIG. 21 is a pixel circuit diagram of a self-luminous device of the present invention.

FIG. 22 is a block diagram of a driving circuit of a self-luminous device of the present invention.

FIG. 23 illustrates a method for manufacturing a TFT.

FIG. 24 illustrates a method for manufacturing a TFT.

FIG. 25 illustrates a method for manufacturing a TFT.

FIG. 26 is a diagram of an electronic device using the self-luminous device of the present invention.

FIG. 27 is a diagram illustrating a pixel portion of a self-luminous device using a conventional driving method, and a ratio between the length of a display period and the length of a divided display period.

FIG. 28 is a diagram illustrating a pixel portion of a self-luminous device using a conventional driving method, and a ratio of a lighting period to a non-lighting period.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 641 G09G 3/20 641E 641R H05B 33/08 H05B 33/08 33/14 33/14 A F Terms (Reference) 3K007 AB00 AB03 AB04 AB05 BA06 BB06 CA01 CB01 DA00 DB03 EB00 FA01 5C080 AA06 BB05 DD04 DD05 EE19 EE29 FF11 JJ03 JJ04 JJ06 5C094 AA01 AA07 AA22 AA53 AA56 BA03 BA09 BA27 EA01 DB01 DA07 FB20 GA10

Claims (16)

[Claims] An EL element, a memory, and a first TFT
And a self-luminous device having a plurality of pixels provided with a second TFT and a third TFT, wherein a source region and a drain region of the first TFT are
One receives a digital video signal, and the other receives the third video signal.
And a source electrode and a drain region of the second TFT.
One is connected to the memory and the other is the third
A source region of the third TFT is connected to a first power supply, and a drain region of the third TFT is connected to the EL element. 2. The memory according to claim 1, wherein the memory includes three n-channel TFTs and three p-channel TFTs.
A self-luminous device comprising a channel type TFT. 3. The method according to claim 2, wherein a gate electrode of any one of the three n-channel TFTs is connected to a gate electrode of the first TFT. The self-luminous device, wherein the one gate electrode is connected to a gate electrode of the second TFT included in a different pixel. 4. The memory according to claim 2, wherein the memory has two sets of an n-channel TFT and a p-channel TFT whose gate electrodes are connected to each other. The channel type TFT is
The drain region is connected to each other, and the two sets of the n-channel TFT and the p-channel TFT have a gate electrode connected to another pair of drain regions, and the n-channel TFT and the p-channel TFT Of the two sets of TFTs, one of the pair of drain regions is the second TFT.
A self-luminous device connected to a source region or a drain region of the FT. 5. An EL device, an SRAM, and a first TFT.
And a self-luminous device having a plurality of pixels provided with a second TFT and a third TFT, wherein a source region and a drain region of the first TFT are
One receives a digital video signal, and the other receives the third video signal.
And a source electrode and a drain region of the second TFT.
One is connected to the SRAM and the other is connected to the third
A source region of the third TFT is connected to a first power supply, and a drain region of the third TFT is connected to the EL element. 6. The SRAM according to claim 5, wherein the SRAM has two n-channel TFTs and two p-channel TFTs.
A self-luminous device comprising a channel type TFT. 7. The SRAM according to claim 6, wherein the SRAM has two sets of an n-channel TFT and a p-channel TFT whose gate electrodes are connected to each other. ,
The drain region is connected to each other, and the two sets of the n-channel TFT and the p-channel TFT have a gate electrode connected to another pair of drain regions, and the n-channel TFT and the p-channel TFT Of the two sets of TFTs, one of the pair of drain regions is the second TFT.
A self-luminous device connected to the source region or the drain region of the FT. 8. An EL element, a memory, and a first TFT
And a driving method of a self-luminous device having a plurality of pixels provided with a second TFT and a third TFT, wherein a p-bit is connected to a gate electrode of the third TFT via the first TFT. The digital signal of the p-th bit is input to the memory via the first TFT and the second TFT, and the digital signal of the p-th bit is written to the memory via the first TFT. A period in which the q-th digital signal is input to the gate electrode of the third TFT and the p-th digital signal written in the memory is held, and the p-th digital signal held in the memory is held. A period during which a digital signal is read out and inputted to the gate electrode of the third TFT, wherein the p-th digital signal and the q-bit digital signal cause the third T A method of driving a self-luminous device, wherein light emission of the EL element is controlled by controlling FT switching. 9. An EL element, a memory, and a first TFT
And a driving method of a self-luminous device having a plurality of pixels provided with a second TFT and a third TFT, wherein input of a digital video signal to the pixel is controlled by the first TFT. Some of the bits of the digital video signal input to the pixel are controlled to be written to and read from the memory by the second TFT, and are read from the memory. The switching of the third TFT is controlled by a digital video signal of some bits or the digital video signal input to the pixel, and the light emission of the EL element is controlled by the third TFT. A method for driving a self-luminous device. 10. A method for driving a self-luminous device having a plurality of pixels provided with an EL element and a memory, wherein a plurality of sub-frame periods are provided in one frame period. At least one of the plurality of divided subframe periods includes at least one of the plurality of divided subframe periods.
A digital video signal is written in the memory, and the digital video signal is read from the memory in a divided subframe period that appears after the divided subframe period in which the digital video signal is written in the memory. A driving method of the self-luminous device, wherein light emission of the EL element is controlled by a digital video signal input to the pixel or the read digital video signal. 11. The memory according to claim 8, wherein the memory includes three n-channel TFTs and three p-channel TFTs.
A method for driving a self-luminous device, comprising: a channel type TFT. 12. An EL device, an SRAM, and a first TFT.
And a driving method of a self-luminous device having a plurality of pixels provided with a second TFT and a third TFT, wherein a p-bit is connected to a gate electrode of the third TFT via the first TFT. A digital signal of the eye is input to the SRAM through the first TFT and the second TFT.
A period during which the p-th digital signal is written, a q-th digital signal is input to the gate electrode of the third TFT via the first TFT, and
A period during which the p-th digital signal written in the RAM is held, and a period during which the p-th digital signal held in the SRAM is read and input to the gate electrode of the third TFT The switching of the third TFT is controlled by the p-th digital signal and the q-th digital signal, whereby light emission of the EL element is controlled. Driving method of the self-luminous device. 13. An EL element, an SRAM, and a first TFT.
And a driving method of a self-luminous device having a plurality of pixels provided with a second TFT and a third TFT, wherein input of a digital video signal to the pixel is controlled by the first TFT. In the digital video signal input to the pixel, a part of the bits are transferred to the SRAM by the second TFT.
And reading from the SRAM is controlled, and switching of the third TFT is performed by a digital video signal of some bits read from the SRAM or a digital video signal input to the pixel. Is controlled, and the light emission of the EL element is controlled by the third TFT. 14. A method for driving a self-luminous device having a plurality of pixels provided with an EL element and an SRAM, wherein a plurality of sub-frame periods are provided in one frame period, and the plurality of sub-frame periods are provided. At least one of the plurality of divided subframe periods includes at least one of the plurality of divided subframe periods.
In one embodiment, a digital video signal is written in the SRAM, and the digital video signal is read from the SRAM in a divided subframe period that appears after the divided subframe period in which the digital video signal is written in the SRAM. A driving method of the self-luminous device, wherein light emission of the EL element is controlled by a digital video signal input to the pixel or the read digital video signal. 15. The method according to claim 12, wherein:
In the paragraph, the SRAM includes two n-channel TFTs and two p-channel TFTs.
A method for driving a self-luminous device, comprising: a channel type TFT. 16. A driving method of a self-luminous device according to claim 8, wherein said plurality of divided sub-frame periods do not appear continuously.