JP2002198461A - Plastic package and its manufacturing method - Google Patents
Plastic package and its manufacturing methodInfo
- Publication number
- JP2002198461A JP2002198461A JP2000398117A JP2000398117A JP2002198461A JP 2002198461 A JP2002198461 A JP 2002198461A JP 2000398117 A JP2000398117 A JP 2000398117A JP 2000398117 A JP2000398117 A JP 2000398117A JP 2002198461 A JP2002198461 A JP 2002198461A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- copper foil
- plastic package
- copper
- core substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004033 plastic Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 123
- 238000007747 plating Methods 0.000 claims abstract description 83
- 229910052802 copper Inorganic materials 0.000 claims abstract description 67
- 239000010949 copper Substances 0.000 claims abstract description 67
- 239000011889 copper foil Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 229910000679 solder Inorganic materials 0.000 claims abstract description 22
- 239000004020 conductor Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 238000004080 punching Methods 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 4
- 239000002585 base Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 description 2
- 239000001569 carbon dioxide Substances 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- -1 and the like Chemical compound 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 229960003280 cupric chloride Drugs 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- XPPKVPWEQAFLFU-UHFFFAOYSA-N diphosphoric acid Chemical compound OP(O)(=O)OP(O)(O)=O XPPKVPWEQAFLFU-UHFFFAOYSA-N 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229940005657 pyrophosphoric acid Drugs 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、コア基板の一面側
に外部接続端子パッドを有するプラスチックパッケージ
及びその製造方法に係り、より詳細には、コア基板の貫
通孔を銅めっきで閉塞し、ビアホール直下に半田ボール
接続用の外部接続端子パッドを有するプラスチックパッ
ケージ及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plastic package having an external connection terminal pad on one side of a core substrate and a method for manufacturing the same, and more particularly, to a via hole formed by closing a through hole of a core substrate with copper plating. The present invention relates to a plastic package having an external connection terminal pad for connecting a solder ball directly below, and a method of manufacturing the same.
【0002】[0002]
【従来の技術】近年の半導体素子の高性能化、小型化に
ともない、半導体素子を搭載するためのプラスチックパ
ッケージには、外部接続端子の多端子化、半導体素子の
実装性、低コスト化、放熱特性、低インピーダンス化等
の観点から、ボールグリッドアレイ型のプラスチックパ
ッケージが多く用いられている。このボールグリッドア
レイ型のプラスチックパッケージの半田ボール接続用の
外部接続端子パッドの形成場所はビアホール導体と接続
させて、ビアホールから離れたところに形成されていた
が、この状態では、半導体素子の高密度化に伴うパッケ
ージ寸法の大型化を抑えることができないので、ビアホ
ールの上に直接外部接続端子パッドを形成する方法が進
められている。2. Description of the Related Art In recent years, as semiconductor devices have become higher in performance and smaller in size, plastic packages for mounting semiconductor devices have increased the number of external connection terminals, mountability of semiconductor devices, lower cost, and heat dissipation. From the viewpoints of characteristics, low impedance, and the like, ball grid array type plastic packages are often used. In the ball grid array type plastic package, the external connection terminal pads for connecting the solder balls were formed at positions away from the via holes by connecting to the via hole conductors. Since it is not possible to suppress an increase in package size due to the development, a method of forming an external connection terminal pad directly on a via hole has been promoted.
【0003】このビアホール上の外部接続端子パッドの
形成には、従来の貫通型のビアホールの内部を樹脂、導
電性ペースト又はめっき等で充填する方法が採用されて
いる。具体的には、ビアホールに樹脂で孔埋めを行い、
樹脂の表面に無電解銅めっき及び電解銅めっきを形成す
る、ビアホールに導電性ペーストで孔埋めを行い、直接
電解銅めっきを形成する、ビアホールに特殊な添加剤又
はパルス波形の電源を用いて直接めっきによって孔埋め
する、ビアホールの中に柱状にめっきを成長させるビア
ポスト法で形成する等の方法がある。しかしながら、ビ
アホールの中に充填物を埋め込んで形成する場合には、
充填後にビアホールの開口部を平坦に研磨する必要があ
り、工程の増加とコストアップの要因となっている。ま
た、ビアホール径が小さく、プラスチックパッケージの
厚みが薄くなると研磨が非常に難しくなり、厚みが0.
15以下になると平坦に研磨することが不可能に近くな
る。そこで、微小なビアホールや厚みの薄いプラスチッ
クパッケージの場合には、従来の貫通型のビアホールの
一方の開口部を塞いだ形のブラインドビアとするのが有
効な方法として採用されている。In forming the external connection terminal pads on the via holes, a conventional method of filling the inside of the through-type via holes with resin, conductive paste, plating or the like has been adopted. Specifically, filling the via holes with resin,
Form electroless copper plating and electrolytic copper plating on the surface of the resin, fill the via holes with a conductive paste and form electrolytic copper plating directly, directly use special additives or pulse waveform power supply in the via holes There is a method of filling the hole by plating, a method of forming a plating in a via hole in a via hole by a via post method, and the like. However, when the filling is formed by burying the filler in the via hole,
After filling, the opening of the via hole needs to be polished flat, which causes an increase in steps and cost. Also, if the via hole diameter is small and the thickness of the plastic package is small, polishing becomes very difficult, and the thickness is less than 0.1 mm.
When it is less than 15, it becomes almost impossible to polish flat. Therefore, in the case of a small via hole or a thin plastic package, a blind via in which one opening of a conventional through-type via hole is closed is adopted as an effective method.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、前述し
たような従来のプラスチックパッケージ及びその製造方
法では、未だ解決すべき次のような問題があった。 (1)ビアホールの開口部の一方側が塞がれたブライン
ドビアは、銅めっきを施す時にめっき液のビアホールの
底部への供給がされにくく、ビアホール内のめっき厚み
が薄くなったり、ビアホール内に気泡が溜まってめっき
が形成されない場合が発生する。 (2)ビアホールのアスペスト比(長さ/径)が大きく
(1.0以上)なると、ビアホール内のめっき液の流れ
が極端に悪くなり、めっき厚みが薄くなったり、めっき
の形成されないところが発生し、安定してブラインドビ
ア内に銅めっきが形成できない。 本発明は、このような事情に鑑みてなされたものであっ
て、ビアホールの底部となる銅箔にめっき液の循環を可
能とする孔を穿設しておき、ビアホール内に銅めっきを
安定して形成させると同時に形成する銅で孔を閉塞して
外部接続端子パッド部を形成するプラスチックパッケー
ジ及びその製造方法を提供することを目的とする。However, the conventional plastic package and the method for manufacturing the same as described above have the following problems to be solved. (1) In a blind via in which one side of the opening of the via hole is closed, it is difficult for the plating solution to be supplied to the bottom of the via hole when copper plating is performed, so that the plating thickness in the via hole is reduced or bubbles are generated in the via hole. Accumulate and no plating is formed. (2) When the aspect ratio (length / diameter) of the via hole becomes large (1.0 or more), the flow of the plating solution in the via hole becomes extremely poor, and the plating thickness becomes thin or the plating is not formed. The copper plating cannot be stably formed in the blind via. The present invention has been made in view of such circumstances, and a hole that allows circulation of a plating solution is formed in a copper foil serving as a bottom portion of a via hole to stabilize copper plating in the via hole. It is an object of the present invention to provide a plastic package in which an external connection terminal pad portion is formed by closing a hole with copper formed at the same time as forming the same and a method of manufacturing the same.
【0005】[0005]
【課題を解決するための手段】前記目的に沿う本発明に
係るプラスチックパッケージは、絶縁性基材の両面に回
路基板となる銅箔を貼ったコア基板の一方側の面に半田
ボール接続用の外部接続端子パッドを備えるボールグリ
ッドアレイ型のプラスチックパッケージにおいて、外部
接続端子パッドは、コア基板に設けられたビアホールの
一方側の面の銅箔に形成された小孔を銅めっきで閉塞し
てなる部分を含んでいる。これにより、小孔からめっき
液を流入させてビアホール内に銅めっきを安定して形成
させ、同時に銅めっきでビアホール底部の銅箔部の小孔
を閉塞させて、外部接続端子パッド部を有するプラスチ
ックパッケージを提供することができる。ここで、ビア
ホールの一方側の銅箔に形成された小孔の孔径は、他方
側の面の銅箔及び絶縁性基材に貫通形成された抜き孔の
径よりも小さいのが好ましい。これにより、形成された
銅めっき厚み分で銅箔の小孔を閉塞させ、確実に非貫通
孔からなるビアホールを有するプラスチックパッケージ
を提供できる。According to the present invention, there is provided a plastic package according to the present invention, comprising a core substrate having a circuit board on both sides of an insulative base material and a solder ball connecting surface on one side. In a ball grid array type plastic package having external connection terminal pads, the external connection terminal pads are formed by closing small holes formed in copper foil on one side of via holes provided in a core substrate with copper plating. Includes parts. This allows the plating solution to flow in from the small hole to stably form copper plating in the via hole, and at the same time, close the small hole in the copper foil portion at the bottom of the via hole by copper plating to form a plastic having an external connection terminal pad portion. Package can be provided. Here, the hole diameter of the small hole formed in the copper foil on one side of the via hole is preferably smaller than the diameter of the hole formed through the copper foil and the insulating base material on the other side. Thereby, the small hole of the copper foil is closed by the formed copper plating thickness, and the plastic package having the via hole formed of the non-through hole can be surely provided.
【0006】前記目的に沿う本発明に係るプラスチック
パッケージの製造方法は、絶縁性基材の両面に銅箔を貼
ったコア基板の一方側の面に半田ボール接続用の外部接
続端子パッドを備えるボールグリッドアレイ型のプラス
チックパッケージの製造方法において、コア基板の他方
側の銅箔面より穿設し、絶縁性基材を貫通する抜き孔を
形成し、コア基板の一方側の面に設けられている銅箔を
堰部とし、しかも堰部の実質的中央部分を小孔とする貫
通孔を形成する工程と、コア基板の両面側に設けられて
いる銅箔の表面及び貫通孔に銅めっきを施して導体層を
形成すると共に、小孔を閉塞して非貫通孔からなるビア
ホールを形成する工程と、コア基板の一方側及び他方側
に施された導体層に所定のエッチング処理を行って導体
配線パターンを形成する工程と、ビアホール位置に対応
して一方側の導体配線パターンに形成される外部接続端
子パッドを除いて一方側及び他方側の所定部分にソルダ
ーレジスト膜を形成する工程とを有する。これにより、
めっき液の流れをよくして貫通孔の内壁に銅めっきを安
定して形成させることができ、同時に銅めっきでビアホ
ール底部の銅箔部の小孔を閉塞することができるので、
銅厚の均一なブラインドビアを形成できる。また、小孔
を有する貫通孔に銅めっきを行うので、小孔からめっき
液が流入してめっき液の流れがよく、アスペスト比に関
係なく貫通孔の壁面に一定の厚みの銅めっきを施すこと
ができる。ここで、小孔の孔径は貫通孔に施す銅めっき
厚みの2倍以下であるのがよい。これにより、析出する
銅でビアホール底部の銅箔部の小孔を確実に閉塞でき、
銅箔部に外部接続端子パッドを形成できる。A method of manufacturing a plastic package according to the present invention, which meets the above object, is directed to a ball provided with external connection terminal pads for solder ball connection on one surface of a core substrate having copper foil adhered to both surfaces of an insulating substrate. In the method of manufacturing a grid array type plastic package, a punched hole is formed from the copper foil surface on the other side of the core substrate to penetrate the insulating base material, and is provided on one surface of the core substrate. A step of forming a through hole having a copper foil as a weir and a small hole substantially in the center of the weir, and applying copper plating to the surface and the through hole of the copper foil provided on both sides of the core substrate. Forming a via layer comprising a non-through hole by closing a small hole, and performing a predetermined etching process on the conductive layer provided on one side and the other side of the core substrate to form a conductive layer. Shape pattern And a step, and forming a solder resist film on a predetermined portion of the corresponding to the via hole position on the other hand, except the external connection terminal pads formed on the conductor wiring pattern on the side one side and the other side of. This allows
Since the flow of the plating solution can be improved and copper plating can be stably formed on the inner wall of the through hole, and at the same time, the small hole in the copper foil portion at the bottom of the via hole can be closed by copper plating,
A blind via with a uniform copper thickness can be formed. In addition, since copper plating is performed on through holes having small holes, the plating solution flows from the small holes and the flow of the plating solution is good, and copper plating of a constant thickness is applied to the wall surfaces of the through holes regardless of the aspect ratio. Can be. Here, the diameter of the small hole is preferably not more than twice the thickness of the copper plating applied to the through hole. Thereby, the small hole of the copper foil part at the bottom of the via hole can be reliably closed with the precipitated copper,
External connection terminal pads can be formed on the copper foil portion.
【0007】[0007]
【発明の実施の形態】続いて、添付した図面を参照し
て、本発明を具体化した実施の形態につき説明し、本発
明の理解に供する。ここに、図1は本発明の一実施の形
態に係るプラスチックパッケージの部分拡大側断面図、
図2は同プラスチックパッケージのコア基板の貫通孔の
説明図、図3(A)〜(E)は本発明の一実施の形態に
係るプラスチックパッケージの製造方法を説明する部分
拡大側断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, with reference to the accompanying drawings, embodiments of the present invention will be described for the understanding of the present invention. Here, FIG. 1 is a partially enlarged side sectional view of a plastic package according to an embodiment of the present invention,
FIG. 2 is an explanatory view of a through hole of a core substrate of the plastic package, and FIGS. 3A to 3E are partially enlarged side sectional views illustrating a method of manufacturing a plastic package according to an embodiment of the present invention. .
【0008】図1に示すように、本発明の一実施の形態
に係るプラスチックパッケージ10はボールグリッドア
レイ型であって、絶縁性基材の一例であるプラスチック
基材11の両面それぞれに回路基板となる銅箔12、1
2aを貼り付けたコア基板13の一方側の面に、ソルダ
ーレジスト膜14の開口部から露出した半田ボール15
接続用の外部接続端子パッド16を備えている。そし
て、この外部接続端子パッド16は、コア基板13に設
けられたビアホール17の一方側の面の銅箔12aに形
成された小孔21aを無電解銅めっきと電解銅めっきか
らなる銅めっき18で閉塞してなる部分を含んでいる。
また、外部接続端子パッド16の銅めっき18上には、
銅めっき18の酸化を防止するため、及び半田ボール1
5の接着性をよくするために、ニッケルめっき及び金め
っきからなるカバーめっき19が施されている。なお、
外部接続端子パッド16が形成される面とは反対側の面
にも、ソルダーレジスト膜14の開口部から露出し、半
導体素子とボンディングワイヤで接続されるワイヤボン
ドパッド20等が形成されており、この部分にもニッケ
ルめっき及び金めっきからなるカバーめっき19が施さ
れている。As shown in FIG. 1, a plastic package 10 according to an embodiment of the present invention is of a ball grid array type, and has a circuit board and a plastic substrate 11 on both sides of a plastic substrate 11 which is an example of an insulating substrate. Copper foil 12, 1
The solder ball 15 exposed from the opening of the solder resist film 14 is formed on one surface of the core substrate 13 to which
An external connection terminal pad 16 for connection is provided. The external connection terminal pads 16 are formed by forming small holes 21a formed in the copper foil 12a on one side of the via holes 17 provided in the core substrate 13 with copper plating 18 made of electroless copper plating and electrolytic copper plating. Includes closed sections.
Also, on the copper plating 18 of the external connection terminal pad 16,
In order to prevent oxidation of the copper plating 18 and the solder ball 1
In order to improve the adhesiveness of No. 5, cover plating 19 made of nickel plating and gold plating is applied. In addition,
On the surface opposite to the surface on which the external connection terminal pads 16 are formed, wire bond pads 20 and the like which are exposed from the opening of the solder resist film 14 and are connected to the semiconductor element by bonding wires are formed. This portion is also provided with a cover plating 19 made of nickel plating and gold plating.
【0009】図2に示すように、コア基板13の銅箔1
2aに形成される小孔21aの孔径Aは、コア基板13
の銅箔12に形成された抜き孔21b、及びプラスチッ
ク基材11に形成された抜き孔21cの孔径Bよりも小
さい。これにより、銅めっき液は小孔21a、抜き孔2
1b、21cからなる貫通孔21を通してよく流動する
ので、貫通孔21の内側面に銅がよく析出して銅めっき
18が形成され、しかも、銅箔12aの小孔21aは銅
めっき18により閉塞される。[0009] As shown in FIG.
The hole diameter A of the small hole 21a formed in the core substrate 13a
The hole diameter B of the hole 21b formed in the copper foil 12 and the hole B of the hole 21c formed in the plastic substrate 11 are smaller than the hole diameter B. As a result, the copper plating solution is supplied to the small hole 21a and the hole 2
1b and 21c, the copper flows well through the through-hole 21 formed by the through-hole 21 and copper is deposited on the inner surface of the through-hole 21 to form the copper plating 18, and the small holes 21a of the copper foil 12a are closed by the copper plating 18. You.
【0010】次いで、図3を参照して、本発明の一実施
の形態に係るプラスチックパッケージの製造方法を説明
する。先ず、図3(A)に示すように、1層又は多層の
高耐熱性のBT樹脂(ビスマイレイミドトリアジンを主
成分にした樹脂)やポリイミド樹脂等からなるプラスチ
ック基材11の両面に、銅箔12、12aを接合してコ
ア基板13を形成する。コア基板13に貼り付けられる
銅箔12、12aの厚みは、通常10〜70μmであ
り、銅の純度は、99.8%以上のものを使用してい
る。Next, a method of manufacturing a plastic package according to an embodiment of the present invention will be described with reference to FIG. First, as shown in FIG. 3 (A), one side or multiple layers of a high heat-resistant BT resin (resin containing bismaileimide triazine as a main component), a polyimide resin, or the like is coated on both surfaces of a plastic substrate 11 with copper. The core substrates 13 are formed by joining the foils 12 and 12a. The thickness of the copper foils 12 and 12a to be attached to the core substrate 13 is usually 10 to 70 μm, and the purity of copper is 99.8% or more.
【0011】図3(B)に示すように、コア基板13の
他方側の面の銅箔12の表面を薄く(約5μm程度)エ
ッチングしてレーザー照射時の反射を抑えてレーザーの
吸収を良好にしてから炭酸ガスレーザーを用いてコア基
板13の他方側の面から、例えば、18μsecを1回
と10μsecを4回のサイクルショットを行うことで
コア基板13に貫通孔21を穿設する。すなわち、コア
基板13の他方側の銅箔12に抜き孔21bをあけ、プ
ラスチック基材11を貫通する抜き孔21cを形成し、
コア基板13の一方側の面の銅箔12aを堰部22と
し、この堰部22の実質的中心部に抜き孔21b、21
cより小径の小孔21aを形成する。炭酸ガスレーザー
のレーザー強度の調整、両面の銅箔12、12aのそれ
ぞれの厚み、及び銅箔12aの表面状態によって、小孔
21aの孔径を任意の大きさに調整させて穿孔すること
ができる。As shown in FIG. 3 (B), the surface of the copper foil 12 on the other side of the core substrate 13 is etched thinly (about 5 μm) to suppress reflection during laser irradiation and improve laser absorption. Then, the through hole 21 is formed in the core substrate 13 by performing a cycle shot of, for example, once at 18 μsec and four times at 10 μsec from the other surface of the core substrate 13 using a carbon dioxide laser. That is, a hole 21 b is made in the copper foil 12 on the other side of the core substrate 13, and a hole 21 c penetrating the plastic substrate 11 is formed.
The copper foil 12a on one surface of the core substrate 13 is used as a weir 22, and holes 21b and 21 are formed at substantially the center of the weir 22.
A small hole 21a smaller than c is formed. Depending on the adjustment of the laser intensity of the carbon dioxide gas laser, the respective thicknesses of the copper foils 12 and 12a on both sides, and the surface condition of the copper foil 12a, the hole diameter of the small holes 21a can be adjusted to an arbitrary size and the holes can be formed.
【0012】図3(C)に示すように、小孔21a、抜
き孔21b、21cからなる貫通孔21が穿設されたコ
ア基板13にパラジウム等の触媒を付与後、ホルマリン
を還元剤とする強アルカリ浴中で無電解銅めっきを施
す。これにより、貫通孔21の内側面に形成された無電
解銅めっきの導体膜を介してコア基板13の両面表層が
電気的に導通状態となる。次いで、無電解銅めっきが施
されたコア基板13を、例えば、硫酸銅、ピロリン酸等
からなるめっき浴中に陰極側の被めっき物として配置
し、陽極側に銅板を配設し、電圧を印加することで、コ
ア基板13の無電解銅めっきが施されている表層及び貫
通孔21に金属銅を析出させ、電解銅めっきの被膜を形
成する。銅箔12、12aの表面上及び貫通孔21の壁
面上に無電解銅めっき及び電解銅めっきからなる銅めっ
き18を施して導体層を形成する。この銅めっき18に
よって、小孔21aが閉塞されて非貫通孔からなるビア
ホール17が形成される。As shown in FIG. 3 (C), after a catalyst such as palladium is applied to the core substrate 13 having the through-holes 21 formed of the small holes 21a, the holes 21b and 21c, formalin is used as a reducing agent. Perform electroless copper plating in a strong alkaline bath. As a result, both surface layers of the core substrate 13 are brought into an electrically conductive state via the electroless copper-plated conductor film formed on the inner side surface of the through hole 21. Next, the core substrate 13 on which the electroless copper plating has been performed is disposed as a plating object on the cathode side in a plating bath made of, for example, copper sulfate, pyrophosphoric acid, and the like, and a copper plate is disposed on the anode side, and a voltage is applied. By applying the voltage, metal copper is deposited on the surface layer of the core substrate 13 on which the electroless copper plating is performed and the through-holes 21 to form a film of the electrolytic copper plating. Copper plating 18 made of electroless copper plating and electrolytic copper plating is applied on the surfaces of the copper foils 12 and 12a and the wall surfaces of the through holes 21 to form conductor layers. The small holes 21a are closed by the copper plating 18 to form the via holes 17 formed of non-through holes.
【0013】図3(D)に示すように、コア基板13表
面の銅めっき18の上の両全面に形成されたフォトレジ
スト膜に導体配線パターン形成のためのパターンマスク
を合わせ、紫外線露光を行い、現像を行って、導体配線
パターン以外の部分のフォトレジスト膜を削除すること
で、エッチングレジストマスクを形成し、塩化第二鉄溶
液、塩化第二銅溶液、アルカリエッチャント、過酸化水
素−硫酸系エッチャント等のエッチング液を噴射して、
エッチングレジストマスクで覆われていない部分の銅め
っき(無電解銅めっき及び電解銅めっき)18及び銅箔
12、12aをエッチングする。エッチングを行った
後、導体配線パターンを覆っているエッチングレジスト
マスクの表面に剥離液をスプレーで噴射し、フォトレジ
ストを膨潤させながら洗い流すことで、剥離、除去して
導体配線パターン23を形成する。As shown in FIG. 3D, a pattern mask for forming a conductor wiring pattern is aligned with a photoresist film formed on both surfaces of the copper plating 18 on the surface of the core substrate 13, and ultraviolet light exposure is performed. Developing and removing the photoresist film in portions other than the conductor wiring pattern to form an etching resist mask, a ferric chloride solution, a cupric chloride solution, an alkali etchant, a hydrogen peroxide-sulfuric acid system By spraying etchant such as etchant,
The copper plating (electroless copper plating and electrolytic copper plating) 18 and the copper foils 12 and 12a which are not covered with the etching resist mask are etched. After the etching, a stripping solution is sprayed onto the surface of the etching resist mask covering the conductor wiring pattern, and the photoresist is swollen while swelling, thereby peeling and removing to form a conductor wiring pattern 23.
【0014】図3(E)に示すように、導体配線パター
ン23の形成されたコア基板13の両面側に、例えば、
半田ボール接続用の外部接続端子パッド16や、半導体
素子とボンディングワイヤで接続するのに使用するワイ
ヤボンドパッド等が開口部から露出するようにソルダー
レジスト膜14を形成する。ソルダーレジスト膜14に
よって半田付着を防止したり、導体配線パターンへの汚
れ、傷、腐食等の防止をおこなっている。ここで、導体
配線パターン23に形成されソルダーレジスト膜14の
開口部から露出した外部接続端子パッド16は、ビアホ
ール17の底部となる銅箔12a及び小孔21aに施さ
れた銅めっき18の外表面側に形成されている。更に、
この外部接続端子パッド16やワイヤボンドパッド等の
銅めっき18のソルダーレジスト膜14で覆われない部
分には、ニッケルめっき及び金めっきからなるカバーめ
っき19を施す。As shown in FIG. 3E, for example, on both sides of the core substrate 13 on which the conductor wiring pattern 23 is formed, for example,
The solder resist film 14 is formed so that the external connection terminal pads 16 for connecting the solder balls, the wire bond pads used for connecting to the semiconductor element with the bonding wires, and the like are exposed from the openings. The solder resist film 14 prevents the solder from adhering and prevents the conductor wiring pattern from being stained, scratched, corroded, and the like. Here, the external connection terminal pads 16 formed on the conductor wiring pattern 23 and exposed from the openings of the solder resist film 14 are formed on the outer surfaces of the copper foil 12a serving as the bottom of the via hole 17 and the copper plating 18 provided on the small holes 21a. Formed on the side. Furthermore,
Cover plating 19 made of nickel plating and gold plating is applied to portions of the copper plating 18 such as the external connection terminal pads 16 and the wire bond pads which are not covered with the solder resist film 14.
【0015】ここで、銅箔12aの堰部22の実質的中
心部に形成する小孔21aの孔径は、貫通孔21に施す
銅めっき18の厚みの2倍以下に形成するのがよい。銅
めっき18をするとき、銅箔12aに小孔21aが開い
ているので、小孔21aから貫通孔21の中へのめっき
液の流動を可能とし、貫通孔21の壁面への銅の形成を
促進することができると共に、小孔12aの孔径が2倍
以下であれば、所望とするめっき厚みに形成することで
小孔21aを閉塞することができる。The diameter of the small hole 21a formed substantially in the center of the dam 22 of the copper foil 12a is preferably not more than twice the thickness of the copper plating 18 applied to the through hole 21. When the copper plating 18 is performed, since the small holes 21a are opened in the copper foil 12a, the plating solution can flow from the small holes 21a into the through-holes 21 to form copper on the wall surfaces of the through-holes 21. If the hole diameter of the small hole 12a is twice or less, the small hole 21a can be closed by forming it to a desired plating thickness.
【0016】なお、上述の図3(B)に示す、レーザー
を用いたコア基板13への貫通孔21の穿設において
は、コア基板13の他方側の面の銅箔12の表面を薄く
エッチングしてからレーザー照射を行っているが、これ
に限定されるものではない。貫通孔21の穿設は、他方
側の面の銅箔12の表面にレーザーの熱効率を向上する
ことができるシート、例えば、三菱ガス化学製のレーザ
ーシート(商品名)等を貼り付けてからレーザーで貫通
孔21を穿設することもできる。この場合は、銅箔12
を薄くすることを必要としない。When the through hole 21 is formed in the core substrate 13 using a laser as shown in FIG. 3B, the surface of the copper foil 12 on the other side of the core substrate 13 is thinly etched. The laser irradiation is performed after that, but it is not limited to this. The perforation hole 21 is formed by attaching a sheet capable of improving the thermal efficiency of the laser, for example, a laser sheet (trade name) manufactured by Mitsubishi Gas Chemical Co., to the surface of the copper foil 12 on the other side, and then applying the laser. It is also possible to form the through-hole 21 by using. In this case, the copper foil 12
Does not require thinning.
【0017】また、予め他方側の面の銅箔12上の抜き
孔21bをエッチングで穿設しておいて、レーザーの出
力を下げて銅箔12に傷を与えないようにし、この銅箔
12をレーザーマスクとするコンフォーマルマスク法で
貫通孔21を穿設することもできる。更に、この方法に
おいては、一方側の面の銅箔12aをエッチングして小
孔21aを穿孔しておくこともできる。Further, a hole 21b in the copper foil 12 on the other side is formed in advance by etching, and the laser output is reduced so that the copper foil 12 is not damaged. The through-hole 21 can also be formed by a conformal mask method using as a laser mask. Furthermore, in this method, the copper foil 12a on one side may be etched to form the small holes 21a.
【0018】[0018]
【発明の効果】請求項1、2記載のプラスチックパッケ
ージにおいては、外部接続端子パッドは、コア基板に設
けられたビアホールの一方側の面の銅箔に形成された小
孔を銅めっきで閉塞してなる部分を含んでいるので、貫
通孔に銅を安定して形成させ、同時に銅めっきで貫通孔
底部の銅箔部の小孔を閉塞して外部接続端子パッド部を
形成できる。特に請求項2記載のプラスチックパッケー
ジにおいては、ビアホールの一方側の銅箔に形成された
小孔の孔径は、他方側の面の銅箔及び絶縁性基材に貫通
形成された抜き孔の径よりも小さいので、形成された銅
の厚みで小孔を閉塞し、確実に非貫通孔からなるビアホ
ールを形成することができる。In the plastic package according to the first and second aspects, the external connection terminal pad closes a small hole formed in the copper foil on one surface of the via hole provided in the core substrate by copper plating. Therefore, copper can be stably formed in the through-hole, and at the same time, the small hole of the copper foil portion at the bottom of the through-hole can be closed by copper plating to form the external connection terminal pad portion. In particular, in the plastic package according to claim 2, the diameter of the small hole formed in the copper foil on one side of the via hole is larger than the diameter of the hole formed through the copper foil on the other side and the insulating base material. Therefore, the small hole can be closed by the thickness of the formed copper, and the via hole composed of the non-through hole can be surely formed.
【0019】請求項3、4記載のプラスチックパッケー
ジの製造方法においては、コア基板の他方側の銅箔面よ
り穿設し、絶縁性基材を貫通する抜き孔を形成し、コア
基板の一方側の面に設けられている銅箔を堰部とし、し
かも堰部の実質的中央部分を小孔とする貫通孔を形成す
る工程と、コア基板の両面側に設けられている銅箔の表
面及び貫通孔に銅めっきを施して導体層を形成すると共
に、小孔を閉塞して非貫通孔からなるビアホールを形成
する工程と、コア基板の一方側及び他方側に施された導
体層に所定のエッチング処理を行って導体配線パターン
を形成する工程と、ビアホール位置に対応して一方側の
導体配線パターンに形成される外部接続端子パッドを除
いて一方側及び他方側の所定部分にソルダーレジスト膜
を形成する工程とを有するので、めっき液の流動がよく
でき、貫通孔の壁面に銅めっきを安定して形成させるこ
とができ、銅の析出と共に貫通孔底部の銅箔部の小孔を
閉塞することができるので、銅箔部に外部接続端子パッ
ド部を備えたプラスチックパッケージを製造できる。特
に、請求項4記載のプラスチックパッケージの製造方法
においては、小孔の孔径は貫通孔に施す銅めっき厚みの
2倍以下であることで、析出する銅の厚みで貫通孔底部
の銅箔部の小孔を確実に閉塞できる。According to a third aspect of the present invention, there is provided a method of manufacturing a plastic package, wherein a hole is formed from the copper foil surface on the other side of the core substrate to form a through hole penetrating the insulating substrate. Forming a through hole having a copper foil provided on the surface of the weir as a weir, and having a substantially central portion of the weir as a small hole, and the surface of the copper foil provided on both sides of the core substrate and A step of forming a conductor layer by applying copper plating to the through-hole, forming a via hole composed of a non-through-hole by closing the small hole, and a method of forming a predetermined conductor layer on one side and the other side of the core substrate. A step of forming a conductor wiring pattern by performing an etching process, and applying a solder resist film to predetermined portions on one side and the other side except for external connection terminal pads formed on the one side conductor wiring pattern corresponding to via hole positions. Forming process and Because it has, the flow of the plating solution can be good, copper plating can be stably formed on the wall surface of the through hole, and the small hole of the copper foil portion at the bottom of the through hole can be closed with the deposition of copper, A plastic package having an external connection terminal pad portion on a copper foil portion can be manufactured. In particular, in the method of manufacturing a plastic package according to claim 4, the diameter of the small hole is not more than twice the thickness of the copper plating applied to the through hole, so that the thickness of the copper to be deposited is less than the thickness of the copper foil at the bottom of the through hole. Small holes can be reliably closed.
【図1】本発明の一実施の形態に係るプラスチックパッ
ケージの部分拡大側断面図である。FIG. 1 is a partially enlarged side sectional view of a plastic package according to an embodiment of the present invention.
【図2】同プラスチックパッケージのコア基板の貫通孔
の説明図である。FIG. 2 is an explanatory diagram of a through hole in a core substrate of the plastic package.
【図3】(A)〜(E)は本発明の一実施の形態に係る
プラスチックパッケージの製造方法を説明する部分拡大
側断面図である。3A to 3E are partially enlarged side sectional views illustrating a method for manufacturing a plastic package according to an embodiment of the present invention.
10:プラスチックパッケージ、11:プラスチック基
材、12、12a:銅箔、13:コア基板、14:ソル
ダーレジスト膜、15:半田ボール、16:外部接続端
子パッド、17:ビアホール、18:銅めっき、19:
カバーめっき、20:ワイヤボンドパッド、21:貫通
孔、21a:小孔、21b、21c:抜き孔、22:堰
部、23:導体配線パターン10: plastic package, 11: plastic substrate, 12, 12a: copper foil, 13: core substrate, 14: solder resist film, 15: solder ball, 16: external connection terminal pad, 17: via hole, 18: copper plating, 19:
Cover plating, 20: Wire bond pad, 21: Through hole, 21a: Small hole, 21b, 21c: Open hole, 22: Weir, 23: Conductor wiring pattern
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 23/12 Q ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 23/12 Q
Claims (4)
を貼ったコア基板の一方側の面に半田ボール接続用の外
部接続端子パッドを備えるボールグリッドアレイ型のプ
ラスチックパッケージにおいて、前記外部接続端子パッ
ドは、前記コア基板に設けられたビアホールの前記一方
側の面の銅箔に形成された小孔を銅めっきで閉塞してな
る部分を含んでいることを特徴とするプラスチックパッ
ケージ。1. A ball grid array type plastic package having an external connection terminal pad for solder ball connection on one surface of a core substrate in which copper foil serving as a circuit substrate is attached to both surfaces of an insulating substrate. A plastic package, wherein the external connection terminal pad includes a portion formed by closing a small hole formed in the copper foil on the one surface of the via hole provided in the core substrate with copper plating.
において、前記ビアホールの前記一方側の銅箔に形成さ
れた小孔の孔径は、他方側の面の銅箔及び前記絶縁性基
材に貫通形成された抜き孔の径よりも小さいことを特徴
とするプラスチックパッケージ。2. The plastic package according to claim 1, wherein the diameter of the small hole formed in the copper foil on one side of the via hole is formed so as to penetrate through the copper foil on the other side and the insulating base material. A plastic package characterized by being smaller than the diameter of the punched hole.
板の一方側の面に半田ボール接続用の外部接続端子パッ
ドを備えるボールグリッドアレイ型のプラスチックパッ
ケージの製造方法において、前記コア基板の他方側の銅
箔面より穿設し、前記絶縁性基材を貫通する抜き孔を形
成し、前記コア基板の一方側の面に設けられている前記
銅箔を堰部とし、しかも該堰部の実質的中央部分を小孔
とする貫通孔を形成する工程と、前記コア基板の両面側
に設けられている銅箔の表面及び前記貫通孔に銅めっき
を施して導体層を形成すると共に、前記小孔を閉塞して
非貫通孔からなるビアホールを形成する工程と、前記コ
ア基板の一方側及び他方側に施された前記導体層に所定
のエッチング処理を行って導体配線パターンを形成する
工程と、前記ビアホール位置に対応して一方側の前記導
体配線パターンに形成される外部接続端子パッドを除い
て一方側及び他方側の所定部分にソルダーレジスト膜を
形成する工程とを有することを特徴とするプラスチック
パッケージの製造方法。3. A method of manufacturing a ball grid array type plastic package having an external connection terminal pad for connecting a solder ball on one surface of a core substrate having copper foil adhered to both surfaces of an insulating substrate. Drilled from the copper foil surface on the other side of the substrate, forming a through hole penetrating the insulating base material, the copper foil provided on one surface of the core substrate as a weir, and Forming a through hole having a substantially central portion of the weir portion as a small hole, and forming a conductor layer by applying copper plating to the surface of the copper foil provided on both sides of the core substrate and the through hole. Forming a via hole formed of a non-through hole by closing the small hole, and forming a conductor wiring pattern by performing a predetermined etching process on the conductor layer provided on one side and the other side of the core substrate. And the step of Forming a solder resist film on predetermined portions on one side and the other side except for external connection terminal pads formed on the one side of the conductor wiring pattern corresponding to the rule position. Package manufacturing method.
の製造方法において、前記小孔の孔径は前記貫通孔に施
す銅めっき厚みの2倍以下であることを特徴とするプラ
スチックパッケージの製造方法。4. The method of manufacturing a plastic package according to claim 3, wherein the diameter of the small hole is not more than twice the thickness of the copper plating applied to the through hole.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000398117A JP2002198461A (en) | 2000-12-27 | 2000-12-27 | Plastic package and its manufacturing method |
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JP2000398117A JP2002198461A (en) | 2000-12-27 | 2000-12-27 | Plastic package and its manufacturing method |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7183647B2 (en) | 2003-04-24 | 2007-02-27 | Shinko Electric Industries, Co., Ltd. | Wiring substrate and electronic parts packaging structure |
WO2007023284A1 (en) * | 2005-08-24 | 2007-03-01 | Fry's Metals Inc. | Reducing joint embrittlement in lead-free soldering processes |
EP2077702A2 (en) | 2008-01-07 | 2009-07-08 | Fujitsu Ltd. | Wiring board and manufacturing method thereof and wiring board assembly |
EP2448381A1 (en) | 2010-10-27 | 2012-05-02 | Fujitsu Limited | Wiring board having a plurality of vias |
KR101351188B1 (en) | 2008-02-29 | 2014-01-14 | 삼성테크윈 주식회사 | Ball grid array package printed-circuit board and manufacturing method thereof |
CN115397137A (en) * | 2022-08-30 | 2022-11-25 | 德中(天津)技术发展股份有限公司 | Method for manufacturing multilayer circuit board by laser-making conductive pattern and electrically interconnecting different surfaces |
CN115460784A (en) * | 2022-08-30 | 2022-12-09 | 德中(天津)技术发展股份有限公司 | Method for manufacturing double-sided circuit boards by laser directing conductive patterns and electrically interconnecting different sides |
WO2023282350A1 (en) * | 2021-07-09 | 2023-01-12 | 住友電気工業株式会社 | Printed wiring board |
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2000
- 2000-12-27 JP JP2000398117A patent/JP2002198461A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7183647B2 (en) | 2003-04-24 | 2007-02-27 | Shinko Electric Industries, Co., Ltd. | Wiring substrate and electronic parts packaging structure |
US7557450B2 (en) | 2003-04-24 | 2009-07-07 | Shinko Electric Industries Co., Ltd. | Wiring substrate and electronic parts packaging structure |
WO2007023284A1 (en) * | 2005-08-24 | 2007-03-01 | Fry's Metals Inc. | Reducing joint embrittlement in lead-free soldering processes |
US8191757B2 (en) | 2005-08-24 | 2012-06-05 | Fry's Metals, Inc. | Reducing joint embrittlement in lead-free soldering processes |
EP2077702A2 (en) | 2008-01-07 | 2009-07-08 | Fujitsu Ltd. | Wiring board and manufacturing method thereof and wiring board assembly |
EP2077702A3 (en) * | 2008-01-07 | 2011-02-16 | Fujitsu Ltd. | Wiring board and manufacturing method thereof and wiring board assembly |
KR101351188B1 (en) | 2008-02-29 | 2014-01-14 | 삼성테크윈 주식회사 | Ball grid array package printed-circuit board and manufacturing method thereof |
EP2448381A1 (en) | 2010-10-27 | 2012-05-02 | Fujitsu Limited | Wiring board having a plurality of vias |
WO2023282350A1 (en) * | 2021-07-09 | 2023-01-12 | 住友電気工業株式会社 | Printed wiring board |
JP7485223B2 (en) | 2021-07-09 | 2024-05-16 | 住友電気工業株式会社 | Printed Wiring Boards |
CN115397137A (en) * | 2022-08-30 | 2022-11-25 | 德中(天津)技术发展股份有限公司 | Method for manufacturing multilayer circuit board by laser-making conductive pattern and electrically interconnecting different surfaces |
CN115460784A (en) * | 2022-08-30 | 2022-12-09 | 德中(天津)技术发展股份有限公司 | Method for manufacturing double-sided circuit boards by laser directing conductive patterns and electrically interconnecting different sides |
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