JP2002149440A - Method for verifying logic circuit and device for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and device for verifying a logic circuit capable of suppressing the deterioration of verifying efficiency due to logical simulation using overlapped verification patterns. SOLUTION: This method is provided with a test program generation step for generating a test program by using random numbers, a software simulation execution step for performing software simulation using the test program, a verification execution judgment step for judging whether or not verification using the test program should be executed based on the software simulation executed result and already verified pattern history information, a logical simulation execution step for executing the test program on a logic circuit to be tested by the logical simulation when it is judged that the verification should be executed, an expected value comparison step for comparing the logical simulation executed result with an expected value, and an already verified pattern history information update step for updating the already verified pattern history information by information related with the verification pattern included in the test program when the expected value compared results are mutually coincident.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for verifying a logic circuit, and more particularly to performing verification using random number data.

[0002]

2. Description of the Related Art In recent years, as LSIs become more sophisticated and highly integrated, an enormous amount of verification patterns and test programs including them are required for function verification and logic verification, and the verification time is also prolonged. In order to solve such a problem, automatic generation of a test program, in particular, automatic generation of a test program and automation of a verification flow using random numbers capable of generating various verification patterns have been considered. As one of them, for example, there is a "test method of a data processing device" disclosed in Japanese Patent Laid-Open No. 6-231000. Here, as a conventional example, FIG.
No. 000 will be described.

FIG. 32 is a flowchart showing a series of processes of a test method for a data processing device, which is a conventional example.
In FIG. 32, first, it is determined whether or not an arbitrary number of tests (for example, once, twice, or the like) predetermined in step S3200 has been performed. If the number of tests has not reached the desired number, the flow advances to step S3202 to generate a test instruction group for executing a test of the data processing device using the random number data. If the number of tests has reached an arbitrary number, in step S3201, the processor information obtained in step S3205 to be described later is decoded, data is converted, and information to be fed back is created. In step S3202, the information created in step S3201 is created. With reference to the feedback information, a test command group is generated while correcting the trajectory. Next, in step S3203, step S3
The expected value of the test instruction group is obtained by simulating the test instruction group generated in 202. Next, in step S3204, the test command group generated in step S3202 is executed by the data processing device under test, and in step S3205, processor information relating to the logical operation and microprogram operation of the data processing device under test at that time is collected. . Then, in step S3206, it is checked whether the expected value generated in step S3202 and the execution result value in step S3204 match, and if they do not match, an error message is output in step S3207. ,
A series of processing operations ends.

As described above, the result of execution of the previously generated test instruction group (information on the logical operation and microprogram operation of the apparatus) is fed back to the next test instruction group generated by random number data input, and verification is still performed. It is possible to generate a test instruction group for verifying a part that is not performed, that is, a part where a logic circuit, a microprogram, or the like is not operating. As a result, it is possible to automatically correct the occurrence of bias in the test and the occurrence of test omission, thereby avoiding the execution of meaningless tests and duplicate tests. Also,
As described above, by effectively executing a valid test instruction, the verification period can be shortened.

[0005]

However, in the test method using random number data as in the above conventional example, the execution result on the data processing device under test is used as feedback information used for generating a test instruction group. Therefore, the data must be executed once by the data processor under test to obtain the feedback information. When the operation of the data processing device under test is simulated by a logic simulator or the like for verification, the simulation speed is slow and the execution time is long. For this reason, there has been a problem that when a duplicate pattern that has already been verified is input to the data processing apparatus under test, the loss of the verification time becomes very large. However, if the test instruction group generated based on the feedback information does not always overlap the verified pattern at that time, the above-described problem does not occur. However, in test program generation using random numbers,
The probability that duplicate patterns are generated at the beginning of verification is relatively low, but the probability that each time verification is performed (the number of test programs to be generated increases), the generated test programs include already verified patterns. If, for example, the internal state of the data processing device under test (data transition of a certain register, etc.) is set as a verification item, all the internal states at the time of executing the test instruction are controlled. However, it is extremely difficult to generate a test instruction group so that it does not overlap with the verified pattern, and even if the test instruction group is generated using feedback information as in the related art, the duplicate pattern is included. Thus, the above-described problem occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a logic circuit verification method and a logic circuit verification method capable of avoiding a prolonged verification time due to verification using a test program including many overlapping patterns. The purpose is to:

[0007]

According to a first aspect of the present invention, there is provided a logic circuit verification method for verifying a logic circuit under test by logic simulation. A test program generating step of generating a test program by using the software simulation execution step of executing the test program on a software simulator and outputting a software simulation execution result; and A verification execution determining step of determining whether to execute verification of the logic circuit under test using the test program, based on verified pattern history information that is information on the pattern; and performing verification in the verification execution determining step. If judged A logic simulation execution step of executing the test program on the logic circuit under test by logic simulation and outputting a logic simulation execution result; an expectation value comparison step of comparing the logic simulation execution result with an expected value; A verified pattern history for updating the verified pattern history information with information on a verified pattern included in the test program verified in the logic simulation execution step, when the expected value and the logic simulation execution result match in the step; And an information updating step.

According to a second aspect of the present invention, there is provided the logic circuit verification method according to the first aspect, wherein the verification execution determination step is included in the test program based on the software simulation execution result. The number of new patterns is detected, and when the number of new patterns is equal to or larger than a certain threshold, it is determined that verification is to be performed.

According to a third aspect of the present invention, there is provided the logic circuit verification method according to the second aspect, wherein the test program determined not to execute the verification in the verification execution determination step and the software program. A test program storing step of storing at least one or more wear simulation execution results, wherein, when it is determined in the verification execution determining step that the verification is not to be performed continuously for a given number of times, the test program storing step is performed. In the test program saved in
A test program including the largest number of new patterns is selected, and verification is executed using the selected test program.

According to a fourth aspect of the present invention, there is provided the logic circuit verification method according to the first aspect, wherein the step of determining whether or not to execute the verification is performed based on the result of the software simulation. The number of used resources is detected, and when the number of used new resources is equal to or larger than a certain threshold, it is determined that verification is to be performed.

According to a fifth aspect of the present invention, there is provided the logic circuit verification method according to the first aspect, wherein the step of determining whether to execute the verification includes the step of: The number of times of execution of an instruction is detected, and when the same instruction in the test program is repeatedly executed by a certain threshold or more, it is determined that verification is not executed.

According to a sixth aspect of the present invention, there is provided the logic circuit verification method according to the first aspect, wherein the verification execution determining step includes the step of:
Analyzing whether the logic circuit under test includes a pattern outside a verification item that is a pattern not to be verified, and determining not to execute verification when including the pattern outside the verification item,
It is like that.

According to a seventh aspect of the present invention, there is provided a logic circuit verification method according to the first aspect, wherein the software simulation execution result is obtained based on the software simulation execution result.
The method further includes a simulation end state analysis step of analyzing the simulation end state, and when the simulation end state is not a desired end state, repeats execution of the software simulation under different end conditions until the simulation end state becomes a desired end state. It is like that.

According to an eighth aspect of the present invention, in the logic circuit verification method according to the seventh aspect, an end condition in which the simulation end state becomes a desired end state is set in the logic simulation step. The method further comprises a logic simulation end condition setting step of setting as a logic simulation end condition.

According to a ninth aspect of the present invention, in the logic circuit verification method according to the first aspect, it is determined whether or not the set number of verification items is larger than a certain threshold value. The method further includes a verification item number determination step of determining not to perform verification when the number is large,
It is like that.

According to a tenth aspect of the present invention, in the logic circuit verifying method of the ninth aspect, the threshold value is related to a size of a data storage unit for storing the verified pattern history information. It is like that.

Further, in the logic circuit verification method according to the present invention, in the logic circuit verification method according to the first aspect, in the expected value comparison step, the logic simulation execution result and the expected value may be different. In case,
An error occurrence pattern analysis step for analyzing which pattern in the test program caused the error is further provided.

A logic circuit verification method according to a twelfth aspect of the present invention is the logic circuit verification method according to the eleventh aspect, wherein the logic circuit verification method is based on error occurrence pattern history information that is information on an error occurrence pattern that has occurred so far. An error occurrence pattern determination step of determining to execute verification when the error occurrence pattern is not included in the test program; and information on the error occurrence pattern analyzed in the error occurrence pattern analysis step. An error occurrence pattern history information updating step of updating information is further provided.

According to a thirteenth aspect of the present invention, there is provided the logic circuit verification method according to the first aspect, wherein the logic simulation execution result and the expected value do not match in the expected value comparing step. And an error occurrence test program recording step of recording the test program or error occurrence test program information which is information capable of regenerating the test program.

According to a fourteenth aspect of the present invention, there is provided a logic circuit verification method according to the first aspect, wherein the error occurrence test program information is information capable of regenerating a test program in which an error has occurred. Further comprising an error generation test program generation step of generating an error generation test program, wherein a test program used for verification is generated in the test program generation step or in the error generation test program generation step. To choose.

According to a fifteenth aspect of the present invention, there is provided a logic circuit verification apparatus for verifying a logic circuit under test by logic simulation, comprising: a program realizing verification means for verifying the logic circuit under test. Verification means storage device for storing, execution device for executing a program stored in the verification means storage device, and data output or referenced when the execution device executes the program stored in the verification means storage device A data storage device for storing the test program, wherein the verification device stored in the verification device storage device generates a test program using a random number and stores the test program in the data storage device; and the test program Is executed on a software simulator, and the software simulation execution result is stored in the data simulator. A software simulation execution unit to be stored in the storage device, and a verification of the logic circuit under test using the test program based on the software simulation execution result and verified pattern history information which is information on the verified pattern. Verification execution determining means for determining whether to perform the verification, and when the verification execution determining means determines that the verification is to be performed, the test program is executed on the logic circuit under test by logic simulation, and the logic simulation execution result is obtained. A logic simulation executing means stored in the data storage device, an expected value comparing means for comparing the logic simulation execution result with an expected value, and a case where the expected value and the logic simulation execution result match in the expected value comparing means In addition, the verified putter The history information includes the verified pattern history information updating means for updating the information on the verified pattern included in the test program is obtained by way.

The logic circuit verification device according to claim 16 of the present invention is the logic circuit verification device according to claim 15, wherein the verification execution determination means is included in the test program based on the software simulation execution result. New pattern number counting means for detecting the number of new patterns, and new pattern number determining means for determining whether the number of new patterns detected by the new pattern number counting means is greater than or equal to a threshold value, According to a result of the judgment by the judging means, it is judged whether or not the verification of the logic circuit under test using the test program is executed.

According to a seventeenth aspect of the present invention, there is provided the logic circuit verification device according to the sixteenth aspect, wherein the test program determined not to execute the verification by the verification execution determination means and the software Test program storage means for storing at least one or more wear simulation execution results in the data storage device, wherein the test execution determination means determines that the test program A test program including the largest number of the new patterns among the test programs stored by the storage unit is selected, and the verification is executed using the selected test program.

The logic circuit verification device according to claim 18 of the present invention is the logic circuit verification device according to claim 15, wherein the verification execution determining means determines a new resource of the test program based on the software simulation execution result. New resource number counting means for detecting the number of used resources, and new resource number determining means for determining whether the new resource usage number detected by the new resource number counting means is greater than or equal to a certain threshold, According to the determination result of the means, it is determined whether to execute the verification of the logic circuit under test using the test program.

According to a nineteenth aspect of the present invention, in the logic circuit verification device according to the fifteenth aspect, the verification execution determining means determines each of the test programs in the test program based on the software simulation execution result. An instruction execution number counting means for detecting an instruction execution number; and an instruction execution number determination means for determining whether the execution number detected by the instruction execution number counting means is smaller than a certain threshold value. According to the determination result of the means, it is determined whether to execute the verification of the logic circuit under test using the test program.

According to a twentieth aspect of the present invention, in the logic circuit verification device according to the fifteenth aspect, the verification execution determining means determines that the test program is based on the software simulation execution result. An analysis is performed to determine whether the logic circuit under test includes a pattern outside a verification item that is a pattern not to be verified, and it is determined that verification is not performed when the pattern includes the pattern outside the verification item.

According to a twenty-first aspect of the present invention, in the logic circuit verification device according to the fifteenth aspect, a simulation end state analyzing means for analyzing a simulation end state from the software simulation execution result is further provided. When the simulation end state analysis means does not determine that the simulation end state is a desired end state, the software simulation is repeatedly executed under different end conditions until the simulation end state reaches a desired end state.

The logic circuit verification device according to claim 22 of the present invention is the logic circuit verification device according to claim 21, wherein the termination condition that the simulation termination state becomes a desired termination state is determined by the logic simulation execution means. And a logic simulation end condition setting means for setting as the end condition of the logic simulation in the above.

A logic circuit verification device according to a twenty-third aspect of the present invention is the logic circuit verification device according to the fifteenth aspect, wherein it is determined whether or not the set number of verification items is larger than a certain threshold value. The apparatus further includes a verification item number determination unit that determines not to execute the verification when the number is large.

The logic circuit verification device according to claim 24 of the present invention is the logic circuit verification device according to claim 23, wherein the threshold value relates to a size of a data storage unit for storing the verified pattern history information. It is like that.

According to a twenty-fifth aspect of the present invention, in the logic circuit verification apparatus according to the fifteenth aspect, when the expected value comparison means does not match the logic simulation execution result with the expected value. And an error occurrence pattern analysis means for analyzing which pattern in the test program caused the error.

According to a twenty-sixth aspect of the present invention, in the logic circuit verifying apparatus according to the twenty-fifth aspect, the error occurrence pattern analysis means includes an error analysis simulation for specifying a pattern in which an error has occurred. Executing the test program on a software simulator with the end condition determined by the error analysis simulation end condition determining means for determining the simulation end condition of the error analysis; The test program is executed on the logic circuit under test by a logic simulation under an ending condition determined by the error analysis software simulation executing means for storing a value in the data storage unit and the error analysis simulation ending condition determining means. I An error analysis logic simulation execution unit that stores the error analysis logic simulation execution result in the data storage unit; the error analysis expected value output by the error analysis software simulation execution unit; An error analysis expected value comparison unit that compares the error analysis logic simulation execution result output by the logic simulation execution unit; an error analysis end determination unit that determines whether to end the error analysis process; And an error analysis pattern display means for displaying an occurrence pattern.

The logic circuit verification device according to claim 27 of the present invention is the logic circuit verification device according to claim 25 or 26, wherein the error occurrence pattern history is information on an error occurrence pattern that has occurred so far. Based on the information, an error occurrence pattern determination unit that determines to execute a verification when the error occurrence pattern is not included in the test program, and the error occurrence pattern analysis unit analyzes the error occurrence pattern based on information on the error occurrence pattern analyzed by the error occurrence pattern analysis unit. An error occurrence pattern history information updating means for updating occurrence pattern history information is further provided.

According to a twenty-eighth aspect of the present invention, in the logic circuit verification device according to the fifteenth aspect, when the expected value comparison means does not match the logic simulation execution result with the expected value. And an error occurrence test program recording means for recording the test program or error occurrence test program information, which is information capable of regenerating the test program, in the data recording device.

According to a twenty-ninth aspect of the present invention, there is provided the logic circuit verification device according to the fifteenth aspect, wherein the error generation test program information is information that can regenerate a test program in which an error has occurred. An error occurrence test program generating means for generating an error occurrence test program, and a test program for selecting whether the test program used for verification is generated by the test program generation means or the error generation test program generation means. The apparatus further includes a generation selection unit.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an outline of a logic circuit verification method of the present invention will be described with reference to the flowchart of FIG. FIG. 1 is a flowchart showing an outline of the logic circuit verification method of the present invention. In FIG. 1, first, in step S1
In step S00, a test program is generated using random numbers.
The test program generated in 00 is executed on a software simulator to output a software simulation execution result. Here, the software simulator refers to a simulator that realizes the function of the data processing device under test by software such as C language. Next, in step S108, the software simulation execution result output in step S101 is compared with verified pattern history information which is information on a verified pattern of a test program verified so far in step S103, which will be described later. It is determined whether to execute the verification using the test program generated in step S100. If it is determined in step S108 that the verification is to be executed, in step S103, the test program is executed on the logic circuit under test by a logic simulation using a logic simulator to output a logic simulation execution result, and the process proceeds to step S104. If it is not determined that the verification has been performed, the process proceeds to step S
Returning to 100, another test program is generated. Next, in step S104, step S103
And compares the logic simulation execution result output with the expected value. If the expected value matches the logic simulation execution result in step S104, the verified pattern history information is updated in step S105 with information on the verified pattern included in the test program verified in step S103. I do.

As described above, in the logic circuit verification method of the present invention, a test program including many duplicated patterns (less new patterns) is prevented from being executed on a logic simulator having a low verification speed, and the verification time is extended. Can be suppressed. Hereinafter, embodiments of the present invention will be described.

(Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described with reference to FIGS. First,
The configuration of the logic circuit verification device according to the first embodiment will be described with reference to FIG. FIG. 2 is a block diagram of the logic circuit verification device according to the first embodiment.

In FIG. 2, the logic circuit verification device according to the first embodiment includes a verification means storage unit 220 for storing programs for implementing each means (described later) for verifying a logic circuit, A CPU 221 for executing each verification means stored in the unit 220,
221 is provided with a data storage unit 222 for storing data to be output or referred to when each of the verification units stored in the verification unit storage unit 220 is executed. The verification unit storage unit 220 and the data storage unit 222 are realized by a memory, a hard disk, or the like.

The verification means stored in the verification means storage unit 220 include a test program generation means 200, a software simulation execution means 201, a new pattern number counting means 207, and a new pattern number determination means 2
02, a verification execution determination unit 208, a logic simulation execution unit 203, an expected value comparison unit 204, and a verified pattern history information update unit 205, which are executed by the CPU 221 to verify the logic circuit. Is what you do. Hereinafter, each verification unit will be described. The test program generation means 200 generates a test program 223 using random numbers and
The software simulation executing means 201 executes the test program 223 created by the test program generating means 200 on the software simulation, and stores the software simulation execution result 225 in the data storage section 222. Is output to New pattern number counting means 20
7 is the software simulation execution means 20
The number of new patterns included in the test program 223 is counted based on the software simulation execution result 225 output in step 1 and the verified pattern history information 206. The verification execution determination unit 208 determines whether the number of new patterns counted by the new pattern number counting unit 207 is equal to or greater than a threshold. The software simulation execution result and the data storage unit 222
Is compared with the verified pattern history information 206 which is information on the verified patterns stored in the test program, and it is determined whether or not to execute the verification using the test program. Further, the logic simulation executing means 203
Executes the test program 223 on the logic circuit under test by a logic simulation using a logic simulator when the new pattern number determination means 202 determines that the verification is to be executed, and outputs the logic simulation execution result 226 to the data The expected value comparison means 204 compares the logic simulation execution result 226 output from the logic simulation execution means 203 with the expected value 224 output from the software simulation execution means 201. Compared with verified pattern history information updating means 2
05, when the expected value comparison means 204 matches the expected value 224 with the logic simulation execution result 226, the verified pattern history information 20
6 is updated with information on a verification pattern included in the test program verified by the logic simulation executing means 203.

Next, according to the flowchart of FIG. 3, the processing operation of the logic circuit verification device in the first embodiment will be described.
This will be described with reference to FIG.

FIG. 3 is a diagram showing Embodiment 1 of the present invention.
FIG. 4 is a flowchart illustrating a series of processing operations of the logic circuit verification device. FIG. 4 is an output example of each unit of the logic circuit verification method according to the first embodiment.

In the first embodiment, first, in step S300, the test program generating means 200 outputs the random number output from the random number generator (not shown) and the test instruction information 400 of the logic circuit under test (FIG. 4).
(A)), the test program 401 (FIG. 4)
(B)) is generated and output to the data storage unit 222.
Specifically, the random number generator randomly generates eight integers from 0 to 7, and selects an instruction having the generated value as an index from the test instruction information 400. For example, if 0 is generated by the random number generator, the index 0
"SET FR0, 1" instruction is selected. Then, the first selected instruction is set as the first instruction of the test program, and thereafter, it is repeated five times in total, and an instruction group generated from the five instructions selected as described above is set as the test program.

Next, in step S301, the software simulation executing means 201 converts the test program 401 generated in step S300 into
A software simulation execution result 402 (FIG. 4C), which is information on the executed instruction, is obtained and output to the data storage unit 222. In the first embodiment, it is assumed that five instructions included in the test program 401 have been executed in order. Note that the information included in the software simulation execution result 402 may include not only information on the executed instruction but also information on the internal state of the logic circuit under test (data transition of a certain register, etc.). Further, in the first embodiment, in step S301, the expected value 40 used in step S304 described later is used.
3 (FIG. 4D) is also generated and output to the data storage unit 222. The expected value 403 includes the values stored in the registers FR0, FR1, FR2, FR3, FR7 when the software simulation of the test program 401 has been completed.

Next, in step S307, the new pattern number counting means 207 uses the software simulation execution result 402 (FIG. 4C) and the verified pattern history information 404 (FIG. 4E).
The number of new patterns included in the test program 401 is counted. In the first embodiment, whether or not all eight instructions from 0 to 7 included in the test instruction information 400 (FIG. 4A) operate normally is set as a verification item, and a verified pattern is set. The history information 404 includes indices 0 to 7 corresponding to the indices of the instructions included in the test instruction information 400, flag information indicating whether each index has been verified (1) or not verified (0). Shall be included. Specifically, first, the software simulation execution result 402 (FIG. 4)
The information of the executed instruction is obtained from (c)). In the first embodiment, among the instructions included in the test instruction information 400,
Five instructions 0, 7, 1, 3, and 2 are being executed. Next, it is detected from the verified history information 404 (FIG. 4E) whether the above five instructions have been verified or not, and the number of unverified instructions is counted. In the first embodiment, among the instructions 0 to 7 included in the verified history information 404,
Since the instructions 0, 1, and 6 have already been verified, among the instructions executed in the software simulation execution result 402, the instructions 7, 3, and 2 are unverified instructions, and the number of new patterns is 3.

Next, in step S302, the number-of-new-patterns determination means 202 compares the number of new patterns counted in step S307 with an arbitrary threshold value, and determines whether or not to execute verification using the test program 401. Here, if the number of new patterns is equal to or greater than the threshold,
In step S303, a logic simulation is performed by the physical simulation execution unit 203 using the test program 401. If the number of new patterns is smaller than the threshold, the process returns to step S300, and another test program is generated by the test program generation unit 200. I do. Here, specifically, if the threshold value is 3 in the first embodiment, the number of new patterns (3) obtained by the new pattern number counting means 207 in step S307 is equal to or larger than the threshold value (3). The test program 401 is executed on the logic circuit under test by the logic simulation executing means 203, and a logic simulation execution result 405 (FIG. 4F) is output. This logic simulation execution result 405 is
Registers FR0, FR1, FR2, FR at the end of the logic simulation of test program 401
3, including the value stored in FR7. The threshold value used for the determination in step S303 may be a value set arbitrarily by the verifier, or a value automatically set based on the total number of verified items or the number of unverified items, in addition to a predetermined value.

Next, in step S304, the expected value 403 generated in step S301 and the
The logic simulation execution result 405 generated in step 03 is compared by the expected value comparison means 204. Specifically, the register FR output to the expected value 403 (FIG. 4D)
0, FR1, FR2, FR3, FR7, and the register FR output to the logic simulation execution result 405 (FIG. 4F).
The values 0, FR1, FR2, FR3, and FR7 are compared with the values 1, 2, 0, 1, and 1, respectively. In step S304, the expected value 403 and the logic simulation execution result 405
If they match, the process proceeds to step S305, and if they do not match, the series of processing operations ends. Embodiment 1
Since all the values match, step S305 is performed.
In, the verified pattern history information updating means 205 updates the verified pattern history information 404, and the updated verified pattern history information 406 (FIG. 4 (g))
Get. In the test program 401 according to the first embodiment, since five instructions 0, 7, 1, 3, and 2 among the instructions 0 to 7 included in the verified history information 404 are verified, the corresponding index Is updated to verified (1), and the updated verified pattern history information 406 (FIG. 4G).

The above-described series of verification processing is ended. For example, the above-described series of verification processing may be repeatedly executed up to a certain end condition such as a designated number of times. In the first embodiment, the test instruction information 400 of the logic circuit under test shown in FIG. 4A is used as an example.
The test instruction information is not limited to this.

As described above, according to the first embodiment, the number of new patterns (unverified items) included in the test program generated by using the random numbers is calculated from the result of executing the software simulation and generated. When the number of new patterns included in the test program is small (the number of verified patterns is large), another test program is regenerated. , The increase in the verification time can be suppressed.

(Embodiment 2) Hereinafter, Embodiment 2 of the present invention will be described with reference to FIGS. First,
The configuration of the logic circuit verification device according to the second embodiment will be described with reference to FIG. FIG. 5 is a block diagram showing a configuration of the logic circuit verification device according to the second embodiment.

In FIG. 5, reference numeral 509 denotes a test program for storing the test program generated by the test program generation means 500 and the test program storage information 527 which is information on the number of new patterns included in the test program in the data storage unit 522. It is a storage means. The other configuration is the same as that of the first embodiment, and the description is omitted.

Next, the processing operation of the logic circuit verification device according to the second embodiment will be described with reference to FIGS. 4 and 7 in accordance with the flowchart of FIG. FIG. 6 is a flowchart showing a series of processing operations of the logic circuit verification device according to the second embodiment, and FIGS. 4 and 7 are examples of output by each means of the logic verification method according to the second embodiment. .

In the second embodiment, first, at step S60
0, the test program generation means 500 uses the random number output from the random number generator (not shown) and the test instruction information 400 of the logic circuit under test (FIG. 4A) to generate a test program 401 ( FIG. 4B) is generated,
The data is output to the data storage unit 422. This test program generation method is the same as in the first embodiment.

Next, in step S601, the software simulation executing means 501 executes the test program 401 generated in step S600 on a software simulator, and a software simulation execution result 402 which is information on the executed instruction. (FIG. 4C) is obtained and output to the data storage unit 422. In the second embodiment, an expected value 403 (FIG. 4) used in step S604 described later is determined by software simulation executed in step S601.
(D)) is generated and output to the data storage unit 422. The expected value 403 is stored in the register FR when the software simulation of the test program 401 is completed.
0, FR1, FR2, FR3, and FR7.

Next, in step S607, the new pattern number counting means 507 causes the data storage section 42
2, the software simulation execution result 402 and the verified pattern history information 404
The number of new patterns included in the test program 401 is counted using (FIG. 4E). The calculation method of the number of new patterns is the same as that of the first embodiment, and the number of new patterns is 3 in the second embodiment.

Next, in step S602, the number of new patterns determined in step S607 is compared with an arbitrary threshold by the new pattern number determination means 502. If it is determined in step S602 that the new pattern is larger than a certain threshold, the process proceeds to step S603, where the logic simulation execution unit 603 performs a logic simulation using the test program 401. If it is determined in step S602 that the number of new patterns is smaller than the threshold, in step S609, the test program storage unit 509 uses the test program 401, the expected value 403, and the step S60.
After storing the number of new patterns included in the test program counted in step 7 in the data storage unit 522,
Returning to 600, another test program is generated by the test program generation means 500. However, if the number of new patterns is smaller than the threshold value twice consecutively, step S6
09 in the test program stored in step S09 and the test program generated at that time, the test program including the largest number of new patterns is used.
In 603, a logic simulation is performed by the logic simulation execution means 503. Specifically, in the second embodiment, assuming that the threshold value is 4, the number of new patterns (3) counted in step S607 is smaller than the threshold value (4), and thus the test program 401 (FIG. 4B) in step S609. , Expected value 403 (FIG. 4D),
And the number of new patterns (3) is saved, and step S6
00 and another test program 700 (FIG. 7A)
Generate Then, in step S601, a software simulation is executed using the regenerated test program 700, and a software simulation execution result 701 (FIG. 7B) and an expected value 702 are obtained.
7 (c) is generated and output to the data storage unit 422. In step S607, the data storage unit 422
Simulation execution result 7 stored in
01 (FIG. 7B) and verified pattern history information 4
04 (FIG. 4E), the number of new patterns included in the regenerated test program 700 is counted. Here, the number of new patterns is two, and step S6
02, it is determined that the number of new patterns (2) is smaller than the set threshold value (4), which means that the number of new patterns included in the test program twice consecutively is smaller than the threshold value. So step S60
9, a test program that includes a larger number of new patterns is selected from the test program 401 stored in step 9 and the test program 700 generated this time, and a logic simulation is performed using the selected test program. More specifically, since the number of new patterns included in the test program 401 (FIG. 4B) and the test program 700 (FIG. 7A) are three and two, respectively, 401 is selected, and a logic simulation is performed using the test program 401 in step S603. Step S60
The threshold value used for the determination of 2 may be a value arbitrarily set by a verifier, or a value automatically set based on the number of all verified items or the number of unverified items, in addition to a predetermined value. Further, in the second embodiment, when the number of new patterns is smaller than the threshold value twice consecutively, the test program storage unit 50
9 is used to select a test program from the data stored. However, the number of test programs stored by the test program storage means is arbitrary, and in this case, a new pattern is continuously (arbitrary number + 1) times. When it is smaller than the threshold value, a test program to be verified is selected and a logic simulation is executed. Step S after this
Steps 603 to S605 are the same as those in the first embodiment, and a description thereof will not be repeated.

As described above, according to the second embodiment, the number of new patterns (unverified items) included in the test program generated by using the random numbers is calculated from the result of executing the software simulation, and the number of generated new patterns is calculated. When the number of new patterns included in the test program is small (the number of verified patterns is large), another test program is regenerated. Therefore, a test program including many duplicated patterns can be executed on a logic simulator with a low verification speed. , It is possible to suppress an increase in the verification time due to the execution. When a test program with a small number of new patterns is continuously generated, control is performed to perform verification using the test program with the largest number of new patterns. It is possible to avoid the loss of the verification time due to the infinite repetition between.

(Embodiment 3) Hereinafter, Embodiment 3 of the present invention will be described with reference to FIGS. First, the configuration of the logic circuit verification device according to the third embodiment will be described with reference to FIG. FIG. 8 is a block diagram showing a configuration of the logic circuit verification device according to the third embodiment of the present invention.

In FIG. 8, reference numeral 807 denotes a software simulation execution result 825 output from the software simulation execution means 801 and the data storage unit 8.
New resource number counting means for counting the number of new resources included in the test program generated by the test program generation means 800 based on the verified pattern history information 806 stored in the storage means 22; The new resource count determining means for determining whether or not the number of new resources counted in 807 is equal to or greater than a certain threshold value. The test program includes the new resource count counting means 807 and the new resource count determining means 802 described above. The verification execution determination unit 808 that determines whether to execute the verification executes the verification of the logic circuit under test using the test program by the logic simulation execution unit 803 when the number of new resources is equal to or more than a certain threshold value. If the number of resources is smaller than a certain threshold It is to determined to generate another test program again by strike program generation unit 800. The other configuration is the same as that of the first embodiment, and the description is omitted here.

Next, the processing operation of the logic circuit verification device according to the third embodiment will be described with reference to FIG. 10 according to the flowchart of FIG. FIG. 9 is a flowchart illustrating a series of processing operations of the logic circuit verification device according to the third embodiment. FIG. 10 is an output example of each unit of the logic circuit verification method according to the third embodiment.

In the third embodiment, first, at step S 90
0, the test program generating means 800
Using a random number output from a random number generator (not shown) and test instruction information 1000 (FIG. 10A) of the logic circuit under test, a test program 1001 (FIG. 10B) is generated and data is generated. Output to the storage unit 822. This test program generation method is the same as in the first embodiment.

Next, in step S901, the software simulation executing means 801 executes the test program 1001 generated in step S900 on a software simulator, and executes a software simulation execution result 1002 which is information on the executed instruction. (FIG. 10C) and the data storage unit 822
Output to In the third embodiment, step S9
01 by software simulation
Expected value 1003 used in step S904 described later
(FIG. 10D) is generated and output to the data storage unit 822.

Next, in step S907, the software simulation execution result 1002 (FIG. 10 (c))
The number of new resources included in the test program 1001 is counted using the verified pattern history information 1004 (FIG. 10E) which is information on the verified pattern. In the third embodiment, F
R0, FR1, FR2, FR3, FR4, FR5, FR
It is assumed that eight registers 6, FR7 can be used, and whether all the eight registers are used in the verification and whether or not they operate normally is set as a verification item. The verified pattern history information 1004 includes the above-described eight registers, and whether each register has been verified (1) or not verified (0).
It is assumed that flag information indicating whether or not this is included. Specifically, first, the software simulation execution result 1
From 002 (FIG. 10C), information on resources used in the software simulation is obtained. Here, five registers FR0, FR1, FR2, FR3, and FR7 are used. Next, the above-mentioned five registers detect whether the data has been verified or not, from the verified pattern history information 1004 (FIG. 10E), and count the number of unverified resources. In the third embodiment, among the eight registers included in the verified pattern history information 1004, the registers FR0 and FR1 have already been verified.
Of the registers included in FIG.
Registers 7, 7, and 3 become new resources,
The number of new resources is three.

Next, in step S 902, the number of new resources included in the test program 1001 counted in step S 907 is compared with an arbitrary threshold value, and it is determined whether verification using the test program 1001 is to be performed. If the number of new resources is equal to or larger than the threshold, the logic simulation executing means 8 is executed in step S903.
In step 03, a logic simulation is performed using the test program 1001. If the number of new resources is smaller than the threshold, the process returns to step S900 to generate another test program. Specifically, when the threshold is set to 3 in the third embodiment, the number of new resources (3) counted in step S907 is determined to be equal to or larger than the threshold (3), and the process proceeds to step S903. This step S90
The threshold value used for the determination of 2 may be a value arbitrarily set by a verifier, or a value automatically set based on the number of all verified items or the number of unverified items, in addition to a predetermined value.

In step S 903, the logic simulation executing means 803 executes the test program 1
001 is executed on the logic circuit under test by logic simulation using a logic simulator, and a logic simulation execution result 1005 (FIG. 10F) is output to the data storage unit 822. The logic simulation execution result 1005 indicates that the registers FR0, FR1,
It contains the values stored in FR2, FR3, and FR7, respectively.

Next, in step S904, the expected value 1003 generated in step S902 and the
Logic simulation execution result 100 generated in 903
Compare 5 If the expected value 1003 and the logic simulation execution result 1005 match, the process proceeds to step S905, and if they do not match, a series of processes ends. This expected value comparison method is the same as in the first embodiment. In the third embodiment, all the values match, so the process proceeds to step S905.

Next, in step S905, the verified pattern history information updating means 805 updates the verified pattern history information 1004 to obtain updated verified pattern history information 1006 (FIG. 10 (g)).
Specifically, the test program 100 of the third embodiment
In FIG. 1, verified pattern history information 1004 (FIG. 10)
Among the eight registers included in (e)), FR0, F0
Since the five registers R7, FR1, FR3 and FR2 have been verified, the flags of the corresponding registers are updated to verified (1), and the updated verified pattern history information 1006 is obtained. Note that the series of verification processing is completed as described above. For example, the series of verification processing may be repeatedly performed up to a certain end condition such as a designated number of times.

As described above, according to the third embodiment, the number of new resources (unverified items) included in the test program generated by using random numbers is calculated from the result of executing the software simulation and generated. When the number of new resources included in the test program is small (the number of verified patterns is large), another test program is regenerated, so that a test program containing many duplicate resources can be executed on a logic simulator with a low verification speed. , It is possible to suppress an increase in the verification time due to the execution of the process.

Embodiment 4 Hereinafter, FIGS. 11 to 13
The fourth embodiment of the present invention will be described with reference to FIG. When generating a test program using random numbers, if an instruction to be generated includes an instruction that causes loop processing or a branch instruction, a test program in which the same instruction is repeatedly executed indefinitely (or many times) is generated. May be generated. When verification is performed using such a test program, only some instructions (patterns) are repeatedly executed, and the verification efficiency deteriorates. In the fourth embodiment, by counting the number of instruction executions in a test program, a test program in which the same instruction is repeatedly executed indefinitely (or many times) is prevented from being executed on a logic simulator. is there.

First, the configuration of the logic circuit verification device according to the fourth embodiment will be described with reference to FIG. FIG. 11 is a block diagram illustrating a configuration of a logic circuit verification device according to the fourth embodiment. In FIG. 11, 110
7 counts the number of executions of each instruction included in the test program based on the software simulation execution result 1125 obtained by the software simulation execution unit 1101, using the test program generated by the test program generation unit 1100. Instruction execution number counting means 1102 is an instruction execution number determination means for determining whether or not the number of executions of each instruction counted by the instruction execution number counting means 1107 is smaller than a certain threshold value.
7. The verification execution determining means 1108 for determining whether or not to execute the verification using the test program, comprising the instruction execution number determining means 1102 and the logic simulation executing means when the execution number of each instruction is smaller than the threshold. In step 1103, the test circuit is verified using the test program. If the number of executions of each instruction is equal to or greater than the threshold, the test program generation unit 1100 determines that another test program is to be generated. The other configuration is the same as that of the first embodiment, and the description is omitted here.

Hereinafter, according to the flowchart of FIG.
The processing operation of the logic circuit verification device according to the fourth embodiment will be described with reference to FIG. FIG. 12 is a flowchart showing a series of processing operations of the logic circuit verification device according to the fourth embodiment. FIG. 13 is an output example of each unit of the logic circuit verification method according to the fourth embodiment.

In the fourth embodiment, first, in step S1
At 200, the test program generating means 1100 outputs a random number output from a random number generator (not shown) and test instruction information 1300 of the logic circuit under test (see FIG. 13).
(A)), the test program 1301 (FIG. 13)
(B)) is generated and output to the data storage unit 1122.
This test program generation method is the same as in the first embodiment.

Next, in step S1201, the software simulation executing means 1201 generates the test program 130 generated in step S1200.
1 is executed on a software simulator, and a software simulation execution result 1302 (FIG. 13C) as information on the executed instruction is obtained and output to the data storage unit 1122. In the fourth embodiment, of the five instructions included in test program 1301, the first two
Instructions “SET FR0,1”, “SETLC0,
3 "is executed, and then two instructions" SUB F
R2, FR0, 1 "," AND FR4, FR0, 1 "
Is repeated three times, and then the last instruction “ADD F
R1, FR0, 1 "are executed. In the fourth embodiment, the software simulation executed in step S1201 performs the following step S1201.
An expected value 1303 (FIG. 13D) used in step 1204 is generated and output to the data storage unit 1122.

Next, in step S 1207, the number of executions of each instruction included in the test program 1301 is counted by the instruction execution number counting means 1107 using the software simulation execution result 1302. In the fourth embodiment, of the five instructions included in the test program 1301 (FIG. 13B), three instructions “SET FR0,1”, “SET L
C0,3 "," ADDFR1, FR0,1 "executed once, and two more instructions" SUB FR2, FR0,1 ",
"AND FR4, FR0, 1" is executed three times.

Next, in step S1202, the instruction execution count determining means 1102 executes step S1207.
By comparing the number of executions of each instruction included in the test program 1301 counted in the above with an arbitrary threshold value, it is determined whether or not to execute the verification using the test program 1301. If the number of executions of the instruction is smaller than the threshold, the test program 13 is executed in step S1203.
A logic simulation is performed by using 01. If the number of executions of the instruction is equal to or more than the threshold, the process returns to step S1200, and another test program is generated by the test program generation unit 1100. Here, specifically, in the fourth embodiment, assuming that the threshold value is 3, the test program 1301
SUB FR2, FR0,
Since the number of executions (3) of “1” and “AND FR4, FR0, 1” is equal to or greater than the threshold (3), another test program 130 is executed in the test program generation step S1200.
4 (FIG. 13E), a software simulation is executed using the test program 1304 regenerated in step S1201, and a software simulation execution result 1305 (FIG. 13F)
And an expected value 1306 (FIG. 13 (g)) and output it to the data storage unit 1122. Then, in step S1207, the number of executions of each instruction included in the regenerated test program 1304 is counted. Here, of the five instructions included in the test program 1304, three instructions “SET FR0,1”, “SUB FR2, F”
R0,1 "and" SET LC0,2 "are executed once, and the other two instructions" AND FR4, FR0,1 "," ADD
FR1, FR0, 1 "are executed twice. Then, again in step S1202, the instruction execution count determining means 1102 determines the number of executions of each instruction included in the regenerated test program 1304 counted in step S1207. It is compared with the threshold value (3) to determine whether to execute the verification using the test program 1304. In this case, the number of executions of each of the five instructions included in the test program 1304 is smaller than the threshold value (3). Therefore, the process proceeds to step S1203, where a logic simulation is performed using the regenerated test program 1304. The subsequent processes from step S1203 to step S1205 are the same as those in the first embodiment.

As described above, according to the fourth embodiment, the number of executions of each instruction included in the test program generated by using the random numbers is calculated from the software simulation execution result, and the same instruction is repeated many times. In the case of a test program to be executed, another test program is regenerated. It can be suppressed.

(Embodiment 5) Hereinafter, FIGS. 33 to 35
The fifth embodiment of the present invention will be described with reference to FIG. If the logic circuit under test has a restriction that, for example, each of the instructions A and B can be executed alone but these instructions cannot be executed consecutively, the instructions A and B in the logic circuit under test If the verification is executed using a test program including a pattern for continuously executing the verification, the operation does not operate normally, and the verification result becomes an error. The cause of this error is the specification of the logic circuit under test, not a test program error.However, when the error is detected, the cause of the error is not known. However, the verifier had to perform an error analysis, which reduced efficiency. In order to avoid such an error, when instructions are generated, instructions A, B
There is also a method to add a constraint that does not generate consecutively, but if the test program contains a branch instruction or performs verification taking into account interrupt processing, etc., the executed instructions will be in the generated instruction order However, it is difficult to completely satisfy these restrictions by the above method. Therefore, in the fifth embodiment, it is analyzed whether the software simulation execution result includes pattern information outside verification items (in this case, instructions A and B are continuously executed), and if so, another test program is generated. It is something to do.

First, the configuration of the logic circuit verification device according to the fifth embodiment will be described with reference to FIG. FIG. 33 is a diagram illustrating a configuration of a logic circuit verification device according to the fifth embodiment of the present invention.

In FIG. 33, reference numeral 3307 denotes a test program generation unit 3 based on the software simulation execution result 3325 output from the software simulation execution unit 3301 and the non-verification item pattern information 3327 which is information on a pattern not to be verified.
A non-verification item pattern analysis unit that analyzes whether or not the test program 3323 generated in 300 includes a pattern that is not to be verified. The verification using the test program includes the non-verification item pattern analysis unit 3307. Verification execution determining means 33 for determining whether or not to perform
08, if the test program 3323 does not include a pattern not to be verified, the logic simulation executing means 3303 executes verification of the logic circuit under test using the test program 3323, Is included, the test program generation means 3300 determines to generate another test program. The other configuration is the same as that of the first embodiment, and the description is omitted here.

Hereinafter, according to the flowchart of FIG.
The processing operation of the logic circuit verification device according to the fifth embodiment will be described with reference to FIG. FIG. 34 is a flowchart showing a series of processing operations of the logic circuit verification device according to the fifth embodiment, and FIG. 36 is an output example of each unit of the logic circuit verification method according to the fifth embodiment.

In the fifth embodiment, first, at step S34
At 00, the test program 3501 (FIG. 35A) is generated by the test program generating means 3300, and then, at step S3401, the software simulation executing means 3301 executes the test program 3501 on a software simulator, and Wear simulation execution result 3502 (FIG. 35)
(B)) is output. The above processing is the same as in the first embodiment.

Next, in step S3402, the non-verification item pattern analysis means 3307 executes step S34.
01 and the non-verification item pattern information 3503 (FIG. 35) which are information on the software simulation execution result 3502 output in step S01 and the pattern not to be verified.
From (c)), it is analyzed whether or not the test program 3501 includes a pattern outside the verification item. Here, if the pattern outside the verification item is not included in the test program, in step S3403 the test program 35
A logic simulation is performed by using 01. If a pattern outside the verification item is included in the test program, the process returns to step S3400, and another test program is generated by the test program generation unit 3300. Here, specifically, in the fifth embodiment, the pattern in which the “SUB” instruction is executed after the “ADD” instruction is the non-verification item pattern information 3503 (FIG. 3).
5 (c)). From the software simulation execution result 3502 at this time,
When the execution instruction is analyzed, first the “SET” instruction, then the “SUB” instruction, the “ADD” instruction, the “SUB” instruction,
It can be seen that the “MVD” instruction is being executed. As a result, “ADD”, “SUB”, which are patterns outside the verification items,
Since the continuous execution of instructions is included in the test program 3501, the process returns to step S3400 again to generate another test program. The processing from step S3400 to step S3402 described above is repeated until a test program not including the pattern outside the verification item is generated. If a test program not including the pattern outside the verification item is generated, the process proceeds to step S3403. A logic simulation is performed using the generated test program. Steps S3403 to S340 after this
The processing in 5 is the same as in the first embodiment.

As described above, according to the fifth embodiment, it is analyzed whether or not the test program generated by using the random numbers includes the predetermined verification item and the pattern. Since another test program is regenerated until the pattern outside the verification item is no longer included, errors due to abnormal operation of the logic circuit under test due to the specifications of the logic circuit under test are eliminated, and verification efficiency is improved. It is possible to do.

Embodiment 6 Hereinafter, FIGS. 14 to 16
The sixth embodiment of the present invention will be described with reference to FIG. First, the configuration of the logic circuit verification device according to the sixth embodiment will be described with reference to FIG. FIG. 14 is a block diagram showing a configuration of a logic circuit verification device according to the sixth embodiment of the present invention.

In FIG. 14, reference numeral 1401 denotes a test program 1 generated by the test program generation means 1400.
423 is a software simulation execution unit that executes 423 on a software simulator under preset termination conditions and outputs a software simulation execution result 1425 to the data storage unit 1422.
409 is the software simulation executing means 1
A simulation end state analysis means for analyzing a simulation end state from the software simulation execution result 1425 output in 401. If the simulation end state is not a desired end state, the software simulation is executed again under different end conditions. Is what you do. Reference numeral 1410 denotes a logic simulation end condition setting unit that sets the changed end condition to the logic simulation end condition in the logic simulation execution unit 1403 when the simulation end condition is changed by the simulation end state analysis unit 1409. . The other configuration is the same as that of the first embodiment, and the description is omitted here.

Hereinafter, according to the flowchart of FIG.
The processing operation of the logic circuit verification device according to the sixth embodiment will be described with reference to FIG. FIG. 15 is a flowchart showing a series of processing operations of the logic circuit verification device according to the sixth embodiment, and FIG. 16 is an output example of each unit of the logic circuit verification method according to the sixth embodiment.

In the sixth embodiment, first, at step S15
At 00, the test program generating means 1400 outputs the random number output from the random number generator (not shown) and the test instruction information 16 of the logic circuit under test shown in FIG.
The test program 1 shown in FIG.
601 is generated and output to the data storage unit 1422. This test program generation method is the same as in the first embodiment.

Next, in step S1501, the software simulation executing means 1401 generates the test program 160 generated in step S1500.
1 is executed on the software simulator, a software simulation execution result 1602 (FIG. 16C), which is information on the executed instruction, is generated and output to the data storage unit 1422. As shown in FIG. 16C, the software simulation execution result 1602 indicates the executed instruction and a flag indicating whether the execution of the instruction has been completely completed (0: midway execution, 1: end of execution).
Is included. In the sixth embodiment, of the instructions included in the test program 1601, four instructions “SET
FR0, 1 "," MVD FR7, FR0 "," AD
D FR1, FR0, 1 "," AND FR4, FR
"0,1" is executed in one simulation cycle, and "MP
Y FR8, FR0, 1 "are executed in two simulation cycles, and the simulation end condition is set to end the simulation after the execution of four simulation cycles. In the sixth embodiment, By the software simulation executed in step S1501, an expected value 1603 (FIG. 16) used in step S1504 described below is used.
(D)) is generated and output to the data storage unit 1422.

Next, in step S1509, the simulation end state analysis means 1409 analyzes the software simulation execution result 1602 obtained in step S1501, and determines whether the simulation end state is a desired end state. If the simulation end state is not the desired end state, the process returns to step S1501, and the software simulation is performed again under different end conditions. Specifically, in the sixth embodiment, assuming that the simulation is terminated in a state where execution of a certain instruction is completely terminated, the software simulation execution result 1602
(FIG. 16 (c)) shows that the simulation is “MPY
Since the FR8, FR0, 1 "instruction has been terminated in the middle of execution, the termination condition is changed to a setting of terminating the simulation after executing five simulation cycles, and the software simulation execution means 1401 again executes the software in step S1501. Execute software simulation and execute software simulation result 1
604 (FIG. 16E) and expected value 1605 (FIG.
(F)) is generated and output to the data storage unit 1422. The end condition is set by adding or reducing an arbitrary number (here, one simulation cycle is added to five simulation cycles) to the initially set number of simulation cycles (here, four simulation cycles). Then, the setting of the end condition is changed. Then, in step S1509, the simulation end state is analyzed from the software simulation execution result 1605 (FIG. 16E), and the simulation is executed in step S1501 using the test program 1601 under the reset end condition set here. Since the four instructions have been completely completed, the process moves to step S1507.

Next, in step S1507, the new pattern number counting means 1407 uses the software simulation execution result 1604 and the verified pattern history information 1606 (FIG. 16 (g)) to generate a new pattern included in the test program 1601. Count the number of patterns. This new pattern number counting method is the same as that of the first embodiment, and the number of new patterns is 3 in the sixth embodiment.

Next, in step S1502, the new pattern number determination means 1402 determines whether or not the number of new patterns has reached step S1507.
By comparing the number of new patterns included in the test program 1601 counted in the above with an arbitrary threshold value, it is determined whether or not the verification using the test program 1601 is executed. If the number of new patterns is equal to or larger than the threshold, a logic simulation is performed in step S1503 using the test program 1601. If the number of new patterns is smaller than the threshold, another test program is generated in step S1500. Specifically, in the sixth embodiment, when the threshold is set to 3, the number of new patterns (3) obtained in step S1507 is equal to or larger than the threshold (3).
In 1503, the logic simulation executing means 14
03, a logic simulation using the test program 1601 is executed.

However, before executing the logic simulation in step S1503, in step S1510, the logic simulation end condition setting means 1410
As a result, the end condition (5
(End simulation after execution of simulation cycle) is set as an end condition of the logic simulation performed in step S1503 described later. Subsequent processing operations in steps S1503 to S1505 are the same as those in the first embodiment.

As described above, according to the sixth embodiment, when verification is performed using a test program generated using random numbers, when the simulation end state in the software simulation is not the desired end state, Since different end conditions are automatically set again and the software simulation is executed until a desired end state is obtained, it is inappropriate to compare expected values.
For example, it is possible to avoid verification in which the simulation is completed during the execution of a plurality of cycle instructions. In addition, since the end condition changed to the desired end state is automatically reflected in the end condition of the logic simulation for the verification, the execution result output by the software simulation and the execution result output by the logic simulation are compared. Can be prevented from shifting by changing the termination condition.

(Embodiment 7) Hereinafter, FIGS.
The seventh embodiment of the present invention will be described with reference to FIG. First, the configuration of the logic circuit verification device according to the seventh embodiment will be described with reference to FIG. FIG. 17 is a block diagram illustrating a configuration of a logic circuit verification device according to the seventh embodiment.

In FIG. 17, reference numeral 1709 denotes verified pattern history information 17 which is information on a verified pattern.
06 is a verified pattern history information size calculating means for calculating a required size on the data storage unit from the set number of verification items when recording 06 in the data storage unit 1722. Reference numeral 1710 denotes the verified pattern history information. 1706
Is a data storage unit size detecting means for detecting the size of the data storage unit 1722 for recording the data. The data required to record the verified pattern history information 1706 calculated by the verified pattern history information size calculating means 1709 is indicated by 1711. When the size of the storage unit 1722 exceeds the size of the data storage unit detected by the data storage unit size detection unit 1710, a warning item is notified to a verifier and verification is terminated. The other configuration is the same as that of the first embodiment, and the description is omitted here.

Next, according to the flowchart of FIG.
The processing operation of the logic circuit verification device according to the seventh embodiment will be described with reference to FIG. FIG. 18 is a flowchart showing a series of processing operations of the logic circuit verification device according to the seventh embodiment, and FIG. 19 is an output example of each unit of the logic circuit verification method according to the seventh embodiment.

In the seventh embodiment, first, at step S18
In step 09, the verified pattern history information size calculation unit 1709 calculates the size of the verified pattern history information 1706, which is information on the verified pattern, from the set number of verification items. Specifically, in the first example of the seventh embodiment, the test instruction information 1 shown in FIG.
Whether or not all eight instructions from 0 to 7 included in the 900 operate normally is set as a verification item, and the verified pattern history information 1901 (FIG. 19 (b)) includes the test instruction information 1900. Index of each instruction (0 to
For 7), it is assumed that 1-bit flag information indicating whether verified (1) or unverified (0) is included. As a result, the size of the verified pattern history information 1901 is 1
Bit × 8 (0 to 7) = 8 bits.

Next, in step S1810, the data storage unit size detection means 1710 stores the verified pattern history information 1901 in the data storage unit 1722.
Detect the size of Specifically, here, the size of the data storage unit 1722 for recording the verified pattern history information 1901 is 4 bits.

Next, in step S1811, the verified pattern history information 1 calculated in step S1809
The size (8 bits) of the data storage unit 901 is compared with the size (4 bits) of the data storage unit 1722 that records the verified pattern history information 1901 detected in step S1810. In this case, the verified pattern history information 1901 cannot be recorded in the data storage unit 1722 because the size of the verified pattern history information 1901 is larger than the size of the data storage unit 1722 that records it. Therefore, a warning is issued to the verifier that the number of verification items is too large, and the verification is terminated. It should be noted that the number of settable verification items can be calculated backward from the size of the data storage unit 1722 for recording the detected verified pattern history information and shown to the verifier.

Further, in the second example of the seventh embodiment, FIG.
Whether or not all four instructions from 0 to 3 included in the test instruction information 1902 shown in FIG. 9C operate normally is set as a verification item, and is set in the verified pattern history information 1903 (FIG. 19D). Is assumed to include 1-bit flag information indicating whether the index (0-3) of each instruction included in the test instruction information 1902 has been verified (1) or not verified (0). Thus, the size of the verified pattern history information 1903 is 1 bit × 4 (0 to 3) = 4 bits. Also, here, verified pattern history information 1
The size of the data storage unit 1722 for recording 902 is 8 bits.

Next, in step S1811, the size of the verified pattern history information 1903 (4 bits)
And the size (8 bits) of the data storage unit 1722 that records the verified pattern history information 1902. In this case, since the size of the verified pattern history information 1903 is smaller than the size of the data storage unit 1722 for recording the same, the process proceeds to the next step S1800. The following processing from step S1800 to step S1805 is the same as in the first embodiment.

As described above, according to the seventh embodiment, the size of the verified history information for recording the information on the verified pattern at the time of verification is calculated from the number of verification items set at the start of the verification. When the size becomes larger than the size of the data storage unit such as a hard disk that records pattern history information, a warning is issued and the verification is terminated. The verification is started in a state in which the number of verification items is set, and it is possible to prevent the data storage unit such as the hard disk from becoming full during the verification and causing a damage to the disk system or the like.

(Embodiment 8) Hereinafter, FIGS.
Embodiment 8 of the present invention will be described with reference to FIG. First, the configuration of the logic circuit verification device according to the eighth embodiment will be described with reference to FIG. FIG. 20 is a block diagram showing a configuration of the logic circuit verification device according to the eighth embodiment.

In FIG. 20, reference numeral 2015 denotes an expected value comparison unit 2004 in which the expected value 2024 output from the software simulation execution unit 2001 does not match the logic simulation execution result 2026 output from the logic simulation execution unit 2003. An error occurrence pattern analysis means for analyzing an error occurrence pattern;
Reference numeral 15 denotes an error analysis simulation end condition determination unit 2009, an error analysis software simulation execution unit 2010, an error analysis logic simulation execution unit 2011, an error analysis expected value comparison unit 2012, and an error analysis end determination unit. 2013 and an error analysis pattern display means 2014. Hereinafter, each unit included in the error occurrence pattern analysis unit 2015 will be described. The error analysis simulation end condition setting unit 2009 sets the simulation end condition in the analysis simulation for specifying the pattern in which the error has occurred, the end condition in the previous simulation (software simulation, logic simulation), and the expectation by the expected value comparison unit 2004. The error analysis software simulation execution means 2010 is determined from the result of the value comparison.
The test program 2 with the termination condition determined in 009
023 is executed on the software simulator, and the expected value for error analysis 2027 is output to the data storage unit 2022. The logic simulation for error analysis execution means 2011 is determined by the error analysis simulation end condition determination means 2009. The test program 2023 is executed on the logic circuit under test by a logic simulation using a logic simulator under the ending condition, and a logic simulation execution result 2028 for error analysis is output to the data storage unit 2022. The value comparison means 2012 includes an error analysis expected value 2027 output from the error analysis software simulation execution means 2010 and an error analysis logic simulation output from the error analysis logic simulation execution means 2011. Deployment execution result is to compare the 2028. The error analysis end determination means 2013 is the error analysis simulation end condition determination means 200.
9 to determine whether to end a series of error analysis processes from the error analysis expected value comparison means 2012 to the error analysis expected value comparison means 2012 based on simulation end conditions in the software simulation execution means 2001 and the logic simulation execution means 2003. The pattern display means 2014 displays an error occurrence pattern analyzed by the error analysis simulation end condition determination means 2009 to the error analysis expected value comparison means 2012.

Next, according to the flowchart of FIG.
The processing operation of the logic circuit verification device according to the eighth embodiment will be described with reference to FIG. FIG. 21 is a flowchart showing a series of processing operations of the logic circuit verification device according to the eighth embodiment, and FIG. 22 is an output example of each unit of the logic circuit verification method according to the eighth embodiment.

In the eighth embodiment, first, at step S21
00, the test program 2 shown in FIG.
200 is generated and output to the data storage unit 2022. This test program generation method is the same as in the first embodiment.

Next, in step S2101, the software simulation executing means 2001 executes the test program 220 generated in step S2100.
0 is executed on the software simulator under a certain termination condition, a software simulation execution result 2201 (FIG. 22B), which is information on the executed instruction, is obtained and output to the data storage unit 2022. Here, in the eighth embodiment, five instructions “SET FR0, 1”, “MVD FR7, F
R0 "," ADD FR1, FR0, 1 "," AND
FR4, FR0, 1 "," OR FR3, FR0, 1 "
Shall be executed in one simulation cycle,
It is assumed that the simulation end condition is set to end the simulation after four simulation cycles have been executed. In the eighth embodiment, an expected value 2202 (FIG. 22C) used in step S2104 described later is generated by software simulation executed in step S2101 and output to the data storage unit 2022.

Next, in step S2107, the software simulation execution result 2201 (FIG.
(B)), and the number of new patterns included in the test program 2200 is counted using the verified pattern history information 2203 (FIG. 22D) which is information on the verified patterns recorded in the data storage unit 2022. I do. The method of counting the number of new patterns is the same as that of the first embodiment, and the number of new patterns is 3 in the eighth embodiment.

Next, in step S2102, the new pattern number determination means 2002 executes step S210.
The number of new patterns included in the test program 2200 counted in Step 7 is compared with an arbitrary threshold value, and it is determined whether or not to execute the verification using the test program 2200. If the number of new patterns is equal to or larger than the threshold, a logic simulation is performed in step S2103 using the test program 2200. If the number of new patterns is smaller than the threshold, the process returns to step S2100 and another test program Generate Specifically, if the threshold is set to 3 in the eighth embodiment, the number of new patterns (3) counted in step S2002 is equal to or larger than the threshold (3).
Proceeding to 2103, a logic simulation using the test program 2200 is executed.

Next, in step S2103, the logic simulation executing means 2003 executes the test program 2200 (FIG. 22A) on the logic circuit under test by logic simulation using a logic simulator, and the logic simulation execution result 2204 (Figure 2
2 (e)) is output to the data storage unit 2022. However,
The termination condition of the logic simulation in step S2103 is the same as the termination condition in step S2101.

Next, in step S2104, the expected value comparing means 2004 compares the expected value 2202 (FIG. 22C) generated in step S2101 with the expected value 2202 in FIG.
Logic simulation execution result 220 generated in 103
4 (FIG. 22 (e)). This expected value comparison method is the same as that of the first embodiment.
And the logic simulation execution result 2204 are determined to be inconsistent.

Then, in step S2104, it is determined that the expected value comparison results do not match. Therefore, the process proceeds to step S2115, and the executed four instructions “SET F” are executed.
R0, 1 "," MVD FR7, FR0 "," ADD
FR1, FR0, 1 "," AND FR4, FR0,
It is analyzed which instruction of "1" caused the error.

First, in step S2109, the end condition of the error analysis simulation (software simulation and logic simulation) to be executed to analyze the error occurrence pattern is determined by the error analysis simulation end condition determining means 2009. It is determined from the end condition and the expected value comparison result. Specifically, the previous simulation end condition is “end after execution of four simulation cycles”.
(The end conditions in step S2101 and step S2103), and the previous expected value comparison result is “mismatch”
(Expected value comparison result in step S2104). As a method for determining the simulation end condition, when the previous expected value comparison result does not match, (the number of execution simulation cycles under the previous simulation end condition) − (the number of execution simulation cycles under the previous simulation end condition) Half the number of cycles)
Is the simulation end condition for analyzing the error occurrence pattern, and if the previous expected value comparison result matches, (execution simulation cycle number in the previous simulation end condition) + (execution of the previous simulation end condition) The number of cycles (half of the number of simulation cycles) is set as the end condition of the simulation for analyzing the error occurrence pattern. Here, since the expected value comparison result in step S2104, which is the previous expected value comparison result, does not match, (the number of execution simulation cycles under the previous simulation end condition (4 simulation cycles)) − (the previous simulation end condition The cycle number of half of the execution simulation cycle number (2 simulation cycles) = 2 simulation cycles is the end condition of the simulation for analyzing the error occurrence pattern.

Next, in step S 2110, software simulation execution means 201 for error analysis
0, the end condition (2
At the end of the simulation cycle, the test program 2200 is executed on the software simulator to generate an expected value for error analysis 2205 (FIG. 22F) and output it to the data storage unit 2022.

Next, in step S2111, the error analysis logic simulation executing means 2011 executes the test program 2200 under the termination condition determined in step S2109 (finished after execution of two simulation cycles) by a logic simulation using a logic simulator. Executed on the logic circuit, and executed logic analysis result for error analysis 2206 (FIG. 22 (g))
Is output to the data storage unit 2022.

In step S 2112, the error analysis expected value comparison means 2012 executes step S 2112.
Error analysis expected value 2205 generated in 2110
(FIG. 22 (f)) and the error analysis logic simulation execution result 220 output in step S2111.
6 (FIG. 22 (g)). The expected value comparison method for error analysis is the same as that in step S2104 described above, and it is determined that the expected value for error analysis 2205 and the execution result 2206 of the logic analysis for error analysis match.

Next, in step S2113, the error analysis end determination means 2013 executes step S210.
Step S210 determines whether or not to end the series of error occurrence pattern analysis processing from Step 9 to Step S2112.
The determination is made based on 1 and the end condition of the simulation (software simulation, logic simulation) in step S2103. Specifically, step S2
101 and the number of execution simulation cycles of the simulation end condition in step S2103 (4) <
= (2 n) is calculated (here, 4 <
= 2 squared so that n = 2), step S21
When Step 10 and Step S2111 have been executed n times, it is determined that the process has been completed. Here, since the number of executions of steps S2110 and S2111 is one, it is not determined that the processing is completed, and the process returns to step S2109 again.

In step S2109, the next simulation end condition is determined. Specifically, here, the previous simulation end condition is “end after execution of two simulation cycles”, and the previous expected value comparison result in step S2112 is “match”. The number of execution simulation cycles (2 simulation cycles) of the termination condition) + (half the number of execution simulation cycles (1 simulation cycle) of the previous simulation termination condition) = 3 simulation cycles is set as the termination condition.

Next, step S2110 and step S21
In step 2111, the end condition determined in step S2109 (end after execution of three simulation cycles)
And simulate each with the expected value for error analysis 2
207 (FIG. 22 (h)) and an error analysis logic simulation execution result 2208 (FIG. 22 (i)) are output to the data storage unit 2022.

Next, in step S 2112, the error analysis expected value 2207 is compared with the error analysis logic simulation execution result 2208. This error analysis expected value comparison method may be the same as that in step S2104 described above. Here, it is determined that the error analysis expected value 2207 matches the error analysis logic simulation execution result 2208.

Then, in step S2113, it is determined whether or not the above-described series of error occurrence pattern analysis processing ends. Here, since the number of executions of steps S2110 and S2111 is two, the error occurrence pattern analysis processing ends.

Next, in step S2114, the error occurrence pattern display means 2014 displays the information in step S2114.
An error occurrence pattern is determined and displayed from the simulation end condition determined in 109 and the expected value comparison result in step S2112. This error occurrence pattern determination method is such that if the expected value comparison result in step S2112 is “match”, the instruction next to the last instruction executed under the simulation end condition determined in step S2109 is replaced with the error occurrence pattern. And step S21
If the expected value comparison result in step 12 is “mismatch”, the last instruction executed under the simulation end condition determined in step S2109 is set as the error occurrence pattern.
Here, since the expected value comparison result in step S2112 is “match”, the instruction “AN” next to the last instruction executed under the simulation end condition (terminated after executing three simulation cycles) determined in step S2109.
DFR4, FR0, 1 "are error occurrence patterns.
Note that the series of verification processing is completed as described above. For example, the series of verification processing may be repeatedly executed up to a certain end condition such as a designated number of times.

As described above, according to the eighth embodiment, the logic circuit verification method further includes an error occurrence pattern analysis step of analyzing which pattern of the test program has caused the error, and the error generation pattern analysis step is performed using random numbers. If the expected value and the logic simulation execution result do not match (error) in the verification with the test program, the system automatically analyzes and displays which instruction in the test program caused the error. The error analysis work for the verifier can be reduced, and the verification efficiency can be improved.

Embodiment 9 Hereinafter, FIGS. 23 to 25 will be described.
Embodiment 9 of the present invention will be described with reference to FIG. During verification of the logic circuit, there is a problem in the logic circuit, and an error may occur when a certain verification pattern is executed. At that time, if the problem included in the logic circuit can be repaired immediately, the same error does not occur even if the verified pattern in which the error has occurred is executed again. However, the designer of the problematic circuit may have other tasks, or it may take time to check whether the repair of the problematic circuit will cause another problem to spread to other circuits. May not be renovable immediately. Then, if the same verification pattern as the verification pattern in which the error has occurred is executed before the repair of the problematic circuit, an error occurs each time, and the verification efficiency deteriorates. In the ninth embodiment, information on an error occurrence pattern generated in the previous verification is recorded, and execution of a test program including the error occurrence pattern is stopped, so that a problematic circuit is repaired. In the meantime, verification of another circuit is advanced.

First, the configuration of the logic circuit verification device according to the ninth embodiment will be described with reference to FIG.
FIG. 23 shows a configuration of a logic circuit verification device according to the ninth embodiment of the present invention. In FIG. 23, 231
8 is based on the software simulation execution result 2325 output by the software simulation execution means 2301 and the error occurrence pattern history information 2317 stored in the data storage unit 2322 and relating to the error occurrence pattern generated by the previous verification. It is detected whether the test program 2323 generated by the test program generation means 2300 includes an error occurrence pattern, and if the error generation pattern is not included, the process proceeds to the new pattern number counting means 2307. If an occurrence pattern is included, an error occurrence pattern determination unit that determines that another test program is to be generated again in the test program generation unit 2300, and 2316 is an error occurrence pattern analysis unit 231. From the information on the error occurrence pattern is analyzed in an error occurrence pattern history information 2
This is an error occurrence pattern history information updating unit that updates 317. The other configuration is the same as that of the eighth embodiment, and the description is omitted.

Next, according to the flowchart of FIG.
The processing operation of the logic circuit verification device according to the ninth embodiment will be described with reference to FIG. FIG. 24 is a flowchart showing a series of operation processing of the logic circuit verification device according to the ninth embodiment, and FIG. 25 is an output example of each unit of the logic circuit verification method according to the ninth embodiment.

In the ninth embodiment, first, at step S24
At 00, the test program generation means 2300 generates the test program 2500 shown in FIG. This test program generation method is the same as in the eighth embodiment.

Next, in step S2401, the software simulation executing means 2301 generates the test program 250 generated in step S2400.
0 is executed on the software simulator under a certain end condition, and a software simulation execution result 2501 (FIG. 25B), which is information on the executed instruction, is output to the data storage unit 2322. Here, Embodiment 9
Now, the five instructions “SET FR0,1”, “MVD FR7, FR” included in the test program 2500
0 "," ADD FR1, FR0, 1 "," AND F
R4, FR0, 1 "and" OR FR3, FR0, 1 "are executed in one simulation cycle, and the simulation end condition is set to end the simulation after executing four simulation cycles. In the ninth embodiment, an expected value 2502 (FIG. 25 (c)) used in step S2404, which will be described later, is generated by a software simulation executed in step S2401.
322.

Next, in step S2418, the error occurrence pattern determination means 2318 executes the software simulation execution result 2501 and error occurrence pattern history information 2503 (FIG. 25 (d)) which is information on the error occurrence patterns that have occurred so far. )), It is detected whether or not the test program 2500 includes an error occurrence pattern that has occurred so far.
Specifically, here, as the error occurrence pattern that has already occurred, “AN
DFR4, FR0, 1 ”are recorded. In the ninth embodiment,“ AN ”is included in the software simulation execution result 2501 shown in FIG.
Since the DFR4, FR0, 1 "instruction is included, the test program 2500 is executed in step S2418.
Is determined to include an error occurrence pattern, and the process returns to step S2400 to return to another test program 2504.
(FIG. 25E) is generated and output to the data storage unit 2322. In step S2401, the software program is executed on the software simulator using the regenerated test program 2504, and the software simulation execution result 2505 (FIG. 25F) and the expected value 250
6 (FIG. 25G) to the data storage unit 2322. Software simulation execution result 2 executed using the regenerated test program 2504
Since 505 does not include the “AND FR4, FR0, 1” instruction stored in the error occurrence pattern history information 2503, it is determined in step S2418 that the test program 2504 does not include the error occurrence pattern. It moves to S2407. Subsequent processing from step S2407 to step S2415 is the same as in the eighth embodiment.

In the ninth embodiment, step S240 is performed.
0 to the result of the processing in step S2415, step S2
In 404, the expected value 2506 (FIG. 25 (g)) output in step S2401 and the logic simulation execution result 2507 (FIG. 2) output in step S2403
5 (h)) is not the same, and the error occurrence pattern analyzed in step S2415 corresponds to “OR FR3,” in the test program 2504.
Assume that the instruction is a FR0,1 "instruction.

Next, in step S2416, the "ORFR3, FR0, 1" instruction is recorded in the error occurrence pattern history information 2317 from the error occurrence pattern analyzed in step S2415 by the error occurrence pattern history information updating means 2316. Error history information 2 after
508 (FIG. 25 (i)). Note that the series of verification processing is completed as described above. For example, the series of verification processing may be repeatedly executed up to a certain end condition such as a designated number of times.

As described above, according to the ninth embodiment, a verified pattern in which an error has occurred once in verification with a test program generated using random numbers is recorded as error occurrence pattern history information, and the error Until the end of the repair of the circuit that is the cause, the verification using the test program containing the pattern that causes the same error recorded in the error occurrence pattern history information is stopped, so that the same It is possible to prevent the verification efficiency from being deteriorated due to the occurrence of an error a plurality of times.

Embodiment 10 Hereinafter, FIGS. 26 to 2
Embodiment 10 of the present invention will be described with reference to FIG. First, the configuration of the logic circuit verification device according to the tenth embodiment will be described with reference to FIG. FIG.
FIG. 15 is a diagram showing a configuration of a logic circuit verification device according to the tenth embodiment.

In FIG. 26, when the expected value comparing means 2604 indicates that the expected value 2624 of the software simulation executing means 2601 and the logic simulation execution result 2626 of the logical simulation executing means 2603 do not match, an error 2609 is generated. This is an error occurrence test program recording unit that records, in the error occurrence test program information 2610, a test program including an occurrence pattern or information for regenerating the test program. The other configuration is the same as that of the first embodiment, and the description is omitted here.

Next, according to the flowchart of FIG.
Regarding the logic circuit verification device according to the tenth embodiment,
This will be described with reference to FIG. FIG. 27 is a flowchart showing a series of processing operations of the logic circuit verification device according to the tenth embodiment, and FIG.
5 is an output example of each unit of the logic circuit verification method at 0.

In the tenth embodiment, first, at step S2
At 700, a random number generated from a random number generator (not shown) by the test program generation means 2600 and the test instruction information 2 of the logic circuit under test shown in FIG.
Using 800, a test program 2801 shown in FIG. 28B is generated and output to the data storage unit 2622. This test program generation method is the same as in the first embodiment.

Next, in step S2701, the software simulation executing means 2601 executes the test program 280 generated in step S2700.
1 (FIG. 28 (b)) is executed on a software simulator, and a software simulation execution result 2802 (FIG. 28 (c)), which is information on the executed instruction, is output to the data storage unit 2622. Embodiment 1
In the case of 0, the software simulation executed in the step S2701 causes a step S2704 to be described later.
Then, an expected value 2803 (FIG. 28D) to be used is generated and output to the data storage unit 2622.

Next, in step S2707, the software simulation execution result 2802 (FIG. 28 (c)) is
The number of new patterns included in the test program 2801 is counted using verified pattern history information 2804 (FIG. 28E) that is information on verified patterns. The method of counting the number of new patterns is the same as that of the first embodiment, and the number of new patterns is three in the tenth embodiment.

Next, in step S2702, the new pattern number determination means 2602 executes step S270.
The number of new patterns included in the test program 2801 counted in step 7 is compared with an arbitrary threshold value, and it is determined whether or not to execute the verification using the test program 2801 (FIG. 28B). This determination method is the same as in the first embodiment. Specifically, in the tenth embodiment, the threshold is set to 3, and the number of new patterns (3) counted in step S2707 is equal to or larger than the threshold (3).
A logic simulation using 801 is executed.

Next, in step S2703, the logic simulation executing means 2603 executes the test program 2801 (FIG. 28 (b)) on the logic circuit under test by logic simulation using a logic simulator, and the logic simulation execution result 2805 (Figure 2
8 (f)).

Next, in step S 2704, the expected value comparison means 2604 compares the expected value 2803 (FIG. 28D) generated in step S 2701 with the expected value
Logic simulation execution result 280 generated in 703
5 (FIG. 28 (f)). This expected value comparison method is the same as that of the first embodiment.
03 and the logic simulation execution result 2805 are determined to be inconsistent.

In step S 2704, the expected value 2803
And the logic simulation result 2805 are determined to be inconsistent, so that in step S2709
The error occurrence test program recording means 2609 stores a test program 2801 including an error occurrence pattern or information capable of regenerating the test program 2801,
It is recorded in the data storage unit 2622 as the error occurrence test program information 2610. In the tenth embodiment, only the index in the test instruction information 2800 corresponding to the instruction included in the test program 2801 is recorded. Specifically, the test program 2801 (FIG. 28)
(B)) contains five instructions “SETFR0,1”,
"MVD FR7, FR0", "ADD FR1, FR
0, 1 "," OR FR3, FR0, 1 "," SUB
Test instruction information 2800 corresponding to FR2, FR0, 1 "
Indexes 0, 7, 1, 3, 2 in FIG.
Is recorded in the error occurrence test program information 2610. Example 2806 of error test program information after recording
Is shown in FIG.

The original test program 2801 is reproduced, for example, by recording the entire test program 2801 in the error occurrence test program information 2610 or by recording the type of random number used when the test program 2801 was generated. The same effect can be obtained as long as the information can be generated. Note that a series of verification processes is completed as described above. For example, the above-described series of verification processes are repeatedly executed until a certain end condition such as a designated number of times, and information on a plurality of test programs is recorded in the error occurrence test program information. You may do it.

As described above, according to the tenth embodiment,
When verifying with a test program generated using random numbers, error test program information, which is information that can regenerate the test program in which an error occurred, is automatically recorded and saved. After completion of the repair of the failure of the circuit, re-verification using only the test program in which the error has occurred becomes easy.

(Embodiment 11) FIGS. 29 to 3
Embodiment 11 of the present invention will be described with reference to FIG. If an error occurs during verification using a test program that uses random numbers, the circuit that caused the error is repaired, and then the test program that caused the error before the repair was run to check the operation of the repaired circuit Need to be re-verified using In the eleventh embodiment, first, a test program is created and verified, or a test program in which an error has occurred in the previous verification is regenerated and verified to select a circuit. The re-verification can be performed using only a test program in which an error has occurred before.

First, the eleventh embodiment will be described with reference to FIG.
, The configuration of the logic circuit verification device will be described.
FIG. 29 is a block diagram showing a configuration of a logic circuit verification device according to Embodiment 11 of the present invention.

In FIG. 29, reference numeral 2911 denotes a test program used for verification,
0, or an error generation test program generation unit 2912, which will be described later, selects whether to generate a test program in which an error has occurred from error generation test program information 2910, which is information that can be regenerated. And 291
Reference numeral 2 denotes an error generation test program generation unit that generates a test program 2923 to be verified from the error generation test program information 2910 and stores it in the data storage unit 2922. Other configurations are the same as those in the first embodiment.
The description is omitted here.

Next, according to the flowchart of FIG.
The processing operation of the logic circuit verification device according to the eleventh embodiment will be described with reference to FIG. FIG.
32 is a flowchart illustrating a series of processing operations of the logic circuit verification device according to the eleventh embodiment. FIG. 31 illustrates an output example of each unit of the logic circuit verification method according to the eleventh embodiment.

In the eleventh embodiment, first, in step S3
In step 011, the test program generation selection means 291
According to 1, the test program used for verification is
It is selected whether to generate the data in 3000 or in step S3012. In the eleventh embodiment, it is assumed that the verifier selects either one.
It is assumed that has been selected.

Next, in step S3012, the error occurrence test program generating means 2912 causes the error occurrence test program information 3100 (FIG. 31A).
From the test program 3101 to be verified (FIG. 31)
(B)) is generated. In the eleventh embodiment, the error occurrence test program information 3100 includes the indexes 0, 7 in the test instruction information 3102 (FIG. 31C) corresponding to the instruction included in the test program in which the error has occurred.
It is assumed that only 1, 3, and 2 are recorded, and in this step S3012, the index and the test instruction information 310
2 (FIG. 31 (c)) and the test program 3101
(FIG. 31B) is generated and output to the data storage unit 2922. Specifically, the test instruction information 3102 (FIG. 31)
In (c)), the instruction “SE” whose index is “0”
TFR0,1 "is the first instruction of the test program, and thereafter, similarly, instructions" MVDFR7, FR0 "," ADD FR1, F2 "corresponding to indexes 7, 1, 3, and 2
R0,1 "," OR FR3, FR0,1 "," SUB
FR2, FR0, 1 "are instructions of the test program.

The processing from step S3001 to step S3005 thereafter is the same as in the first embodiment. However, in step S3011, step S30
If 12 is selected and the purpose of verification is re-verification using a test program in which an error has occurred in the past, it is preferable that the processing performed in steps S3007 and S3002 be stopped.

The error occurrence test program information 2
When information regarding a plurality of test programs in which an error has occurred is recorded in 910, the series of processes described above can be performed on the plurality of test programs, and verification can be performed continuously.

As described above, according to the eleventh embodiment,
First, a test program that uses a random number to generate a test program, selects a test program that uses normal random numbers, or regenerates an error-generated test program to select whether to perform verification Since the steps are provided, it is easy to perform re-verification using only the test program in which the error has occurred, after completing the repair of the circuit which is the cause of the error.

[0154]

As described above, according to the logic circuit verification method of the first aspect of the present invention, a test program is generated using random numbers in a verification method for verifying a logic circuit under test by logic simulation. A test program generation step, a software simulation execution step of executing the test program on a software simulator and outputting a software simulation execution result, and a verified pattern being information on the software simulation execution result and the verified pattern. A verification execution determining step of determining whether to execute verification of the logic circuit under test using the test program based on the history information; and the test program when the verification execution determining step determines that the verification is to be performed. The logical simulation A logic simulation execution step of executing the logic simulation test result on the logic circuit under test and outputting a logic simulation execution result; an expectation value comparison step of comparing the logic simulation execution result with an expectation value; and the expectation value comparison step. And a verified pattern history information updating step of updating the verified pattern history information with information on a verified pattern included in the test program verified in the logic simulation executing step, when the logical simulation execution result matches. Test program that contains many duplicate patterns,
By not executing the simulation on a logic simulation with a slow verification speed, the verification time can be lengthened.

Further, according to the logic circuit verification method of the present invention, in the logic circuit verification method of the first aspect, the verification execution determining step includes the step of: The number of new patterns included is detected, and when the number of new patterns is equal to or greater than a certain threshold, it is determined that verification is to be performed. Therefore, a test program including many duplicated patterns is detected and the verification speed is low. It can be prevented from being executed on the logic simulation.

According to a third aspect of the present invention, in the logic circuit verifying method of the second aspect, the test program determined not to execute the verification in the verification execution determining step; and And a test program storing step of storing at least one or more of the software simulation execution results. When the verification execution determining step determines that the verification is not to be executed continuously for a given number of times, the test program A test program including the largest number of the new patterns is selected from the test programs saved in the saving step, and the verification is performed using the selected test program. Are generated consecutively, the number of new patterns in the Controlled to perform verification using a large test program, it can be avoided loss verification time by repeating the between test program generation and new pattern number decision indefinitely.

According to a fourth aspect of the present invention, in the logic circuit verifying method of the first aspect, the step of determining whether to execute the verification is performed based on the result of the software simulation. Since the number of new resources used is detected and it is determined that the verification is executed when the number of new resources used is equal to or greater than a certain threshold value, a test program including a large number of duplicate resources is detected, and a logic simulation with a low verification speed is performed. Can be prevented from being executed.

According to the logic circuit verification method of the present invention, in the logic circuit verification method of the first aspect, the verification execution determining step includes the step of: The number of executions of each instruction is detected, and when the same instruction in the test program is repeatedly executed by a certain threshold or more, it is determined that verification is not to be executed. Therefore, a test program that repeatedly executes the same instruction is detected. Therefore, it can be prevented from being executed on a logic simulation having a low verification speed.

Further, according to the logic circuit verification method of the present invention, in the logic circuit verification method of the first aspect, the verification execution determining step includes the step of determining whether the test program is executed based on the software simulation execution result. It is analyzed whether the logic circuit under test includes a pattern outside the verification item which is a pattern not to be verified, and when the logic circuit under test includes the pattern outside the verification item, it is determined that the verification is not performed. The logic circuit under test does not operate abnormally due to the specification and no error occurs, and the verification efficiency can be improved.

According to the logic circuit verification method of the present invention, in the logic circuit verification method of the present invention, a simulation end state for analyzing the simulation end state based on the software simulation execution result. An analysis step is further provided, and when the simulation end state is not the desired end state, the software simulation is repeatedly executed under different end conditions until the simulation end state becomes a desired end state. Can avoid inappropriate verification, for example, a simulation that is terminated during execution of a multi-cycle instruction.

Further, according to the logic circuit verification method of the present invention, in the logic circuit verification method of the present invention, the termination condition in which the simulation termination state becomes a desired termination state is determined by the logic simulation. Since a logic simulation end condition setting step of setting as a logic simulation end condition in the step is further provided, the execution result output by the software simulation and the execution result output by the logic simulation change the simulation end condition. This can prevent the displacement.

According to the logic circuit verification method of the ninth aspect of the present invention, in the logic circuit verification method of the first aspect, it is determined whether or not the set number of verification items is larger than a certain threshold value. The method further includes a verification item number determination step of determining that verification is not to be performed when the number of verification items is large, so that a verifier starts verification in a state where a large number of verification items are erroneously set. Can be prevented from becoming full and causing damage to the disk system or the like.

According to a tenth aspect of the present invention, in the logic circuit verifying method according to the ninth aspect, the threshold value is determined by the size of a data storage unit for storing the verified pattern history information. Therefore, it is possible to prevent the verification from starting by setting the number of verification items exceeding the size that the verifier can erroneously record data.

Further, according to the logic circuit verification method of the present invention, in the logic circuit verification method of the first aspect, in the expected value comparing step, the logical simulation execution result and the expected value may be different from each other. In the case of a mismatch, an error occurrence pattern analysis step for analyzing which pattern in the test program caused the error is further provided, so that it is possible to automatically determine which instruction in the test program caused the error. The error analysis work required for the verifier to be analyzed and displayed by the user can be reduced, and the verification efficiency can be improved.

According to the logic circuit verification method of the twelfth aspect of the present invention, in the logic circuit verification method of the eleventh aspect, error occurrence pattern history information, which is information of an error occurrence pattern that has occurred so far, is stored. Based on an error occurrence pattern determination step of determining to execute verification when the error occurrence pattern is not included in the test program, and information on the error occurrence pattern analyzed in the error occurrence pattern analysis step,
Since the method further includes an error occurrence pattern history information updating step of updating the error occurrence pattern history information, it is possible to avoid a decrease in verification efficiency due to occurrence of the same error a plurality of times.

Further, according to the logic circuit verification method of the present invention, in the logic circuit verification method of the first aspect, in the expected value comparison step, the logic simulation execution result and the expected value are different. In case,
An error occurrence test program recording step of recording the test program or error occurrence test program information, which is information capable of regenerating the test program, is further provided, so that repair of a defect of a circuit causing an error has been completed. Later, it can be re-verified by the test program in which the error occurred.

According to the logic circuit verification method of the present invention, in the logic circuit verification method of the present invention, an error generation test program which is information capable of regenerating a test program in which an error has occurred. From the information,
An error generation test program generation step of generating an error generation test program is further provided, and a test program used for verification is generated in the test program generation step or in the error generation test program generation step. Whether to perform verification using a normal test program or to perform re-verification using only the test program in which an error occurred after completing the repair of the circuit that caused the error, etc. Can be selected.

Further, according to the logic circuit verification device of the present invention, in a verification device for verifying a logic circuit under test by logic simulation, a verification means for verifying the logic circuit under test is realized. A verification unit storage device for storing a program, an execution device for executing the program stored in the verification unit storage device, and an output or referenced when the execution device executes the program stored in the verification unit storage device. A data storage device for storing data stored in the data storage device, wherein the verification device stored in the verification device storage device generates a test program using a random number and stores the test program in the data storage device; The test program is executed on a software simulator, and the result of the software simulation Software simulation execution means stored in a data storage device, and verification of the logic circuit under test using the test program based on the software simulation execution result and verified pattern history information that is information on the verified pattern. Verification execution determining means for determining whether or not to execute the test program, and when the verification execution determining means determines that the verification is to be executed, the test program is executed on a logic circuit under test by a logic simulation, and the logic simulation execution result is obtained. In the data storage device, an expected value comparing unit that compares the logical simulation execution result with an expected value, and the expected value and the logical simulation execution result match in the expected value comparing unit. The verified Pattern history information updating means for updating the pattern history information with the information on the verified patterns included in the test program, so that a test program containing many duplicated patterns can be executed on a logic simulator having a low verification speed. It is possible to provide a verification device that can suppress an increase in verification time due to the execution of the verification device.

According to the logic circuit verification device of the present invention, in the logic circuit verification device of the present invention, the verification execution determining means may determine whether the test program is to be executed based on the software simulation execution result. New pattern number counting means for detecting the number of new patterns included, and new pattern number determining means for determining whether the number of new patterns detected by the new pattern number counting means is equal to or greater than a certain threshold value, Since it is determined whether or not to execute the verification of the logic circuit under test using the test program based on the determination result of the pattern number determination unit, a test program including many duplicated patterns is detected, and the verification speed is low. It is possible to suppress the increase in verification time by executing on a logic simulator. It is possible to provide a that verification device.

Further, according to the logic circuit verification device of the present invention, in the logic circuit verification device of the present invention, the test program determined not to execute the verification by the verification execution determining means; A test program storage unit for storing at least one or more of the software simulation execution results in the data storage device; and when the verification execution determination unit determines that the verification is not to be performed continuously for an arbitrary number of times,
The test program including the largest number of the new patterns is selected from among the test programs stored by the test program storage unit, and the verification is performed using the selected test program. When a small number of test programs are generated consecutively, control is performed so that the test program with the largest number of new patterns among them is used for verification, and the test program generation and the determination of the number of new patterns are repeated indefinitely. Verification device that can avoid a loss of verification time due to the above.

According to the logic circuit verification device of the present invention, in the logic circuit verification device of the present invention, the verification execution determining means may determine the test program based on the software simulation execution result. New resource number counting means for detecting a new resource usage number, and new resource number determination means for determining whether the new resource usage number detected by the new resource number counting means is above a certain threshold, A determination is made as to whether or not to execute the verification of the logic circuit under test using the test program based on the determination result of the number determination means. Therefore, a test program containing many duplicated resources is detected, and a logic having a low verification speed is detected. The increase in verification time due to running on the simulator can be suppressed. It is possible to provide a verification device.

Further, according to the logic circuit verification device of the present invention, in the logic circuit verification device of the present invention, the verification execution determining means may determine whether or not the test program is executed based on the software simulation execution result. Instruction execution number counting means for detecting the number of executions of each of the instructions; and instruction execution number determination means for determining whether the execution number detected by the instruction execution number counting means is smaller than a certain threshold value. A determination is made as to whether or not to execute the verification of the logic circuit under test using the test program, based on the determination result of the number-of-times determination means. Provides a verification device that can suppress an increase in verification time due to execution on a simulator Rukoto can.

According to the logic circuit verification device of the present invention, in the logic circuit verification device of the present invention, the verification execution judging means may execute the test program based on the software simulation execution result. It is analyzed whether the logic circuit under test includes a pattern outside the verification item which is a pattern not to be verified, and when the logic circuit under test includes the pattern outside the verification item, it is determined that the verification is not performed. It is possible to provide a verification device capable of preventing the logic circuit under test from operating abnormally due to the specification and causing an error and improving the verification efficiency.

According to the logic circuit verification device of the present invention, in the logic circuit verification device of the present invention, a simulation end state analyzing means for analyzing a simulation end state from the software simulation execution result. The simulation end state analysis means repeats the execution of the software simulation under different end conditions until the simulation end state is not the desired end state until the simulation end state is a desired end state. It is possible to provide a verification device that can avoid verification that is inappropriate for performing a value comparison, such as ending a simulation during execution of a multi-cycle instruction.

Further, according to the logic circuit verification device of the present invention, in the logic circuit verification device of the present invention, the termination condition in which the simulation termination state becomes a desired termination state is determined by the logic simulation. A logic simulation end condition setting means for setting as a logic simulation end condition in the execution means is further provided, so that the end condition obtained by changing the simulation end state to a desired end state is automatically reflected on the logic simulation end condition. By performing the verification by performing the verification, it is possible to provide a verification device that can prevent the execution result output by the software simulation from being shifted from the execution result output by the logic simulation.

According to the logic circuit verification device of the present invention, it is determined whether or not the set number of verification items is larger than a certain threshold value. When the number of verification items is large, a verification item number determination unit that determines that verification is not to be performed is further provided. Start,
It is possible to provide a verification device that can prevent a storage device such as a hard disk from becoming full during verification and causing damage to a disk system or the like.

According to the logic circuit verification device of the present invention, in the logic circuit verification device of the present invention, the threshold value is determined by the size of a data storage unit for storing the verified pattern history information. Therefore, it is possible to provide a verification device that can prevent the verification from being started by setting the number of verification items exceeding the size that the verifier can erroneously record data.

According to the logic circuit verification device of the present invention, in the logic circuit verification device of the present invention, the expected value comparing means does not match the logic simulation execution result with the expected value. In the case of
Since an error occurrence pattern analysis means for analyzing which pattern in the test program caused the error is further provided, it is possible to reduce the error analysis work for the verifier and improve the verification efficiency. .

According to the logic circuit verification device of the twenty-sixth aspect of the present invention, in the logic circuit verification device of the twenty-fifth aspect, the error occurrence pattern analysis means includes an error analysis device for specifying a pattern in which an error has occurred. Executing the test program on a software simulator with the error analysis simulation end condition determining means for determining the simulation end condition for the simulation for the error and the end condition determined by the error analysis simulation end condition determining means for the error analysis; The test program on the logic circuit under test by a logic simulation under the end condition determined by the error analysis software simulation executing means for storing the expected value for use in the data storage unit and the error analysis simulation end condition determining means. Real An error analysis logic simulation execution unit that stores the error analysis logic simulation execution result in the data storage unit; the error analysis expected value output by the error analysis software simulation execution unit; Error analysis expected value comparison means for comparing the error analysis logic simulation execution result output by the analysis logic simulation execution means; error analysis end determination means for determining whether to end the error analysis processing; Error analysis pattern display means for displaying the generated error occurrence pattern, so that when a test program generated using random numbers does not match an expected value and a logic simulation execution result (error) in verification, Which in the test program Automatically analyzing whether an error has occurred in the decree, it is possible to provide a verification device for displaying.

According to the logic circuit verification device of claim 27 of the present invention, in the logic circuit verification device of claim 25 or claim 26, an error occurrence information which is information on an error occurrence pattern which has occurred so far is provided. Based on the pattern history information, an error occurrence pattern determination unit that determines to execute verification when the error occurrence pattern is not included in the test program, and information on the error occurrence pattern analyzed by the error occurrence pattern analysis unit. The error occurrence pattern history information updating means for updating the error occurrence pattern history information is further provided, so that a verified pattern in which an error has once occurred in verification with a test program generated using random numbers is used as history information. Record and modify the circuit that is causing the error Up to the point of such ends, by stopping the verification using a pattern for generating the same error, it is possible to provide a verification device to avoid deterioration of the verification efficiency due to the same error occurs more than once.

According to the logic circuit verification device of the present invention, in the logic circuit verification device of the present invention, the expected value comparing means does not match the result of the logic simulation execution with the expected value. In the case of
An error occurrence test program recording unit for recording the test program or error occurrence test program information, which is information capable of regenerating the test program, in the data recording device is further provided. It is possible to provide a verification device that can perform re-verification using a test program in which an error has occurred after completion of repair or the like.

According to the logic circuit verification device of the present invention, in the logic circuit verification device of the present invention, an error occurrence test program which is information capable of regenerating a test program in which an error has occurred. From the information, an error occurrence test program generation means for generating an error occurrence test program and a test program to be used for verification are selected by the test program generation means or by the error generation test program generation means. Provided is a verification device that further includes a test program generation selection unit, so that re-verification using only a test program in which an error has occurred can be easily performed after repair of a failure of a circuit causing an error has been completed. Can be.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an outline of a basic process of the present invention.

FIG. 2 is a diagram illustrating a configuration of a logic circuit verification device according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing a series of processing operations of the logic circuit verification device according to the first embodiment of the present invention.

FIG. 4 is a specific example of data used in the first embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a logic circuit verification device according to a second embodiment of the present invention.

FIG. 6 is a flowchart showing a series of processing operations of the logic circuit verification device according to the second embodiment of the present invention.

FIG. 7 is a specific example of data used in Embodiment 2 of the present invention.

FIG. 8 is a diagram showing a configuration of a logic circuit verification device according to a third embodiment of the present invention.

FIG. 9 is a flowchart showing a series of processing operations of the logic circuit verification device according to the third embodiment of the present invention.

FIG. 10 is a specific example of data used in Embodiment 3 of the present invention.

FIG. 11 is a diagram showing a configuration of a logic circuit verification device according to a fourth embodiment of the present invention.

FIG. 12 is a flowchart illustrating a series of processing operations of the logic circuit verification device according to the fourth embodiment of the present invention.

FIG. 13 is a specific example of data used in Embodiment 4 of the present invention.

FIG. 14 is a diagram illustrating a configuration of a logic circuit verification device according to a sixth embodiment of the present invention.

FIG. 15 is a flowchart showing a series of processing operations of the logic circuit verification device according to the sixth embodiment of the present invention.

FIG. 16 is a specific example of data used in Embodiment 6 of the present invention.

FIG. 17 is a diagram illustrating a configuration of a logic circuit verification device according to a seventh embodiment of the present invention.

FIG. 18 is a flowchart showing a series of processing operations of the logic circuit verification device according to the seventh embodiment of the present invention.

FIG. 19 is a specific example of data used in Embodiment 7 of the present invention.

FIG. 20 is a diagram illustrating a configuration of a logic circuit verification device according to an eighth embodiment of the present invention.

FIG. 21 is a flowchart showing a series of processing operations of the logic circuit verification device according to the eighth embodiment of the present invention.

FIG. 22 is a specific example of data used in the eighth embodiment of the present invention.

FIG. 23 is a diagram illustrating a configuration of a logic circuit verification device according to a ninth embodiment of the present invention.

FIG. 24 is a flowchart showing a series of processing operations of the logic circuit verification device according to the ninth embodiment of the present invention.

FIG. 25 is a specific example of data used in Embodiment 9 of the present invention.

FIG. 26 is a diagram showing a configuration of a logic circuit verification device according to a tenth embodiment of the present invention.

FIG. 27 is a flowchart showing a series of processing operations of the logic circuit verification device according to the tenth embodiment of the present invention.

FIG. 28 is a specific example of data used in the tenth embodiment of the present invention.

FIG. 29 is a diagram illustrating a configuration of a logic circuit verification device according to an eleventh embodiment of the present invention.

FIG. 30 is a flowchart showing a series of processing operations of the logic circuit verification device according to the eleventh embodiment of the present invention.

FIG. 31 is a specific example of data used in Embodiment 11 of the present invention.

FIG. 32 is a flowchart showing a test method of a conventional data processing device.

FIG. 33 is a diagram showing a configuration of a logic circuit verification device according to a fifth embodiment of the present invention.

FIG. 34 is a flowchart showing a series of processing operations of the logic circuit verification device according to the fifth embodiment of the present invention.

FIG. 35 is a specific example of data used in the fifth embodiment of the present invention.

[Explanation of symbols]

200, 500, 800, 1100, 1400, 170
0, 2000, 2300, 2600, 2900, 330
0 Test program generating means 201, 501, 801, 1101, 1401, 170
1, 2001, 2301, 2601, 2901, 330
1 Software simulation execution means 202, 502, 1402, 1702, 2002, 23
02, 2602, 2902 New pattern number determination means 203, 503, 803, 1103, 1403, 170
3, 2003, 2303, 2603, 2903, 330
3 logic simulation execution means 204, 504, 804, 1104, 1404, 170
4, 2004, 2304, 2604, 2904, 330
4 Expected value comparison means 205, 505, 805, 1105, 1405, 170
5, 2005, 2305, 2605, 2905, 330
5 verified pattern history information updating means 206, 506, 806, 1106, 1406, 170
6, 2006, 2306, 2606, 2906, 330
6 verified pattern history information 207, 507, 1407, 1707, 2007, 23
07, 2607, 2907 New pattern number counting means 208, 508, 808, 1108, 1408, 170
8, 2008, 2308, 2608, 2908, 330
8 Verification execution determination means 220, 520, 820, 1120, 1420, 172
0, 2020, 2320, 2620, 2920, 332
0 Verification means storage unit 221, 521, 821, 1121, 1421, 172
1, 2021, 2321, 2621, 2921, 332
1 CPU 222, 522, 822, 1122, 1422, 172
2, 2022, 2322, 2622, 2922, 332
2 Data storage unit 223, 523, 823, 1123, 1423, 172
3, 2023, 2323, 2623, 2923, 332
3 Test programs 224, 524, 824, 1124, 1424, 172
4, 2024, 2324, 2624, 2924, 332
4 Expected value 225, 525, 825, 1125, 1425, 172
5, 2025, 2325, 2625, 2925, 332
5 Software simulation execution results 226, 526, 826, 1126, 1426, 172
6, 2026, 2326, 2626, 2926, 332
6 Logic simulation execution result 509 Test program storage means 527 Test program storage information 802 New resource number determination means 807 New resource number counting means 1102 Instruction execution number determination means 1107 Instruction execution number counting means 1409 Simulation end state analysis means 1410 Logical simulation end condition Setting means 1709 Verified pattern history information size calculation means 1710 Data storage unit size detection means 1711 Verification item number determination means 2009 Error analysis simulation end condition determination means 2010 Error analysis software simulation means 2011 Error analysis logic simulation means 2012 Error Analysis expected value comparison means 2013 Error analysis end determination means 2014 Error occurrence pattern display Step 2015, 2315 Error occurrence pattern analysis means 2027 Error analysis expected value 2028 Error analysis logic simulation execution result 2316 Error occurrence pattern history information updating means 2317 Error occurrence pattern history information 2318 Error occurrence pattern determination means 2609 Error occurrence test program storage means 2610, 2910 Error occurrence test program information 2911 Test program generation selection means 2912 Error occurrence test program generation means 3307 Verification item out-of-verification pattern analysis means 3327 Pattern information outside verification items

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuo Takahashi 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 2G032 AA01 AB01 AC08 AE12 AG01 AG05 AG10 AL00 5B046 AA08 BA09 JA04 JA05 5B048 AA01 CC02 DD06

Claims (29)

[Claims] 1. A verification method for verifying a logic circuit under test by logic simulation, comprising: a test program generating step of generating a test program using random numbers; and executing the test program on a software simulator to execute a software simulation. A software simulation execution step of outputting a result; and verifying the logic circuit under test using the test program based on the software simulation execution result and verified pattern history information that is information on the verified pattern. A verification execution determination step of determining whether or not the verification execution is performed in the verification execution determination step. A logic simulation execution step of outputting a row result; an expectation value comparison step of comparing the logic simulation execution result with an expectation value; if the expectation value and the logic simulation execution result match in the expectation value comparison step, A logic pattern verification method comprising: updating the verified pattern history information with information on a verified pattern included in the test program verified in the logic simulation execution step. 2. The logic circuit verification method according to claim 1, wherein the verification execution determination step detects a number of new patterns included in the test program from a result of executing the software simulation, and determines a threshold value of the number of new patterns. In the above case, it is determined that verification is to be performed. 3. The logic circuit verification method according to claim 2, wherein at least one of the test program determined not to be verified in the verification execution determination step and the software simulation execution result are stored. The method further comprises a storage step, wherein, in the verification execution determination step, when it is determined that verification is not to be performed continuously for an arbitrary number of times, the new pattern number is included in the test program stored in the test program storage step. A logic circuit verification method comprising: selecting a test program including the largest number of the test programs; and performing verification using the selected test program. 4. The logic circuit verification method according to claim 1, wherein the verification execution determination step detects a new resource usage number of the test program from the software simulation execution result, and includes a threshold value for the new resource usage number. In the above case, it is determined that verification is to be performed. 5. The logic circuit verification method according to claim 1, wherein the verification execution determination step detects the number of executions of each instruction in the test program from a result of the software simulation execution, and determines the same number in the test program. A logic circuit verification method, comprising: determining that verification is not executed when an instruction is repeatedly executed by a certain threshold or more. 6. The method of verifying a logic circuit according to claim 1, wherein the step of determining whether to execute the verification is based on a result of the execution of the software simulation, wherein the test program is a pattern other than a verification item that is a pattern that the logic circuit under test does not execute. A logic circuit verification method for analyzing whether a pattern is included or not and determining that verification is not executed when the pattern is included in the pattern outside the verification item. 7. The logic circuit verification method according to claim 1, further comprising a simulation end state analyzing step of analyzing the simulation end state from the software simulation execution result, wherein the simulation end state is a desired end state. If not, a software circuit execution method is repeated under different end conditions until a desired end state is obtained. 8. The logic circuit verification method according to claim 7, wherein an end condition for setting the simulation end state to a desired end state is set as an end condition of the logic simulation in the logic simulation step. A logic circuit verification method, further comprising: 9. The logic circuit verification method according to claim 1, wherein it is determined whether or not the set number of verification items is larger than a certain threshold value, and if the number of verification items is large, it is determined that the verification is not to be executed. A logic circuit verification method, further comprising a determining step. 10. The logic circuit verification method according to claim 9, wherein the threshold value is related to a size of a data storage unit that stores the verified pattern history information. 11. The logic circuit verification method according to claim 1, wherein in the expected value comparing step, when the logic simulation execution result and the expected value do not match, an error occurs in any pattern in the test program. A logic circuit verification method, further comprising: an error occurrence pattern analysis step of analyzing whether the error has occurred. 12. The logic circuit verification method according to claim 11, wherein the error occurrence pattern is not included in the test program based on error occurrence pattern history information that is information on an error occurrence pattern that has occurred up to that time. An error occurrence pattern determining step of determining to execute verification, and an error occurrence pattern history information updating step of updating the error occurrence pattern history information from information on the error occurrence pattern analyzed in the error occurrence pattern analysis step. A logic circuit verification method, comprising: 13. The logic circuit verification method according to claim 1, wherein in the expected value comparing step, when the logic simulation execution result and the expected value do not match, the test program or information capable of regenerating the test program. A logic circuit verification method, further comprising: an error occurrence test program recording step of recording the error occurrence test program information. 14. The method according to claim 1, wherein an error occurrence test program is generated from error occurrence test program information that is information that can regenerate an error-generated test program. A logic circuit verification method, further comprising: first selecting whether to generate a test program used for verification in the test program generation step or in the error occurrence test program generation step. 15. A verification device for verifying a logic circuit under test by logic simulation, comprising: a verification device storage device for storing a program for realizing a verification device for verifying the logic circuit under test; An execution device for executing the stored program; and a data storage device for storing data output or referenced when the execution device executes the program stored in the verification device storage device, wherein the verification device storage The verification means stored in the device generates a test program using a random number and stores the test program in the data storage device; and executes the test program on a software simulator to execute the software simulation. Software simulation for storing results in the data storage device An execution unit, based on the software simulation execution result and verified pattern history information that is information on the verified pattern, verifying whether to perform verification of the logic circuit under test using the test program. Execution determination means; and a logic for executing the test program on the logic circuit under test by logic simulation when the verification execution determination means determines that the verification is to be executed, and storing the logic simulation execution result in the data storage device. Simulation execution means; expected value comparison means for comparing the logic simulation execution result with an expected value; if the expected value and the logic simulation execution result match in the expected value comparison means, the verified pattern history information Is included in the test program. A verified pattern history information updating means for updating based on the information on the verified pattern. 16. The logic circuit verification device according to claim 15, wherein the verification execution determining unit detects a new pattern number included in the test program from the software simulation execution result; A new pattern number judging means for judging whether or not the number of new patterns detected by the new pattern number counting means is equal to or greater than a certain threshold value; and A logic circuit verification device, which determines whether to verify a logic circuit under test. 17. The logic circuit verification device according to claim 16, wherein at least one or more of the test program and the software simulation execution result determined not to be verified by the verification execution determination unit are stored in the data storage device. A test program storing unit for storing the new pattern in the test program stored by the test program storing unit when the verification execution determining unit determines that verification is not to be performed continuously for an arbitrary number of times. A logic circuit verification device, comprising: selecting a test program including the largest number of programs; and performing verification using the selected test program. 18. The logic circuit verification device according to claim 15, wherein the verification execution determining unit detects a new resource usage number of the test program from the software simulation execution result; A new resource number judging unit for judging whether or not the new resource usage number detected by the resource number counting unit is equal to or greater than a certain threshold value. A logic circuit verification device, which determines whether to verify a test logic circuit. 19. The logic circuit verification device according to claim 15, wherein the verification execution determination unit includes: an instruction execution number counting unit configured to detect an execution number of each instruction in the test program from the software simulation execution result; Means for determining whether the number of times of execution detected by the number of times of instruction execution is smaller than a certain threshold value; and A logic circuit verification device, which determines whether to verify a test logic circuit. 20. The logic circuit verification device according to claim 15, wherein the verification execution determination unit determines that the test program is a pattern that is not verified by the logic circuit under test from the software simulation execution result. A logic circuit verification device, comprising: analyzing whether a pattern is included; and determining not to execute verification when the pattern includes the pattern outside the verification item. 21. The logic circuit verification device according to claim 15, further comprising: a simulation end state analyzing unit that analyzes a simulation end state from the software simulation execution result, wherein the simulation end state is determined by the simulation end state analysis unit. A logic circuit verification device characterized by repeating execution of software simulation under different end conditions until the end state is not the desired end state. 22. The logic circuit verification apparatus according to claim 21, wherein an end condition for setting the simulation end state to a desired end state is set as an end condition of the logic simulation in the logic simulation executing means. A logic circuit verification device, further comprising: means. 23. The logic circuit verification device according to claim 15, wherein it is determined whether the set number of verification items is larger than a certain threshold value, and if the number of verification items is large, the number of verification items to be determined not to execute the verification is determined. A logic circuit verification device, further comprising a determination unit. 24. The logic circuit verification device according to claim 23, wherein the threshold value is related to a size of a data storage unit that stores the verified pattern history information. 25. The logic circuit verification device according to claim 15, wherein an error has occurred in any of the patterns in the test program when the expected value comparing means does not match the logic simulation execution result with the expected value. A logic circuit verification device, further comprising: an error occurrence pattern analysis means for analyzing whether the error occurs. 26. The logic circuit verification device according to claim 25, wherein the error occurrence pattern analysis means determines a simulation end condition of an error analysis simulation that specifies a pattern in which an error has occurred. Means for executing the test program on a software simulator under an end condition determined by the error analysis simulation end condition determining means, and storing an expected value for error analysis in the data storage unit. Simulation execution means, executing the test program on a logic circuit under test by a logic simulation under an end condition determined by the error analysis simulation end condition determination means,
An error analysis logic simulation execution unit that stores the error analysis logic simulation execution result in the data storage unit; the error analysis expected value output by the error analysis software simulation execution unit; Error analysis expected value comparison means for comparing the error analysis logic simulation execution result output by the logic simulation execution means; error analysis end determination means for determining whether to end the error analysis processing; A logic circuit verification device, comprising: an error analysis pattern display means for displaying an occurrence pattern. 27. The logic circuit verification device according to claim 25, wherein the error occurrence pattern is stored in the test program based on error occurrence pattern history information that is information on an error occurrence pattern that has occurred so far. An error occurrence pattern determination unit that determines to execute verification when not included, and an error occurrence pattern history information update unit that updates the error occurrence pattern history information with information on the error occurrence pattern analyzed by the error occurrence pattern analysis unit A logic circuit verification device, further comprising: 28. The logic circuit verification device according to claim 15, wherein the test program or the test program can be regenerated when the expected value comparison means does not match the logic simulation execution result with the expected value. A logic circuit verification device, further comprising: an error occurrence test program recording unit that records error occurrence test program information as information in the data recording device. 29. The error generation test program generating means according to claim 15, wherein the error generation test program is generated from the error generation test program information which is information capable of regenerating the test program in which the error has occurred. And a test program generation selecting means for selecting whether a test program to be used for verification is generated by the test program generation means or the error occurrence test program generation means. Verification device.