JP2002108264A - Active matrix display device and driving method thereof - Google Patents

Abstract

(57) [Summary] In an active matrix display device, when multi-gradation display is performed by a combination of binary or multi-valued write voltages in a temporally weighted sub-frame, image quality such as flicker or false contour is displayed. Challenges had arisen. SOLUTION: The polarity inversion time is shifted for each sub-frame within a frame period, and is combined with line inversion.
By making the polarities of the sub-frames different within the frame, flicker is reduced. The number of scanning lines is L, the horizontal scanning period is H,
When the signal line applied voltage level is A and the number of display gradations is B, one frame period is “H × L × (B−1) / (A−1)”.
The scanning lines are selectively scanned a plurality of times in one frame period in a predetermined order so as to be shorter than the scanning lines, and at least the adjacent scanning lines have different subframes, thereby suppressing flicker and false contour.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving an active matrix type liquid crystal display device or an EL (electroluminescence) display device, and more particularly to a method of driving a binary or multi-valued pixel write voltage in a temporally weighted sub-frame period. Multi-tone display is performed by a combination.

[0002]

2. Description of the Related Art A display device used in a small portable device driven by a battery is required to consume less power, and a liquid crystal display device is a representative display device meeting the demand. In particular, when gradation display is performed in an active matrix type liquid crystal display device, typically a liquid crystal display device using a three-terminal thin film transistor (TFT) as a switching element, a waveform of an analog value is applied to the signal line and switching is performed. A method of charging a pixel to this potential via an element has been generally used. These configuration examples are shown in FIG. 5 and will be described with reference to the drawings. In FIG. 5, reference numeral 100 denotes an active matrix type liquid crystal panel, and signal lines S1 to S
n, a lead line of the scanning lines G1 to Gm orthogonal to the n, and a switching element near the intersection thereof. S
i is a certain signal line, Gj is a certain scanning line, 101 is an example of a switching element near their intersection, in this case, a general three-terminal thin film transistor (TFT). 10
Reference numeral 2 denotes a liquid crystal element, and a counter electrode Vcom is formed on a side facing the transistor 101. Reference numeral 103 denotes a storage capacitor that assists the capacitance component of the liquid crystal element 102 and prevents image quality from deteriorating. In many cases, the opposite electrode is commonly connected separately as Vst. These intersections 104 on the transistor side correspond to pixel electrodes. To briefly explain the operation, the potential of the scanning line Gj becomes high once in one frame period.
The transistor 101 is turned on, and the pixel electrode 104, that is, the liquid crystal capacitor 102 and the storage capacitor 103 are charged to the counter electrode Vcom up to the potential of the signal line Si at this time. After that, the scanning line Gj becomes low potential, the transistor 101 is turned off, and the charged potential is held for one frame period. In addition, liquid crystal is usually driven by AC,
The counter electrode Vcom and the common electrode Vst of the storage capacitor are applied with a pulse-like waveform inverted in synchronization with the signal line Si, and the signal line S
It is also common to reduce the amplitude of i. Reference numeral 111 denotes a signal-side shift register composed of a plurality of flip-flops. Data is sequentially shifted by a CKH signal and an STH signal from the outside to form timing for sampling a video signal. FIG. 5 shows an example of a digital video signal.
At 12, the signal is latched by the output signal of the shift register 111, converted into an analog signal by the D / A conversion circuit 113, and applied to the signal lines S 1 to Sn. Scan side is C
The scanning line G includes a shift register 121 and a buffer 122 that sequentially scan at the timing of the KV signal and the STV signal.
1 to Gm are driven by a pulse waveform.

In the above driving method, the D / A conversion circuit 11
Generally, an operational amplifier is provided as a current buffer for charging / discharging the signal line capacitance as a load in the output stage No. 3, which is a factor that increases the power consumption of the drive circuit. This is because a static current continuously flows in analog circuits such as a D / A conversion circuit and an operational amplifier even when the load is not charged or discharged. In this specification, the above driving method is referred to as “analog driving”.
Shall be called.

In contrast to the above-described analog drive, a drive for performing gray scale display by a combination of binary pixel write voltages in a subframe period weighted temporally without using an analog circuit such as a D / A conversion circuit or an operational amplifier. The basic principle of the method will be described in detail. For ease of explanation, the pixel write voltage is set to a binary fixed voltage.
It may be a multi-valued fixed voltage equal to or greater than the value. FIG. 6 shows the configuration. Components having the same functions as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 114 denotes a decoder and an analog switch for selecting one of the binary fixed voltages VH and VL according to the digital video signal. These have a very simple configuration compared to the above-described D / A conversion circuit, and consume very little power because a static current hardly flows.

Next, the principle of displaying a gray scale by using binary fixed voltages VH and VL will be described with reference to FIG. By dividing the frame period for displaying the entire image into a plurality of temporally weighted sub-frame periods and applying VH or VL to the pixel electrode in each sub-frame period,
Perform temporal pulse width modulation. If the fixed voltage is binary,
The number of subframes matches the number of bits of the input data. Subframes SF4 to SF1 are allocated corresponding to the most significant bit (MSB) to the least significant bit (LSB) of the data. FIG. 7 shows an example of 4 bits and 16 gradations, and 16 gradations are displayed by a combination of the fixed voltages VH and VL in the weighted subframes SF1 to SF4. For example, when the gradation data is 11 in decimal, that is, “1011” in binary, the VL corresponding to “0” is selected in the subframe SF3, and corresponds to “1” in the subframes SF1, SF2, and SF4. VH is selected. Note that “0” may correspond to VH and “1” may correspond to VL in accordance with the voltage-transmittance characteristic (VT characteristic) of the liquid crystal element.

Each sub-frame period includes a writing period and a holding period. The writing period is constant in one horizontal scanning period in any sub-frame, and the sub-frame is weighted by a constant multiple of a power of 2 in the horizontal scanning period. ing.
That is, when H is one horizontal scanning period, N is the number of all subframes, and L is the number of scanning lines, the i-th subframe period is (where i = 1, 2,..., N) (2) To the (i-1) th power) × L × H. In the waveform of line 1 in FIG. 7, a pulse portion corresponds to a writing period, and the other portion corresponds to a holding period.
Since one frame period is the sum of all subframe periods, (1 + 2 + 4 +... +2 to the (N-1) th power) × L × H =
It is expressed as (2 N -1) × L × H. FIG. 8 shows a specific example of the writing period and the holding period of each scanning line when the number L of scanning lines is 16 and the number of subframes is 4.

In this specification, the driving method using the sub-frame structure as described above is referred to as “digital driving”.

[0008]

However, in the above-mentioned digital driving, in the configuration of the active matrix display device shown in FIG. 5, the scanning lines are simply scanned sequentially from top to bottom as shown in FIG. The holding time of the sub-frame period for the upper bits increases, while the one horizontal period H is restricted by the writing characteristics of the active matrix liquid crystal panel 100 in FIG.
Has a problem that the frame period increases and flicker called flicker occurs, or the number of scanning lines L and the number of gradations (the number of subframes) cannot be increased.

In addition, because of the sub-frame structure, when a moving image is displayed, a false contour is generated near a crossing of a 2n boundary such as "16" or "8". Had.

An object of the present invention is to solve the above-mentioned conventional problems and to provide an active matrix display device in which flicker and false contours are suppressed, and a driving method thereof.

[0011]

In order to achieve this object, an active matrix display device according to the present invention comprises a scanning line number L, a scanning line selection period H, a signal line applied voltage level A, a display gradation. When the number is B, the scanning lines are selectively scanned a plurality of times in one frame period in a predetermined order so that one frame period is shorter than H × L × (B-1) / (A-1). , On adjacent scan lines,
Change the order and timing of subframes.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows that the number L of display lines is 16, the number N of subframes is 4 (SF1, SF2, SF3, SF4), and the subframe holding period is temporally weighted in a ratio of 1: 2: 4: 8. The timing chart for selecting each scanning line when 16 gradations are displayed by a combination of these is shown.
In FIG. 1, "black circles" indicate a writing period, and hatching and numbers indicate the order of subframes. First, in the first scanning line, information of SF1 is written in the first horizontal scanning period (1H), the state (SF1) is held from 2H to 5H, information of SF2 is written in 6H, and information of SF2 is written in 7H to 14H.
The state (SF2) is maintained until H, and SF3 at 15H.
Is written, the state (SF3) is held from 16H to 31H, the information of SF4 is written at 32H, and the state (SF3) is held from 33H to 64H. SF1: writing period: 1H, holding period : 2H-5H SF2; writing period: 6H, holding period: 7H-14H SF3; writing period: 15H, holding period: 16H-31H SF4; writing period: 32H, holding period: 33H-64H. SF1, writing period: 5H, holding period: 6H to 9H SF2; writing period: 60H, holding period: 61H to 68H (4H) SF3; writing period: 43H, holding period: 44H to 59H SF4; writing period: 10H, Holding period: 11H to 42H In the third scanning line, SF1; writing period: 9H, holding period 10H to 13H SF2; writing period: 14H, holding period: 15H to 22H SF3; writing period: 23H, holding period: 24H to 39H SF4; writing period: 40H, holding period: 41H to 72H (8H) 4th row scanning In the line, SF1; writing period: 13H, holding period: 14H to 17H SF2; writing period: 4H, holding period: 5H to 12H SF3; writing period: 51H, holding period: 52H to 67H (3H) SF4; writing period: 18H, holding period: 19H to 50H Similarly, by selectively scanning each scanning line in the order shown in FIG. 1 (writing period), one frame becomes 64H,
This is about 1/4 of 240H in FIG. 8, and flicker can be suppressed. The odd-numbered scanning lines are SF1, SF2, SF
In the order of 3, SF4, the even-numbered scanning lines are SF4, SF
Since subframes are configured in the order of 3, SF2, and SF1, the timing and direction of the 2 @ n boundary at which false contours occur are different between even-numbered lines and odd-numbered lines, so that false contours can be suppressed. Further, the scanning order is not limited to that shown in FIG. 1. As shown in FIG. 2, even if the order of the subframes is all the same, the timing of the 2 nth boundary between adjacent scanning lines, preferably the weighting of the heaviest weight By shifting the subframe, false contour can be suppressed.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
FIG. 3 is a configuration diagram of an active matrix display device according to a second embodiment of the present invention. In FIG. 3, 1
Reference numeral 00 denotes an active matrix display panel, which includes signal lines S1 to Sn, lead lines of scanning lines G1 to Gm orthogonal to the signal lines S1 to Sn, and a switching element near an intersection thereof. Reference numeral 111 denotes a signal-side shift register composed of a plurality of flip-flops. Data is sequentially shifted by a CKH signal and an STH signal from the outside to form a sampling timing of a video signal. The example of FIG. 3 shows an example of a digital video signal. A video signal of a plurality of bits is latched in a latch 112 by an output signal of a shift register 111, and is latched by a decoder / analog switch
To set any of the binary fixed voltages VH and VL to the signal lines S1 to S1
Add to Sn. The above is the same as the configuration in FIG.
A scanning control circuit 123 selects scanning lines in a predetermined order according to an externally selected scanning line signal ADV, and drives the scanning lines G1 to Gm through a buffer 122 in a pulsed manner. By configuring the timing of the writing period in FIG. 1 or 2 by the selected scanning line signal ADV and the scanning control circuit 123, an active matrix display device in which flicker and false contours are suppressed can be realized. If a decoder is used as the scanning control circuit, selective scanning can be performed in an arbitrary order with a simple circuit configuration according to the selected scanning line address information.
Here, the electro-optical element of the active matrix display panel may be a liquid crystal configuration shown in FIG. 5 or an electroluminescent display panel using the light emitting element shown in FIG. Since the light-emitting element 106 of the electroluminescent display panel shown in FIG. 4 is a current-driven element, by adding a second switching element 105 for current driving, the terminal of the first switching element 104 is changed to the state shown in FIG. By performing sub-frame driving in the same manner as described above, a desired gradation display can be performed. When the optical modulation element is a liquid crystal, the liquid crystal generally responds to the effective value of the applied voltage, so that the display quality may be impaired depending on the relationship between the response speed and the pulse width of the subframe. By greatly shortening the frame period, the degree of freedom in setting one frame period is improved, so that the selection range of the liquid crystal characteristics can be expanded.

In the embodiment of the first invention, the number of scanning lines is 16, the number of display gradations is 16, and one frame period is six.
4H, but is not limited to this. Needless to say, the number of scanning lines and the number of gradations can be set as desired.
The one frame period is not limited to the minimum value determined from the number of scanning lines and the ratio and number of subframes, but may be determined based on the characteristics of the optical modulation element. Further, although the subframes are different between the odd-numbered rows and the even-numbered rows, the present invention is not limited to this combination. For example, the subframes may be changed every two rows. Although the scanning line control circuit 123 is a decoder in the embodiment of the second invention, the number of external signal lines is reduced by using a serial / parallel conversion circuit using a shift register and a latch like a signal line driving circuit. Any configuration may be used as long as the circuit can perform scanning in an order other than sequential scanning. Although 114 is a decoder / analog switch, any configuration may be used as long as it can selectively output a plurality of fixed voltages to the signal lines S1 to Sn.

[0016]

As described above, according to the present invention, the number of scanning lines is set to L,
When the scanning line selection period is H, the signal line applied voltage level is A, and the number of display gradations is B, one frame period is shorter than H × L × (B−1) / (A−1). As described above, the scanning lines are selectively scanned a plurality of times in one frame period in a predetermined order, and the adjacent scanning lines
By changing the order and timing of the subframes, an excellent active matrix display device capable of suppressing flicker and false contour can be realized.

[Brief description of the drawings]

FIG. 1 is a scanning line selection timing chart according to a first embodiment of the present invention;

FIG. 2 is another scanning line selection timing chart according to the first embodiment of the present invention;

FIG. 3 is a configuration diagram of an active matrix display device according to a second embodiment of the present invention.

FIG. 4 is a pixel configuration diagram of an active matrix display device according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of an active matrix display device for explaining conventional analog driving.

FIG. 6 is a configuration diagram of an active matrix display device for explaining conventional digital driving.

FIG. 7 is a configuration diagram of a subframe for explaining conventional digital driving.

FIG. 8 is a scanning line selection timing chart for explaining conventional digital driving.

[Explanation of symbols]

 Reference Signs List 100 active matrix display panel 101, 105 switching element 102 liquid crystal element 103 storage capacitor 104 pixel electrode 106 light emitting element 111, 121 shift register 112 latch 113 D / A conversion circuit 114 decoder / analog switch 122 buffer 123 scanning control circuit

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Claims (10)

[Claims] An active matrix display device having at least one or more switching elements at intersections of a plurality of signal lines and a plurality of scanning lines divides one frame period into a plurality of weighted subframes. A driving method for performing a grayscale display higher than the voltage level applied to the signal line by the combination of the above, wherein the number of scanning lines is L, the horizontal scanning period is H, the signal line applied voltage level is A, and the number of display gradations is When B, the scanning lines are selectively scanned a plurality of times in one frame period in a predetermined order so that one frame period is shorter than H × L × (B-1) / (A-1); A method for driving an active matrix display device, comprising at least one combination of scanning lines having different subframes between adjacent scanning lines. 2. The method of driving an active matrix display device according to claim 1, wherein the order of the sub-frames differs between adjacent scanning lines. 3. The active matrix display device according to claim 1, wherein the order of the subframes is the same in adjacent scanning lines, and the temporal shift thereof is longer than the lightest weighted subframe period. Drive method. 4. A plurality of signal lines provided on a first substrate, a signal line drive circuit for driving the plurality of signal lines, a plurality of scan lines orthogonal to the signal lines, and a scan line drive circuit for driving the signal lines And at least one or more switching elements provided in the vicinity of the intersection of the signal line and the scanning line, and a pixel electrode connected to the switching element, facing the first substrate via an electro-optical element. A second substrate having a counter electrode, wherein the scanning line driving circuit selectively scans each of the scanning lines a plurality of times in a predetermined order during one frame period, and wherein the signal line driving circuit comprises: , By selecting and outputting one value of a plurality of fixed voltage levels smaller than the number of display gray scales, all pixels belonging to each scanning line are temporally weighted in a plurality of sub-frame periods. Pair of levels When performing multi-gradation display by combination, when the number of scanning lines is L, the horizontal scanning period is H, the signal line applied voltage level is A, and the number of display gradations is B, one frame period is H × L × Scan lines are selectively scanned a plurality of times in one frame period in a predetermined order so as to be shorter than (B-1) / (A-1), and at least adjacent scan lines do not match subframes. An active matrix display device, comprising: 5. The active matrix display device according to claim 4, wherein the order of the subframes is different between adjacent scanning lines. 6. The active according to claim 4, wherein the order of the sub-frames is the same in adjacent scanning lines, and the temporal shift thereof is longer than the lightest weighted sub-frame period. Matrix display device. 7. The active matrix display device according to claim 4, wherein the heaviest weighted subframe is divided into at least two. 8. The active matrix display device according to claim 4, wherein the electro-optical element is a liquid crystal. 9. The active matrix display device according to claim 8, wherein one frame period is set to a predetermined value according to the electro-optical response characteristics of the liquid crystal. 10. The active matrix display device according to claim 4, wherein the electro-optical element is a light emitting substance.