JP2002091384A - Lcd driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent destruction and erroneous display of display elements and the degradation of a display panel by improving the malfunction of a driving signal to be supplied to the display panel when power source is applied. SOLUTION: This LCD(liquid crystal display) driver is constituted by being provided with a logical gate 11 which performs the logical operation between the output of the unit shift register of the n-th bit and an inversion output in which the output of the unit shift register of the (n+1)th bit is inverted and outputs the logical value of the logical operation as a signal for generating a liquid crystal driving signal corresponding to the display data of the n-th bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display in which a driving signal generated in accordance with a shift output of a data transfer shift register in which the same circuit is cascaded and display data is sequentially transferred is supplied to a liquid crystal display panel. The present invention relates to an LCD (Liquid Crystal Display) driver for driving a panel.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a configuration of a conventional liquid crystal driver IC. In FIG. 4, display data (DI) of n bits (for example, n = 240 in FIG. 4) is used for data transfer in which unit shift registers (1 bit) are cascaded in synchronization with a transfer clock signal (CP). The display data of the n-th bit shifted by the shift register 21 is shifted by a corresponding shift output Qn (Q1 to Q2).
40). That is, the display data of the first bit is output as a shift output Q1, and the display data of the second bit is shifted after the display data of the first bit and the display data of the first bit is output.
Output as 2. Data transfer shift register 21
Output from the liquid crystal output control circuit 2
2 for level conversion and the like, and the liquid crystal output Gn
The signals are output from the liquid crystal output control circuit 22 as (G1 to G240) and supplied to the display panel as liquid crystal drive signals on the scanning line side.

FIG. 5 is a diagram showing the configuration of the data transfer shift register 21 shown in FIG. In FIG. 5, the data transfer shift register 21 is configured by cascade-connecting a plurality of unit shift registers (1 bit). Here, the configuration of the unit shift register will be described by taking, as an example, the unit shift register of the first bit that provides the shift output Q1. The unit shift register includes inverters (inverting circuits) 2 and 5, clocked inverters 1 and 6 whose conduction is controlled by a first clock signal (FB) obtained by inverting a transfer clock signal (CP), Clock signal (F) obtained by inverting the clock signal (FB)
And clocked inverters 3 and 4 controlled to conduct. The first clock signal (FB) is provided as an output of the inverter 7 receiving the transfer clock signal (CP), and the second clock signal (F) is received from the inverter 8 receiving the first clock signal. Provided as output.

[0004] The clocked inverter 1 outputs the output Q of the preceding stage.
0 '(display data DI in FIG. 4) and outputs A1B
To the input of the inverter 2. Inverter 2 receives output A1B of clocked inverter 1 and supplies output A1 to respective inputs of clocked inverter 3 and clocked inverter 4. Clocked inverter 3
Receives the output A1 of the inverter 2 and gives the output A1B to the input of the inverter 2. Clocked inverter 4
Receives output A1 of inverter 2 and provides output Q1B to the input of inverter 5. Inverter 5 receives output Q1B of clocked inverter 4, and applies output Q1 'to clocked inverter 6 and the respective inputs of clocked inverter 1 of the second bit unit shift register. The output Q1 'of the inverter 5 is provided as a shift output Q1 via the buffer gate 9. Clocked inverter 6 receives output Q1 ′ of inverter 5 and provides output Q1B to the input of inverter 5. FIG. 6 shows the operation timing in the above configuration.

[0005] In such a configuration, when power is turned on, the shift output may be at a high level depending on circuit constants and circuit thresholds. The fact that at least one of the shift outputs becomes high level means that the unit shift registers having the same configuration are cascaded as shown in FIG.
In addition, since the circuit constants and the circuit thresholds of the unit shift registers become the same by being manufactured in the same manner, all the shift outputs become high level. FIG. 7 shows the operation timing when the power is turned on in the configuration shown in FIG. Thus, when the power is turned on, the data transfer shift register 21
When all the shift outputs become high level, the liquid crystal output Gn is generated by the shift output Qn, so that all the liquid crystal outputs output from the liquid crystal output control circuit 22 also become high level. As a result, a current flows simultaneously from the liquid crystal output control circuit 22 to a load such as a capacitance on the display panel side.

The liquid crystal output control circuit 22 operates on a relatively high power supply system, for example, a power supply system of about -20 V to +20 V. Therefore, a large amount of current flows from the liquid crystal output control circuit 22 to the load on the display panel at the same time. However, as shown in the operation timing chart of FIG. 6, the liquid crystal output control circuit 22 controls the current of the internal circuit so that only one liquid crystal output is at a high level during one cycle of the transfer clock signal. The specifications are set and are not designed to withstand the large current as described above. For this reason, when the above-described large current flows through the liquid crystal output control circuit 22, there is a possibility that circuit elements such as transistors constituting the liquid crystal output control circuit 22 are destroyed. When a high-level liquid crystal output is simultaneously supplied to the display panel from the liquid crystal output control circuit 22, the scanning lines of the display panel are simultaneously driven, and a display other than the expected display is performed on the display panel, which may cause a malfunction. there were. Furthermore, when a large amount of current is supplied to the display panel, it adversely affects the power supply circuit of the display panel,
Deterioration of the display panel was caused.

[0007]

As described above,
In a conventional liquid crystal driver for driving a liquid crystal display panel, the same circuit is cascaded, and the liquid crystal output supplied to the display panel when the power of the liquid crystal driver is turned on depends on the circuit constant and circuit threshold of the circuit. Were all at high level. As a result, a large amount of current flows in a circuit that supplies a liquid crystal output to a display panel, and a problem that elements of the circuit may be destroyed is caused. In addition, there has been a problem that scanning lines of the display panel are simultaneously driven to cause erroneous display.

Accordingly, the present invention has been made in view of the above, and it is an object of the present invention to improve a defect of a drive signal supplied to a liquid crystal display panel at the time of turning on a power supply, and to provide a device destruction, an erroneous display and An object of the present invention is to provide a liquid crystal driver in which deterioration of a display panel is prevented.

[0009]

In order to achieve the above object, a means for solving the problem is that a plurality of the same unit shift registers are cascaded, and a plurality of bits of liquid crystal display data are transferred serially. A data transfer shift register for outputting a signal for generating a liquid crystal drive signal for driving the liquid crystal based on the liquid crystal display data, wherein the data transfer shift register includes an output of the unit shift register of the n-th bit; A) a logic gate which takes a logic with an inverted output obtained by inverting the output of the unit shift register of the bit and outputs the logical value as a signal for generating the liquid crystal drive signal corresponding to the liquid crystal display data of the nth bit. It is characterized by having.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a data transfer shift register of a liquid crystal driver according to one embodiment of the present invention. The feature of the embodiment shown in FIG. 1 is that the buffer 9 shown in FIG. 5 is deleted and the unit shift register of the n-th (n = 1, 2,...) Bit is different from the conventional configuration shown in FIG. , The output Qn 'of the inverter 5 (hereinafter, this output is referred to as the previous shift output Qn' of the unit shift register) is used as one input, and the output Qn 'of the next stage ((n + 1) th bit) before the unit shift register Shift output Q (n +
1) 'A negative AND (NAND) gate 11 having the inverted signal Q (n + 1) B as the other input, and receiving and inverting the output of the NAND gate 11, inverting the inverted output to n bits of the data transfer shift register The other configuration is the same as the configuration shown in FIG. 5 in that the inverter 12 for providing the shift output Qn of the eye is provided. Last stage NAND gate 1
As the other input of 1, a dummy unit shift register that does not provide a shift output to the liquid crystal output control circuit 22 is provided as a next stage of the last unit shift register, and a previous shift output in the dummy unit shift register is inverted. What is necessary is just to give the changed signal. Alternatively, when the operation speed and the wiring length do not matter, for example, a signal Q1B obtained by inverting the previous shift output Q1 ′ of the unit shift register of the first bit may be provided. The inverter 12 may not be provided. In such a case, a logical product (AND) is used instead of the NAND gate 11.
A gate may be provided. In this case, the shift output Qn of the data transfer shift register is provided as the output of the AND gate. Note that, in FIG. 1, components having the same reference numerals as those in FIG. 5 have similar functions, and description thereof will be omitted.

In such a configuration, as shown in the operation timing at power-on in FIG. 2, when all previous shift outputs Qn 'of each unit shift register attain a high level at the time of power-on, a NAND gate One input of 11 is supplied with the high level of the previous shift output Qn ', and the other input is supplied with the low level of the signal QnB obtained by inverting the previous shift output Qn' in the next unit shift register. As a result, the output of the NAND gate 11 goes high, the output is inverted by the inverter 12, and all the shift outputs Qn of the data transfer shift register go low. Therefore, all the liquid crystal outputs Gn output from the liquid crystal output control circuit 22 are also at the low level according to the shift output Qn of the data transfer shift register.

On the other hand, in a normal operation, before a display data is supplied to the data transfer shift register, a low-level reset signal is supplied to the data transfer shift register and transferred, and the previous shift output Qn 'in each unit shift register is transferred. Is reset to low level. In such a state, a signal QnB obtained by inverting the previous shift output Qn 'of the next unit shift register, that is, a high level signal is applied to the other input of the NAND gate 11, so that the normal operation shown in FIG. When low-level or high-level display data is applied to the shift output Qn 'of the unit shift register (high-level display data in FIG. 3), the display data It is output as a shift output Qn via one input.

As described above, in the above embodiment, when the power is turned on, the previous shift output Qn 'of the unit shift register is output.
Are all at high level, all the shift outputs Qn of the data transfer shift register are at low level, so that all the liquid crystal outputs Gn output from the liquid crystal output control circuit 22 are at low level, as in the prior art. It is possible to prevent a current from flowing simultaneously from the liquid crystal output control circuit 22 to the load of the display panel. This prevents the circuit elements such as the transistors constituting the liquid crystal output control circuit 22 from being destroyed. Further, the scanning lines of the display panel are not driven at the same time, and the display panel does not display erroneously. Further, a large amount of current is not supplied to the display panel, and deterioration of the display panel is avoided.

[0015]

As described above, according to the present invention, the output of the unit shift register of the n-th bit and (n +
1) Since the logic with the inverted output obtained by inverting the output of the unit shift register of the bit is calculated and the liquid crystal drive signal is generated based on the logical value, all the liquid crystal drive signals become low level when the power is turned on. It is possible to prevent elements of a circuit that generates and outputs a drive signal from being destroyed. Further, simultaneous driving of the scanning lines of the display panel can be avoided, and erroneous display of the display panel can be prevented. Further, a large amount of current is not supplied to the display panel, and it is possible to prevent deterioration of the display panel.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a data transfer shift register of an LCD driver according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing when power is turned on in FIG. 1;

FIG. 3 is a diagram showing operation timings in a normal operation in FIG. 1;

FIG. 4 is a diagram showing a configuration of a conventional LCD driver.

FIG. 5 is a diagram showing a configuration of a data transfer shift register shown in FIG. 4;

FIG. 6 is a diagram showing operation timings during a normal operation in FIG. 5;

FIG. 7 is a diagram showing an operation timing at the time of power-on in FIG. 5;

[Explanation of symbols]

 1, 3, 4, 6 Clocked inverter 2, 5, 7, 8, 12 Inverter 11 NAND gate 21 Data transfer shift register 22 Liquid crystal output control circuit

Continued on the front page F-term (reference) 2H093 NA31 NC01 NC22 ND47 5C006 AC21 AF25 AF43 AF67 BB11 BC14 BF03 FA33 5C080 AA10 BB05 DD19 FF12 JJ02 JJ03 JJ04

Claims (1)

[Claims] A plurality of the same unit shift registers are cascaded, a plurality of bits of liquid crystal display data are serially transferred, and a signal for generating a liquid crystal drive signal for driving a liquid crystal based on the transferred liquid crystal display data is output. A shift register for data transfer, wherein the shift register for data transfer performs a logic operation between an output of the unit shift register of the nth bit and an inverted output obtained by inverting an output of the unit shift register of the (n + 1) th bit. And a logic gate for outputting the logic value as a signal for generating the liquid crystal drive signal corresponding to the liquid crystal display data of the nth bit.