JPH11339491A - Shift register and load driver utilizing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress occurrence of erroneous operation resulting from transmission lag of clock pulse while preventing occurrence of abnormal driving state of a load. SOLUTION: When a bidirectional shift register 21 is shifted to the right, a clock supply circuit 29 switches a first buffer circuit 30 to high impedance state and a second buffer circuit 31 to low impedance state in response to a low level switching command signal Sc provided at a switching terminal 33 and delivers a clock pulse Pc in the direction of an arrow B to a clock line 27. When the bidirectional shift register 21 is shifted to the left, the clock supply circuit 29 switches the first buffer circuit 30 to low impedance state and the second buffer circuit 31 to high impedance state in response to a high level switching command signal Sc provided at the switching terminal 33 and delivers a clock pulse Pc in the direction of an arrow A to the clock line 27.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a shift register device having a built-in bidirectional shift register and a load driving device using the shift register device.

[0002]

2. Description of the Related Art For example, in a driver IC for driving a matrix type display device such as an EL panel, a plurality of scanning electrodes (or data electrodes) of the EL panel are provided.
Is controlled based on the parallel output of the bidirectional shift register.

FIG. 4 schematically shows a configuration of a control signal generating circuit used for such a purpose. In FIG. 4, a bidirectional shift register 1 is of a serial input / parallel output type composed of a plurality of flip-flops 2 and a gate circuit group (not shown). Left shift input terminal 4
Are connected via bidirectional buffer circuits 5 and 6, respectively. The clock terminals of the flip-flops 2 are connected to a common clock line 7.
A clock pulse Pc supplied from a not-shown EL controller through a clock pulse input terminal 8 is supplied to the clock line 7 through a buffer circuit 9.

Although not shown, the right shift input terminal 3
The right shift data signal and the left shift data signal are selectively supplied to the left shift input terminal 4 and the parallel output terminal 1 of the bidirectional shift register 1 is provided.
From the group a, a bit signal corresponding to the input data signal is output. And such a bidirectional shift register 1
The high voltage output circuits provided in one-to-one correspondence with the respective scanning electrodes (or the respective data electrodes) of the EL panel are individually driven by the respective bit output signals from.

[0005]

When a driver IC is formed by integrating the control signal generation circuit as described above, the electrical characteristics of the clock line 7 are restricted, and the clock on the clock line 7 is restricted. A phenomenon occurs in which the transmission time of the pulse Pc gradually delays as the transmission distance increases. For this reason, in the configuration of FIG. 4, the supply direction of the clock pulse Pc and the bidirectional shift register 1
Are in the same shift direction (during the right shift state), the output of the flip-flop 2 located at the preceding stage is inverted at the time before the clock pulse Pc is input to the flip-flop 2 located at the subsequent stage. When such a state occurs, an erroneous operation that a data signal passes through the flip-flop 2 occurs. In particular, in the configuration shown in FIG. 4, when the above-described malfunction occurs, unnecessary power is supplied to the scanning electrodes (or data electrodes) of the EL panel, which is a load. For this reason, there arises a problem that it is difficult to drive the load normally, for example, the above-mentioned malfunction causes useless power consumption and disturbance of a displayed image.

The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide a shift register device capable of suppressing the possibility of malfunction due to a clock pulse transmission delay. A second object is to provide a driving means for supplying a current to a load based on an output of a bidirectional shift register, and to provide a driving state of the load due to a malfunction of the bidirectional shift register. An object of the present invention is to provide a load driving device capable of preventing a situation in which an abnormality occurs in a vehicle.

[0007]

Means for Solving the Problems To achieve the first object, the means described in claim 1 can be adopted. According to this means, the bidirectional shift register (21)
If the input direction of the data signal to the clock line is, for example, a right shift direction (this is referred to as a forward direction), the signal direction switching means (29) changes the supply direction of the clock pulse to the clock line (27) to Switching is performed so as to be in a direction opposite to the right shift direction (this direction is referred to as a reverse direction). When the input direction of the data signal to the bidirectional shift register (21) is the left shift direction (reverse direction), the signal direction switching means (29) changes the supply direction of the clock pulse to the clock line. , So as to be in the opposite direction (forward direction) to the left shift direction.

As described above, when the supply direction of the clock pulse and the shift direction of the bidirectional shift register (21) are opposite to each other, the transmission time of the clock pulse on the clock line (27) depends on the transmission distance. Even if the phenomenon occurs that delays as the length increases,
In the bidirectional shift register (21), the output of the flip-flop (22) located at the preceding stage is inverted at the time before the clock pulse is input to the flip-flop (22) located at the subsequent stage in the shift direction. Fear is gone. As a result, it is possible to suppress the possibility that a malfunction in which the data signal passes through the flip-flop occurs as in the related art. In this case, the switching control of the supply direction of the clock pulse by the signal direction switching means (29) is performed every time the shift direction of the bidirectional shift register (21) is reversed, so that a malfunction may occur. Characteristics can be suppressed at all times.

According to the second aspect, the clock line (2) is responsive to one of the first and second switch elements (30, 31) being inverted to a low impedance state.
7) is switched, the first and second switch elements (3) are switched.
Since the inversion operation of (0, 31) can be performed only by inputting the switching command signal, the switching control of the clock pulse supply direction can be performed extremely easily.

When the bidirectional shift register (21) is of a serial output type, the signal direction switching means (29) controls the bidirectional shift register (21) in a bidirectional manner with respect to the clock pulse supply direction. In a state where the shift direction of the shift register is controlled to be in the opposite direction, even if a phenomenon occurs in which the transmission time of the clock pulse on the clock line is delayed as the transmission distance becomes longer. The clock pulse is applied at the earliest timing to the flip-flop (22) located at the last stage (that is, the output stage) in the bidirectional shift register (21). As a result, the phenomenon that the operation speed of the bidirectional shift register (21) is reduced by the delay time of the clock pulse does not occur.

[0011] In order to achieve the second object, means as described in claim 6 can be employed. According to this means, the driving means (14) performs an operation of selectively energizing the plurality of loads (11a) based on each bit output of the bidirectional shift register (21) in the shift register device. In this case, the input direction of the data signal to the bidirectional shift register (21) is, for example, a right shift direction (forward direction).
In this case, the signal direction switching means (29) switches the clock pulse supply direction to the clock line (27) so as to be in the opposite direction (reverse direction) to the right shift direction. The input direction of the data signal to the bidirectional shift register (21) is the left shift direction (reverse direction).
If the signal direction switching means (29)
The supply direction of the clock pulse to the clock line is
Switching is performed in the direction opposite to the left shift direction (forward direction).

As described above, when the clock pulse supply direction and the shift direction of the bidirectional shift register (21) are opposite to each other, the transmission time of the clock pulse on the clock line (27) depends on the transmission distance. Even in the case where the phenomenon occurs that the delay becomes longer as the length increases, in the bidirectional shift register (21), the clock pulse before the clock pulse is input to the flip-flop (22) located at the subsequent stage in the shift direction. At this point, there is no possibility that the output of the flip-flop (22) located at the preceding stage is inverted. As a result, it is possible to suppress the possibility that a malfunction in which the data signal passes through the flip-flop (22) occurs as in the related art. Accordingly, it is possible to prevent a situation in which an abnormality occurs in the driving state of the load (11a) by the driving means due to a malfunction of the bidirectional shift register (21). In this case, the switching control of the supply direction of the clock pulse by the signal direction switching means (29) is performed every time the shift direction of the bidirectional shift register (21) is reversed, so that a malfunction may occur. , That is, the possibility that an abnormality occurs in the drive state of the load (11a) can be always suppressed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a driver IC for driving an EL panel will be described below with reference to FIGS. FIG. 3 is a functional block diagram showing a schematic configuration of the entire driver IC 12 for driving the EL panel 11 which is a matrix type display device. FIG. 3 shows, for example, the EL panel 11.
1 shows a driver IC 12 for applying a high voltage to a plurality of scanning electrodes 11a (corresponding to a load in the present invention) of the present invention. Can be applied to a driver IC for applying a high voltage to the driver IC.

In FIG. 3, a driver IC 12 includes a control circuit 13 and a driving unit 1 corresponding to a driving unit according to the present invention.
4 is configured to be integrated into a single chip. The driving unit 14 includes a plurality of high voltage output units 15 for applying a high voltage to each scanning electrode 11a of the EL panel 11 through an output terminal 14a, one input terminal of the high voltage output unit 15, and a control circuit. 13 and a voltage level conversion unit 16 arranged between them, and specifically has a circuit configuration as shown in FIG.

That is, in FIG. 2, the high voltage output unit 1
Reference numeral 5 denotes a complementary P-channel high-voltage MOSFET 17 and an N-channel high-voltage MOSF between a power supply terminal VDDH for generating a high voltage and a ground terminal.
ET18 is connected in series, and each MOS
The FETs 17 and 18 have a push-pull configuration in which an output terminal 14a is connected to their common connection point. still,
Each of the MOSFETs 17 and 18 is, for example, an LDMOS (Lateral Double-diffuse) so as to obtain a sufficient withstand voltage.
d MOS: lateral double diffusion MOSFET).

The voltage level converter 16 includes a voltage dividing circuit 19 composed of a plurality of diffused resistors 19a and an N-channel type high breakdown voltage MOSFET 20 composed of, for example, LDMOS between a power supply terminal VDDH and a ground terminal. Are connected by a series circuit of
A voltage dividing signal Sd is generated from an output terminal 19b of the voltage dividing circuit 19 in the ON state of the voltage dividing circuit 19, and is supplied to the gate of the MOSFET 17.

The drive section 14 has a pair of input terminals 14 b and 14 c for receiving an operation command signal (for example, a high level signal of about 5 V) from the control circuit 13, and one input terminal 14 b is connected to the gate of the MOSFET 20. Connected
The other input terminal 14c is connected to the gate of the MOSFET 17. The above-described MOSFETs 17, 1 and 1
8, 20 include flywheel diodes 17a, 18
a and 20a are connected in parallel.

Therefore, in the drive unit 14, when an operation command signal is input to the input terminal 14b, the MOSFET 20 in the voltage level conversion unit 16 is turned on, and the voltage dividing circuit 19 connects the power supply terminal VDDH and the ground. The high voltage applied between the terminals is divided to output a divided signal Sd having a voltage level lower than the voltage level of the power supply terminal VDDH by a predetermined amount (more than the gate threshold voltage of the MOSFET 17). The MOSFET 17 is turned on by the pressure signal Sd. Thereby, the power terminal V is connected to the output terminal 14a.
High voltage output from DDH is provided. Also,
When an operation command signal is input to the input terminal 14c,
Since the MOSFET 18 is turned on, the output terminal 14a is connected to the ground terminal.

FIG. 1 shows a specific configuration of the control circuit 13 for supplying an operation command signal to the drive unit 14, which will be described below. That is,
In FIG. 1, a bidirectional shift register 21 is of a serial input / serial / parallel output type comprising a plurality of flip-flops 22 and a gate circuit group (not shown). And the left shift input terminal 24 via bidirectional buffer circuits 25 and 26, respectively. The input terminals 23 and 24 are supplied with a data signal output from an unillustrated EL controller directly or through another control circuit.

The clock terminal of each flip-flop 22 is connected to a common clock line 27. The clock line 27 receives a clock pulse Pc supplied from an EL controller (not shown) to a clock pulse input terminal 28. , Through a clock supply circuit 29 (corresponding to the signal direction switching means in the present invention).

The clock supply circuit 29 includes a first three-state buffer circuit 30 (corresponding to a first switch element in the present invention; hereinafter, abbreviated as a first buffer circuit) and a second three-state buffer circuit 31. (Corresponding to a second switch element in the present invention: hereinafter, abbreviated as a second buffer circuit), and an inverter circuit 32.

In this case, the first buffer circuit 30 applies the clock pulse Pc to the clock line 27 in the direction of arrow A (forward direction: right side of the bidirectional shift register 21) while a high level signal is applied to its gate terminal. (Corresponding to the shift direction) and a high impedance state in which the passage of the clock pulse Pc is inhibited while a low level signal is applied to the gate terminal. , A switching command signal Sc (binary signal) supplied to the switching terminal 33 from an EL controller (not shown).

The second buffer circuit 31 applies a clock pulse Pc to the clock line 27 in the direction of arrow B (reverse direction: left shift of the bidirectional shift register 21) while a high level signal is applied to the gate terminal of the second buffer circuit 31. (Corresponding to the direction) and a high impedance state in which the passage of the clock pulse Pc is prohibited while a low level signal is applied to the gate terminal. Switching terminal 3
The switching command signal Sc given to the control signal No. 3 is given via an inverter circuit 34.

Accordingly, in the clock supply circuit 29, when the switching command signal Sc applied to the switching terminal 33 is at a high level, the first buffer circuit 30 exhibits a low impedance state and the second buffer circuit 3
Since 1 assumes a high impedance state, the clock pulse Pc is applied to the clock line 27 in the direction of arrow A. In the clock supply circuit 29, when the switching command signal Sc applied to the switching terminal 33 is at a low level, the second buffer circuit 31 exhibits a low impedance state and the first buffer circuit 30 sets a high level. Since the clock pulse Pc becomes the impedance state, the clock pulse Pc is applied to the clock line 2.
7 in the direction of arrow B.

The above-described bidirectional shift register 21, the bidirectional buffer circuits 25 and 26, the clock supply circuit 29, and the like constitute a shift register device to which the present invention is applied.

On the other hand, a parallel output signal output from each bit of the bidirectional shift register 21 is supplied to a plurality of drive unit control logic circuits 35 corresponding to the respective bits. When the input bit signal is at a high level, the drive control logic circuit 35
Then, a high-level operation command signal is output to the input terminals 14b of the drive unit 4 (at this time, a low-level signal is output to the input terminals 14c of the drive unit 14). When the input bit signal is at a low level, the input terminal 1
A high-level operation command signal is output to the group 4c (at this time, a low-level signal is output to the group of input terminals 14b of the drive unit 14).

Therefore, in the driving section 14, when a high-level bit signal is output from the bidirectional shift register 21, the input terminal 14b corresponding to the bit is output.
Since the operation command signal is input to the
6 and the MO in the high-voltage output unit 15.
The SFETs 17 are sequentially turned on, whereby the output terminal 1
4a is connected to the power supply terminal VHDD. In the driving unit 14, when the low-level bit signal is output from the bidirectional shift register 21, the operation command signal is input to the input terminal 14c corresponding to the bit, so that the high-voltage output The MOSFET 18 in the unit 15 is turned on, and the output terminal 14a is connected to the ground terminal.

In the configuration of this embodiment described above, when the input direction of the data signal to the bidirectional shift register 21 is, for example, the right shift direction (when the data signal is input to the right shift input terminal 23). Is controlled to supply a low-level switching command signal Sc to the switching terminal 33. Then, the clock supply circuit 29
The supply direction of the clock pulse Pc to the clock line 27 is switched so as to be in the direction of arrow B which is opposite to the right shift direction. When the input direction of the data signal to the bidirectional shift register 21 is the left shift direction (when the data signal is input to the left shift input terminal 24), the clock supply circuit 29 outputs the clock signal to the clock line. The supply direction of the clock pulse Pc to 27 is switched so as to be in the direction of arrow A which is the direction opposite to the left shift direction.

As described above, when the supply direction of the clock pulse Pc and the shift direction of the bidirectional shift register 21 are opposite to each other, the transmission time of the clock pulse Pc on the clock line 27 becomes longer. Even if the phenomenon occurs that the clock pulse Pc is delayed in the bidirectional shift register 21, the clock pulse Pc
At the time before the signal is input, there is no possibility that the output of the flip-flop 22 located at the preceding stage is inverted. As a result, the data signal is applied to the flip-flop 22 as in the prior art.
Can be suppressed. Therefore, it is possible to prevent a situation in which an abnormality occurs in the drive state of the scan electrode 11a by the drive unit 14 due to a malfunction of the bidirectional shift register 21.

In this case, the switching control of the supply direction of the clock pulse Pc by the clock supply circuit 29 is performed every time the shift direction of the bidirectional shift register 21 is reversed, so that a malfunction may occur. In addition, it is possible to always suppress the possibility that an abnormality occurs in the driving state of the scanning electrode 11a due to such a malfunction.

Further, in the present embodiment, the supply direction of the clock pulse Pc by the clock supply circuit 29 as described above can be switched only by changing the level of the switching command signal Sc input to the switching terminal 33. With this configuration, switching control of the supply direction of the clock pulse Pc can be performed extremely easily.

In the case where the serial output of the bidirectional shift register 21 is used, as described above, the supply direction of the clock pulse Pc and the shift direction of the bidirectional shift register 21 are controlled by the clock supply circuit 29. In the state controlled to be in the opposite direction, the clock line 2
7, the transmission time of the clock pulse Pc is delayed as the transmission distance becomes longer, but the flip-flop located at the last stage (output stage) in the bidirectional shift register 21. The clock pulse Pc is given at the earliest timing. As a result, the phenomenon that the operation speed of the bidirectional shift register 21 is delayed by the delay time of the clock pulse Pc does not occur.

It should be noted that the present invention is not limited to the above-described embodiment, and the following modifications or extensions are possible. Although the serial / parallel output type bidirectional shift register 21 has been described as an example, it is needless to say that the present invention can be applied to a parallel output type or serial output type bidirectional shift register. Of course, the load to be driven is not limited to the scanning electrodes 11a and the data electrodes 11b of the EL panel 11. Although the three-state buffer circuit is used as the first and second switch elements, the switch element may be configured by combining gate circuits and the like. The resistor in the voltage dividing circuit 19 may be made of, for example, polycrystalline silicon.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a configuration of a main part of an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing a configuration of a driving unit.

FIG. 3 is a functional block diagram showing a schematic configuration of a driver IC.

FIG. 4 is a functional block diagram showing a conventional configuration.

[Explanation of symbols]

11 is an EL panel (matrix display device), 11a is a scanning electrode (load), 11b is a data electrode (load), 12
Is a driver IC, 13 is a control circuit, 14 is a driving unit (driving means), 15 is a high voltage output unit, 16 is a voltage level conversion unit, 21 is a bidirectional shift register, 22 is a flip-flop, 27 is a clock line, 29 Denotes a clock supply circuit (signal direction switching means), 30 denotes a first three-state buffer circuit (first switch element), and 31 denotes a second three-state buffer circuit (second switch element).

Claims (8)

[Claims] 1. A shift circuit comprising a bi-directional shift register (21) comprising a plurality of flip-flops (22) and supplying a clock pulse for each flip-flop (22) from a common clock line (27). The register device, further comprising: signal direction switching means (29) provided so as to be capable of switching the supply direction of the clock pulse to the clock line (27) in a forward / reverse direction, wherein the signal direction switching means (29) comprises: A shift register device, characterized in that a supply direction of a clock pulse to the clock line (27) is controlled to be opposite to an input direction of a data signal supplied to the register (21). 2. The signal direction switching means (29) inverts between a low impedance state in which a clock pulse is applied to the clock line (27) in a forward direction and a high impedance state in which passage of a clock pulse is prohibited. And a second switch element (31) for inverting between a low impedance state in which the clock pulse is applied in the opposite direction to the clock line (27) and a high impedance state in which passage of the clock pulse is prohibited. Wherein only one of the first and second switch elements (30, 31) is selectively inverted to a low impedance state in response to an input of a switching command signal. 2. The shift register device according to 1. 3. The shift register device according to claim 1, wherein said bidirectional shift register is of a parallel output type. 4. The shift register device according to claim 1, wherein said bidirectional shift register is of a serial output type. 5. The bidirectional shift register (21),
3. The shift register device according to claim 1, wherein the shift register device is of a serial / parallel output type. 6. A shift comprising a bi-directional shift register (21) comprising a plurality of flip-flops (22) and receiving clock pulses for each flip-flop (22) from a common clock line (27). A load driving device comprising: a register device; and driving means (14) for selectively energizing a plurality of loads (11a) based on each bit output of the bidirectional shift register (21). And a signal direction switching means (29) provided so as to be capable of switching the supply direction of the clock pulse to the bidirectional shift register (21). The supply direction of the clock pulse to the clock line (27) is controlled to be opposite to the input direction of Load driving apparatus according to claim and. 7. The driving means (14) includes a high voltage output circuit (15) for generating a high voltage based on the output of the bidirectional shift register (21).
The load driving device according to claim 6, wherein the output of (5) is provided to the load (11a). 8. The load of the matrix type display device (1)
1) scanning electrode (11a) or data electrode (1).
The load driving device according to claim 6, wherein the load driving device is 1b).