JP2002084071A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board where an electronic part is incorporated in a build-up layer coping with higher density of wiring, the continuity between the electronic part and the internal wiring layer is assured when an IC chip is mounted and a peeling never occurs in the build-up layer. SOLUTION: The wiring board is provided where, comprising a core substrate 2 and a build-up layer 16, an IC chip 44 is mounted. An electronic part 10 is incorporated at least in such build-up layer 16 as the mounting position of the IC chip 44 is projected in the thickness direction of the wiring board. The wiring board 1 has such relations as α4<α3<=α1<α2 where α2 is a thermal expansion factor of the build-up layer 16, α3 is that of the electronic part 10, and α4 is that of the IC chip 44.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board on which electronic components are incorporated and on which an IC chip is mounted.

[0002]

2. Description of the Related Art In recent years, with the demand for higher density and higher performance of wiring substrates, electronic components are built in a build-up layer in which insulating layers and wiring layers formed on the surface of a core substrate are alternately laminated. (Japanese Unexamined Patent Publication No.
See Japanese Patent Application Laid-Open No. 1-274734). The wiring board (electronic circuit device) is connected to a land formed on the surface of a circuit board serving as a core material via a conductive resin with a solder bump protruding from the bottom surface of the electronic component, thereby connecting the electronic component to the core material. By mounting directly on the surface of the circuit board, high density is supported.

[0003]

However, in the wiring board of the above-described embodiment, depending on the combination of the thermal expansion coefficient between the circuit board serving as the core material, the electronic component, and the build-up layer, the electronic component and the wiring layer may not be connected to each other. In some cases, the connection wiring may be disconnected, or the insulating layer in the build-up layer may be peeled off. In particular, when the IC chip is mounted on the main surface of the wiring board, the above-described inconvenience is more likely to occur. The present invention solves the above-described problems in the conventional technology, incorporates an electronic component in a build-up layer in order to cope with a higher density of wiring, and further incorporates an electronic component when an IC chip is mounted. It is an object of the present invention to provide a wiring board which ensures conduction with an internal wiring layer and prevents peeling in a build-up layer.

[0004]

According to the present invention, a thermal expansion coefficient between a core substrate, a build-up layer, an electronic component, and an IC chip constituting a wiring board is fixed to a certain relationship. It was made inspired by the provisions of That is, one wiring board of the present invention (claim 1)
A wiring board having a core substrate and a build-up layer, wherein electronic components are incorporated in the build-up layer, a thermal expansion coefficient α1 of the core substrate, a thermal expansion coefficient α2 of the build-up layer, and Thermal expansion coefficient α3 of the electronic component
Has a relationship shown in Expression 3.

[0005]

[Equation 3] α3 ≦ α1 <α2

According to this, since the thermal expansions of the core substrate, the build-up layer, and the electronic component match each other, conduction between the electronic component and the internal wiring layer can be ensured, and the build-up layer Of the insulating layer can be reliably prevented. In particular, since the thermal expansions of the core substrate and the electronic component match each other, poor connection between the electronic component and the core substrate can be reliably prevented. Therefore, it is possible to stably provide a wiring board that can cope with high-density and miniaturization of wiring and that can achieve high performance. Note that the build-up layer refers to a portion of a laminated structure in which wiring layers and insulating layers are alternately laminated on at least one of the front surface and the back surface of the core substrate. The coefficient of thermal expansion of the build-up layer refers to the coefficient of thermal expansion of the insulating layer portion in the laminated structure including the wiring layer and the insulating layer. This is because the wiring layer is generally capable of being plastically deformed, so that the influence of thermal expansion need not be considered small. In addition, the coefficient of thermal expansion referred to here indicates a coefficient of thermal expansion along a direction parallel to the main surface of the wiring board.

In addition to the above-mentioned core substrate, a multi-layer substrate comprising a plurality of insulating layers and one or a plurality of wiring layers (internal wiring) formed between the insulating layers, in addition to the form comprising only a single insulating layer, is also available. included. The terminals of the IC chip and the electrodes of the electronic component may be directly connected to each other, or the terminals of the IC chip and the electrodes of the electronic component may be connected in a state where the electronic component is completely embedded in the build-up layer. They may not be directly connected, but may be connected to each other via a wiring layer or via conductor. in addition,
The above electronic components include capacitors, inductors, filters, resistors, low noise amplifiers (LNA), transistors,
It includes a SAW filter, an LC filter, an antenna switch module, a coupler, a diplexer, a duplexer, and the like. In addition, a chip-shaped electronic component and an electronic component unit in which a plurality of such chip-shaped electronic components are set are also included.

Another wiring board of the present invention (Claim 2)
Is a wiring board having a core substrate and a build-up layer and mounting an IC chip, wherein at least the IC
The electronic component is built in the build-up layer formed by projecting the mounting position of the chip in the thickness direction of the wiring board, and the coefficient of thermal expansion α1 of the core substrate, the coefficient of thermal expansion α2 of the build-up layer, The coefficient of thermal expansion α3 of the electronic component and the coefficient of thermal expansion α4 of the IC chip are in a relationship represented by Formula 4.

[0009]

## EQU4 ## α4 <α3 ≦ α1 <α2

According to this wiring board, the thermal expansion of the core substrate, the build-up layer, the electronic component, and the thermal expansion of the IC chip match each other, so that conduction between the electronic component or the IC chip and the internal wiring layer is maintained. In addition to the above, the peeling of the insulating layer in the build-up layer can be reliably prevented. In particular, since the thermal expansions of the core substrate, the electronic component, and the IC chip match each other, the connection failure between the electronic component and the core substrate is reliably prevented, and the connection failure between the electronic component and the IC chip is also prevented. it can. Therefore, it is possible to more easily cope with high density and miniaturization of wiring, and it is possible to reliably provide a high-performance wiring board.

In general, the build-up layer is flexible and compliant, so that it can withstand a thermal expansion mismatch.
Since IC chips and electronic components have high elasticity, it is difficult to withstand a thermal expansion mismatch. Equation 4 takes these into consideration. Further, the position where the IC chip is mounted is not limited to the position on the first main surface of the wiring board, but also includes the position in the build-up layer at a position where all or a part of the built-in electronic component overlaps in plan view. It is.
Furthermore, the terminals of the IC chip may be directly connected to the electrodes of the electronic component, or the terminals of the IC chip and the electrodes of the electronic component may be connected in a state where the electronic component is completely embedded in the build-up layer. They may not be directly connected, but may be connected to each other via a wiring layer or via conductor. In addition, the present invention includes:
In any one of the above wiring boards, the electronic component also includes a wiring board that is embedded in the built-up layer via at least one insulating layer on at least one of a front surface and a back surface of the core substrate. Can be

Further, the present invention also includes a wiring board in which the core substrate has a coefficient of thermal expansion α1 of 40 ppm / ° C. or less. According to this, the core substrate itself can reliably suppress the breakage or peeling of the insulating layer in the build-up layer described above, and can prevent the thermal expansion of electronic components and IC chips from affecting the core substrate and the build-up layer. It can be prevented more reliably. Note that the thermal expansion coefficient α1 of the core substrate is
If it exceeds 40 ppm / ° C., it is difficult to practically satisfy the relations of the above formulas 3 and 4, so the content was set to less than this.
In addition, it is desirable that the coefficient of thermal expansion α1 be 35 ppm / ° C. or less.

Further, according to the present invention, there is provided a wiring board wherein the thermal expansion coefficient α2 of the build-up layer is 75 ppm / ° C. or less.
(Claim 4) is also included. According to this, similarly to the above, damage to the insulating layer in the build-up layer can be reliably suppressed, and the influence on the core substrate and the build-up layer due to thermal expansion of electronic components and IC chips can be more reliably prevented. If the coefficient of thermal expansion α2 exceeds 75 ppm / ° C., it is difficult to practically satisfy the relations of the above formulas 3 and 4, so the value is set to less than this. The desirable coefficient of thermal expansion α2 is 70 pp.
m / ° C. or less.

In addition, the present invention also includes a wiring board (Claim 5) in which the terminals of the IC chip and the electrodes of the electronic component are directly connected. According to this, the above IC
Conduction between the chip and the electronic component can be ensured in the shortest and assured manner, a stable function can be exhibited between the two, and the electrical characteristics such as a reduction in loop inductance can be enhanced. It should be noted that the electronic component is
It is also possible to use a wiring board that is also built in the build-up layer on which the C chip is mounted and the build-up layer on the opposite side of the core substrate with the core substrate therebetween. In this case, a plurality of electronic components can be embedded substantially symmetrically on the front surface and the back surface of the core substrate. For this reason, a plurality of electronic components can be built into a wiring board of a certain thickness, which leads to higher density wiring,
It becomes easy to provide a wiring board that can easily cope with higher functions and higher performance.

[0015]

Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a cross section of a main part of a wiring board 1 corresponding to claim 2 of the present invention. The wiring board 1 includes a core substrate 2, a plurality of insulating layers 17, 21, 25, 31, 35, 39 and wiring layers 18, 22, 26, 32, 36, 40 on the front surface 3 and the back surface 4. And build-up layers 16 and 30 alternately laminated. The core substrate 2 is made of, for example, a composite material of glass-epoxy resin, and has a surface 3 and a back surface 4 with a thickness of about 0.8 mm.
And an insulating plate material having a rectangular shape in a plan view. The coefficient of thermal expansion α1 of the core substrate 2 is about 15 ppm / ° C. As shown in FIG. 1, a plurality of through holes 6 penetrate between the front surface 3 and the back surface 4 of the core substrate 2, and a through hole conductor 8 and a filling resin 9 are formed therein.

The wiring layer 18 on the surface 3 of the core substrate 2
A substantially square electronic component 10 is mounted on the wiring 18a in plan view. The electronic component 10 is, for example, a box-shaped chip capacitor, and has a plurality of electrodes 12 made of Cu protruding on its upper surface with a thickness of about several tens μm.
The coefficient of thermal expansion α3 of the electronic component 10 is about 6 to 13 pp.
m / ° C. (in the present embodiment, for example, 10 ppm / ° C.). A plurality of electrodes 13 are provided on the bottom side of the electronic component 10.
Are embedded, and solder bumps 14 project from the surfaces thereof with a thickness of about several tens of μm. By reflowing the bumps 14, each bump 14 and the wiring 18a are individually connected. In this case, an electrical connection may be made between the bump 14 and the wiring 18a with an anisotropic conductive film or an anisotropic conductive resin interposed therebetween. As the chip capacitor, for example, a ceramic capacitor in which a dielectric layer mainly containing barium titanate and an electrode layer mainly containing Ni are alternately laminated is used. Also,
The wiring layer 18 (wiring 18 a)
And the wiring layer 32 below the back surface 4 of the core substrate 2 through the conductive layer.

As shown in FIG. 1, above the surface 3 of the core substrate 2, insulating layers 17, 21, 25 made of an epoxy resin containing an inorganic filler, for example, silica filler, are provided.
The build-up layer 16 in which the Cu wiring layers 18, 22, 26 are alternately stacked is formed. The thermal expansion coefficient α2 of the build-up layer 16 is about 65 ppm / ° C. In via holes 19 and 23 formed in insulating layers 17 and 21,
Via conductors 20 and 2 connecting between wiring layers 18, 22 and 26
4 are formed. A plurality of solder bumps 28 penetrating the insulating layer 25 and projecting higher than the first main surface 29 are formed at predetermined positions on the uppermost wiring layer 26 (under the solder resist layer 25). Each bump 28
It is individually connected to a plurality of terminals 46 protruding from the bottom surface of the IC chip 44 mounted on the first main surface 29.

Further, as shown in FIG.
Penetrates the insulating layers 17, 21 and 25, and the upper surface thereof is flush with the uppermost insulating layer (solder resist layer) 25 and forms a part of the first main surface 29. The plurality of electrodes 12 protruding from the upper surface of the electronic component 10 are also individually connected to the terminals 46 of the IC chip 44 by soldering or the like.
The thermal expansion coefficient α4 of the IC chip 44 is about 3 to 4 p.
pm / ° C. The bottom surface of the IC chip 44 and the first main surface 29
Is filled with an underfill material (not shown) so as to seal the solder bumps 28, the electrodes 12, and the terminals 46.

Further, as shown in FIG. 1, below the back surface 4 of the core substrate 2, insulating layers 31, 35, 39 made of epoxy resin containing silica filler and wiring layers 32,
The build-up layer 30 in which the layers 36 and 40 are alternately stacked is formed. Among these, via conductors 34 and 38 for connecting the wiring layers 32, 36 and 40 are formed in the via holes 33 and 37 in the insulating layers 31 and 35, respectively. Also, the second main surface 42 of the insulating layer (solder resist layer) 39 located at the lowermost layer
A part of the wiring layer 40 is exposed in the openings 39a, 39a provided toward the substrate, and Ni and Au are formed on the surface.
Connection terminals 40a, 40a covered with a plating film are formed. These connection terminals 40a are used for connection to a printed board such as a motherboard (not shown) on which the wiring board 1 itself is mounted. Incidentally, a pin (not shown) made of a copper-based or iron-based alloy may be joined to the connection terminal 40a via a Sn-Sb-based alloy solder.

As shown in FIG. 1, the IC chip 44 has a first position at a position directly above a position where the electronic component 10 is incorporated.
Mounted on the main surface 29. In other words, the electronic component 10
Indicates the position (mounting area) where the IC chip 44 is mounted,
It is built in the build-up layer 16 projected in the thickness direction of the wiring board 1. Moreover, the plurality of terminals 46 of the IC chip 44 and the plurality of electrodes 12 of the electronic component 10 are directly connected. Therefore, the loop inductance between the two can be reduced. By the way, there is a relationship of the following equation (5) between the thermal expansion coefficients α1, α2, α3 of the core substrate 2, the build-up layer 16, and the electronic component 10. That is, the thermal expansion coefficient α2 of the build-up layer 16
Is larger than the thermal expansion coefficients α1 and α3 of the core substrate 2 and the electronic component 10, and the thermal expansion coefficient α3 of the electronic component 10 is equal to or smaller than the thermal expansion coefficient α1 of the core substrate 2. It is set in advance on the substrate 1.

[0021]

[Equation 5] α3 ≦ α1 <α2

Therefore, when placed in a high temperature environment,
Even if the electronic component 10 expands, the build-up layer 16 expands more than that. Therefore, the connection between the bumps 14 of the electronic component 10 and the wiring 18a of the wiring layer 18 can be easily maintained, and even if the electronic component 10 expands, the insulating layers 17, 21, and 25 of the build-up layer 16 are further increased. Because of expansion, peeling or breakage can be prevented. Moreover, by matching the thermal expansion of the core substrate 2 and the electronic component 10 as in Equation 5, poor connection between them can be prevented.
The control of the coefficient of thermal expansion α1 of the core substrate 2 and the coefficient of thermal expansion α2 of the build-up layer 16 is controlled by the core substrate 2 and the insulating layer 1
This is performed by adjusting the shape, particle size, compounding amount, and the like of the glass cloth and the inorganic filler contained in the resin that forms No. 7 and the like. Equation 5 shows that the thermal expansion coefficient α of the IC chip 44 is
When 4 is further added, the thermal expansion coefficients α1 to α4 have the relationship of Expression 6. That is, the thermal expansion coefficient α4 of the IC chip 44 is smaller than the thermal expansion coefficient α3 of the electronic component 10 and smaller than the thermal expansion coefficients α2 and α1 of the build-up layer 16 and the core substrate 2. It is set in advance.

[0023]

[Equation 6] α4 <α3 ≦ α1 <α2

For this reason, as shown in FIG.
Even if the IC chip 44 expands during the heating of the solder bumps 28 when the IC chip 44 is mounted on the main surface 29, the thermal expansion coefficient α4 is smaller than the thermal expansion coefficient α3 of the electronic component 10; It does not affect the build-up layer 16 or the core substrate 2. Therefore, the connection between the terminal 46 of the mounted IC chip 44 and the electrode 12 of the electronic component 10 can be easily maintained for a long period of time, and the conduction between the two can be stably and reliably achieved. According to the wiring board 1 as described above, the conduction between the electronic component 10 mounted on the surface 3 of the core substrate 1 and the wiring layer 18 of the build-up layer 16 can be reliably and stably obtained. Via conductor 8
Stable conduction can also be achieved between the electronic component 10 and the wiring layers 22, 26, 32, 36, 40. Further, the mounted IC chip 44 is also connected via the solder bump 28 and the wiring layer 26,
Stable continuity with each wiring layer can be obtained. In addition, since the IC chip 44 and the electronic component 10 directly connect the terminal 46 and the electrode 12, conduction can be ensured at the shortest distance,
In addition, it is possible to contribute to enhancing electrical characteristics such as reduction of loop inductance.

A manufacturing process for obtaining the wiring board 1 will be described with reference to FIGS. As shown in FIG. 2A, the front surface 3 and the back surface 4 of the core substrate 2 having a thickness of about 0.8 mm
Copper foils 3a and 4a having a thickness of several tens of μm are coated in advance, and through holes 6 and 6 are drilled at predetermined positions by a drill. Next, after plating catalyst nuclei such as Pd are previously attached to the inner surfaces of the through holes 6 and 6, electroless copper plating and electrolytic copper plating are performed. As a result, as shown in FIG. 2B, through-hole conductors 8, 8 are formed on the inner surfaces of the through-holes 6, 6, and a filling resin 9 is formed on the inside. Also, by applying a known build-up technique (subtractive method in this case) to the copper foils 3a and 4a, as shown in FIG. The wiring layer 18 of the pattern and the wiring layer 32 below the back surface 4 are formed. Wiring layers 18, 32
Are also connected to the upper end or the lower end of the through-hole conductor 8, so that they can be conducted to each other.

Further, as shown in FIG. 2C, solder bumps 14 protruding from the bottom side of the electronic component 10 are individually brought into contact with the plurality of wirings 18a, and the bumps 14 are reflowed to connect them. I do. As a result, the electronic component 10 is mounted on the surface 3 of the core substrate 2. Next, as shown in FIG.
2 and insulating layers 17 and 3 mainly composed of epoxy resin.
Form one. The thickness of the insulating layer 17 is about half or less of the thickness of the electronic component 10. Next, as shown in FIG.
Laser irradiation or the like is performed on predetermined positions of the insulating layers 17 and 31 to form conical via holes 19 and 33.
Note that CO ₂ , YAG, excimer laser, or the like is used as the laser. A copper plating film (not shown) is formed on the entire surfaces of the insulating layers 17 and 31 including the via holes 19 and 33, and a known build-up technique (here, a semi-additive method) is applied thereto. As a result, as shown in FIG. 3B, via conductors 20 and 34 are formed in via holes 19 and 33, respectively.
However, on the insulating layer 17 and below the insulating layer 31, the wiring layer 22,
36 are formed individually.

Further, as shown in FIG.
Above and below the wiring layer 36, insulating layers 21 and 3 similar to those described above.
5 is formed. Next, after forming via holes 23 and 37 in the insulating layers 21 and 35 and forming a copper plating film in the same manner as described above, a known build-up technique is performed. As a result, FIG.
As shown in (A), wiring layers 26 and 40 including via conductors 24 and 38 are formed on the insulating layer 21 and below the insulating layer 35. Further, as shown in FIG. 4B, insulating layers (solder resist layers) 25 and 39 are formed on the wiring layer 26 and below the wiring layer 40.
To form At this time, the surface of the insulating layer 25 is
By being flattened to be flush with the top surface of 0,
A first main surface 29 extending between the two is formed.

A hole is formed in a predetermined position of the uppermost insulating layer 25 by laser irradiation or the like, and solder is printed on the exposed wiring layer 26, as shown in FIG. A plurality of solder bumps 28 are provided on both sides (around)
It is formed higher than the main surface 29. Also, at predetermined positions of the lowermost insulating layer 39, the build-up technique is performed to form openings 39a, 39a facing the second main surface 42 side. A part of the wiring layer 40 is exposed at the bottom thereof,
By coating the surface with Ni and Au plating films,
Connection terminals 40a, 40a are formed. This connection terminal 4
0a is used for connection with a motherboard (not shown) on which the wiring board (1 ') itself is mounted.

By the above manufacturing steps, as shown in FIG. 4C, the electronic component 10 is built in the build-up layer 16 on the front surface 3 of the core substrate 2, and the upper and lower surfaces 4 A wiring board 1 'corresponding to claim 1 of the present invention, wherein the build-up layers 16 and 30 are formed on the electronic component 10 and the IC chip 44 can be mounted directly on the built-in electronic component 10. be able to. The materials of the thermal expansion coefficients α1 to α3 of the core substrate 2, the electronic component 10, and the build-up layer 16 are selected so as to maintain the relationship of the above equation (5). Further, the known build-up technique includes a technique of laminating an insulating layer of a film or liquid resin, a technique of forming a via hole by photolithography or laser processing, and further, a semi-additive method, a full-additive method, or Techniques for forming via conductors and wiring layers by a subtractive method are included, but not limited thereto.

FIG. 5 shows a cross section of a main part of a wiring board 1a in an application form of the wiring board 1. As shown in FIG. Wiring board 1a
As shown in FIG. 5, on the first main surface 29 directly above the electronic component 10 built in the build-up layer 16, the core substrate 2 and the build-up layers 16 and 30 are provided. An electronic component 10a is also built in a symmetrical position of the buildup layer 30 with the core substrate 2 interposed therebetween. As shown in FIG. 5, a wiring layer 32 having a plurality of wirings 32a is formed under the back surface 4 of the core substrate 2 to individually connect to a plurality of solder bumps 14 projecting from the upper surface of the electronic component 10a. I have. The electronic component 10 a penetrates the insulating layers 31, 35, and 39, and the bottom surface thereof is the second main surface 42 below the lowermost insulating layer 39.
It is built so as to be on the same plane as. The second main surface 42
The opening 39a and the connection terminal 40a on the side are formed at positions where the electronic component 10a is removed as shown in FIG.

The coefficient of thermal expansion α of the core substrate 2, the electronic component 10a, and the build-up layer 30 in the wiring substrate 1a
1 to α3 also satisfy the relationship shown in Expression 5 above.
Each material is set in advance. According to the above wiring board 1a, the electronic components 10, 10a and the wiring layers 18, 3
2 is reliably and stably provided, and the electronic component 1
The continuity between 0, 10a and the through-hole conductor 8
Can be surely conducted through. In addition, the conduction between the IC chip 44 mounted on the first main surface 29 and the electronic component 10 and the conduction between the IC chip 44 and the wiring layer 26 can be stably obtained. Furthermore,
The electrode 12 protruding from the bottom surface of the electronic component 10a can be directly connected to a terminal (not shown) of a mother board such as a printed circuit board. Therefore, the internal wiring and the plurality of electronic components 10 and 10a can be arranged at a high density, and it is possible to easily respond to a demand for high functionality and high performance.

FIG. 6 shows a cross section of a main part of a wiring board 50 of a different form. The wiring board 50 includes a core substrate 51 located at the center in the thickness direction, and a build-up layer BU1 in which a plurality of insulating layers 54, 66, 74 and wiring layers 58, 64, 72 are alternately stacked on a surface 52 thereof. And a build-up layer BU2 in which a plurality of insulating layers 55, 67, 75 and wiring layers 59, 65, 73 are alternately stacked below the back surface 53 of the core substrate 51. The core substrate 51 is made of, for example, a glass-epoxy resin-based insulating material and has a thickness of about 0.4 m.
m is an insulating plate material having a rectangular shape in plan view. The coefficient of thermal expansion α1 of the core substrate 51 is about 15 ppm / ° C.

The insulating layers 54 and 55 are made of an insulating resin of an epoxy resin containing silica filler and have a thickness of about 30 μm.
m. Further, the wiring layers 58 and 59 are formed of copper plating and have a thickness of about 15 μm. As shown in FIG. 6, a plurality of through holes 61 penetrate between a surface 56 of the insulating layer 54 and a back surface 57 of the insulating layer 55 with the core substrate 51 interposed therebetween, and a through hole conductor 62 and the filling resin 63 are individually formed. The through-hole conductor 62 is connected to the wiring layers 64 and 65 at the upper end or the lower end, and is also connected to the wiring layers 58 and 59 at an intermediate position. On the wiring 64a in the wiring layer 64 on the surface 56 of the insulating layer 54, a substantially square electronic component 70 in a plan view is mounted. The electronic component 70 is, for example, a box-shaped chip capacitor, and has a plurality of electrodes 79 made of Cu protruding on its upper surface with a thickness of about several tens of μm.

Further, the thermal expansion coefficient α3 of the electronic component 70 is about 6 to 13 ppm / ° C. A plurality of electrodes 71a are buried on the bottom surface side of the electronic component 70, and solder bumps 71 protrude on the surface thereof with a thickness of about several tens of μm.
By reflowing the bumps 71, each bump 71 and the wiring 64a are individually connected. In this case, an electrical connection may be made between the bump 71 and the wiring 64a with an anisotropic conductive film or an anisotropic conductive resin interposed therebetween. As the chip capacitor, for example, a ceramic capacitor in which a dielectric layer mainly containing barium titanate and an electrode layer mainly containing Ni are alternately laminated is used. Further, the wiring layer 64 (wiring 64 a) is also connected to the through-hole conductor 62 and is also electrically connected to the wiring layer 65 below the back surface 57 of the insulating layer 55 via the wiring layer 64.

As shown in FIG. 6, the surface 56 of the insulating layer 54
Above this, an insulating layer 66 made of epoxy resin and a solder resist layer (insulating layer) 74, a copper wiring layer 64,
72 are alternately stacked, and together with the wiring layer 58 and the insulating layer 54, form the build-up layer BU1. The thermal expansion coefficient α2 of the build-up layer BU1 is about 65 ppm
/ ° C. The via holes formed in the insulating layer 66 include:
A via conductor 68 connecting between the wiring layers 64 and 72 is formed. The uppermost wiring layer 72 (solder resist layer 74)
A plurality of solder bumps 78 penetrating through the solder resist layer 74 and protruding higher than the first main surface 76 are formed at predetermined positions of (lower layer). The solder bump 78 is made of S
n-Ag, Pb-Sn, Sn-Ag-Cu, Sn
A plurality of low melting point alloys such as Cu-based or Sn-Zn-based, and projecting from the bottom surface of an IC chip (semiconductor element) 80 mounted on the first main surface 76 which is the surface of the build-up layer BU1. The terminal 82 is individually connected.

Further, as shown in FIG.
Penetrates the insulating layers 66 and 74, and the upper surface thereof is flush with the uppermost solder resist layer 74 to form a part of the first main surface 76. The plurality of electrodes 79 projecting from the upper surface of the electronic component 70 are also directly connected to the terminals 82 of the IC chip 80 individually by soldering or the like. The thermal expansion coefficient α4 of the IC chip 80 is about 3 to 4 ppm / ° C. Between the bottom surface of the IC chip 80 and the first main surface 76,
An underfill material (not shown) is filled so as to seal the solder bumps 78, the electrodes 79, and the terminals 82.

Further, as shown in FIG. 6, below the back surface 57 of the insulating layer 55, an insulating layer 67 made of the same resin as described above is provided.
And a solder resist layer (insulating layer) 75 and a wiring layer 65,
73 are alternately stacked to form the build-up layer BU2 together with the wiring layer 59 and the insulating layer 55. Via conductors 6 connecting between wiring layers 65 and 73 are provided in via holes in insulating layer 67.
9 is formed. Further, in the plurality of openings 81 provided toward the second main surface 77 side of the solder resist layer 75 located at the lowermost layer, a part of the wiring layer 73 is exposed, and the surface of the wiring layer 73 is plated with Ni and Au. The connection terminal 83 covered with the film is formed. These connection terminals 83 are used for connection to a printed board such as a motherboard (not shown) on which the wiring board 50 itself is mounted. Note that a gap 60 can be provided inside the wiring layer 59 to insulate the wiring layer 59 from the through-hole conductor 62.

As shown in FIG. 6, the IC chip 80 has a first position at a position immediately above a position where the electronic component 70 is embedded.
Mounted on main surface 76. In other words, the electronic component 70
Indicates the position (mounting area) where the IC chip 80 is mounted,
Build-up layer BU projected in the thickness direction of wiring substrate 50
1 is built in. In addition, the plurality of terminals 82 of the IC chip 80 and the plurality of electrodes 7 of the electronic component 70
9 is directly connected, so that the loop inductance between the two can be reduced. By the way, the following equation 7 is established between the thermal expansion coefficient α1 of the core substrate 51, the thermal expansion coefficient α2 of the build-up layer BU1, and the thermal expansion coefficient α3 of the electronic component 70. That is, build-up layer B
The coefficient of thermal expansion α2 of U1 is larger than the coefficient of thermal expansion α1 of the core substrate 51 and the coefficient of thermal expansion α3 of the electronic component 70, and the coefficient of thermal expansion α3 of the electronic component 70 is the same as the coefficient of thermal expansion α1 of the core substrate 51? Or smaller than this in the wiring board 50.

[0039]

[Equation 7] α3 ≦ α1 <α2

Therefore, when the electronic component 70 expands under a high temperature environment, the build-up layer BU1 expands more than that. Therefore, the connection between the bump 71 of the electronic component 70 and the wiring 64a of the wiring layer 64 is easily maintained, and even if the electronic component 70 expands, the build-up layer BU1 is formed.
Since the insulating layers 66 and 74 expand more, it is possible to prevent the layers from being peeled or damaged. Moreover, as shown in Equation 7, the core substrate 51 and the insulating layer 5 of the build-up layer BU1 are formed.
By matching the thermal expansion of the electronic components 70 with the 4, 66, 74, it is also possible to prevent poor connection between the three components. Equation 7 shows that the thermal expansion coefficient α of the IC chip 80 is
When 4 is further added, the thermal expansion coefficients α1 to α4 have the relationship of Expression 8. That is, the thermal expansion coefficient α4 of the IC chip 80 is smaller than the thermal expansion coefficient α3 of the electronic component 70 and smaller than the thermal expansion coefficients α2 and α1 of the build-up layer BU1 and the core substrate 51. It is set in advance.

[0041]

[Equation 8] α4 <α3 ≦ α1 <α2

For this reason, as shown in FIG.
Even when the IC chip 80 expands during the heating of the solder bumps 78 when the IC chip 80 is mounted on the main surface 76, the thermal expansion coefficient α4 is smaller than the thermal expansion coefficient α3 of the electronic component 70. Build-up layer BU1 and core substrate 5
No effect on 1 Therefore, the connection between the terminal 82 of the mounted IC chip 80 and the electrode 79 of the electronic component 70 is reliably maintained, so that it is possible to stably and reliably establish conduction between the two.

According to the wiring board 50 as described above, the continuity between the electronic component 70 built in the build-up layer BU1 and the wiring layer 64 of the build-up layer BU1 can be ensured and stably provided. And through-hole conductor 6
2, the electronic component 70 and the wiring layers 58, 59, 65,
Conduction can be stably conducted between the first and third members. In addition, I
The C chip 80 also has stable conduction with each of the above wiring layers via the solder bumps 78 and the wiring layers 72 and the like. In addition, since the IC chip 80 and the electronic component 70 directly connect the terminal 82 and the electrode 79, the IC chip 80 and the electronic component 70 can be connected more reliably at the shortest distance, and the electrical characteristics such as the loop inductance can be reduced. Can also contribute.

7 to 9, the wiring substrate 50 is obtained.
The manufacturing process for the following will be described. As shown in FIG.
Front surface 52 and back surface of core substrate 51 having a thickness of about 0.4 mm
53, copper foils 52a and 53a having a thickness of several tens μm
Coated. On such copper foils 52a and 53a,
Has a predetermined pattern by well-known photolithography technology
Forming an etching resist and performing etching
As a result, as shown in FIG.
A wiring layer 58 following the above pattern
59 is formed. At this time, a gap 60 is formed in the wiring layer 59.
To achieve. Next, the wiring layers 58 and 59 and the core substrate 51
Apply epoxy resin on the front surface 52 and the back surface 53
Then, as shown in FIG. 7B, insulating layers 54 and 55 are formed.
You. Further, as shown in FIG.
At the predetermined position on the 6 side, CO ₂, YAG, or excimer
Irradiation with laser L such as a laser
The rill is inserted along the thickness direction of the core substrate 51 or the like.

As a result, as shown in FIG. 7C, through holes 61 penetrating the wiring layers 58, 59 are formed. Next, Pd is formed on the inner surface of each through hole 61 in advance.
Then, electroless copper plating and electrolytic copper plating are performed after attaching a catalyst core for plating. As a result, as shown in FIG. 7D, through-hole conductors 62, 62 are formed along the inner walls of the through-holes 61, 61. At the same time, the insulating layer 5
4 and the back surface 57 of the insulating layer 55, copper plating layers 56a and 57a are formed. Further, after the filling resin 63 is formed inside the through-hole conductor 62, the upper and lower ends thereof are plated with a lid. Next, by applying a known build-up technique (here, a subtractive method) to the copper plating layers 56a and 57a, the wiring 64a is included on the surface 56 of the insulating layer 54 as shown in FIG. A wiring layer 64 having a predetermined pattern is formed under the back surface 57 of the insulating layer 55 by the wiring layer 65.
Are formed respectively. Since the wiring layers 64 and 65 are also connected to the upper end or the lower end of the through-hole conductor 62, they can be electrically connected to each other.

Further, as shown in FIG. 8B, solder bumps 71 protruding from the bottom side of the electronic component 70 are individually brought into contact with the plurality of wirings 64a, and the bumps 71 are reflowed to connect them. I do. As a result, the electronic component 70 is mounted on the surface 56 of the insulating layer 54 in the build-up layer BU1. Next, as shown in FIG. 8C, insulating layers 66 and 67 mainly composed of epoxy resin are formed on the wiring layer 64 and below the wiring layer 65. Insulating layer 66
Is about half or less of the thickness of the electronic component 70.

Next, as shown in FIG.
Laser irradiation or the like is applied to predetermined positions 6 and 67 to form conical via holes 68a and 69a. Note that CO ₂ , YAG, excimer laser, or the like is used as the laser. After a plating resist (not shown) is formed on the entire surfaces of the insulating layers 66 and 67 including the via holes 68a and 69a, a known build-up technique (here, a semi-additive method) is applied thereto. As a result, FIG.
As shown in (A), via conductors 68, 69 are provided in the via holes 68a, 69a on the insulating layer 66 and the insulating layer 67, respectively.
Below, wiring layers 72 and 73 of a predetermined pattern are individually formed.

Further, as shown in FIG.
Insulating layers (solder resist layers) 74 and 75 similar to those described above are formed above and below the wiring layer 73. As a result, the build-up layers BU1, BU2 are formed. At this time, the surface of the solder resist layer 74 is flattened so as to be flush with the upper surface of the electronic component 70, thereby forming the first main surface 76 extending between them. By piercing a predetermined position of the uppermost solder resist layer 74 by laser irradiation or the like and printing solder on the exposed wiring layer 72, FIG.
As shown in (B), a plurality of solder bumps 78 are formed on both sides (around) of the electronic component 70 so as to protrude higher than the first main surface 76. Also, a predetermined position of the lowermost solder resist layer 75 is subjected to a build-up technique to form a plurality of openings 81 opening to the second main surface 77 side. Multiple openings 8
The wiring 83 of the wiring layer 73 is exposed at the bottom of the wiring layer 73. The wiring 83 is formed as a connection terminal by coating the surface thereof with a Ni and Au plating film. The connection terminal (wiring 83) is used for connection to a motherboard (not shown) on which the wiring board 50 itself is mounted.

According to the above manufacturing steps, as shown in FIG. 9B, the electronic component 70 is built in the build-up layer BU1 above the core substrate 51, and on the front surface 52 and the lower surface 53 of the core substrate 51. Build-up layers BU1 and BU2 are formed at the same time, and the I
The C chip 80 can be mounted. As a result, the wiring board 50 shown in FIG. 6 corresponding to the first and second aspects of the present invention can be obtained. The core substrate 51, the electronic component 70,
The materials of the thermal expansion coefficients α1 to α3 of the build-up layer BU1 are selected so as to maintain the relationship of the expression (7).
Further, the known build-up technique includes a technique of laminating an insulating layer of a film or liquid resin, a technique of forming a via hole by photolithography or laser processing, and further, a semi-additive method, a full-additive method, or Techniques for forming via conductors and wiring layers by a subtractive method include, but are not limited to.

FIG. 10 shows a cross section of a main part of a wiring board 50a in an application form of the wiring board 50. As shown in FIG. 10, the wiring board 50a has the same core substrate 51 as the wiring board 50 and the build-up layers BU1 and BU2, and the first board directly above the electronic component 70 built in the build-up layer BU1. The IC chip 80 is mounted on the main surface 76. Moreover, the build-up layer BU sandwiching the core substrate 51
An electronic component 70a is also built in a position symmetrical to the electronic component 70 in FIG. As shown in FIG. 10, under the back surface 57 of the insulating layer 55 in the build-up layer BU2, a wiring having a plurality of wirings 65a for individually connecting to a plurality of solder bumps 71 protruding from the upper surface of the electronic component 70a. A layer 65 is formed.

The electronic component 70a includes insulating layers 67 and 7
5 and is built in the build-up layer BU2 such that the bottom surface of the electronic component 70a is flush with the second main surface 77 which is the lower surface of the lowermost solder resist layer (insulating layer) 75. . The opening 81 on the second main surface 77 side
And the wiring 83 exposed at the bottom and serving as a connection terminal
As shown in FIG. 10, it is formed at a position where the electronic component 70a is removed. In the wiring substrate 50a, the thermal expansion coefficient α of the core substrate 51, the electronic component 70, and the build-up layer BU1
1 to α3 satisfy the relationship of Expression 7 above, and include the core substrate 51, the electronic component 70a, and the build-up layer BU2.
Are set in advance so that the thermal expansion coefficients α1 to α3 satisfy the relationship shown in Expression 7 above.

According to the above wiring board 50a, the conduction between the electronic components 70, 70a and the wiring layers 64, 65 can be ensured and stably provided, and the conduction between the electronic components 70, 70a can be established through the through holes. Conduction can be ensured through the conductor 62. Further, the continuity between the IC chip 80 mounted on the first main surface 76 and the electronic component 70a and the connection between the IC chip 80 and the wiring layer 6
Conduction with 5, 73 can be stably obtained. Also, the electronic component 7
The electrode 79 projecting from the bottom surface of Oa can be directly connected to a terminal of a motherboard such as a printed circuit board. Therefore, the internal wiring and the plurality of electronic components 70 and 70a can be arranged at a high density, and it is possible to easily respond to demands for high functionality and high performance.

The present invention is not limited to the embodiments described above. For example, only one electronic component may be incorporated in the build-up layer 16, BU1, or the like as described above. Conversely, a plurality of electronic components may be incorporated in the buildup layer 16, BU1, etc., apart from each other. Further, the chip-shaped electronic component includes the chip capacitor 10.
In addition to passive components such as chip-shaped inductors, resistors, and filters, active components such as transistors, memories, and low-noise amplifiers (LNAs),
The W-filter, the LC filter, the antenna switch module, the coupler, the diplexer, the duplexer, and the like, and the electronic components of different types are connected to each other by the build-up layer 16 and the BU1.
It is also possible to install them together at the same position inside the device.

Further, the material of the core substrates 2 and 51 is the same as that of the glass-epoxy resin composite material,
Glass woven fabric having mechanical strength, flexibility, ease of processing, etc., and a glass fiber-resin system which is a composite material of glass fiber such as glass woven fabric and resin such as epoxy resin, polyimide resin or BT resin Materials may be used. Alternatively, a composite material of an organic fiber and a resin such as a polyimide fiber or a resin-resin composite material in which a resin such as an epoxy resin is impregnated with a fluorine-based resin having a three-dimensional network structure such as PTFE having continuous pores is used. It is also possible to use.
The material of the wiring layers 18 and 32 is Ni, Ni-Au, Au, Ag, Ag-Pd, in addition to the copper plating.
Mo or W may be used, or it may be formed by a method such as applying a conductive resin without using metal plating.

Further, the via conductor 20 and the like are not limited to the conical shape following the via hole 19 and the like, and may be a filled via in a form filling the via hole. Alternatively, a staggered configuration in which the via conductors are stacked with their axes shifted may be used, or a configuration in which a wiring layer extending in the planar direction is interposed in the middle. Also, the insulating layer 17,
The material such as 31 has a three-dimensional network structure such as a polyimide resin, a BT resin, a PPE resin, or a PTFE having continuous pores having the same heat resistance and pattern moldability, in addition to the above-mentioned epoxy resin as a main component. A resin-resin composite material in which a resin such as an epoxy resin is impregnated into a fluorine resin can be used. For the formation of the insulating layer, a method of thermocompression bonding of an insulating film can be used in addition to a method of applying a liquid resin by a roll coater.

Further, the first main surfaces 29 of the wiring boards 1 and 50,
The connection with the IC chips 44 and 80 mounted on 74
The solder bumps (flip chip bumps) 28 and 78
In addition, flip chip pads, wire bonding pads
Or with a TAB connection pad formed
May be used. In addition, the electronic component 10 and the like
BaTiO₃High-dielectric ceramics
Was used, but PbTiO₃, PbZrO₃, Ti
O₂, SrTiO₃, CaTiO₃, MgTiO₃, K
NbO₃, NaTiO₃, KTaO ₃, PbTaO₃,
(Na_1/2Bi_1/2) TiO₃, Pb (Mg_1/2W
_{1 / 2}) O₃, (K_1/2Bi_1/2) TiO₃Mainly
What is used as a component may be used.

Further, although the material of the electrode 12 and the like in the capacitor of the electronic component 10 and the like is mainly composed of Cu, Pt, Ag, Ag-P which is compatible with the electronic component.
t, Ag-Pd, Pd, Au, Ni and the like can be used. In addition, a capacitor such as the electronic component 10 may be made of a dielectric layer mainly composed of a high dielectric ceramic or Ag.
-An electrode layer made of Pd or the like, resin, Cu plating, Ni
A capacitor may be formed by combining a via conductor or a wiring layer made of plating or the like. A plurality of mounting areas can be formed on the first main surface 29 of the wiring board 1 or the like, and a plurality of IC chips 44 and the like can be individually mounted in each area.

[0058]

The wiring board of the present invention described above.
According to the first aspect, thermal expansion between the core substrate, the build-up layer, and the electronic component matches each other, so that conduction between the electronic component and the internal wiring layer can be secured, and peeling in the build-up layer can be ensured. Can be reliably prevented. Therefore, it is possible to stably provide a wiring board that can cope with high-density and miniaturization of wiring and that can achieve high performance.
According to another wiring board of the present invention (claim 2), a core board, a build-up layer, an electronic component, and an IC
Since the thermal expansions between the chips match each other, conduction between the electronic component or the IC chip and the internal wiring layer can be secured, and peeling in the build-up layer can be reliably prevented. Therefore, it is possible to more easily cope with high density and miniaturization of wiring, and it is possible to reliably provide a high-performance wiring board. Further, according to the wiring board of the fifth aspect, the IC
Electrical connection between the chip and the electronic component can be obtained in the shortest and reliable manner, a stable function can be exhibited between the two, and electrical characteristics such as reduction of loop inductance can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a main part of a wiring board according to one embodiment of the present invention.

2 (A) to 2 (D) are schematic views showing respective manufacturing steps for obtaining the wiring board of FIG. 1.

3 (A) to 3 (C) are schematic views showing respective manufacturing steps following FIG. 2 (D).

4 (A) and 4 (B) are schematic views showing respective manufacturing steps following FIG. 3 (C), and FIG. 4 (C) is a sectional view showing the obtained wiring board.

FIG. 5 is a sectional view showing a main part of a wiring board which is an application form of the wiring board of FIG. 1;

FIG. 6 is a cross-sectional view showing a main part of a wiring board according to another embodiment of the present invention.

FIGS. 7A to 7D are schematic views showing respective manufacturing steps for obtaining the wiring board of FIG. 6;

8 (A) to 8 (C) are schematic views showing respective manufacturing steps following FIG. 7 (D).

9 (A) and 9 (B) are schematic views showing respective manufacturing steps following FIG. 8 (C).

FIG. 10 is a sectional view showing a main part of a wiring board which is an application of the wiring board of FIG. 6;

[Explanation of symbols]

 1, 1 ', 1a, 50, 50a Wiring board 2, 51 ... Core board 10, 10a, 70, 70a Electronic component 12, 79 ... Electronic component Electrodes 16, 30, BU1, BU2 ... Build-up layers 44, 80 ... IC chips 46, 82 ... IC chip terminals

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Michihiro Matsushima 14-18 Takatsuji-cho, Mizuho-ku, Nagoya-shi, Aichi F-term in Japan Special Ceramics Co., Ltd. 5E346 AA12 AA43 CC04 CC05 CC09 CC10 CC32 DD02 DD03 DD22 DD32 DD33 EE33 FF01 FF07 FF15 GG15 GG17 HH16

Claims (5)

[Claims] 1. A wiring board having a core substrate and a build-up layer, wherein an electronic component is built in the build-up layer, a coefficient of thermal expansion α1 of the core substrate, and a thermal expansion coefficient of the build-up layer. A wiring board, wherein the coefficient of expansion α2 and the coefficient of thermal expansion α3 of the electronic component have a relationship represented by Formula 1. [Equation 1] α3 ≦ α1 <α2 2. A semiconductor device comprising a core substrate and a build-up layer, and
A wiring board on which a C chip is mounted, wherein at least a mounting position of the IC chip is projected in a thickness direction of the wiring board, wherein the electronic component is incorporated in the build-up layer; Wherein the thermal expansion coefficient α1, the thermal expansion coefficient α2 of the build-up layer, the thermal expansion coefficient α3 of the electronic component, and the thermal expansion coefficient α4 of the IC chip are in a relationship represented by Formula 2. substrate. ## EQU2 ## α4 <α3 ≦ α1 <α2 3. The thermal expansion coefficient α1 of the core substrate is 40 pp.
3. The wiring board according to claim 1, wherein the temperature is not more than m / ° C. 4. 4. The thermal expansion coefficient α2 of the build-up layer is 7
The wiring board according to claim 1, wherein the wiring board has a concentration of 5 ppm / ° C. or less. 5. The wiring board according to claim 1, wherein terminals of the IC chip and electrodes of the electronic component are directly connected.