JP2001345868A - Interface circuit - Google Patents

Abstract

(57) Abstract: Provided is an interface circuit that can prevent a malfunction by including a circuit that invalidates an enable signal even if noise that satisfies a latch condition of a serial decoder is input at a reference voltage or higher. An output of a comparator circuit for shaping a waveform of an enable input signal voltage and an output of an inverter circuit connected in series with an output of a comparator circuit for shaping a waveform of a data input signal voltage are input. When the data input signal voltage is lower than the reference voltage, the output of the comparator circuit 6 for shaping the waveform of the enable input signal voltage is output. When the data input signal voltage is higher than the reference voltage, the output of the inverter circuit 4 is output. Is provided, the output switch 14 is provided to enable the noise even when the noise corresponding to the latch condition of the serial decoder is input to the data signal input terminal and the enable signal input terminal with a voltage value higher than the reference voltage of the comparator circuit. By invalidating the input signal voltage, it becomes a condition that does not conform to the latch condition, Prevent the work.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an interface circuit in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A serial decoder is used as a control circuit of a semiconductor integrated circuit. However, due to the nature of the control circuit, it is necessary to shape an input signal waveform of the serial decoder in order to prevent malfunction. Therefore, an interface circuit for shaping an input signal waveform of a conventionally used serial decoder will be described.

FIG. 4 shows a conventional interface circuit. In FIG. 4, 1 is a data signal input terminal,
2 is an enable signal input terminal, 3 is a clock signal input terminal, 4 is a comparator circuit connected to the data signal input terminal 1, 6 is a comparator circuit connected to the enable signal input terminal 2, and 7 is a clock signal input terminal 3. The connected comparator circuit 8 is the data signal input terminal 1
, An output terminal of a comparator circuit 6 connected to the enable signal input terminal 2; an output terminal of a comparator circuit 7 connected to the clock signal input terminal 3; Is GN
D terminal, 12 is a power supply terminal, 13 is a reference voltage input terminal of a comparator circuit, Q1, Q2, Q7, Q8, Q12, Q
13, Q18, Q19, Q20, Q21, Q26, Q2
7 is a PNP transistor, Q3 to Q6, Q14 to Q1
7, Q22 to Q25 are NPN transistors, R1 to R3
Is a resistor, and I1 to I3 are current sources.

A conventional interface circuit includes a comparator circuit 4 connected to a data signal input terminal 1 and a comparator circuit 6 connected to an enable signal input terminal 2.
And a comparator circuit 7 connected to the clock signal input terminal 3.

Next, the operation of the interface circuit configured as described above will be described with reference to FIG. When a signal voltage is input to each of the data signal input terminal 1, the enable signal input terminal 2, and the clock signal input terminal 3, the comparator circuit 4 outputs the data to the reference voltage input terminal 13 of the comparator. Comparing the data input signal voltage [(1) in FIG. 5] input from the data signal input terminal 1 and outputting LOW when the data input signal voltage is lower than the reference voltage; If the voltage is higher than the reference voltage, HI is output [(4) in FIG. 5]. The comparator circuit 6 includes a reference voltage input from a reference voltage input terminal 13 of the comparator and an enable input signal voltage input from the enable signal input terminal 2.
[(2) of FIG. 5] is compared, and if the enable input signal voltage is lower than the reference voltage, LOW is output, and if the enable input signal voltage is higher than the reference voltage, HI is output.
[(5) in FIG. 5]. The comparator circuit 7 compares the reference voltage input from the reference voltage input terminal 13 of the comparator with the clock input signal voltage [(3) in FIG. 5] input from the clock signal input terminal 3 to determine whether the clock input signal voltage is a reference voltage. Outputs LOW when the voltage is lower than the voltage, and outputs HI when the clock input signal voltage is higher than the reference voltage.
[(6) in FIG. 5]. As a result, the normal input signal voltage is shaped into a highly accurate square wave and output, and malfunction can be prevented even if noise less than the reference voltage is input.

[0006]

However, in the above-mentioned conventional configuration, a malfunction occurs when a high voltage is input to all the terminals of the IC due to, for example, static electricity or the like and a noise corresponding to the latch condition of the serial decoder is input at a reference voltage or higher. Will wake up.

[0007] In the present invention, in view of the conventional problems,
Noise that applies to the latch conditions of the serial decoder
It is an object of the present invention to provide an interface circuit that can prevent a malfunction by providing a circuit that invalidates an enable signal even when a data signal input terminal and an enable signal input terminal are input with a voltage value higher than a reference voltage of a comparator circuit. I do.

[0008]

According to the first aspect of the present invention, there is provided an interface circuit for shaping a waveform of a data input signal voltage, a comparator circuit for shaping a waveform of an enable input signal voltage, and a clock. A comparator circuit for shaping the waveform of the input signal voltage, an inverter circuit connected in series with an output terminal of the comparator circuit for shaping the waveform of the data input signal voltage, and a comparator circuit for shaping the waveform of the enable input signal voltage. An output and an output of the inverter circuit are input, and when the data input signal voltage is lower than a reference voltage input to the comparator circuit, an output of a comparator circuit for shaping the waveform of the enable input signal voltage is output, and the data input signal is output. Voltage is higher than the reference voltage input to the comparator circuit In the above case, by providing an output changeover switch for outputting the output of the inverter circuit, the noise that satisfies the latch condition of the serial decoder is more than the reference voltage of the comparator circuit at the data signal input terminal and the enable signal input terminal. Even when a voltage value is input, malfunction can be prevented by invalidating the enable signal.

In the interface circuit according to a second aspect of the present invention, the comparator circuit for shaping the waveform of the data input signal voltage, the comparator circuit for shaping the waveform of the enable input signal voltage, and the waveform of the clock input signal voltage. A comparator circuit for shaping, and a current mirror circuit with a PNP transistor connected in series with a collector terminal of a current mirror circuit with an NPN transistor on the reference voltage input terminal side of the comparator circuit for shaping the waveform of the data input signal voltage. An inverter circuit and an output terminal of the inverter circuit are connected to a collector terminal on the input side of a current mirror circuit formed by an NPN transistor for output in a comparator circuit for shaping the waveform of the enable input signal voltage. Times When the data input signal voltage is lower than the reference voltage input to the comparator circuit, the output of the comparator circuit that shapes the waveform of the enable input signal voltage is output. By providing an output changeover switch for outputting an output, noise that satisfies the latch condition of the serial decoder is input to the data signal input terminal and the enable signal input terminal with a voltage value equal to or higher than the reference voltage of the comparator circuit. Even in such a case, malfunction can be prevented by invalidating the enable signal.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In an interface circuit according to the present invention, an inverter circuit connected in series to an output of a comparator circuit for shaping a waveform of an enable input signal voltage and an output of a comparator circuit for shaping a waveform of a data input signal voltage. When the data input signal voltage is lower than a reference voltage, an output of a comparator circuit for shaping the waveform of the enable input signal voltage is output, and when the data input signal voltage is higher than the reference voltage. By providing an output switch for outputting the output of the inverter circuit, noise matching the latch condition of the serial decoder is input to the data signal input terminal and the enable signal input terminal with a voltage value equal to or higher than the reference voltage of the comparator circuit. In this case, by disabling the enable signal, the latch condition And incompatible conditions, it is possible to prevent the malfunction.

An embodiment of the present invention will be described below with reference to FIGS. The same components as those in FIG. 4 showing the conventional example are denoted by the same reference numerals and described. FIG. 1 shows a block diagram of an interface circuit according to an embodiment of the present invention. In FIG. 1, 1 is a data signal input terminal, 2 is an enable signal input terminal, 3 is a clock signal input terminal, 4 is a comparator circuit, 5 is an inverter circuit, 6 and 7 are comparator circuits, and 8 is an output terminal of the comparator circuit 4. , 9 is an output terminal of the comparator circuit 6, 10 is an output terminal of the comparator circuit 7, and 14 is an output switch.

In FIG. 1, an output terminal of a comparator circuit 4 for shaping a waveform of a data input signal voltage and an inverter circuit 5 are connected in series, and a comparator circuit for shaping the output of the inverter circuit 5 and the waveform of an enable input signal voltage. And the output of the comparator circuit 6 for shaping the waveform of the enable input signal voltage when the data input signal voltage is lower than the reference voltage. Is higher than the reference voltage, the output of the inverter circuit 5 can be output. As a result, even if noise that satisfies the latch condition of the serial decoder is input to the data signal input terminal and the enable signal input terminal with a voltage value equal to or higher than the reference voltage of the comparator circuit, invalid operation of the enable signal causes malfunction. Can be prevented.

FIG. 2 shows an example of an interface circuit according to an embodiment of the present invention, wherein 1 is a data signal input terminal, 2 is an enable signal input terminal, 3 is a clock signal input terminal, 4 is a comparator circuit, 5 Is an inverter circuit, 6 and 7 are comparator circuits, 8 is an output terminal of the comparator circuit 4, 9 is an output terminal of the comparator circuit 6,
10 is an output terminal of the comparator circuit 7, 11 is a GND terminal, 12 is a power supply terminal, 13 is a reference voltage input terminal, 14 is an output switch, Q1, Q2, Q7, Q8, Q1.
2, Q13, Q18, Q19, Q20, Q21, Q2
6, Q27 are PNP transistors, Q3 to Q6, Q9,
Q14 to Q17, Q22 to Q25 are NPN transistors, R1 to R3 are resistors, and I1 to I3 are current sources.

An example of the interface circuit according to the present embodiment shown in FIG. 2 includes a comparator circuit 7 for shaping the waveform of the clock input signal voltage, a comparator circuit 4 for shaping the waveform of the data input signal voltage, and the comparator circuit. NPN transistors Q4 and Q6 constituting
A current mirror circuit comprising an NPN transistor Q9 having a common base terminal with the NPN transistors Q4 and Q6, and a PNP transistor Q10 and a PNP transistor having a collector terminal connected in series with the collector terminal of the NPN transistor Q9. Inverter circuit 5 composed of a current mirror circuit with transistor Q11
A comparator circuit 9 for shaping the waveform of the enable input signal voltage; and an output NPN of the comparator circuit 9
A current mirror circuit including transistors Q14 and Q16; and a PNP transistor Q11 of the inverter circuit 5 connected to a collector terminal of the NPN transistor Q14.
And an output changeover switch 14 configured by connecting the collector terminals.

The operation of the interface circuit configured as described above will be described with reference to FIG. FIG.
FIG. 7 shows waveforms of respective parts when noise matching the latch condition of the serial decoder is input to the data signal input terminal 1 and the enable signal input terminal 2 with a voltage value equal to or higher than the reference voltage of the comparator in the embodiment of the present invention. ing.

When an input signal voltage is input to each of the data signal input terminal 1, enable signal input terminal 2, and clock signal input terminal 3, the comparator circuit 7 sets the reference voltage and clock input from the reference voltage input terminal 13 to the same. The clock input signal voltage input from the signal input terminal 3 [FIG.
(3)], and outputs LOW when the clock input signal voltage is lower than the reference voltage, and outputs HI when the clock input signal voltage is higher than the reference voltage [(6) in FIG. 3]. . The comparator circuit 4 has a reference voltage input terminal 1
3 is compared with the data input signal voltage [(1) in FIG. 3] input from the data signal input terminal 1. When the data input signal voltage is lower than the reference voltage, L is set.
It outputs OW and outputs HI when the data input signal voltage is higher than the reference voltage [(4) in FIG. 3]. The comparator circuit 6 compares the reference voltage input from the reference voltage input terminal 13 with the enable input signal voltage [(2) in FIG. 3] input from the enable signal input terminal 2, and the enable input signal voltage is higher than the reference voltage. When the input signal voltage is lower than the reference voltage, LOW is output. When the enable input signal voltage is higher than the reference voltage, HI is output.
Is higher than the potential of the reference voltage input terminal 13, the current output from the NPN transistor Q9 forming the current mirror circuit together with the NPN transistors Q4 and Q6 of the comparator circuit 4 is equal to the inverter. A PNP transistor Q10 which is a component of the circuit 5,
Q11 flows into the current mirror circuit, and as a result, the output of the inverter circuit 5
Since a current is supplied to the collector terminal of the NPN transistor Q14 of the output current mirror circuit constituted by the PN transistors Q14 and Q16, the output of the output switch 14 outputs the output of the inverter circuit 8. Therefore, the output of the comparator circuit 6 becomes LOW [(5) in FIG. 3].

Conversely, when the potential of the data signal input terminal 1 is lower than the potential of the reference voltage input terminal 13, no current is supplied from the comparator circuit 4 to the inverter circuit 5, and as a result, No current is supplied from the output to the collector terminal of the NPN transistor Q14 constituting the output current mirror circuit of the comparator circuit 6, and the output of the output switch 14 outputs the output of the comparator circuit 6.

As described above, according to the present embodiment, even when the noise that satisfies the latch condition of the serial decoder is equal to or higher than the reference voltage, the enable signal can be invalidated to make the latch condition unsuitable. Can be prevented

[0019]

As described above, according to the present invention, the serial decoder malfunctions if noise that satisfies the latch conditions of the serial decoder is input at a reference voltage or higher. Erroneous operation of the serial decoder can be prevented by providing a circuit that invalidates the enable signal when noise that satisfies the latch condition is input at a reference voltage or higher.

[Brief description of the drawings]

FIG. 1 is a block diagram of an interface circuit according to an embodiment of the present invention.

FIG. 2 is a detailed diagram of an interface circuit illustrating an embodiment of the present invention.

FIG. 3 is a waveform chart of each part for explaining the operation of the embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating an example of a conventional interface circuit.

FIG. 5 is a waveform chart of each section for explaining the operation of the embodiment of the conventional interface circuit.

[Explanation of symbols]

Reference Signs List 1 data signal input terminal 2 enable signal input terminal 3 clock signal input terminal 4 comparator circuit 5 inverter circuit 6 comparator circuit 7 comparator circuit 8 output terminal of comparator circuit 4 9 output terminal of comparator circuit 6 10 output terminal of comparator circuit 11 GND Terminal 12 Power supply terminal 13 Reference voltage input terminal 14 Output switch Q1, Q2, Q7, Q8, Q10, Q11, Q12, Q
13, Q18, Q19, Q20, Q21, Q26, Q2
7 PNP transistors Q3 to Q6, Q9, Q14 to Q17, Q22 to Q25
NPN transistor R1, R2, R3 Resistance I1, I2, I3 Current source

Claims (2)

[Claims] A comparator circuit for shaping a waveform of a data input signal voltage; a comparator circuit for shaping a waveform of an enable input signal voltage; a comparator circuit for shaping a waveform of a clock input signal voltage; An inverter circuit connected in series with an output terminal of a comparator circuit for shaping a waveform; an output of the comparator circuit for shaping the waveform of the enable input signal voltage and an output of the inverter circuit as inputs; When the voltage is lower than the reference voltage input to the circuit, the output of the comparator circuit for shaping the waveform of the enable input signal voltage is output. When the data input signal voltage is higher than the reference voltage input to the comparator circuit, the inverter circuit Equipped with an output selection switch that outputs the output of Interface circuit characterized and. A comparator circuit for shaping the waveform of the data input signal voltage; a comparator circuit for shaping the waveform of the enable input signal voltage; a comparator circuit for shaping the waveform of the clock input signal voltage; An inverter circuit composed of a current mirror circuit composed of a PNP transistor connected in series with a collector terminal of a current mirror circuit composed of an NPN transistor on a reference voltage input terminal side of a comparator circuit for shaping a waveform, and a waveform of the enable input signal voltage. An output terminal of the inverter circuit is connected to a collector terminal on an input side of a current mirror circuit by an output NPN transistor in a comparator circuit to be shaped, and when the data input signal voltage is lower than a reference voltage input to the comparator circuit,
An output changeover switch that outputs an output of a comparator circuit that shapes the waveform of the enable input signal voltage and that outputs an output of the inverter circuit when the data input signal voltage is higher than a reference voltage input to the comparator circuit. The interface circuit according to claim 1, wherein: