JP2001339306A - Compression circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compression circuit without dispersion in electric characteristic of components and change in characteristic due to an ambient temperature change. SOLUTION: An analog/digital converter 1 applies analog/digital conversion to an input signal, an absolute value calculation circuit 21 obtains an absolute value of an output of the analog/digital converter, a level detection circuit 22 detects a maximum value in the absolute values obtained by the absolute value calculation circuit 21 at least over a half period of the input signal, an attack time release time processing circuit 23 adds a change in the maximum value on the basis of a change as a comparison result between the detected maximum value and the detected level of one preceding sample, the direction in the change, and a predetermined attack time and a predetermined release time, to the maximum value to obtain the detected level of one preceding sample, and a compression arithmetic processing circuit 24 compresses the input signal on the basis of the detected level subjected to the attack time and release time processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compression circuit which can be used for a syllable compander provided in a radio communication device.

[0002]

2. Description of the Related Art A conventional compression circuit is performed by analog signal processing. Specifically, as shown in FIG.
An input signal Vin such as an audio signal is supplied to a rectifier 12, where the rectifier 12 generates a DC signal corresponding to the level of the input signal Vin, and varies the gain of the amplifier 11 in proportion to the level of the DC signal. The input signal Vin is amplified by the amplifier 11, and the amplified output Vout of the amplifier 11 is sent out as a compressed output via the buffer 14.

Here, the response speed of the rectifier 12 with respect to the speed at which the level of the input signal changes is determined by the capacitance of the capacitor 13 cooperating with the rectifier 12 and the input impedance of the rectifier 12.

For example, at the time of compression processing with a compression ratio of 2, the input signal Vin and the output signal Vo are based on the output of the rectifier 12.
Vout = 0.3162 × √ (Vin)
The gain of the amplifier 11 is controlled so that As a result,
In decibel expression, Vout = 0.5 × Vin (dB)
And a compression ratio of 2 is obtained.

[0005]

However, when an input signal is compressed by the above-described conventional compression circuit, variations in electrical characteristics of components such as an amplifier, a rectifier, and a buffer, and a change in an ambient temperature. There is a problem that the characteristics change due to the above. Another problem is that the response speed of the signal output from the rectifier changes due to the change in the capacitance of the capacitor.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a compression circuit in which the electrical characteristics of components do not vary and the characteristics do not change due to a change in ambient temperature.

[0007]

A compression circuit according to the present invention is a compression circuit for compressing an input signal, the A / D conversion means for A / D converting the input signal, and the absolute value of the A / D conversion output. An absolute value calculating means for obtaining a value; and a level detecting means for detecting a maximum value among absolute values of at least a half cycle of the input signal obtained by the absolute value calculating means. And performing a compression operation.

According to the compression circuit of the present invention, the maximum value of the input signal for compression is obtained by obtaining the absolute value of the input signal and obtaining the maximum value of the absolute value obtained over at least a half cycle of the input signal. In order to find the maximum value, the storage period of the input signal data that has been digitally converted is also a half period, and the compression operation is performed based on this maximum value. However, it is sufficient to store the absolute value of the digitally converted input signal data for a half cycle of the input signal in order to obtain the maximum value, and the storage capacity of the memory for storage can be reduced.

In the compression circuit according to the present invention, the amount of change, the direction of the change, and the result of comparing the maximum value detected by the level detection means with the value of the detection level one sample before are compared with the compression circuit according to the first aspect. Attack time and release time processing means for adding a change based on a predetermined attack time and release time to the maximum value and making it a detection level one sample before. The compression operation is performed based on the value.

Therefore, according to the compression circuit of the present invention, the response speed is suppressed from abrupt change of the maximum value for the compression action based on the attack time and the release time, so that the input speed is reduced when the compression action is executed. The processing no longer follows the instantaneous change in the signal, and is similar to the case where the compression circuit is configured by an analog circuit, but is caused by the change in the electrical characteristics of the electric circuit components in the case of the analog circuit. The tracking characteristic does not change.

In the compression circuit according to the present invention, the maximum value detected by the level detection means is subjected to a compression process based on a compression ratio, and a value 1 / B ( B is a positive number greater than 1), the result of the multiplication is divided by the maximum value, and the result of the division is multiplied by the A / D converted input signal. , And performing a compression operation.

Therefore, according to the compression circuit of the present invention, when the compression operation is performed within a limited numerical range, the result of the compression processing on the maximum value detected by the level detection means is multiplied by the value 1 / B. Then, since the level is once reduced and then multiplied by the value B, no problem occurs even when the compression operation is performed within the limited numerical range.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A compression circuit according to the present invention will be described below with reference to an embodiment.

FIG. 1 is a block diagram showing a configuration of a compression circuit according to an embodiment of the present invention.

The compression circuit 10 according to the embodiment of the present invention shown in FIG. 1 exemplifies a case where the compression ratio is 2.

A compression circuit 10 supplies an input signal to an A / D converter 1 and converts it into a digital signal. A digital signal output from the A / D converter 1 is supplied to a compressor circuit 2 comprising a digital signal processor or the like. The compressed digital signal is supplied to the compressor circuit 2 so that the digital signal is compressed by the D / A converter 3.
To convert it to an analog signal and output it.

The compressor circuit 2 comprises an absolute value calculating circuit 21 for obtaining an absolute value of an input signal in a predetermined time range and a level detecting circuit 22 for detecting a maximum level of the obtained absolute value. A circuit 20, an attack time or release time processing circuit 23 for performing processing based on an attack time or a release time for the absolute value level detected by the absolute value level detection circuit 20, and an attack time and release time processing circuit 23. A compression operation processing circuit 24 for multiplying the processed signal level by the A / D converted input signal to perform a compression process is provided, and sends a compression operation processing output to the D / A converter 3.

The operation of the compression circuit 10 constructed as described above will be described with reference to the flow chart shown in FIG.
A description will be given assuming that in is an audio signal and Vin = A · sin ωt.

The relation between the input signal and the output signal before the compression processing is as shown in FIG. 4A, and corresponds to the reference level of the compression circuit.

The input signal is converted into a digital signal in the A / D converter 1 (step S1), and the absolute value of the digitally converted input signal is calculated (step S2). Here, the processing in step S1 is performed by the absolute value calculation circuit 21.
It corresponds to the processing of.

After step S2, the absolute value data is stored in the memory of the compressor circuit 2 for a predetermined time. Here, since the lower limit of the frequency required for the input signal (audio signal) is 300 Hz, it is equivalent to a half cycle thereof (about 1.67 m).
If the data of (sec) exists, the input signal level can be detected.
The time is set to msec and stored in the memory for a time of 1.86 msec (step S3). Subsequent to step S3, the maximum value in the memory is detected each time A / D conversion sampling is performed (step S4).

Here, steps S3 and S4
Corresponds to the processing of the level detection circuit 22. By taking the absolute value in this way, the maximum level of the positive side and the negative side amplitude can be obtained only on the positive side, and further, in order to obtain the absolute value and obtain the maximum level, the digitally converted input signal The data storage time is also almost half a cycle.

Before the compression operation of the input signal, the response speed of the compressor circuit 2 is adjusted so as to have a time constant substantially so that the processing does not follow an instantaneous change of the input signal. Absorb instantaneous changes in That is, the maximum level detected in step S4 is compared with the detected level after the attack time and release time processing stored in step S7, and the difference and the direction of change are detected (step S5).

As a result of the comparison in step S5, if the maximum level detected in step S4 is higher than the detection level after the processing of the attack time and release time stored in step S7, the stored detection level is increased. , If it decreases, the stored detection level is reduced, and if there is no change in the comparison result, the detection level is not increased or decreased, and the value of the detection level thus obtained is compared with the maximum data at the next sample. (Step S6 to Step S7).

Here, the processing of steps S5 to S7 corresponds to the processing of the attack time / release time processing circuit 23.

Regarding the constants for increasing and decreasing in step S6, the constant in the direction in which the maximum level decreases is called an attack time (attack time), and the constant in the direction in which the maximum level increases is called the release time (release time). . The standard attack time specified in the ITU-T recommendation is 3 msec, and the standard release time is 1
3.5 msec, and is set to this value in step S6.

Next, the attack time and release time processing in the compression circuit 10 will be described in more detail with reference to FIG.

A comparison is made between the maximum level A detected in step S4 and the level A 'subjected to the attack time and release time processing stored in step S7 (step S5). A ′)> 0 is checked (step S6)
1). If it is determined in step S61 that (maximum level A-level A ')> 0, it is checked whether (maximum level A-level A') <0 (step S6).
2). If it is determined in step S62 that (maximum level A−level A ′) <0, then it is the case of maximum level A = level A ′, and the level A ′ by the previous process is set as the detection level following step S62. Used (step S63), step S8 described below is executed.

In step S61, (maximum level A
If it is determined that level A ′)> 0, step S
Following 61, the same condition was also applied the previous time, ie, (maximum level A
It is checked whether (−level A ′)> 0 or (maximum level A = level A ′) (step S64). If it is determined in step S64 that the state was not the same in the previous time, the increase rate ΔA is equal to the increase rate ΔA =
It is obtained by {(A−A ′) / sampling number to reach release time} (step S65), and A ′ = (A
'+ ΔA) is calculated (step S66), and A' calculated in step S66 is stored as a new detection level (step S7).

If it is determined in step S64 that the state is the same as the previous state, step S65 is skipped, and steps S66 and S7 are executed, and the calculated A 'is stored as a new detection level. Is done.

In step S62, (maximum level A
-If it is determined that level A ') <0, step S
After 62, the same condition as the previous time, that is, (maximum level A
It is checked whether (−level A ′) <0 or (maximum level A = level A ′) (step S67). If it is determined in step S67 that the previous state was not the same, the decrease rate ΔA is determined as follows.
It is obtained by {(A′−A) / the number of samplings reaching the attack time} (step S68), and A ′ = (A
'-ΔA) is calculated (step S69), and A' calculated in step S69 is stored as a new detection level (step S7).

If it is determined in step S67 that the previous state was the same, step S68 is skipped, steps S69 and S7 are executed, and the calculated A 'is stored as a new detection level.

If the above is specifically described, step S6
At 1, A = 100 mV, A ′ = 80 mV, and if A = A ′ last time, A−A ′> 0,
In step S64, it is determined that the state is not the same as the previous state, and in step S65, the increase rate ΔA = (100
mV−80 mV) / 10 = 2 mV. Here, the denominator of 10 indicates a case where the release time becomes 13.5 msec by 10 samplings. Therefore, new A ′ = (old A ′ + ΔA) = 80 mV + 2 mV
= 82 mV, and this 82 mV is stored as a new detection level.

In the execution of the next step S5, in step S61, A = 100 mV and A '= (the above-mentioned new detection level) 82 mV.
V) -A '(82 mV)> 0, so step S6
In step 4, it is determined that the state is the same as the previous state, step S65 is skipped, and new A ′ = (old A ′ + ΔA)
= (82mV + 2mV) = 84mV, and this 84mV
V becomes a new detection level and is stored.

In the execution of the next step S5, if A = 64 mV and A '= (the above-mentioned new detection level) 84 mV in step S62, and A-A'> 0 the previous time, A-A ' Since it is <0, it is not the same state as the previous time, and the decrease rate is the decrease rate ΔA = (84 mV−64 mV)
/ 2 = 10 mV. Where the denominator 2 is
Attack time 3msec by two samplings
Is shown. Therefore, new A ′ = (old A
'+ ΔA) = (84 mV-10 mV) = 74 mV, and this 74 mV is stored as a new detection level.

Next, returning to FIG. Step S6
3 or the detection level used in step S
A compression operation for obtaining the square root of the stored detection level value is performed in step 7 (step 8). Here, the detection level used in step S63 and step S63
Since the value of the level stored in step 7 is A, √A is obtained by the calculation in step S8, and compression is performed at a compression ratio of 2. This result is schematically shown in FIG. 4B. In FIG. 4B, the solid line schematically shows the state after the compression processing, and the broken line shows the input signal.

As shown in FIG.
The reason why the level after the compression processing in step S8 exceeds the input signal level is that the magnitude of the signal processed in the compressor circuit 2 including the digital signal processor is (−).
This is because the value is larger than the original value when the square root operation is performed because the value is in the range of 1 to +1).

Subsequent to step S8, a reference level coefficient α for adjusting the reference level is multiplied (step S8).
9). Here, the reference level means the compressor circuit 20
Is a level at which the input and output of the input signal are equal, and at this point, the gain between the input and output signals is 0 dB. Α√A is obtained by executing step S9. Step S9
Is as shown in FIG. 4 (c). FIG.
In (c), the alternate long and short dash line indicates the signal level subjected to the compression processing in step S8, and the signal level subjected to the compression processing is multiplied by the reference level coefficient α in step S9 to obtain the compressed signal level indicated by the solid line. Both intersections are reference levels. In FIG. 4C, a broken line indicates an input signal level.

Although the level of the signal to be compressed can be calculated by the processing in step S9, as is apparent from the display of FIG. 4C, the output signal has a gain for an input signal below the reference level. However, the compressor circuit 2 including the digital signal processor cannot directly calculate the gain. This is because the magnitude of the signal processed in the compressor circuit 2 is in the range of (−1 to +1). Therefore, following step S9, the calculation result α√A in step S9 is multiplied by 1 / B so that the gain is less than 1 (step S10). As a result of the execution of step S10, α√A / B. Here, B is a positive number greater than one.

As shown in FIG. 4D, the operation result of step S9 indicated by a dashed line is reduced by 1 / B as indicated by a solid line to lower the level. FIG.
In (c), the dashed line indicates the input signal level.
In this case, as a result of 1 / B, as described later, a portion having a level higher than the input signal level, that is, a portion having a gain, takes a portion of the input signal level.

Following step S10, step S10
Is divided by the detection level A stored in steps S63 and S7 to obtain a coefficient (step S11). As a result of the calculation in step S11, the coefficient obtained is α√A / (AB) = α / (B√
A). Following step S11, step S11
Is multiplied by the A / D-converted input signal (step S12). The multiplication result in step S12 is A · sin ωt · α / (B√A) = α√A · sin
ωt / B.

Following step S12, step S10
In step S, in order to restore the gain once lowered in step S
The calculation result of step 12 is multiplied by B in step S10 to return to the original signal level (step S13). Step S
13 results in α に よ る A · sin ωt, and the maximum gain by compression becomes B times. As a result, FIG.
As shown in (e), the input signal before the compression processing indicated by the broken line is subjected to the compression-processed output signal indicated by the solid line. The signal obtained in step S13 is output as an analog signal by the D / A converter 3 (step S1).
4).

[0043] Here, adopting as the B example ^{2 4} in step S10. In this case, the maximum gain due to the compression becomes 16 times, and the gain of the small signal decreases. However, as a result of the actual measurement, the signal having the gain of 16 times (about 10 Hz for the input signal) is weak. In order to prevent the S / N from deteriorating due to the compression of the noise component, there was no inconvenience even if the gain by compression was set to a maximum of 16 times.

[0044]

As described above, according to the compression circuit of the present invention, the compression operation can be performed by digital signal processing, and the compression can be performed without variation in the electrical characteristics of the components and no change in the characteristics due to a change in the ambient temperature. A circuit is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a compression circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining an operation of the compression circuit according to the embodiment of the present invention;

FIG. 3 is a flowchart for explaining an attack time and release time process in the compression circuit according to the embodiment of the present invention;

FIG. 4 is an explanatory diagram for explaining an operation of the compression circuit according to the embodiment of the present invention;

FIG. 5 is a circuit diagram of a conventional compression circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D converter 2 Compressor circuit 3 D / A converter 10 Compression circuit 20 Absolute value level detection circuit 21 Absolute value calculation circuit 22 Level detection circuit 23 Attack time and release time processing circuit 24 Compression arithmetic processing circuit

Claims (3)

[Claims] 1. A compression circuit for compressing an input signal, A / D conversion means for A / D converting the input signal, absolute value calculation means for obtaining an absolute value of an A / D conversion output, and absolute value calculation Level detecting means for detecting a maximum value in an absolute value of at least a half cycle of the input signal obtained by the means, and performing a compression operation based on the maximum value detected by the level detecting means. circuit. 2. The compression circuit according to claim 1, wherein the amount of change, the direction of change, the predetermined attack time, and the amount of change obtained as a result of comparing the maximum value detected by the level detection means with the value of the detection level one sample before. Attack time and release time processing means for adding a change based on the release time to the maximum value and the detection level one sample before, comprising:
A compression circuit for performing a compression operation based on a detection level value subjected to attack time processing and release time processing. 3. A compression circuit according to claim 1, wherein the maximum value detected by the level detection means is subjected to a compression process based on a compression ratio, and a value of 1 / B (B is larger than 1) is obtained as a result of the compression process. A large positive number), divide the result of the multiplication by the maximum value, multiply the result of the division by the A / D-converted input signal, and multiply the result of the multiplication by the value B for compression. A compression circuit characterized by performing an operation.