JP3870005B2 - Expansion circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a decompression circuit that can be used in a syllable compander provided in a wireless communication device.
[0002]
[Prior art]
The conventional decompression circuit is performed by analog signal processing. Specifically, as shown in FIG. 5, an input signal Vin such as an audio signal is supplied to the rectifier 12, and a DC signal corresponding to the level of the input signal Vin is generated in the rectifier 12, and the level of the DC signal is set. The gain of the amplifier 11 is varied proportionally, the input signal Vin is amplified by the amplifier 11, and the amplified output Vout of the amplifier 11 is sent as an expanded output via the buffer 14.
[0003]
Here, the response speed of the rectifier 12 to the speed at which the level of the input signal changes is determined by the capacitance of the capacitor 13 that cooperates with the rectifier 12 and the input impedance of the rectifier 12.
[0004]
For example, at the time of the expansion process of the expansion ratio 2, the gain of the amplifier 11 is controlled so that the relationship between the input signal Vin and the output signal Vout is Vout = 10 × (Vin) ² based on the output of the rectifier 12. As a result, in the decibel expression, Vout = 2 × Vin (dB) and an expansion ratio of 2 is obtained.
[0005]
[Problems to be solved by the invention]
However, when the input signal is expanded by the conventional expansion circuit as described above, there is a problem that the characteristics change due to variations in electrical characteristics of components such as amplifiers, rectifiers, and buffers, and changes in ambient temperature. there were. Furthermore, there is a problem that the response speed of the signal output from the rectifier changes due to the change in the capacitance of the capacitor.
[0006]
An object of the present invention is to provide an extension circuit that does not vary in electrical characteristics of components and does not change characteristics due to changes in ambient temperature.
[0007]
[Means for Solving the Problems]
An expansion circuit according to the present invention is an expansion circuit for expanding an input signal, and includes an A / D conversion means for A / D converting the input signal, an absolute value calculation means for obtaining an absolute value of the A / D conversion output, The level detection means for detecting the maximum value in the absolute value over at least half a period of the input signal obtained by the absolute value calculation means, and the maximum value detected by the level detection means and the value of the detection level one sample before were compared. An attack time and release time processing means for adding a change based on the amount of change in the result, the direction of change, and a predetermined attack time and release time to the maximum value to obtain a detection level one sample before is provided. The detection time processed by the release time is multiplied by the value of the A / D conversion output to perform an expansion operation.
[0008]
According to the decompression circuit of the present invention, the maximum value of the input signal for decompression is obtained as the absolute value of the input signal, and the maximum value of the absolute value obtained over at least a half cycle of the input signal. Therefore, the storage period of the digitally converted input signal data may be a half-cycle period, and the expansion operation is performed based on this maximum value. However, it is sufficient to store the absolute value of the input signal data digitally converted for obtaining the maximum value for a half period of the input signal, and the memory capacity for storage can be reduced.
[0010]
Furthermore, according to the expansion circuit according to the present invention, since the response speed is suppressed based on the attack time and the release time, a sudden change in the maximum value for the expansion operation is suppressed. The processing does not follow the general change and becomes the same as the case where the expansion circuit is configured by an analog circuit. On the other hand, the tracking characteristic caused by the change in the electrical characteristic of the electric circuit component when the analog circuit is used There is no change.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an expansion circuit according to the present invention will be described with reference to an embodiment.
[0012]
FIG. 1 is a block diagram showing a configuration of a decompression circuit according to an embodiment of the present invention.
[0013]
The expansion circuit 10 according to the embodiment of the present invention shown in FIG. 1 illustrates the case where the expansion ratio is 2.
[0014]
The decompression circuit 10 supplies the input signal to the A / D converter 1 to convert it into a digital signal, and the digital signal output from the A / D converter 1 is supplied to the expander circuit 2 including a digital signal processor. Thus, the expander circuit 2 performs an expansion operation, and the digital signal expanded in the expander circuit 2 is supplied to the D / A converter 3 to be converted into an analog signal and output.
[0015]
The expander circuit 2 includes an absolute value level detection circuit 20 including an absolute value calculation circuit 21 that calculates an absolute value of an input signal in a predetermined time range and a level detection circuit 22 that detects the maximum level of the obtained absolute value. Are processed by the attack time / release time processing circuit 23 and the attack time / release time processing circuit 23 for performing processing based on the attack time or release time for the absolute value level detected by the absolute value level detection circuit 20. The decompression arithmetic processing circuit 24 that performs the expansion processing by multiplying the signal level and the A / D converted input signal is functionally provided, and the expansion arithmetic processing output is sent to the D / A converter 3.
[0016]
The operation of the decompression circuit 10 configured as described above will be described based on the flowchart shown in FIG. 2 where the input signal Vin is an audio signal and Vin = A · sin ωt.
[0017]
Relationship between input and output signals before the expansion process is you will der as shown in Figure 4 (a).
[0018]
The input signal is converted into a digital signal by the A / D converter 1 (step S1), and the absolute value of the digitally converted input signal is calculated (step S2). Here, the processing in step S 1 corresponds to the processing of the absolute value calculation circuit 21.
[0019]
Following step S2, the absolute value data is stored in the memory of the expander circuit 2 for a predetermined time. Here, since the lower limit of the frequency required for the input signal (audio signal) is 300 Hz, the input signal level can be detected if there is data for half a cycle (about 1.67 msec). The predetermined time is, for example, 1.86 msec, and is stored in the memory for 1.86 msec (step S3). Subsequent to step S3, the maximum value in the memory is detected every time A / D conversion sampling is performed (step S4).
[0020]
Here, the processing in step S3 and step S4 corresponds to the processing of the level detection circuit 22. By taking the absolute value in this way, the maximum level of the positive and negative amplitudes can be obtained only on the positive side, and in addition, the digitally converted input signal is used to obtain the absolute value and obtain the maximum level. The data storage time is almost half a cycle.
[0021]
Before the expansion operation of the input signal, the response speed of the expander circuit 2 is adjusted so that the process does not substantially follow the instantaneous change of the input signal so as to have a time constant. To absorb changes. That is, the maximum level detected in step S4 is compared with the attack time stored in step S7 and the detection level after release time processing, and the difference and the direction of change are detected (step S5).
[0022]
As a result of the comparison in step S5, if the maximum level detected in step S4 is higher than the attack level stored in step S7 and the detection level after release time processing, the stored detection level is increased and decreased. If there is no change in the comparison result, the detection level is not increased or decreased, and the detection level value thus obtained is saved for comparison with the maximum data at the next sample. (Steps S6 to S7).
[0023]
Here, the processing of step S5 to step S7 corresponds to the processing of the attack time / release time processing circuit 23.
[0024]
Regarding the constants for increasing and decreasing in step S6, the constant for the direction in which the maximum level decreases is called attack time (attack time), and the constant for the direction in which the maximum level increases is called release time (release time). The standard attack time specified in the ITU-T recommendation is 3 msec, and the standard release time is 13.5 msec, which is set to this value in step S6.
[0025]
Next, attack time and release time processing in the decompression circuit 10 will be described in more detail with reference to FIG.
[0026]
A level comparison is made between the maximum level A detected in step S4 and the level A ′ subjected to the attack time and release time processing stored in step S7 (step S5), and (maximum level A−level A ′). It is checked whether or not> 0 (step S61). If it is determined in step S61 that (maximum level A−level A ′)> 0 is not satisfied, it is checked whether (maximum level A−level A ′) <0 (step S62). If it is determined in step S62 that (maximum level A−level A ′) <0, the maximum level A = level A ′, and the level A ′ obtained in the previous process is detected as the detection level after step S62. Used (step S63), step S8 described later is executed.
[0027]
If it is determined in step S61 that (maximum level A−level A ′)> 0, whether or not (maximum level A−level A ′)> 0 has been the same in the previous time following step S61, that is, (maximum It is checked whether level A = level A ′) or not (step S64). When it is determined in step S64 that the previous state was not the same as before, the increase rate ΔA is obtained by the increase rate ΔA = {(A−A ′) / the number of sampling times reaching the release time} (step S65). (A ′ + ΔA) is calculated (step S66), and A ′ calculated in step S66 is stored as a new detection level (step S7).
[0028]
If it is determined in step S64 that the state is the same as the previous time, step S65 is skipped, then steps S66 and S7 are executed, and the calculated A ′ is stored as a new detection level.
[0029]
If it is determined in step S62 that (maximum level A−level A ′) <0, whether or not (maximum level A−level A ′) <0 is the same as in the previous time following step S62, that is, (maximum It is checked whether level A = level A ′) or not (step S67). When it is determined in step S67 that the previous state was not the same, the decrease rate ΔA is obtained by the decrease rate ΔA = {(A′−A) / number of sampling times reaching the attack time} (step S68). (A′−ΔA) is calculated (step S69), and A ′ calculated in step S69 is stored as a new detection level (step S7).
[0030]
When it is determined in step S67 that the same state has been obtained in the previous time, step S68 is skipped and steps S69 and S7 are executed, and the calculated A ′ is stored as a new detection level.
[0031]
Specifically, if A = 100 mV, A ′ = 80 mV in step S61, and A = A ′ in the previous time, A−A ′> 0, so that the same state as in the previous time in step S64. In step S65, an increase rate ΔA = (100 mV−80 mV) / 10 = 2 mV is calculated. Here, the denominator 10 indicates a case where the release time is 13.5 msec by sampling 10 times. Therefore, new A ′ = (old A ′ + ΔA) = 80 mV + 2 mV = 82 mV, and this 82 mV becomes a new detection level and is stored.
[0032]
In execution of the next step S5, A = 100 mV, A ′ = (the above-mentioned new detection level) 82 mV in step S61, and A (100 mV) −A ′ (82 mV)> 0 in the previous time, step S64. In step S65, the new A ′ = (old A ′ + ΔA) = (82 mV + 2 mV) = 84 mV, and this 84 mV becomes a new detection level and is saved. The
[0033]
In the execution of the next step S5, if A = 64 mV, A ′ = (the above-mentioned new detection level) 84 mV in step S62, and A−A ′> 0 in the previous time, A−A ′ <0. Instead of the same state as the previous time, the reduction rate is calculated by the reduction rate ΔA = (84 mV−64 mV) / 2 = 10 mV. Here, the denominator 2 indicates a case where the attack time is 3 msec by sampling twice. Therefore, new A ′ = (old A ′ + ΔA) = (84 mV−10 mV) = 74 mV, and this 74 mV becomes a new detection level and is stored.
[0034]
Next, referring back to FIG. The detection level used in step S63 or the value of the detection level stored in step S7 is multiplied by the digitally converted input signal data to perform an expansion operation (step 8). Here, since the level value stored in step S7 is A and the input signal is data of A · sin ωt, it becomes A ² · sin ωt data by the calculation in step S8, and is expanded at an expansion ratio of 2. Will be. This result is schematically shown in FIG. 4B. In FIG. 4B, the solid line schematically shows the state after the expansion process, and the broken line shows the input signal.
[0035]
Subsequent to step S8, the gain coefficient for matching the reference level is multiplied. In this case, limiter processing is performed to limit the upper limit value so as not to overflow due to multiplication (step S9), and then gain coefficient multiplication is performed (step S10). Here, the reference level is a level at which the input signal and the output signal become equal. Since the gain is increased at a level higher than the reference level, the output signal overflows when the input signal exceeds a certain value, so that step S9 is executed. The processing of step S8 to step S10 corresponds to the processing of the decompression arithmetic processing circuit 24.
[0036]
The result of the execution of step S10 is schematically shown in FIG. 4 (c), where the expanded signal indicated by the alternate long and short dash line is indicated by the solid line by the multiplication of the gain coefficient, and is indicated by the broken line. The intersection of the signal and the solid line is the reference level. The output signal data in step S10 is supplied to the D / A converter 3 and converted into an analog signal to be an audio signal (step S11).
[0037]
【The invention's effect】
As described above, according to the expansion circuit according to the present invention, it is possible to perform an expansion operation by digital signal processing, and it is possible to obtain an expansion circuit that is free from variations in the electrical characteristics of components and changes in characteristics due to changes in ambient temperature.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a decompression circuit according to an embodiment of the present invention.
FIG. 2 is a flowchart for explaining the operation of the decompression circuit according to the embodiment of the present invention.
FIG. 3 is a flowchart for explaining attack time and release time processing in the decompression circuit according to the embodiment of the present invention;
FIG. 4 is an explanatory diagram for explaining the operation of the decompression circuit according to the embodiment of the present invention.
FIG. 5 is a circuit diagram of a conventional decompression circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 A / D converter 2 Expander circuit 3 D / A converter 10 Expansion circuit 20 Absolute value level detection circuit 21 Absolute value calculation circuit 22 Level detection circuit 23 Attack time, release time processing circuit 24 Expansion operation processing circuit

Claims (1)

An expansion circuit for expanding an input signal, an A / D conversion means for A / D converting the input signal, an absolute value calculation means for obtaining an absolute value of an A / D conversion output, and an input obtained by the absolute value calculation means Level detection means for detecting a maximum value of absolute values over at least half a cycle of a signal, and the amount of change and direction of change as a result of comparing the maximum value detected by the level detection means with the value of the detection level one sample before And an attack time and release time processing means for adding a change based on a predetermined attack time and release time to the maximum value to obtain a detection level one sample before, and a detection level subjected to attack time processing and release time processing. And a value of the A / D conversion output for expansion operation.

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