JP2001308839A - Circuit and method for clock synchronization - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a clock synchronous circuit and a clock synchronizing method, capable of performing clock synchronization between transmitter- receivers with each other via an asynchronous network. SOLUTION: A frequency-dividing circuit 4 generates an extraction clock, by performing frequency division of a source clock by as many times as the number of prescribed times. A counter 5a counts the receiving timing pulse of a packet transmitted on a fixed cycle for the prescribed number n of comparison packets and generates a count end pulse P1. A counter 7a counts a receiving timing comparison pulse, counted and generated by an extraction clock A2 for the number n of comparison packets and generates a count end pulse P2. A speed code detection circuit 8 detects the speed difference between the count end pulses P1 and P2 and outputs a speed code. An up/down-counter 9 increments or decrements by one, on the basis of the speed code, and a clock- adjustment timing circuit 10 controls the circuit 4, on the basis of a count value B1 and a code B2 of the up/down-counter 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronizing circuit for synchronizing a clock of a slave device with a clock of a master device, and more particularly to a device for transmitting and receiving data via an asynchronous network whose frequency is not synchronized. The present invention relates to a clock synchronization circuit and a clock synchronization method which are preferable.

[0002]

2. Description of the Related Art In continuous data communication performed through an asynchronous network such as a LAN (local area network) in which clocks or data frequencies are not synchronized, clocks between transmitting and receiving devices are asynchronous. In this case, data loss or surplus data occurs.
When performing data communication that requires clock synchronization between such transmitting and receiving devices via an asynchronous network, a method for coping with the problem is to provide a buffer in the receiving device for absorbing a shift in clock frequency with the transmitting device. Are known.

[0003]

However, according to the above-mentioned conventional method, an enormous capacity buffer is required for a receiving device in order to perform long-time continuous data communication without data loss. There's a problem. In addition, when data loss or excess data occurs due to a shift larger than the capacity of the buffer, there is a method to cope with it by signal processing such as data interpolation or deletion of excess data, but this method causes transmission error or signal The quality may deteriorate, and it is difficult to obtain high communication quality.

The present invention has been made in view of such circumstances, and has as its object to provide a clock synchronization circuit and a clock synchronization method capable of performing clock synchronization between transmitting and receiving devices via an asynchronous network. Is to do.

[0005]

According to a first aspect of the present invention, there is provided a clock generating means for generating a clock, comprising: a clock generating unit for generating a clock; First counting means for counting and counting until the count value reaches a predetermined count number, and counting time in a cycle equal to the packet transmission cycle using the clock, wherein the count value is the first count value. A second counting means for counting until reaching a count equal to the counting means, and a counting speed comparing means for comparing a counting speed of the first counting means with a counting speed of the second counting means, The clock generation means is controlled by a result of the comparison of the counting speed.

According to a second aspect of the present invention, in the first aspect of the invention, the clock generating means advances the phase of the clock when the counting speed of the first counting means is faster. When the counting speed of the first counting means is slower, control is performed so as to delay the phase of the clock.

According to a third aspect of the present invention, there is provided a first frequency dividing circuit for generating an extracted clock by dividing a source clock by a predetermined number of times, and a receiving number of packets transmitted in a fixed packet transmission cycle. Predetermined number of comparison packets n
(N; an integer equal to or greater than 1) counting means for generating a first count end pulse for each count, and a predetermined count corresponding to the packet transmission cycle using the extracted clock m (m; an integer equal to or greater than 1), a second count for generating a second count end pulse for each count by counting the number n of reception timing comparison pulses generated for each count. Means, a speed code detection circuit for detecting a speed difference between the first count end pulse and the second count end pulse, and outputting a speed code of the speed difference, and an output from the speed code detection circuit. An up / down counter that counts up, counts down, or does not perform counting based on the speed code to be output, and outputs the count value and the sign of the count value; Based on the count value and the code input from the down counter, characterized by comprising a clock adjustment timing circuit for controlling the first frequency divider.

According to a fourth aspect of the present invention, there is provided a first frequency dividing circuit for generating an extracted clock by dividing a source clock by a predetermined number of times, and a receiving frequency of a packet transmitted in a fixed packet transmission cycle. Predetermined number of comparison packets n
(N; an integer equal to or greater than 1) counting means for generating a first count end pulse for each count, and a predetermined count corresponding to the packet transmission cycle using the extracted clock m (m; an integer equal to or greater than 1), a second count for generating a second count end pulse for each count by counting the number n of reception timing comparison pulses generated for each count. Means, a speed code detecting circuit for detecting a speed difference between the first count end pulse and the second count end pulse and outputting a sign of the speed difference, and dividing the extracted clock by a predetermined number of times. A second frequency divider circuit that generates a clock by dividing the frequency, and using the clock generated by the second frequency divider circuit, the first count end pulse and the second count end pulse A speed difference detection counter that counts a time difference between raw and outputs the count value; and a first value counter based on a count value input from the speed difference detection counter and a code input from the speed code detection circuit. And a clock adjusting timing circuit for controlling the frequency dividing circuit.

According to a fifth aspect of the present invention, there is provided a clock generating step of generating a clock, counting the number of received packets transmitted in a fixed packet transmission cycle, and counting until the counted value reaches a predetermined count. A second counting step of counting time in a cycle equal to the packet transmission cycle using the clock and counting until the count value reaches a count number equal to the first counting step. And a counting speed comparing step of comparing the counting speed of the first counting process and the counting speed of the second counting process, wherein the clock generation process is controlled by a comparison result of the counting speed. It is characterized by that.

According to a sixth aspect of the present invention, in the fifth aspect of the invention, the clock generating step advances the phase of the clock when the counting speed of the first counting step is faster. When the counting speed in the first counting process is lower, the control is performed so as to delay the phase of the clock.

According to an embodiment of the clock synchronization circuit of the present invention, the clock adjustment timing circuit includes a minimum correction value counter for generating a clock correction enable signal for each period obtained by counting a predetermined number by the extracted clock. A correction frequency counter that generates a clock adjustment enable signal by counting the input count value each time the clock correction enable signal is generated, and the first frequency division based on the input code. It is determined which of a disable signal for temporarily stopping the operation of the circuit or a clear signal for clearing the operation of the first frequency dividing circuit and starting the frequency dividing operation again is determined. The signal is generated by the number of times corresponding to the generation period of the clock adjustment enable signal for each one clock of the source clock. Characterized by comprising a control signal generating circuit for.

According to an embodiment of the clock synchronization method of the present invention, a process of generating an extracted clock by dividing a source clock by a predetermined number of times and a method of determining the number of received packets transmitted at a fixed packet transmission cycle by a predetermined number. Counting the number of comparison packets n (n; an integer equal to or greater than 1) and generating a first count end pulse for each count; and a predetermined count corresponding to the packet transmission cycle using the extracted clock. A step of counting a number m (m; an integer of 1 or more), counting the number n of reception timing comparison pulses generated for each count, and generating a second count end pulse for each count, Obtaining a speed control amount of the extracted clock and the speed control direction based on a speed difference between the first count end pulse and the second count end pulse; Based on the speed control amount and the speed control direction, characterized by comprising a process of performing the frequency division control.

In the step of performing the frequency division control, the frequency division control is performed at a frequency corresponding to the speed control amount based on the speed control direction at predetermined intervals. .

[0014]

FIG. 1 is a block diagram showing an example of a basic configuration of an embodiment of the present invention. In this figure, master device 100 uses a master clock generated by master clock generator 120 to transmit packets from transmission buffer 110 at a fixed packet transmission cycle in synchronization with transmission data timing. This master device 1
00 is transmitted to the asynchronous network 20.
The slave device 300, which receives the packet via the “0”, controls the speed of the own slave clock based on the reception timing of the received packet, thereby synchronizing the own slave clock with the master clock of the master device 100. The asynchronous network 200 is a LAN
(Local Area Network) A network in which the clock or data frequencies are not synchronized. Hereinafter, with reference to the drawings, embodiments of the clock synchronization circuit and the clock synchronization method of the present invention provided in the slave device 300 in the above-described configuration of FIG. 1 will be described.

FIG. 2 is a block diagram showing the configuration of the clock synchronization circuit according to the first embodiment of the present invention. In this figure, reference numeral 1 denotes a buffer for receiving and temporarily holding packets transmitted at a fixed packet transmission cycle, and 2 denotes a signal output from the buffer 1, which is turned ON / OFF every time the received packet arrives. Is an edge detection circuit that detects an edge of a packet reception signal that alternately repeats the above and generates a reception timing pulse. The reception timing pulse generated by the edge detection circuit 2 is the master device 100 if there is no distortion or delay of the asynchronous network 200.
Is synchronized with the master clock.

Reference numeral 3 denotes a source clock generator for generating a source clock A1, and 4 denotes a source clock A1 generated by the source clock generator 3 which is frequency-divided by a predetermined number of times to generate an extracted clock A2 of the master device 100 on the transmission side. The frequency dividing circuit 5a, which generates the same period as the master clock, counts the number of reception timing pulses generated by the edge detection circuit 2, and this count value is a predetermined comparison packet number n (n; 1 or more). This counter generates a count end pulse P1 when the count reaches an integer, and clears the count value by the input count reset signal B5 and starts counting again. That is, 5a
Counts time in units of a packet reception cycle, and when this count value reaches a predetermined value, the count end pulse P
This is a counter that generates 1.

Reference numeral 6 denotes a cycle of counting with the extraction clock A2 until a predetermined count m (m; an integer of 1 or more) corresponding to the ratio of the packet transmission cycle of the master device 100 to the cycle of the extraction clock A2 is reached. This is a counter that generates a reception timing comparison pulse. The counter 6 generates a reception timing comparison pulse at a constant period equal to the packet transmission period, and the reception timing comparison pulse is synchronized with the extraction clock A2. A counter 7a counts the number of reception timing comparison pulses generated by the counter 6, and generates a count end pulse P2 when the count value reaches a predetermined comparison packet number n. The count value is cleared by the signal B5, and the counting is started again. That is, reference numeral 7a denotes a counter which counts time in units of a packet transmission cycle and generates a count end pulse P2 when the count value becomes equal to the value of the counter 5a.

Numeral 8 is a speed code detecting circuit for detecting whether the count end pulse P2 output from the counter 7a is faster or slower, that is, the slow speed of the count end pulse P1 output from the counter 5a. Of the count end pulse P2 output from the counter 5a and the count end pulse P1 output from the counter 5a are compared, and the result of the comparison is used to detect the delay between the count end pulses P1 and P2. The result is output as the speed code. This speed code is positive when the output of the count end pulse P1 is fast, while
If the output of the count end pulse P1 is slow, a negative value is output. The speed code detection circuit 8 outputs a comparison end pulse P3 at the input point of the later one of the input count end pulses P1 and P2.

Reference numeral 9 denotes a counter which counts from 0 to 1 in increments. When the speed code output from the speed code detection circuit 8 is positive, it counts up, and when it is negative, it counts down and counts down. Value B1 and count value B
This is an up / down counter that outputs a code B2 of 1 and the count value B1 indicates the speed control amount of the extracted clock A2, and the code B2 indicates the speed control direction of the extracted clock A2. When the count end pulses P1 and P2 are output simultaneously, the speed code detection circuit 8 outputs the speed code as positive or negative, and the up / down counter 9 does not count. Further, when the comparison end pulse P3 is input, the up / down counter 9 performs the counting process and continues to output the count value B1 and the code B2 until the next comparison end pulse P3 is input.

Reference numeral 10 denotes a disable signal B3 for temporarily suspending the operation of the frequency dividing circuit 4 and the operation of the frequency dividing circuit 4 based on the count value B1 and the sign B2 output from the up / down counter 9, and again. And a clock adjustment timing circuit 11 for generating and outputting a clear signal B4 for starting the frequency division operation. The clock adjustment timing circuit 11 is input from the edge detection circuit 2 after the comparison end pulse P3 output from the speed code detection circuit 8 is input. A comparison start detection circuit that outputs a count reset signal B5 when a first reception timing pulse is detected.

In the first embodiment, the speed code detection circuit 8 counts the speed difference between the reception timing pulse synchronized with the master clock of the master device 100 and the reception timing comparison pulse synchronized with the extracted clock A2. Detected as a slow speed between the end pulses P1 and P2,
Based on the detection result, the count end pulses P1, P
2 is synchronized so that the reception timing pulse and the reception timing comparison pulse are synchronized. The speed of the extracted clock A2 is controlled by the control of the frequency dividing circuit 4, and as a result, the extracted clock A2 and the master clock are synchronized.

Assuming that the speed difference detection circuit 8 detects the speed difference every packet transmission cycle, if there is a fluctuation in the packet transmission delay time, the speed control amount and the speed control direction of the extracted clock A2 are affected by the fluctuation. Accordingly, there is a possibility that the synchronization between the extracted clock A2 and the master clock does not go well. Therefore, the frequency of detection of the speed difference by the speed code detection circuit 8 depends on the fluctuation amount of the packet transmission delay time of the asynchronous network 200 through which the packet is transmitted, the clock frequency and the frequency deviation of the clock generation elements of the clock generators 120 and 3, And master device 1
It is determined in consideration of the packet transmission cycle of 00, and is set in advance in the counters 5a and 7a as the number of comparison packets n.
Accordingly, the extraction clock A2, which is speed-controlled by the delay between the count end pulses P1 and P2 generated for each comparison packet number n, is controlled based on the speed difference between the reception timing pulse and the reception timing comparison pulse,
And it is controlled stably. The comparison packet number n value is, for example, any value of several to several hundred packets.

Next, with reference to FIGS.
The operation of the clock synchronous circuit according to the embodiment will be described. FIG. 3 is a waveform diagram for explaining the operation of the clock synchronization circuit of FIG. First, the frequency dividing circuit 4 generates the source clock A1 generated by the source clock generator 3.
Is divided by a preset number of times and output so that the extracted clock A2 has the same cycle as the master clock. The number of comparison packets n is set in advance in the counters 5a and 7a, and the count number m corresponding to the ratio between the packet transmission cycle of the master device 100 and the master clock cycle is set in the counter 6 in advance.

First, the buffer 1 alternately repeats ON / OFF of the packet reception signal every time a packet arrives, and the edge detection circuit 2 detects the edge of the packet reception signal, generates and outputs a reception timing pulse. . Next, the counter 5a counts the reception timing pulse input from the edge detection circuit 2 until the number of comparison packets reaches n, stops counting the reception timing pulse after this count ends, and outputs a count end pulse P1.

The counter 6 circulates and counts with the extraction clock A2 until it reaches the count number m, and outputs a reception timing comparison pulse every time the counting is completed. Next, the counter 7a counts the reception timing comparison pulse output from the counter 6 until the number of comparison packets reaches n, stops counting the reception timing pulse after the count ends, and outputs a count end pulse P2. Next, the speed code detection circuit 8 operates the counter 7a.
End pulse P2 output from the counter and the counter 5a
And outputs a speed code by comparing which one of the count end pulses P1 is output faster, and outputs the count end pulse P1 or P2 which is later, whichever is later. The comparison end pulse P3 is output at the time of input. The up / down counter 9 counts up or down in accordance with the speed code output from the speed code detection circuit 8. When the comparison end pulse P3 is input, the up / down counter 9 processes the count value to obtain a count value B1. As the code B2, the output is continued until the next comparison end pulse P3 is input.

For example, in the waveform diagrams shown in FIGS. 3A to 3C, the pulse Wa1 of the count end pulse P1 in FIG. 3A and the pulse Wb1 of the count end pulse P2 in FIG. When output simultaneously from 5a and 7a, the speed code detection circuit 8 outputs the speed code as positive or negative, and the pulse Wc1 of the comparison end pulse P3 in FIG.
Is output. In this case, the up / down counter 9 does not count, and the count value is “0”. Next, the pulse W of the count end pulse P1 in FIG.
When the pulse Wb2 of the count end pulse P2 in FIG. 3B is output with a delay with respect to a2, a positive speed code is output to control the speed of the extracted clock A2 to be increased, and the speed is increased and decreased. The pulse W is counted up by the counter 9 and is the comparison end pulse P3 in FIG.
After the input of the pulse Wb2, the count value becomes “+1”.
Becomes Next, the count end pulse P1 in FIG.
Similarly, if the pulse Wb3 of the count end pulse P2 in FIG. 3B is output with a delay with respect to the pulse Wa3, a positive speed code is output and the up / down counter 9 further counts up. 3 (c), the pulse Wc3 of the comparison end pulse P3 is inputted after the input of the pulse Wb3.
The count value is “+2”.

Next, when the pulse Wb4 of the count end pulse P2 in FIG. 3B is output faster than the pulse Wa4 of the count end pulse P1 in FIG. 3A, the speed of the extraction clock A2 is reduced. , A negative speed code is output and counted down by the up / down counter 9, and the comparison end pulse P shown in FIG.
After the pulse Wc4 of the third pulse is input, the count value becomes “+1”. The count value of the up / down counter 9 is output as a count value B1 and a sign B2, which are absolute values. As described above, the count value of the up / down counter 9 repeats the up / down count based on the speed difference between the count end pulses P1 and P2 each time the count of the comparison packet number n ends.

Next, when either the count-up or the count-down is performed by the up / down counter 9 and the count value B1 and the code B2 are output, the clock adjustment timing circuit 10 receives the input from the up / down counter 9. Count value B1 and code B
2, a signal of either the disable signal B3 or the clear signal B4 is generated and output to the frequency dividing circuit 4. This disable signal B3 or clear signal B4
Clock adjustment timing circuit 10 for generating any one of
Will be described with reference to FIGS. FIG. 4 is a waveform diagram showing an example of the disable signal B3 generated by the clock adjustment timing circuit 10. FIG. 5 is a waveform diagram showing an example of the clear signal B4 generated by the clock adjustment timing circuit 10.

When the input code B2 is negative, the clock adjustment timing circuit 10 outputs the disable signal B3 as shown in FIG. 4 (b) to control the speed of the extracted clock A2 to decrease. 4 (a) is generated for one source clock A1 and output to the frequency dividing circuit 4. When the disable signal B3 is input, the frequency dividing circuit 4 temporarily stops the frequency dividing operation by one bit of the source clock A1. As a result, the extracted clock A2 shown in FIG. 4C has a waveform shown by a solid line, and in the generation cycle of the disable signal B3, the source clock A1 is smaller than a waveform (shown by a dotted line) in which the disable signal B3 is not generated. The period becomes longer by one clock.

On the other hand, when the input code B2 is positive, the clock adjustment timing circuit 10 separates the clear signal B4 as shown in FIG. 5B in order to increase the speed of the extracted clock A2. The counting of the circuit 4 is completed (falling of the extracted clock A2 indicated by the dotted line in FIG. 5C).
5A is generated one clock before the source clock A1 shown in FIG. When the clear signal B4 is input, the frequency dividing circuit 4 clears the frequency dividing operation and starts the frequency dividing operation again from the initial state. As a result, the extracted clock A2 shown in FIG. 5 (c) has a waveform shown by a solid line, and in the generation cycle of the clear signal B4, the source clock A1 has a waveform which is smaller than a waveform (shown by a dotted line) where the clear signal B4 has not been generated. The period becomes shorter by the amount of the clock.

Next, the disable signal B3 thus generated by the clock adjustment timing circuit 10
Alternatively, the frequency dividing operation in the frequency dividing circuit 4 is controlled by one of the clear signals B4. When the comparison end pulse P3 is input from the speed code detection circuit 8, the comparison start detection circuit 11 starts detecting the reception timing pulse input from the edge detection circuit 2 and detects the reception timing pulse first. Sometimes count reset signal B
5 is output. When the count reset signal B5 is input, the counters 5a and 7a clear their respective count values and start counting again.

It should be noted that the above-described clock adjustment timing circuit 10 uses the code B2 for each predetermined correction cycle.
Disable signal B having a frequency corresponding to count value B1
3 or a clear signal B4.
Until the count value B1 and the sign B2 output from the up / down counter 9 change, that is, at least until each comparison end pulse P3 is generated, the count value B1 and the sign output from the up / down counter 9 continue. Based on B2, constant speed control of the extracted clock A2 is performed.

FIG. 6 is a block diagram showing the configuration of the clock adjustment timing circuit 10 described above. In this figure, reference numeral 21 denotes an input extracted clock A2, a minimum correction value counter for generating a clock correction enable signal C1 for each period obtained by counting the number of preset correction period setting values, and 22 a minimum correction value. Each time the clock correction enable signal C1 is input from the value counter 21, a correction frequency counter that generates the clock adjustment enable signal C2 by counting the input count value B1 with the extracted clock A2, and 23 is a code that is input. Based on B2, a disable signal B3 or a clear signal B4
Is generated, and the determined signal is generated by the number of times corresponding to the generation section of the clock adjustment enable signal C2 input from the correction frequency counter 22 for each one clock of the source clock A1. It is a signal generation circuit. It should be noted that the above-described correction cycle setting value is based on the packet transmission cycle of the master device 100 and each clock generator 1.
An optimum value is determined from the clock frequencies and frequency deviations of the clock generation elements 20 and 3 and the number n of comparison packets set in the counters 5a and 7a.

FIG. 7 is an example of a time chart for explaining the operation of the clock adjustment timing circuit 10. Next, the operation of the clock adjustment timing circuit 10 shown in FIG. 6 will be described with reference to the time chart of FIG. First, the following description is based on the assumption that the correction cycle setting value is set to “4” and “2” is input as the count value B1. First, the minimum correction value counter 21 reads the extracted clock A2 shown in FIG.
A clock correction enable signal C1 shown in FIG. 7B is generated and output every four clocks. Next, when the clock correction enable signal C1 is input, the correction frequency counter 22 sets the input count value B1 to “2”.
Is generated using the extracted clock A2, thereby generating and outputting a clock adjustment enable signal C2 shown in FIG. 7C having a width of two clocks of the extracted clock A2. Next, when the clock adjustment enable signal C2 is input, the control signal generation circuit 23 determines which of the disable signal B3 and the clear signal B4 to generate based on the input code B2. The determined signal is generated for each clock of the source clock A1 by the number of times corresponding to the generation period of the clock adjustment enable signal C2 input from the correction frequency counter 22.

When the input code B2 is negative, the control signal generation circuit 23 changes the disable signal B3 to the generation period of the clock adjustment enable signal C2 in FIG. 7C as shown in FIG. 7D. , Ie, twice. On the other hand, when the input code B2 is positive, the control signal generation circuit 23 changes the clear signal B4 according to the generation period of the clock adjustment enable signal C2 in FIG. 7C, as shown in FIG. Occur twice, that is, twice. The above operation of the clock adjustment timing circuit 10 is repeatedly performed at least until the comparison end pulse P3 is generated, the number of comparison packets set in the counters 5a and 7a, and the number of times according to the correction cycle. .

As described above, in the first embodiment, the number of comparison packets n set in the counters 5a and 7a is n.
Each time the count is completed, the comparison of the speed difference between the reception timing comparison pulse and the reception timing pulse is repeated. Each time, the speed correction of the extracted clock A2 is made faster or slower by the code B2 input to the clock adjustment timing circuit 10. And the correction value for controlling the operation of the frequency dividing circuit 4 is changed by increasing / decreasing the frequency of the speed correction based on the count value B1, so that the packet reception signal and the extracted clock A2 can be more timely synchronized. In the long term, the master clock of the master device 100 and the extracted clock A2 of the slave device 300 can be synchronized.

FIG. 8 is a block diagram showing a configuration of a clock synchronization circuit according to a second embodiment of the present invention. In this figure, the configuration different from that of the clock synchronous circuit according to the first embodiment shown in FIG. A frequency dividing circuit 32 for generating and outputting a clock having a frequency dividing ratio is provided. This speed difference detection counter 31 uses a clock output from the frequency dividing circuit 32 to input a count end pulse P
4, a point that counts the time difference between the occurrences of P5 and outputs the counted number as a count value B1;
Unlike the counters 5 and 7, the counter 7b circulates and counts up to a predetermined comparison packet number n, outputs count end pulses P4 and P5 each time the count ends, and automatically returns to the count 0. This is the point where counting is started again. It should be noted that the frequency division ratio of the frequency dividing circuit 32, that is, the number of frequency divisions, is determined by a predetermined clock adjustment timing circuit 1
0 is set based on the resolution for controlling the speed of the extraction clock A2. Other configurations and operations are the same as those of the first configuration shown in FIG.
This is the same as the embodiment. Hereinafter, with reference to FIGS. 8 and 9, a configuration and an operation different from those of the first embodiment shown in FIG. 2 will be described.

FIG. 9 is a waveform chart for explaining the operation of the clock synchronization circuit of FIG. In FIG. 8, the counters 5b and 7b circulate and count until a predetermined comparison packet number n is reached.
The count end pulses P4 and P5 shown in FIG. When the pulse Wd1 of the count end pulse P4 in FIG. 9A and the pulse We1 of the count end pulse P5 in FIG. 9B are simultaneously output from the counters 5b and 7b, the speed difference detection counter 31 ends the count. Since there is no time difference between the generation of the pulses P4 and P5, the counting is not performed, and “0” is output as the count value B1.

Next, when the pulse We2 of the count end pulse P5 of FIG. 9B is output with a delay from the pulse Wd2 of the count end pulse P4 of FIG. 9A, the speed difference detection counter 31 ends the count. During the time difference t1 between the generation of the pulses P4 and P5, counting is performed with the clock output from the frequency dividing circuit 32, and this count is output as the count value B1. Next, the pulse We3 of the count end pulse P5 of FIG. 9B is output with a time difference equal to or less than the clock width output from the frequency dividing circuit 32 with respect to the pulse Wd3 of the count end pulse P4 of FIG. Then, the speed difference detection counter 31 outputs the count end pulse P
4. It does not count the time difference between the occurrences of P5 and outputs "0" as the count value B1.

Next, when the pulse We4 of the count end pulse P5 in FIG. 9B is output faster than the pulse Wd4 of the count end pulse P4 in FIG. 9A, the speed difference detection counter 31 outputs the count end pulse. During the time difference t2 between the occurrence of P4 and P5, counting is performed with the clock output from the frequency dividing circuit 32, and this count is counted by the count value B
Output as 1. If the count end pulse P5 is output faster than the count end pulse P4 by the time difference equal to or smaller than the clock width output from the frequency divider 32, the speed difference detection counter 31 outputs the count end pulse P5.
4. It does not count the time difference between the occurrences of P5 and outputs "0" as the count value B1.

As described above, the count value B1 of the speed difference detection counter 31 is incremented each time the counting of the number of comparison packets n is completed.
The counting based on the time difference between the generation of the count end pulses P1 and P2, that is, the speed difference between the reception timing pulses, is repeated. Further, the speed code detection circuit 32 determines the speed code based on the count end pulse P4 output from the counter 5b and the count end pulse P5 output from the counter 7b, as in the first embodiment described above. The extracted clock A2 is output as a code B2 indicating the speed control direction.

In the second embodiment described above, the speed difference detection counter 31 detects the time difference between the count end pulses P4 and P5 output from the counters 5b and 7b, and determines the amount of the time difference as the extraction clock A2. The clock adjustment timing circuit 10 sets the count value B1 and the code B indicating the speed control direction as the count value B1 indicating the speed control amount.
2, the speed control of the extracted clock A2 is performed, so that a large time correction of the extracted clock A2 can be performed by detecting the time difference between one count end pulse P4 and P5. Therefore, compared with the synchronization of the extracted clock A2 with the packet reception signal, that is, the master clock, in the first embodiment described above, the extraction clock A2 having a large speed difference with respect to the packet reception signal, that is, the master clock, is faster. Can be synchronized with the packet reception signal, that is, the master clock.

If the speed difference between the count end pulses P4 and P5 is a small time difference smaller than the clock width output from the frequency dividing circuit 32, the count value B1 becomes "0" and the speed correction of the extracted clock A2 is performed. Not done. Therefore, when the speed difference between the packet reception signal, that is, the master clock and the extracted clock A2 is small from the beginning, the first time the speed correction degree of the extracted clock A2 is changed every time the time difference between the count end pulses P1 and P2 is detected. A more stable extracted clock A2 can be obtained as compared with the embodiment.

In the above-described embodiment, if there is fluctuation of the packet transmission interval or fluctuation of the delay time generated in the asynchronous network 200, the packet reception signal is short-term with the master clock of the master device 100. Although not synchronized, the extracted clock A2 of the slave device 300 is synchronized with the master clock of the master device 100 in a long term. In addition, a buffer 1 is provided to temporarily hold received packets.
The fluctuation of the packet transmission interval and the asynchronous network 20
It is possible to absorb the deviation of the received packet caused by the fluctuation of the delay time generated at 0 or the fluctuation of the extracted clock A2.

In the above-described embodiment, the following effects can be obtained. (1) Since the packet reception signal can always be synchronized with the extraction clock A2 having the same cycle as the transmission side master clock, the reception signal is stably reproduced by using the extraction clock A2 as the synchronization signal. be able to. (2) By synchronizing the master clock of the master device 100 with the extracted clock A2 of the slave device 300 for a long period of time, when transmitting and receiving semi-permanently continuous data via the asynchronous network 200, data loss or excess data Communication without the need.

(3) When a plurality of devices are connected on the asynchronous network 200, the connected devices are constituted by one master device 100 and a plurality of other slave devices 300. Extraction clock A2 of all slave devices 300 in transmission packet
Can be synchronized. It can also be used in a communication system in which one mask device 100 polls all slave devices 300.

(4) In the second embodiment, the resolution and the frequency of the speed correction of the extracted clock A2 can be changed by changing the frequency dividing ratio preset in the frequency dividing circuit 32. , It is possible to generate a more stable extracted clock A2 according to the system used.

(5) Since the correction frequency counter 22 is provided, the frequency of the speed correction of the extracted clock A2 increases as the count value B1 increases, so that the phase can be quickly adjusted even with a large phase shift. Can be. (6) FPGA can be composed entirely of digital circuits
And gate arrays are easy.

(7) Clock synchronizing means effective when data such as a modem signal is transmitted through the asynchronous network 200, and is particularly effective when the upper layer protocol does not have a function to cope with a data error. Further, the present invention is also effective when a digital signal of a voice or image signal requiring real-time transmission is transmitted via an asynchronous network such as a LAN.

The essence of the present invention is as follows. Generating a clock; Counting the number of received packets transmitted in a fixed packet transmission cycle until the count reaches a predetermined count; Counting the time in a cycle equal to the packet transmission cycle using the clock generated in the above, and counting until the count reaches a count equal to a predetermined count of. The present invention is not limited to the above-described embodiment in that the counting speed until the predetermined count number is reached is compared with that of the above, and the generation of the clock is controlled based on the comparison result. Here, the difference between the generated clock and the master clock on the transmission side can be detected by comparing the counting speed until the predetermined count number is reached, and control of clock generation based on the comparison result is performed. By performing the above, the deviation can be reduced.

[0051]

As described above, according to the present invention,
Count the number of packets transmitted in a fixed packet transmission cycle, count until the counted value reaches a predetermined count, generate a clock, and use the generated clock to perform the packet transmission cycle. Is counted until the count value reaches a count number equal to the predetermined count number, and the counting speed until both count values reach the predetermined count number is compared. Based on the control of the generation of the clock to be generated, the received signal can be reproduced stably by using this clock as the synchronization signal of the receiving device, and the transmitting and receiving device can be reproduced via the asynchronous network. Clock synchronization can be performed between each other.

Further, if the counting speed until the count of the number of received packets reaches the predetermined count is faster, the phase of the clock is advanced, while the count of the number of received packets is equal to the predetermined count. If the counting speed until the number is reached is slower, the clock generation is controlled so as to delay the phase of the clock, so that the clock synchronization between the transmitting and receiving devices can be performed more accurately.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a basic configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a clock synchronization circuit according to the first embodiment of the present invention.

FIG. 3 is a waveform chart for explaining an operation of the clock synchronization circuit shown in FIG. 2;

FIG. 4 is a clock adjustment timing circuit 10 shown in FIG. 2;
FIG. 6 is a first waveform diagram for explaining the operation of FIG.

FIG. 5 is a clock adjustment timing circuit 10 shown in FIG. 2;
FIG. 4 is a second waveform diagram for explaining the operation of FIG.

FIG. 6 is a clock adjustment timing circuit 10 shown in FIG. 2;
FIG. 3 is a block diagram showing the configuration of FIG.

7 is a clock adjustment timing circuit 10 shown in FIG.
FIG. 6 is a waveform diagram for explaining the operation of FIG.

FIG. 8 is a block diagram illustrating a configuration of a clock synchronization circuit according to a second embodiment of the present invention.

FIG. 9 is a waveform chart for explaining the operation of the clock synchronization circuit shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Buffer 2 Edge detection circuit 3 Source clock generator 4 Divider circuit 5a, 6, 7a Counter 8 Speed code detection circuit 9 Up / down counter 10 Clock adjustment timing circuit 11 Comparison start detection circuit 100 Master device 110 Transmission buffer 120 Master clock generation Device 200 asynchronous network 300 slave device

Continued on the front page F term (reference) 5K028 AA01 KK32 NN32 NN41 5K030 GA11 HA08 HC14 KA21 LA15 5K033 CB15 CC01 DB11 5K047 BB15 GG02 GG11 JJ02 MM56 MM59 9A001 BB02 BB04 CC07 DD10 JJ12 KK37 KK56

Claims (6)

[Claims] 1. Clock generating means for generating a clock, and first counting means for counting the number of received packets transmitted at a fixed packet transmission period and counting until the counted value reaches a predetermined count number. A second counting means for counting time in a cycle equal to the packet transmission cycle using the clock, and counting until the counted value reaches a count equal to the first counting means; A clock comprising counting speed comparing means for comparing the counting speed of the counting means with the counting speed of the second counting means, wherein the clock generating means is controlled by a comparison result of the counting speed. Synchronous circuit. 2. The clock generating means, if the counting speed of the first counting means is faster, advances the phase of the clock. If the counting speed of the first counting means is slower, 2. The clock synchronization circuit according to claim 1, wherein the clock is controlled so as to delay the phase of the clock. 3. A first frequency dividing circuit for generating an extracted clock by dividing a source clock by a predetermined number of times, and a received number of packets transmitted in a fixed packet transmission cycle is determined by a predetermined comparison packet number n ( n: an integer of 1 or more), a first counting means for generating a first count end pulse for each count, and a predetermined count number m corresponding to the packet transmission cycle using the extracted clock. (M; an integer of 1 or more), a second counting means for counting the number n of reception timing comparison pulses generated for each count, and generating a second count end pulse for each count. A speed code detection circuit that detects a speed difference between the first count end pulse and the second count end pulse and outputs a speed code of the speed difference; An up / down counter that counts up, counts down, or performs no counting based on the output speed code, and outputs the count value and the sign of the count value; and a count input from the up / down counter. A clock adjustment timing circuit that controls the first frequency divider circuit based on a value and a sign. 4. A first frequency dividing circuit for generating an extracted clock by dividing a source clock by a predetermined number of times, and a received number of packets transmitted in a fixed packet transmission cycle by a predetermined comparison packet number n ( n: an integer of 1 or more), a first counting means for generating a first count end pulse for each count, and a predetermined count number m corresponding to the packet transmission cycle using the extracted clock. (M; an integer of 1 or more), a second counting means for counting the number n of reception timing comparison pulses generated for each count, and generating a second count end pulse for each count. A speed code detection circuit that detects a speed difference between the first count end pulse and the second count end pulse and outputs a sign of the speed difference; A second frequency divider circuit for generating a clock by dividing the frequency, a first count end pulse and a second count end pulse using a clock generated by the second frequency divider circuit And a speed difference detection counter that counts the time difference between occurrences of the two and outputs the count value.Based on the count value input from the speed difference detection counter and the code input from the speed code detection circuit,
A clock adjustment timing circuit for controlling the first frequency divider circuit. 5. A clock generating step of generating a clock, a first counting step of counting the number of received packets transmitted in a fixed packet transmission cycle, and counting until the counted value reaches a predetermined count number. A second counting step of counting time in a cycle equal to the packet transmission cycle using the clock and counting until the counted value reaches a count equal to the first counting step; A clock comparing step of comparing the counting speed of the counting process with the counting speed of the second counting process, wherein the clock generation process is controlled by a comparison result of the counting speed. Synchronization method. 6. The clock generating step: if the counting speed of the first counting process is faster, advance the phase of the clock; if the counting speed of the first counting process is slower, The clock synchronization method according to claim 5, wherein the clock is controlled so as to delay the phase of the clock.