JP2001308348A - Semiconductor surge protection element and method of manufacturing the same, and electronic circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor surge protection element which is produced by processing both surfaces of a wafer conventionally by a simpler wafer process to achieve a higher element yield at lower cost. SOLUTION: A first n-type ZnO polycrystalline layer, an epitaxial insulating layer and a second n-type ZnO polycrystalline layer are formed on a first electrode by an epitaxial growth method. Then, a second electrode is further provided to manufacture a semiconductor surge protection element. Such an element does not require processing of both surfaces of a wafer. When an overvoltage is applied between the two electrodes, a current flows in the epitaxial insulating layer by tunneling.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a structure and a method for manufacturing a highly reliable and low-cost semiconductor surge protection device for protecting a device from surges such as lightning and noise, and a semiconductor surge protection device. It relates to an electronic circuit.

[0002]

2. Description of the Related Art FIG.
FIG. 1 is a cross-sectional view showing a conventional semiconductor surge protection device described in Japanese Patent Application Laid-Open Publication No. H10-209, in which 13 is a P-type base region, 14 is an N-type base region, 15 is a P-type ohmic anode region,
Denotes an N-type cathode region, 17 denotes an N-type ohmic cathode region, 18 denotes an electrode, and 19, 20, and 21 denote insulating layers, respectively.

[0003] In the conventional semiconductor surge protection device, the area 1
Thyristors are formed by 3, 14, 15, 16 and 17. When a positive surge voltage is applied to the electrode 18, the PN junction composed of the N-type base region 14 and the P-type base region 13 undergoes avalanche breakdown, resulting in 15, 14, 13, 1
The avalanche current flows in the order of the regions 6 and 17. By this avalanche current, the PNP transistor composed of the regions 15, 14, and 13 is turned on.
The NPN transistor consisting of 13, 16, 17 turns on,
The forward thyristor switches.

[0004]

A conventional semiconductor surge protection element for protecting a semiconductor chip from a surge has a structure using both the upper and lower surfaces of a substrate as shown in FIG. Therefore, in order to manufacture such a semiconductor surge protection device, a process technology that can handle both the upper and lower surfaces of the semiconductor substrate is required. For example, a technique of ion-implanting or diffusing P-type impurities and N-type impurities from both upper and lower surfaces is essential. In addition, an insulating film, an electrode, and the like can be formed on both surfaces, and a lithography technique for both upper and lower surfaces is required.

In a semiconductor surge protection device manufactured through such a complicated and long wafer process, it is difficult to maintain the process stably, so that the characteristics of the device greatly vary, leading to a reduction in yield and a reduction in process time. There is a problem that the cost increases with the increase.

[0006]

A semiconductor surge protection device according to the present invention comprises a first N-type semiconductor polycrystalline layer formed on a first electrode and a second N-type semiconductor layer formed on a second electrode. A semiconductor polycrystalline layer, the first N-type semiconductor polycrystalline layer, and the second N-type semiconductor polycrystalline layer.
An insulating layer formed between the first type semiconductor polycrystal layer and the first electrode and the second electrode, through which a current flows by a tunnel phenomenon when an overvoltage exceeding a predetermined level is applied. .

Further, the semiconductor surge protection device of the present invention is formed on the first N-type semiconductor polycrystalline layer, and has at least two-layer structure composed of the insulating layer and the second N-type semiconductor polycrystalline layer. It is a laminated structure having more than one cycle.

In the semiconductor surge protection device according to the present invention, the thickness of the insulating layer is 1 to 30 nm.

Further, in the semiconductor surge prevention element, the above-mentioned insulating layer is an epitaxial insulating layer, an impurity-doped amorphous insulating layer, or an amorphous semiconductor layer.

The method of manufacturing a semiconductor surge protection device according to the present invention includes a step of forming a first N-type semiconductor polycrystal layer on a first electrode by an epitaxial crystal growth method; Forming an insulating layer having a predetermined thickness and exhibiting a tunnel effect thereon, forming a second N-type semiconductor polycrystalline layer on the insulating layer by an epitaxial crystal growth method, and Forming a second electrode on the N-type semiconductor polycrystalline layer.

In the electronic circuit according to the present invention, the above-described semiconductor surge protection element is connected between a signal input pad in the electronic circuit to be protected from surge and the ground.

[0012]

[Embodiment 1] A first N-type zinc oxide (ZnO) polycrystalline layer 2 is formed on a ground connection terminal of a semiconductor chip or a first electrode 1 on a ground line by MOCVD (Metal Organi
(c Chemical Vapor Deposition) method. In addition, as an epitaxial crystal growth method, other than the MOCVD method, for example,
MBE (Molecular Beam Epitaxy) method, ICB (Ion Cl
uster Beam) method, LPCVD (Low Pressure Chemical)
The Vapor Deposition method may be used. Immediately after the completion of the epitaxial growth, the gas in the chamber, which is the epitaxial growth chamber of the MOCVD apparatus, is exhausted by the exhaust device, and the pressure in the chamber is reduced to 1 × 10 ⁻⁵ torr or less.

Subsequently, a silicon dioxide (SiO ₂ ) epitaxial insulating layer 3 is formed on the first N-type ZnO polycrystalline layer 2 by 10 nm.
m epitaxial growth. In addition, as the insulating film type,
For example, another oxide layer such as an aluminum oxide (Al ₂ O ₃ ) epitaxial insulating layer, or silicon nitride (Si ₃ N ₄ )
A nitride insulating layer such as an epitaxial insulating layer may be used.

Immediately after the completion of the epitaxial growth, the gas in the chamber of the MOCVD device is evacuated by the exhaust device,
The pressure is reduced to 1 × 10 ⁻⁵ torr or less. The second N-type ZnO polycrystalline layer 4 is again deposited on the SiO ₂ insulating layer 3 by the MOCVD apparatus.
Epitaxially grow 0 nm. After the completion of the epitaxial growth, the second electrode 5 is formed on the second N-type ZnO polycrystalline layer 4.
Is formed, a surge protection element as shown in FIG. 1 is completed.

The thickness of the epitaxial insulating layer 3 may be set to a value other than 10 nm according to the operating voltage of the semiconductor chip. The thickness of the SiO ₂ insulating layer of 10 nm has a withstand voltage of about 3 V, and both have a proportional relationship. Therefore, it is possible to set the optimum thickness of the insulating layer according to the required withstand voltage. However, from the viewpoint of exhibiting the tunnel effect, the thickness of the layer is preferably 1 to 30 nm.

Embodiment 2 FIG. The laminated structure composed of the SiO ₂ epitaxial insulating layer 3 and the N-type ZnO polycrystalline layer 4 in Example 1 is repeated for n cycles (n ≧ 2), and on the N-type ZnO polycrystalline layer 6 which is the outermost layer of the n-th cycle. The second electrode 5
To form FIG. 2 shows a cross-sectional view after the device is completed.

Embodiment 3 FIG. A first N-type ZnO polycrystalline layer 2 is epitaxially grown to a thickness of 60 nm by an ICB device on a ground connection terminal or a first electrode 1 on a ground line of a semiconductor chip. After the completion of the epitaxial growth, impurities such as bismuth and strontium are continuously ion-implanted to a depth of 10 n from the surface of the first N-type ZnO polycrystalline layer 2.
Then, an impurity-doped amorphous insulating layer 7 is formed over a length of m. The crystal structure of the impurity-doped amorphized insulating layer 7 is further disturbed by the energy at the time of ion implantation than the polycrystalline state, and the ZnO polycrystalline layer 2 is made amorphous. The ZnO layer made amorphous by the addition of the impurity functions as the insulating layer 7. After the ion implantation, a second N-type ZnO polycrystalline layer 4 is epitaxially grown to a thickness of 50 nm on the impurity-doped amorphous insulating layer 7 by an ICB apparatus. After the completion of the epitaxial growth, a second electrode 5 is formed on the second N-type ZnO polycrystalline layer 4. FIG. 3 is a cross-sectional view after the device is completed.

When fabricating an N-type ZnO polycrystalline layer, the cluster of the material to be grown is accelerated at an accelerating voltage in the range of 0.5 to 1.0 V to epitaxially grow. For the ion implantation of impurities such as bismuth and strontium, the optimum range of the acceleration voltage is 103 to 104 V.

Embodiment 4 FIG. The laminated structure composed of the impurity-doped amorphized insulating layer 7 / N-type ZnO polycrystalline layer 4 in Example 3 is repeated n cycles (n ≧ 2), and on the N-type ZnO polycrystalline layer 6 which is the outermost layer in the nth cycle. Then, the second electrode 5 is formed. In this case, the N-type ZnO closest to the surface
No impurity ion implanted layer 9 is formed in the polycrystalline layer 6. FIG. 4 shows a cross-sectional view after the device is completed.

Embodiment 5 FIG. A first N-type Z is provided on the ground connection terminal of the semiconductor chip or on the first electrode 1 on the ground line.
The nO polycrystalline layer 2 is epitaxially grown to a thickness of 50 nm by an ICB apparatus. After epitaxial growth, ICB
By increasing the accelerating voltage of the device, the amorphous ZnO
A layer 8 is formed to a thickness of 10 nm on the first N-type ZnO polycrystalline layer 2. In this case, ZnO clusters are supplied continuously.

Next, a second N-type ZnO is formed by an ICB device.
The polycrystalline layer 4 is formed on the amorphous ZnO layer 8 by 50 nm.
m epitaxial growth. After the completion of the epitaxial growth, a second electrode 5 is formed on the second N-type ZnO polycrystalline layer 4. FIG. 5 shows a cross-sectional view after the completion of the device. The film is formed at an acceleration voltage of 0.5 to 1.0 V when performing epitaxial growth, and at an acceleration voltage of 10 to 100 V when forming an amorphous ZnO layer 8.

Embodiment 6 FIG. The stacked structure composed of the amorphous ZnO layer 8 / N-type ZnO polycrystalline layer 4 in Example 5 is repeated n cycles (n ≧ 2), and the stacked structure is formed on the N-type ZnO polycrystalline layer 6 which is the outermost layer in the nth cycle. Two electrodes 5 are formed. FIG. 6 shows a cross-sectional view after the completion of the device.

Next, the functions of the surge protection elements of the first to sixth embodiments will be described. As shown in FIG. 7, a semiconductor surge protection element 11 is provided between an electronic circuit 9 to be protected from a surge and an input pad 10 for an external signal.
By connecting one of the electrodes to the ground line 12, the electronic circuit 9 can be protected from overvoltage caused by lightning surge, noise, or the like.

FIG. 8 schematically shows an energy band diagram in a laminated structure of first ZnO polycrystalline layer 2 / insulating layer 3 / second ZnO polycrystalline layer 4.
Normally, that is, when there is no overvoltage, the current is insulated because the Schottky barrier is formed by the insulating layer 3. However, when the overvoltage is applied, the current passes through the insulating layer 3 due to a tunnel phenomenon. Such overcurrent flows to the ground line 12 shown in FIG. By flowing an overcurrent at the time of applying an overvoltage to the ground line 12 by such a method, the electronic circuit 9 shown in FIG.
Can be protected.

The surge withstand voltage is as follows:
4 depends on the thickness of the insulating layer 3 sandwiched between the layers. Therefore, as the number of insulating layers increases, the surge withstand voltage increases proportionally.

In the above embodiment, Z is mainly used as a material.
Although the description has been made using nO, it goes without saying that a similar effect can be obtained with other semiconductor materials, for example, semiconductors such as titanium oxide (TiO ₂ ), silicon (Si), and gallium arsenide (GaAs).

[0027]

According to the semiconductor surge protection device of the present invention, the first N-type semiconductor polycrystal layer formed on the first electrode and the second N-type semiconductor polycrystal layer formed on the second electrode Forming between the first N-type semiconductor polycrystalline layer and the second N-type semiconductor polycrystalline layer, and applying an overvoltage of not less than a predetermined value between the first electrode and the second electrode; Was provided with an insulating layer through which current flows due to the tunnel phenomenon. As a result,
A high-performance semiconductor surge protection element can be manufactured by a simple manufacturing process with little variation in element characteristics.

In the semiconductor surge protection device of the present invention,
An N-type semiconductor polycrystalline layer formed on a first electrode;
A stacked structure having at least two cycles or more of a two-layer structure formed of an insulating layer and a second N-type semiconductor polycrystalline layer formed on the type semiconductor polycrystalline layer, and a second electrode formed on the stacked structure. I did it. As a result, a high-performance semiconductor surge protection device corresponding to a required surge withstand voltage can be manufactured by a simple manufacturing process with little variation in device characteristics.

In the semiconductor surge protection device of the present invention,
The thickness of the insulating layer was 1 to 30 nm. As a result, it is possible to manufacture a high-performance semiconductor surge protection device corresponding to a required surge withstand voltage.

Further, in the semiconductor surge arrester of the present invention,
The above-mentioned insulating layer was an epitaxial insulating layer, an impurity-doped amorphous insulating layer, or an amorphous semiconductor layer. As a result, a high-performance semiconductor surge protection device corresponding to a required surge withstand voltage can be manufactured by a simple manufacturing process with little variation in device characteristics.

In the method for manufacturing a semiconductor surge protection device according to the present invention, the method for manufacturing a semiconductor surge protection device according to the present invention includes forming a first N-type semiconductor polycrystalline layer on a first electrode by an epitaxial crystal growth method. Forming an insulating layer having a predetermined thickness and exhibiting a tunnel effect on the first N-type semiconductor polycrystalline layer; and forming a second N-type semiconductor polycrystalline layer on the insulating layer by an epitaxial crystal growth method. A step of forming a crystal layer and a step of forming a second electrode on the second N-type semiconductor polycrystalline layer. As a result, a high-performance semiconductor surge protection device corresponding to a required surge withstand voltage can be manufactured by a simple manufacturing process with little variation in device characteristics.

In the electronic circuit of the present invention, the above-described semiconductor surge protection element is connected between the signal input pad in the electronic circuit to be protected from surge and the ground, so that a high-performance semiconductor surge corresponding to the required surge withstand voltage is provided. A protective element is obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor surge protection device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor surge protection device according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor surge protection device according to a third embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor surge protection device according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor surge protection device according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor surge protection device according to a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of an electronic circuit including the semiconductor surge protection element of the present invention.

FIG. 8 is an energy band diagram of a stacked structure including an N-type ZnO polycrystalline layer / an insulating layer / N-type ZnO polycrystalline layer.

FIG. 9 is a cross-sectional view of a conventional semiconductor surge protection device.

[Explanation of symbols]

1 first electrode, 2 first N-type ZnO polycrystalline layer,
3, 3 ′, epitaxial insulating layer, 4, 4 ′ second N-type ZnO polycrystalline layer, 5 second electrode, 6 ZnO polycrystalline layer, 7, 7 ′ doped amorphous insulating layer, 8, 8 ′ amorphous ZnO layer, 9 electronic circuit, 10 external signal input pad, 11 surge protection element, 12 ground line, 13 P-type base region, 14 N-type base region, 15 P-type ohmic anode region, 16 N-type cathode region, 17 N
Type ohmic cathode region, 18 electrodes, 19 insulating layers, 20 insulating layers, 21 insulating layers

Claims (8)

[Claims] 1. A first N-type semiconductor polycrystalline layer formed on a first electrode, a second N-type semiconductor polycrystalline layer formed on a second electrode, and the first N-type semiconductor polycrystalline layer. Crystal layer and the second
And an insulating layer formed between the first electrode and the second electrode to pass a current by a tunnel phenomenon when a predetermined overvoltage is applied between the first electrode and the second electrode. Semiconductor surge protection element. 2. A laminated structure formed on the first N-type semiconductor polycrystalline layer and having at least two cycles of a two-layer structure composed of the insulating layer and the second N-type semiconductor polycrystalline layer. The semiconductor surge protection device according to claim 1, wherein: 3. The semiconductor surge protection device according to claim 1, wherein said insulating layer has a thickness of 1 to 30 nm. 4. The semiconductor surge protection device according to claim 1, wherein said insulating layer is an epitaxial insulating layer. 5. The semiconductor surge protection device according to claim 1, wherein the insulating layer is an impurity-doped amorphous insulating layer. 6. The semiconductor surge protection device according to claim 1, wherein said insulating layer is an amorphous semiconductor layer. 7. forming a first N-type semiconductor polycrystalline layer on the first electrode by an epitaxial crystal growing method;
Forming an insulating layer having a predetermined thickness and exhibiting a tunnel effect on the first N-type semiconductor polycrystalline layer; and forming a second N-type semiconductor polycrystalline layer on the insulating layer by an epitaxial crystal growing method. Forming a second electrode on the second N-type semiconductor polycrystalline layer. 2. A method for manufacturing a semiconductor surge protection device, comprising: 8. An electronic circuit to be protected from surge, a first N-type semiconductor polycrystalline layer formed on a first electrode, and a second electrode formed between a signal input pad of the electronic circuit and a ground. A second N-type semiconductor polycrystalline layer, formed between the first N-type semiconductor polycrystalline layer and the second N-type semiconductor polycrystalline layer, and formed between the first electrode and the second electrode. An electronic circuit, comprising: a semiconductor surge protection element including an insulating layer through which a current flows due to a tunnel phenomenon when an overvoltage exceeding a predetermined level is applied therebetween.