JP2009158528A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can establish appropriate characteristics, while enabling size reduction, high-voltage resistance and low power consumption. <P>SOLUTION: The semiconductor device 1 includes: an SiC layer 11 which has a larger band gap than that of silicon and wherein a power transistor 2 is formed; a silicon layer 21 which is formed in a specified region above the main surface 11a of the SiC layer 11 and is made of a layer which is different from the SiC layer 11 and wherein an NMOS transistor 3 and a PMOS transistor 4 for a control circuit are formed; and Al wiring 5 for connecting the power transistor 2 of the SiC layer 11 and the NMOS transistor 3 and the PMOS transistor 4 of the silicon layer 21. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a semiconductor layer having a larger band gap than silicon.

  Conventionally, electrical energy conversion devices such as DC / DC converters, AC / DC converters, and regulator ICs have been used in power supply systems of electrical equipment, and are required to be small in size, high withstand voltage, and low in power consumption. In order to realize this requirement, a power transistor having a high breakdown voltage and a low on-resistance is required. For example, a super junction structure has been developed in order to reduce the on-resistance with a high breakdown voltage, but as long as silicon is used as a semiconductor material, performance close to the theoretical value has been realized, and the limit is visible. . Therefore, in order to significantly improve the performance (breakdown voltage and on-resistance) when silicon is used as the semiconductor material, it is effective to use a semiconductor material having a band gap larger than that of silicon. The reason for this will be described below.

  The physical factor that determines the drain breakdown voltage is avalanche breakdown. In avalanche breakdown, electrons moving at high speed by a high electric field generate electron-hole pairs by their kinetic energy, and carriers are amplified like an avalanche (this amplification is called avalanche amplification). It is a phenomenon. Then, since the amplified electrons further generate electron-hole pairs, a large current flows and finally destruction occurs.

  The magnitude of avalanche amplification is determined by the field strength dependence of the generation rate of electron-hole pairs in the semiconductor material. Since this generation rate is inversely proportional to the value of the band gap, a semiconductor material having a large band gap is effective for realizing a high breakdown voltage.

  One factor that determines the on-resistance is the carrier mobility of the substrate. For example, the carrier mobility of a wide band gap semiconductor having a larger band gap than silicon is several times larger than the carrier mobility of silicon.

  The band gap of silicon is about 1.12 eV, the band gap of silicon carbide (SiC) is about 3.26 eV, the band gap of gallium nitride (GaN) is about 3.37 eV, and the band gap of diamond is about 5. 47 eV. For this reason, for example, when SiC is used, a dielectric breakdown electric field strength about 10 times as large as that of silicon can be obtained. Since the on-resistance is inversely proportional to the cube of the dielectric breakdown electric field strength, the use of SiC can make the on-resistance about 1/1000 as compared with the case of using silicon. Conversely, if the same on-resistance value is used, the size can be reduced to about 1/1000 by using SiC. For this reason, it is important to develop a semiconductor device including a semiconductor layer having a large band gap.

  However, when a MOS (Metal Oxide Semiconductor) transistor is formed using a wide band gap semiconductor made of SiC, for example, the channel mobility is extremely low for both electrons and holes due to the deterioration of the crystallinity of the channel region that occurs during manufacturing. When viewed as a CMOS (Complementary MOS) circuit, there is a disadvantage that only inferior characteristics can be obtained as compared with the case of using silicon.

  In addition, a wide band gap semiconductor made of, for example, GaN has a high interface order density, and the manufacturing process becomes complicated. Therefore, there is a disadvantage that it is very difficult to form a CMOS structure. Furthermore, there is a disadvantage that it is difficult to form a p-type layer.

  Because of such inconvenience, conventionally, a wide band gap semiconductor is used to form a power transistor, while a CMOS circuit (CMOS structure) effective for low power consumption for controlling the power transistor is a separate chip. (Semiconductor device) had to be manufactured. Specifically, as illustrated in FIG. 14, a semiconductor device 101 in which a power transistor is formed and a semiconductor device 102 in which a CMOS circuit for controlling the semiconductor device 101 is formed using different chips. It was necessary to configure the package 100 by connecting the 101 and 102 with the metal wire 103. For this reason, there is a disadvantage that it is difficult to downsize the entire device.

  In order to eliminate this inconvenience, a structure in which a SiC layer having a power transistor is formed on a silicon substrate has been proposed (see, for example, Patent Document 1).

In Patent Document 1, a control circuit composed of a MOS transistor is formed on a silicon substrate, and a SiC layer having a power device (power transistor) is formed in a region where no control circuit is formed on the silicon substrate. An improved high voltage device structure is disclosed.
JP 7-254706 A

  Although a detailed manufacturing method is not disclosed in Patent Document 1 above, when a power transistor is formed in an SiC layer, it is usually necessary to maintain good crystallinity during manufacturing in order to reduce the leakage current of the power transistor. It is necessary to perform annealing (heat treatment) at a temperature of about 1500 ° C.

  Further, in the structure of Patent Document 1, when GaN is used instead of SiC, in order to form a high concentration region such as a contact layer, Si or the like is ion-implanted and then annealed at a temperature of about 1200 ° C. Heat treatment) must be performed.

  However, if annealing (heat treatment) is performed at a temperature of 1500 ° C. or 1200 ° C. with a MOS transistor formed on the silicon substrate, impurities doped in the silicon substrate are excessively diffused to function as a device. There is a problem of disappearing.

  Even if annealing (heat treatment) is performed before forming a MOS transistor on a silicon substrate, the silicon substrate is warped and the photolithography process cannot be performed accurately, or stress is generated on the silicon substrate, resulting in variations in device characteristics. There is a problem.

  In the structure as in Patent Document 1, when a SiC layer is formed on the entire main surface of the silicon substrate and then part of the SiC layer is removed and the SiC layer is patterned, the silicon substrate is damaged. Therefore, it is difficult to remove the SiC layer without degrading the characteristics of the MOS transistor on the silicon substrate.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device that can be reduced in size, increased in breakdown voltage, and reduced in power consumption while obtaining good characteristics. Is to provide.

  In order to achieve the above object, a semiconductor device according to one aspect of the present invention has a larger band gap than silicon, a semiconductor layer in which a first transistor is formed, and a predetermined upper side than the main surface of the semiconductor layer. And a second transistor for the control circuit is formed, a silicon layer formed of a layer different from the semiconductor layer, and a wiring for connecting the first transistor of the semiconductor layer and the second transistor of the silicon layer Is provided.

  In the semiconductor device according to this aspect, as described above, by forming the first transistor in the semiconductor layer having a band gap larger than that of silicon, it is possible to increase the breakdown voltage of the first transistor and Power consumption (low on-resistance) can be reduced. In addition, the first transistor is provided in the semiconductor layer, and the second transistor for the control circuit is provided in the silicon layer formed in the predetermined region above the main surface of the semiconductor layer. The second transistor for controlling the current can be formed in one chip (semiconductor device). Accordingly, the semiconductor device can have a high breakdown voltage, low power consumption, and a small size.

  Further, in the semiconductor device according to one aspect, as described above, the semiconductor device has a band gap larger than that of silicon and is formed in a predetermined region above the main surface of the semiconductor layer in which the first transistor is formed. In addition, the second transistor for the control circuit is formed, and the first transistor is formed in the semiconductor layer having a larger band gap than silicon by providing a silicon layer formed of a layer different from the semiconductor layer. Since the silicon layer having the second transistor can be formed in a predetermined region above the main surface of the semiconductor layer, the silicon layer is heated to a high temperature (for example, 1200 ° C. or 1500 ° C. by heat treatment when forming the first transistor). ) Can be suppressed. Thereby, it is possible to suppress the impurity doped in the silicon layer from being excessively diffused and the second transistor from functioning. Moreover, since it can suppress that a silicon layer becomes high temperature (for example, 1200 degreeC or 1500 degreeC), it can suppress that a silicon layer warps or a stress generate | occur | produces. As a result, it is possible to prevent the photolithography process from being performed accurately and the characteristics of the second transistor (semiconductor device) from varying.

  In the semiconductor device according to the aforementioned aspect, the semiconductor layer preferably contains SiC, GaN, or diamond. With this configuration, the band gap of SiC, GaN, and diamond is sufficiently larger than the band gap of silicon, so that the on-resistance of the first transistor formed in the semiconductor layer can be easily and sufficiently reduced. Can do. Thereby, it is possible to easily and sufficiently reduce the power consumption of the semiconductor device.

  In the semiconductor device according to the aforementioned aspect, a protective film is preferably formed between the semiconductor layer and the silicon layer. If comprised in this way, in order to form a silicon layer in the predetermined area | region above the main surface of a semiconductor layer, after forming a silicon layer on the whole main surface of a semiconductor layer (protective film), for example, a silicon layer When the silicon layer is patterned by removing a part of the silicon layer, the silicon layer can be removed while suppressing damage to the semiconductor layer. Thereby, it can suppress that the characteristic of the 1st transistor of a semiconductor layer falls.

  In the semiconductor device according to the aforementioned aspect, an insulating layer is preferably disposed between the semiconductor layer and the silicon layer. With this configuration, even when a large current flows through the semiconductor layer in which the first transistor is formed, it is possible to suppress fluctuations in the potential of the silicon layer. Thereby, it can suppress that the characteristic of a semiconductor device falls.

  In the semiconductor device according to the above aspect, the silicon layer is preferably formed above the main surface of the semiconductor layer after the heat treatment step when forming the first transistor in the semiconductor layer. If comprised in this way, it can suppress easily that a silicon layer becomes high temperature (for example, about 1200 degreeC or about 1500 degreeC) by the heat processing at the time of forming a 1st transistor in a semiconductor layer.

  In the semiconductor device according to the above aspect, the silicon layer is preferably formed by a chemical vapor deposition method at a temperature of 600 ° C. or lower. With this configuration, the silicon layer can be prevented from being heated to a high temperature of, for example, 1200 ° C. or 1500 ° C., so that it is easy for the second transistor (semiconductor device) to not function or to vary in characteristics. Moreover, it can be suppressed.

  In the semiconductor device according to the aforementioned aspect, the silicon layer preferably includes polysilicon or continuous grain boundary crystalline silicon. If comprised in this way, a silicon layer can be easily formed in the predetermined area | region above the main surface of a semiconductor layer. At this time, if the silicon layer is made of continuous grain silicon (CGS), the mobility of electrons (carriers) can be improved as compared to the case where the silicon layer is made of polysilicon. The characteristics of the second transistor (semiconductor device) can be further improved.

  In the semiconductor device according to the aforementioned aspect, the second transistor of the silicon layer preferably has a CMOS structure. With this configuration, since the CMOS structure is effective for reducing power consumption, the power consumption of the second transistor (semiconductor device) can be easily reduced.

  As described above, according to the present invention, it is possible to easily obtain a semiconductor device that can be reduced in size, increased in breakdown voltage, and reduced in power consumption while obtaining good characteristics.

(First embodiment)
FIG. 1 is a cross-sectional view illustrating the structure of a semiconductor device according to a first embodiment of the present invention. First, the structure of the semiconductor device 1 according to the first embodiment of the present invention will be described with reference to FIG.

  The semiconductor device 1 according to the first embodiment of the present invention is used in a power supply system of electrical equipment as an electrical energy conversion device such as a DC / DC converter, an AC / DC converter, and a regulator IC.

  Further, as shown in FIG. 1, the semiconductor device 1 includes a lower region 1a in which a power transistor 2 is formed and an upper region 1b in which an NMOS transistor 3 and a PMOS transistor 4 for a control circuit are formed. . The power transistor 2 in the lower region 1a is electrically connected to the NMOS transistor 3 and the PMOS transistor 4 in the upper region 1b by an Al wiring 5 (partially not shown). The power transistor 2 is an example of the “first transistor” in the present invention, and the NMOS transistor 3 and the PMOS transistor 4 are examples of the “second transistor” in the present invention. The Al wiring 5 is an example of the “wiring” in the present invention.

  Lower region 1a includes single crystal SiC substrate 10, p-type SiC layer 11 formed on single crystal SiC substrate 10, gate oxide film 12 formed on main surface 11a of SiC layer 11, gate oxide A gate electrode 13 made of polysilicon formed in a predetermined region on the film 12 and a protective film 14 formed in a region where the gate electrode 13 on the gate oxide film 12 is not formed. The SiC layer 11 is an example of the “semiconductor layer” in the present invention, and the gate oxide film 12 and the protective film 14 are examples of the “insulating layer” in the present invention.

  The SiC layer 11 has a thickness of about 8 μm and is doped with, for example, Al. A source region 11 b and a drain region 11 c doped with n-type impurities are formed in a predetermined region on the upper surface side of SiC layer 11. The SiC transistor 11 (source region 11b and drain region 11c), the gate oxide film 12, and the gate electrode 13 constitute the power transistor 2.

  The gate electrode 13 and the drain region 11c are connected to the Al wiring 5 through the Ti layer 6, respectively. Although not shown, the source region 11 b is also connected to the Al wiring 5 through the Ti layer 6.

Both the gate oxide film 12 and the protective film 14 are made of a silicon oxide film (SiO ₂ film) and have insulating properties.

  The upper region 1b has a CMOS structure composed of an NMOS transistor 3 and a PMOS transistor 4. The NMOS transistor 3 and the PMOS transistor 4 constitute a control circuit for controlling the power transistor 2.

  The upper region 1b includes a silicon layer 21 formed in a predetermined region on the protective film 14 in the lower region 1a, a gate insulating film 22 formed on the silicon layer 21, and a predetermined region on the gate insulating film 22. The formed gate electrodes 23a and 23b and an insulating film 24 made of a silicon oxide film formed over the entire upper surface of the protective film 14 so as to cover the silicon layer 21, the gate insulating film 22, and the gate electrodes 23a and 23b. ing.

  The silicon layer 21 is made of continuous grain boundary crystalline silicon (CGS) in which crystals are regularly continuous. The silicon layer 21 includes a p-well region 21a doped with boron (B) or the like and an n-well region 21b doped with phosphorus (P) or the like.

  A source region 21c and a drain region 21d doped with phosphorus (P) or the like are formed in a predetermined region on the upper surface side of the p-well region 21a. The NMOS transistor 3 is constituted by the p-well region 21a (source region 21c and drain region 21d), the gate insulating film 22 and the gate electrode 23a of the silicon layer 21.

  On the other hand, a source region 21e and a drain region 21f doped with boron (B) or the like are formed in a predetermined region on the upper surface side of the n well region 21b. The n-well region 21b (source region 21e and drain region 21f), the gate insulating film 22 and the gate electrode 23b of the silicon layer 21 constitute the PMOS transistor 4.

  The gate electrode 23a, source region 21c, drain region 21d constituting the NMOS transistor 3 and the gate electrode 23b, source region 21e and drain region 21f constituting the PMOS transistor 4 are respectively connected to the Al wiring 5 via the Ti layer 6. It is connected to the.

  The NMOS transistor 3 is electrically connected to the power transistor 2 through the Ti layer 6 and the Al wiring 5. The NMOS transistor 3 is electrically connected to the PMOS transistor 4 via the Ti layer 6 and an Al wiring 5 (not shown).

  2 to 8 are cross-sectional views for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIG. A manufacturing process for the semiconductor device 1 according to the first embodiment of the present invention will now be described with reference to FIGS.

  First, as shown in FIG. 2, a p-type SiC layer 11 having a thickness of about 8 μm is formed on a single crystal SiC substrate 10 by epitaxial growth at a temperature of about 1500 ° C. using Ar as a purge gas. At this time, the SiC layer 11 is formed into a p-type by doping Al, for example.

  Then, as shown in FIG. 3, Al, P (phosphorus) or B (boron) is applied to the main surface 11a of the SiC layer 11 in order to adjust the inversion voltage of the region serving as the channel of the power transistor 2 (see FIG. 1). ) Etc. are ion-implanted by a predetermined amount. At this time, in order to suppress the occurrence of crystal defects in the SiC layer 11 due to the ion implantation, the ion implantation is performed while the single crystal SiC substrate 10 (SiC layer 11) is held at a temperature of about 500 ° C. to about 800 ° C. It is desirable to do.

Thereafter, as shown in FIG. 4, a gate oxide film 12 made of a silicon oxide film (SiO ₂ ) is formed on main surface 11a of SiC layer 11 by thermal oxidation. Note that SiC is the only material capable of forming SiO ₂ by thermal oxidation among wide band gap semiconductors.

  Then, polysilicon is grown on the gate oxide film 12. Thereafter, a part of the grown polysilicon is removed by using a photolithography technique and a dry etching technique, so that a gate electrode made of polysilicon is formed in a predetermined region on the gate oxide film 12 as shown in FIG. 13 is formed.

  Then, n-type impurities are ion-implanted into the regions to be the source region 11 b and the drain region 11 c of the SiC layer 11. At this time, in order to suppress the occurrence of crystal defects in the SiC layer 11 due to the ion implantation, the ion implantation is performed while the single crystal SiC substrate 10 (SiC layer 11) is held at a temperature of about 500 ° C. to about 800 ° C. It is desirable to do.

  Thereafter, annealing (heat treatment) is performed at a temperature of about 1200 ° C. or higher in order to activate the implanted impurities. Thereby, the power transistor 2 is formed.

  Then, as shown in FIG. 6, in order to protect the power transistor 2, a protective film 14 made of a silicon oxide film is formed by chemical vapor deposition so as to cover the gate oxide film 12 and the gate electrode 13.

  Next, the silicon layer 21 is formed on the protective film 14 by chemical vapor deposition at a relatively low temperature of about 600 ° C. Then, by irradiating the silicon layer 21 with a laser, the silicon is recrystallized to become continuous grain boundary crystalline silicon.

  Thereafter, boron (B) or the like is ion-implanted into a predetermined region of the silicon layer 21 (a region to be a p-well region 21a (see FIG. 2)), and a predetermined region (n-well region 21b (see FIG. 2) of the silicon layer 21 is also formed. In the region, phosphorus (P) or the like is ion-implanted. Then, by removing a part of the silicon layer 21 using an etching technique, a p-well region 21a and an n-well region 21b are formed in predetermined regions on the protective film 14, as shown in FIG.

  Thereafter, as shown in FIG. 8, a gate insulating film 22 is formed on the upper surface of the silicon layer 21 (p well region 21a and n well region 21b) at a temperature of about 300 ° C. by photo-oxidation.

  Then, phosphorus (P) or the like is ion-implanted into the regions to be the source region 21c and the drain region 21d of the p-well region 21a, and boron (B) is added to the regions to be the source region 21e and the drain region 21f of the n-well region 21b. ) Etc. are ion-implanted.

  Thereafter, annealing (heat treatment) is performed at a temperature of about 600 ° C. in order to activate the implanted impurities.

  Then, as shown in FIG. 1, gate electrodes 23 a and 23 b are formed in a predetermined region on the gate insulating film 22. Thereby, the NMOS transistor 3 and the PMOS transistor 4 are formed.

  Thereafter, an insulating film 24 made of a silicon oxide film is formed on the entire upper surface of the protective film 14 so as to cover the silicon layer 21, the gate insulating film 22, and the gate electrodes 23a and 23b by chemical vapor deposition.

  Then, a contact hole is formed in a predetermined region of the insulating film 24, and a Ti layer 6 as a barrier metal and an Al wiring 5 are formed so as to fill the contact hole. Thereafter, the Al wiring 5 is patterned. Thereby, the power transistor 2, the NMOS transistor 3, and the PMOS transistor 4 are electrically connected.

  As described above, the semiconductor device 1 according to the first embodiment is manufactured.

  In the first embodiment, as described above, by forming the power transistor 2 in the SiC layer 11 having a band gap larger than that of silicon, the power transistor 2 can have a high breakdown voltage and low power consumption. (Lower on-resistance). Further, the power transistor 2 is provided in the SiC layer 11 and is formed in a predetermined region above the main surface 11 a of the SiC layer 11. The silicon layer 21, which is a layer different from the SiC layer 11, has an NMOS for a control circuit. By providing the transistor 3 and the PMOS transistor 4, the power transistor 2 and the NMOS transistor 3 and the PMOS transistor 4 for controlling the power transistor 2 can be formed in one chip (semiconductor device 1). As a result, the semiconductor device 1 can have a high breakdown voltage, low power consumption, and a small size.

  In the first embodiment, after the power transistor 2 is formed in the SiC layer 11 having a larger band gap than silicon, the NMOS transistor 3 and the PMOS transistor 4 are formed in a predetermined region above the main surface 11a of the SiC layer 11. And a silicon layer 21 made of a layer different from the SiC layer 11 is provided, so that the silicon layer 21 is heated to a high temperature (for example, 1200 ° C. or 1500 ° C.) by heat treatment when forming the power transistor 2. It can be suppressed. Thereby, it is possible to prevent the impurity doped in the silicon layer 21 from being excessively diffused and the NMOS transistor 3 and the PMOS transistor 4 (semiconductor device 1) from functioning. Moreover, since it can suppress that the silicon layer 21 becomes high temperature (for example, 1200 degreeC or 1500 degreeC), it can suppress that the silicon layer 21 warps or a stress generate | occur | produces. As a result, it is possible to prevent the photolithography process from being performed accurately and the characteristics of the NMOS transistor 3 and the PMOS transistor 4 (semiconductor device 1) from varying.

  In the first embodiment, since the SiC band gap is sufficiently larger than the silicon band gap, the on-resistance of the power transistor 2 formed in the SiC layer 11 can be easily made sufficiently small. . Thereby, the semiconductor device 1 can be easily and sufficiently reduced in power consumption.

  In the first embodiment, the protective layer 14 is formed between the SiC layer 11 and the silicon layer 21 to form the silicon layer 21 in a predetermined region above the main surface 11 a of the SiC layer 11. In addition, when the silicon layer 21 is formed on the entire surface of the SiC layer 11 (protective film 14) and then the silicon layer 21 is patterned by removing a part of the silicon layer 21, the SiC layer 11 is prevented from being damaged. However, the silicon layer 21 can be removed. Thereby, it can suppress that the characteristic of the power transistor 2 of the SiC layer 11 falls.

  In the first embodiment, the gate oxide film 12 and the protective film 14 having insulating properties are disposed between the SiC layer 11 and the silicon layer 21, so that the SiC layer 11 in which the power transistor 2 is formed is greatly increased. Even when a current flows, the potential of the silicon layer 21 can be suppressed from fluctuating. Thereby, it can suppress more that the characteristic of the semiconductor device 1 falls.

  In the first embodiment, the silicon layer 21 is formed at a temperature of about 600 ° C. or less by a chemical vapor deposition method, thereby suppressing the silicon layer 21 from becoming a high temperature of, for example, 1200 ° C. or 1500 ° C. Therefore, it is possible to easily suppress the NMOS transistor 3 and the PMOS transistor 4 (semiconductor device 1) from functioning or varying in characteristics.

  In the first embodiment, the mobility of electrons (carriers) is improved by configuring the silicon layer 21 with continuous grain boundary crystal silicon as compared with the case where the silicon layer 21 is configured with, for example, polysilicon. Therefore, the characteristics of the NMOS transistor 3 and the PMOS transistor 4 (semiconductor device 1) can be further improved.

  In the first embodiment, since the silicon layer 21 is formed so as to have a CMOS structure including the NMOS transistor 3 and the PMOS transistor 4, the CMOS structure is effective in reducing power consumption. In addition, power consumption can be reduced.

(Second Embodiment)
FIG. 9 is a sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention. First, referring to FIG. 9, in the second embodiment, unlike the first embodiment, a case where a semiconductor layer having a band gap larger than that of silicon is made of GaN will be described.

  As shown in FIG. 9, the semiconductor device 31 according to the second embodiment of the present invention includes a lower region 31a where the power transistor 32 is formed, and an upper region 31b where the NMOS transistor 3 and the PMOS transistor 4 for the control circuit are formed. And is composed of. The power transistor 32 in the lower region 31a and the NMOS transistor 3 and the PMOS transistor 4 in the upper region 31b are electrically connected by an Al wiring 5 (partially not shown). The power transistor 32 is an example of the “first transistor” in the present invention.

  The lower region 31a includes a sapphire substrate 40, an AlN layer 41 formed on the sapphire substrate 40, a GaN layer 42 formed on the AlN layer 41, and an AlGaN layer formed on the main surface 42a of the GaN layer 42. 43, a gate electrode 44 made of Ni, formed in a predetermined region on the AlGaN layer 43, a source electrode 45 and a drain electrode 46 made of Ti, and a gate electrode 44, a source electrode 45 and a drain electrode 46 made of Ti, respectively. A silicon nitride film 47 formed in a region where no gate electrode is formed, and a protective film 48 made of a silicon oxide film formed so as to cover the gate electrode 44, the source electrode 45, the drain electrode 46, and the silicon nitride film 47. Has been. The GaN layer 42, the AlGaN layer 43, the gate electrode 44, the source electrode 45 and the drain electrode 46 constitute a power transistor 32. The GaN layer 42 is an example of the “semiconductor layer” in the present invention, and the silicon nitride film 47 and the protective film 48 are examples of the “insulating layer” in the present invention.

  The AlN layer 41 has a thickness of about 20 nm. The AlN layer 41 functions as a buffer layer for low temperature growth. The GaN layer 42 has a thickness of about 2 μm. The AlGaN layer 43 has a thickness of about 25 nm. The GaN layer 42 and the AlGaN layer 43 form an AlGaN / GaN heterojunction.

  The lower surface of the gate electrode 44 is Schottky-bonded to the AlGaN layer 43, and the upper surface is connected to the Al wiring 5 via the Ti layer 6. The source electrode 45 and the drain electrode 46 are ohmic-bonded to the AlGaN layer 43 at the lower surface and connected to the Al wiring 5 at the upper surface.

  The silicon nitride film 47 has a thickness of about 100 nm. Further, the silicon nitride film 47 and the protective film 48 have insulating properties.

  Since the upper region 31b has the same structure as the upper region 1b of the first embodiment, the description thereof is omitted.

  10 to 13 are cross-sectional views for explaining a manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. A manufacturing process for the semiconductor device 31 according to the second embodiment of the present invention will now be described with reference to FIGS.

  First, as shown in FIG. 10, an AlN layer 41 is grown on a sapphire substrate 40 as a low-temperature growth buffer layer by about 20 nm by metal organic chemical vapor deposition. Then, a GaN layer 42 is grown on the AlN layer 41 by about 2 μm by metal organic chemical vapor deposition. Thereafter, an AlGaN layer 43 is grown on the main surface 42a of the GaN layer 42 by about 25 nm by metal organic chemical vapor deposition. At this time, an AlGaN / GaN heterojunction is formed.

  Then, after depositing Ti on the AlGaN layer 43, a part of the deposited Ti is removed by using a photolithography technique and a dry etching technique, thereby, as shown in FIG. A source electrode 45 and a drain electrode 46 made of Ti are formed in the region. At this time, the lower surfaces of the source electrode 45 and the drain electrode 46 are in ohmic contact with the AlGaN layer 43.

  Thereafter, a silicon nitride film 47 (see FIG. 9) is formed on the entire upper surface of the AlGaN layer 43 so as to cover the source electrode 45 and the drain electrode 46 by chemical vapor deposition. Then, as shown in FIG. 12, the silicon nitride film 47 on the source electrode 45 and the drain electrode 46 is removed by using a photolithography technique and a dry etching technique.

  Then, a region that becomes the gate electrode 44 (see FIG. 9) of the silicon nitride film 47 is removed by using a photolithography technique and a dry etching technique. At this time, part of the AlGaN layer 43 may be removed in order to control the threshold voltage of the power transistor 32.

  Then, after vapor-depositing Ni so as to embed a region to be the gate electrode 44 (see FIG. 9), a part of the deposited Ni is removed by using a photolithography technique and a dry etching technique, thereby obtaining the structure shown in FIG. Thus, the gate electrode 44 that is Schottky-bonded to the AlGaN layer 43 is formed. Thereby, the power transistor 32 is formed.

  Then, as shown in FIG. 9, in order to protect the power transistor 32, a protective film 48 is formed by chemical vapor deposition so as to cover the gate electrode 44, the source electrode 45, the drain electrode 46, and the silicon nitride film 47. Form.

  Thereafter, the upper region 31b (NMOS transistor 3 and PMOS transistor 4 and the like) and the Al wiring 5 are formed using the same manufacturing process as in the first embodiment.

  As described above, the semiconductor device 31 according to the second embodiment is manufactured.

  The other manufacturing processes of the second embodiment are the same as those of the first embodiment.

  In the second embodiment, as described above, the power transistor 32 (semiconductor device 31) can have a high breakdown voltage by forming the power transistor 32 in the GaN layer 42 having a band gap larger than that of silicon. At the same time, low power consumption (low on-resistance) can be achieved.

  The remaining effects of the second embodiment are similar to those of the aforementioned first embodiment.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the above-described embodiment, the example in which the semiconductor device is used as an electrical energy conversion device such as a DC / DC converter, an AC / DC converter, and a regulator IC has been described. However, the present invention is not limited thereto, and the electrical energy conversion is performed. It can also be applied to devices other than devices.

  In the above embodiment, an example in which the power transistor is formed in the semiconductor layer made of SiC or GaN has been described. However, the present invention is not limited to this, and the power transistor may be formed in the semiconductor layer made of diamond, GaAs, or the like. Good.

  In the above-described embodiment, the example in which the heat treatment for manufacturing the NMOS transistor and the PMOS transistor is performed at a temperature of about 600 ° C. has been described. However, the present invention is not limited to this and affects the characteristics of the power transistor. If not, the heat treatment in manufacturing the NMOS transistor and the PMOS transistor may be performed at a temperature higher than about 600 ° C.

  In the above embodiment, an example in which the semiconductor layer is formed of continuous grain boundary crystalline silicon has been described. However, the present invention is not limited thereto, and the semiconductor layer may be formed of polysilicon.

  In the first embodiment, the example in which the gate oxide film is formed on the upper surface of the SiC layer by the thermal oxidation method has been described. However, the present invention is not limited to this, and the silicon oxide film and the silicon oxide film are formed on the upper surface of the SiC layer. A stacked structure of O / N / O may be formed by stacking nitride films.

  In the above embodiment, an example in which a vertical power transistor is formed in a semiconductor layer has been described. However, the present invention is not limited thereto, and a horizontal power transistor may be formed in a semiconductor layer.

1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by 1st Embodiment of this invention shown in FIG. It is sectional drawing which showed the structure of the semiconductor device by 2nd Embodiment of this invention. FIG. 10 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. 9; FIG. 10 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. 9; FIG. 10 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. 9; FIG. 10 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. 9; It is sectional drawing which showed the package provided with the semiconductor device by an example of the past.

Explanation of symbols

1, 31 Semiconductor device 2, 32 Power transistor (first transistor)
3 NMOS transistor (second transistor)
4 PMOS transistor (second transistor)
5 Al wiring (wiring)
11 SiC layer (semiconductor layer)
11a Main surface 12 Gate oxide film (insulating layer)
14, 48 Protective film (insulating layer)
21 Silicon layer 42 GaN layer (semiconductor layer)
42a Main surface 47 Silicon nitride film (insulating layer)

Claims (8)

A semiconductor layer having a larger band gap than silicon and having the first transistor formed thereon;
A silicon layer formed in a predetermined region above the main surface of the semiconductor layer, a second transistor for a control circuit is formed, and is formed of a layer different from the semiconductor layer;
A semiconductor device comprising: a wiring for connecting the first transistor of the semiconductor layer and the second transistor of the silicon layer.   The semiconductor device according to claim 1, wherein the semiconductor layer includes SiC, GaN, or diamond.   The semiconductor device according to claim 1, wherein a protective film is formed between the semiconductor layer and the silicon layer.   The semiconductor device according to claim 1, wherein an insulating layer is disposed between the semiconductor layer and the silicon layer.   The said silicon layer is formed above the main surface of the said semiconductor layer after the heat treatment process at the time of forming the said 1st transistor in the said semiconductor layer, The any one of Claims 1-4 characterized by the above-mentioned. The semiconductor device according to item.   The semiconductor device according to claim 1, wherein the silicon layer is formed by a chemical vapor deposition method at a temperature of 600 ° C. or less.   The semiconductor device according to claim 1, wherein the silicon layer includes polysilicon or continuous grain boundary crystal silicon.   The semiconductor device according to claim 1, wherein the second transistor of the silicon layer has a CMOS structure.

Images