JP2001267320A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a passive element and a shield layer between the wiring layers of a multilayer wiring, where metal is embedded and to avoid cross talk with an active element formed on the upper face of a semiconductor substrate. SOLUTION: Passive elements, such as a capacitor, a resistor and an inductor, are formed on an upper wiring layer constituting the Cu wiring of multiple layers. A shield layer blocking electric and magnetic connection with the passive elements is formed in the lower wiring layer of the passive elements. Thus, the active element of a transistor can be arranged on the semiconductor substrate directory below the passive elements having a large occupying area without crosstalks. Thus, the degree of integration of the semiconductor device is improved markedly. At formation of the CU embedded multilayer wiring, the antireflection film of SiON and the like is used in common with a contact hole and the opening of a wiring groove. Thus, a highly reliable semiconductor device, which avoids generation of crowns at the peripheral part of the contact hole and has high yield and less man-hours, can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a metal-embedded wiring technology of a semiconductor device called a wiring, particularly, a capacitor, a resistor, a passive element such as an inductor, and a semiconductor device in which these shield layers are incorporated in a wiring layer of the metal-embedded multilayer wiring. The present invention relates to the manufacturing method.

[0002]

2. Description of the Related Art Conventionally, passive elements such as MIM (Metal-Insulator-Metal) type capacitors, resistors, and inductors have been widely used as components of semiconductor devices together with active elements such as transistors.

However, when these passive elements and active elements such as transistors are integrated on the same chip to improve the integration density, electrical and magnetic coupling between these passive elements and active elements is required. Has caused the problem of crosstalk. For this reason, an active element cannot be arranged immediately below the passive element, which has been a major obstacle to improvement in the integration density of the semiconductor device.

In particular, an inductor usually used for an analog circuit has a size of several hundred microns square and a large crosstalk due to magnetic induction. Therefore, a transistor cannot be arranged on a silicon substrate immediately below the inductor. Therefore, inductors are used in semiconductor devices consisting of analog circuits.
This hindered chip size reduction.

[0005] In addition, STI (Sha
For the resistor made of conductive polysilicon on the (llow Trench Isolation) region, the size of the polysilicon resistor due to the area of the STI, the variation in the resistance value due to the thermal process, and the increase in the number of processes Was a problem.

In order to improve the integration density of a semiconductor device, it is effective to introduce a metal-embedded multilayer wiring technology called a damascene wiring having excellent flatness. Has the following major technical problems.

That is, after removing the coating type anti-reflection film used for the opening of the contact hole, the metal-embedded multilayer wiring is formed by the conventional method of applying the anti-reflection film necessary for opening the wiring groove pattern again. If it is formed, there is a problem that the antireflection film applied when forming the wiring groove pattern enters the already opened contact hole.

At this time, if the resist film for forming the wiring groove is patterned and the anisotropic etching of the coating type anti-reflection film is performed, the coating type anti-reflection film covering the upper surface of the interlayer insulating film around the contact hole is removed. Can do it,
The coating type antireflection film covering the side wall of the contact hole cannot be sufficiently removed along the depth direction of the contact hole.

In such a state, if the anisotropic etching of the interlayer insulating film for forming the wiring groove is performed, the interlayer insulating film around the contact hole recedes, and as a result, the coating type reflective film covering the inner side wall of the contact hole is formed. The interlayer insulating film in contact with the prevention film remains, and a thin annular residue called a crown is formed. The formation of the crown not only hinders the embedding of the metal material but also causes dust. Referring to FIG. 5, the problem of crown generation in the conventional metal-embedded multilayer wiring technology will be specifically described.

[0010] As shown in FIG.
An interlayer insulating film 2 made of, for example, SiO ₂
A coating type antireflection film 30 is formed thereon. Here, the silicon substrate 1 may be a lower wiring layer. A resist 31 is applied on the coating type anti-reflection film 30 and is subjected to RIE (R)
A pattern of a contact hole to be formed in the interlayer insulating film 2 is opened using eactive ion etching).

Next, as shown in FIG. 5B, using the resist film 31 provided with the opening as a mask, the contact hole reaching the silicon substrate 1 through the coating type anti-reflection film 30 and the interlayer insulating film 2. Then, as shown in FIG. 5C, the coating type antireflection film 30 and the resist film 31 are both removed by ashing.

Next, as shown in FIG. 5D, a coating type anti-reflection film 30 and a resist film 31 are formed again on the interlayer insulating film 2 having the contact holes formed thereon in order to form a wiring groove pattern. The resist film 31 is applied, and a wiring groove pattern is opened in the resist film 31 by using the RIE method. At this time, the coating type anti-reflection film 30 covers not only the upper surface of the interlayer insulating film necessary for opening the wiring groove but also the inner wall of the contact hole.

Next, as shown in FIG. 5E, the coating type antireflection film 30 covering the interlayer insulating film 2 is removed by RIE using the resist film 31 provided with the opening of the wiring groove as a mask. At this time, the coating type antireflection film 30 covering the upper surface of the interlayer insulating film 2 is removed, but the coating type antireflection film 30 covering the inner wall of the contact hole remains without being removed.

Subsequently, if the anisotropic etching by RIE is continued using the resist film 31 provided with the opening of the wiring groove as a mask, as shown in FIG.
Are opened along the pattern of the wiring groove, but the coating type antireflection film 30 covering the inner wall of the contact hole is not removed and is left in a cylindrical shape, and the interlayer insulating film 2 in contact with the coating type antireflection film 30 is formed. Remain in a tapered shape without being etched.

Next, if the coating type antireflection film 30 and the resist film 31 are removed by ashing, as shown in FIG. 5 (g), the area around the opening of the contact hole formed at the bottom of the wiring groove is formed. The residue of the interlayer insulating film 2 called a crown is formed thinly and annularly.

In the metal-embedded multilayer wiring technique, a metal material such as Cu is buried in the wiring groove and the contact hole formed in the interlayer insulating film 2 by using an electroplating method. A metal film to be used as an electrode for electroplating must be sputtered or vapor-deposited on the inner wall of the contact hole to cover this.

However, if a residue called a crown is formed around the contact hole as described above, the metal film serving as an electrode for electroplating is interrupted at this portion, so that the inside of the contact hole is plated by plating. The buried metal cannot be formed sufficiently.

For this reason, it is extremely difficult to manufacture a semiconductor device including a metal-embedded multilayer wiring at a high yield in the related art. Therefore, the metal-embedded multilayer wiring technology is expected to improve the integration density of the semiconductor device. At present, the introduction to practical semiconductor devices has been greatly delayed.

[0019]

As described above, while it is considered promising to introduce a metal embedded multilayer wiring technology in order to improve the integration density of a semiconductor device, a practical semiconductor device is actually used. The introduction to the company was greatly delayed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and solves the problems in the manufacturing process included in the metal-embedded multilayer wiring technology to incorporate a passive element between wiring layers of the metal-embedded multilayer wiring. It is an object of the present invention to provide a high-density semiconductor device and a method of manufacturing the same by providing means for enabling the above-mentioned passive elements and avoiding crosstalk between these passive elements and active elements on a semiconductor substrate. .

[0021]

According to a semiconductor device and a method of manufacturing the same of the present invention, a passive element is formed between wiring layers of a metal-embedded multilayer wiring, and a shield layer is provided between the passive element and an active element on a semiconductor substrate. The crosstalk is prevented by forming the active element, and an active element is arranged immediately below these passive elements to realize a semiconductor device with high integration density.

Further, in order to enable a metal-embedded multilayer wiring suitable for a high-yield manufacturing method of a semiconductor device with a high integration density, an antireflection film such as SiON is commonly used for opening contact holes and wiring grooves. Used to avoid crown formation.

More specifically, a semiconductor device according to the present invention includes a passive element including a capacitor, a resistor, and an inductor formed on a semiconductor substrate, wherein the semiconductor device includes a metal-embedded multilayer wiring, The passive element is formed in an upper wiring layer of the metal-embedded multilayer wiring, and a shield layer formed on an upper surface of the semiconductor substrate to avoid crosstalk between the active element and the passive element is formed by the passive element. The wiring is formed on a wiring layer below the formed upper wiring layer.

Preferably, at least two of the electrode of the capacitor of the semiconductor device, the film resistance of the resistor, and the shield layer of the inductor are formed by dividing a continuous conductive layer made of the same conductive material. It is characterized by becoming.

Preferably, in the semiconductor device, the capacitor and the shield layer of the resistor and the inductor are formed by metal burying means similar to the metal buried multilayer wiring. The buried metal in the metal buried multilayer wiring is made of Cu.

Preferably, the shield layer of the semiconductor device is divided and disposed immediately below the inductor. Further, an active element of the semiconductor device is disposed immediately below the shield layer.

Preferably, in the metal-buried multilayer wiring of the semiconductor device, the anti-reflection film for opening a contact hole and the anti-reflection film for opening a wiring groove formed on the contact hole are the same. It is characterized by consisting of.

More preferably, in the semiconductor device, the continuous conductive layer made of the same conductive material includes
aN, TiAl, TiN, and WN. Further, the antireflection film is made of SiO.
N.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a first interlayer insulating film on a semiconductor substrate;
Forming a first metal buried wiring in the first interlayer insulating film, depositing a second interlayer insulating film on the first interlayer insulating film, and forming a second metal in the second interlayer insulating film. Forming a buried interconnect, depositing a third interlayer insulating film on the second interlayer insulating film, and forming a third metal buried interconnect in the third interlayer insulating film. In the method of manufacturing a semiconductor device, the step of forming the first buried metal wiring includes a step of forming a buried metal shield layer forming a part of the first buried metal wiring, and the step of forming the second buried metal wiring comprises: Forming at least any two of the electrode of the capacitor, the film resistance of the resistor, and the shield layer of the inductor by forming a continuous conductive layer made of the same conductive material. , The third Forming a genus buried wiring
The method includes a step of forming a metal-buried inductor that forms a part of the third metal-buried wiring.

In the method of manufacturing a semiconductor device, the step of forming the metal buried wiring layer includes the steps of depositing an interlayer insulating film on the semiconductor substrate, depositing an anti-reflection film on the interlayer insulating film, Applying a first resist film on the anti-reflection film, forming a contact hole pattern in the resist film, etching the anti-reflection film using the first resist film as a mask, A step of etching the interlayer insulating film using a first resist film and the antireflection film as a mask, a step of removing the first resist film, and a step of applying a second resist film on the semiconductor substrate Forming a wiring groove pattern in the second resist film, etching the antireflection film using the second resist film as a mask, An etching step of forming a wiring groove shallower than the thickness of the interlayer insulating film in the interlayer insulating film using the second resist film and the anti-reflection film as a mask; and removing the second resist film; Embedding a metal material in the contact hole and the wiring groove.

Preferably, the method for manufacturing a semiconductor device comprises:
A step of applying an antireflection film on the interlayer insulating film is included instead of the step of depositing the antireflection film on the interlayer insulating film.

Preferably, the method for manufacturing a semiconductor device further comprises a step of removing the anti-reflection film subsequent to the step of removing the second resist film.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are cross-sectional views showing a structure of a semiconductor device according to a first embodiment of the present invention and a method of manufacturing the same. First, the structural features of the semiconductor device according to the first embodiment will be described.

The main parts of the semiconductor device according to the first embodiment are a Cu-embedded (damascene) multilayer wiring formed on a semiconductor substrate and a Cu-embedded multilayer wiring formed in a first wiring layer of the Cu-embedded multilayer wiring. The Ta layer formed on the shield layer and the second wiring layer above the Cu-embedded shield layer
A capacitor made of N / Ta ₂ O _{5 /} TaN and a metal film resistor having a film of TaN, the TaN shield layer formed on the second wiring layer, and a third wiring layer above the TaN shield layer. It comprises an inductor formed using the formed Cu embedded wiring, and active elements on a semiconductor substrate such as a transistor, which are respectively disposed immediately below each shield layer made of Cu and TaN.

Next, referring to the sectional views shown in FIGS.
The configuration of the semiconductor device according to the embodiment will be described in detail in the order of manufacturing steps. As shown in FIG. 1A, a silicon substrate 1 on which active elements such as transistors (not shown) are formed.
A Cu-embedded shield layer 3 is formed by applying the Cu-embedded multilayer wiring technology of the present invention to the first wiring layer on the first interlayer insulating film 2 covering the first interlayer insulating film 2. The Cu-embedded multilayer wiring technology of the present invention will be described in detail in a second embodiment.

A second interlayer insulating film 4 is formed so as to cover the Cu-embedded shield layer, and the second interlayer insulating film 4 on the second interlayer insulating film 4 is again formed by using the Cu-embedded multilayer wiring technique of the present invention.
A contact hole 5 for connecting the first and second wiring layers to the wiring layer, a Cu buried pad 6, and a Cu buried wiring 7 are formed, and the surfaces thereof are polished by CMP (Chemical Mechanic).
al polishing). Here, the Cu buried pad is a pad for directly connecting between contact holes in a direction perpendicular to the semiconductor substrate. For example, the Cu buried pad is perpendicular to the paper surface like a Cu buried wiring 7 shown in FIG. It is different from the wiring extending in the direction.

Next, as shown in FIG. 1B, a TaN film is deposited by sputtering and patterned to form a TaN electrode 8 forming one electrode of the capacitor so as to be connected to the Cu embedded wiring 7. . Subsequently, as shown in FIG. 1C, a Ta ₂ O ₅ film 9 serving as a dielectric film of the capacitor and a TaN film 10 are stacked and deposited so as to cover the TaN electrode 8 by using the sputtering method.

Next, as shown in FIG. 2D, the Ta ₂ O ₅ film 9 / TaN film 10 deposited on the upper surface of the second interlayer insulating film 4.
By patterning the laminated film made of Ta ₂ O ₅ film 9a /
The TaN film 10a and the TN in the TaN resistor forming region are formed.
a ₂ O ₅ film 9 b / TaN film 10 b, Cu embedded wiring 14 forming an inductor shown in FIG.
It is divided into three regions of the Ta ₂ O ₅ film 9c / TaN film 10c in the formation region of the TaN shielding layer for shielding between.

Subsequently, the nitride film 11 and the third film are formed so as to cover the three divided TaN films 10a, 10b and 10c.
The interlayer insulating film 12 is laminated, and the surface is flattened by CMP polishing.

Next, the TaN films 10a, 10b, 10b, 10b formed on the second wiring layer are connected through Cu embedded contact holes penetrating the nitride film 11 and the third interlayer insulating film 12.
A Cu buried pad and a Cu buried wiring of the third wiring layer connected to 10c are formed. Here, the Cu buried interconnect of the third layer includes an inductor composed of the Cu buried interconnect 14, as shown in the cross-sectional view of FIG.

As described above, the third interlayer insulating film 12 including the inductor is polished by CMP, a fourth interlayer insulating film 13 is deposited thereon, and the Cu interlayer buried contact hole formed in the third interlayer insulating film 12 is used. The embedded Cu pad and the embedded Cu wiring of the third wiring layer are connected to the embedded Cu pad and the Cu embedded wiring of the fourth wiring layer formed on the upper surface of the fourth interlayer insulating film 13. At this time, the Cu
Cu embedded lead wires 15 and 16 of the inductor including the embedded wiring 14 are connected to the inductor.

In the manufacturing process described above, FIG.
As shown in (1), the Cu-embedded shield layer formed in the first wiring layer on the first interlayer insulating film 2 forms a direct contact for directly connecting the Cu-embedded contact hole 5 and the Cu-embedded pad 6 directly to the upper part. Then, it is pulled out to the upper surface of the fourth interlayer insulating film 13 and grounded.

Similarly, the TaN shield layer 10c formed on the second wiring layer on the second interlayer insulating film 4 is
Connected to the TaN shield layer 10c
Fourth interlayer insulating film 1 through a direct contact consisting of a u-buried contact hole and a Cu-buried pad
3 is pulled out to the upper surface and grounded. The fourth wiring layer formed on the upper surface of the fourth interlayer insulating film 13 is covered with a passivation film (not shown) made of a nitride film or the like.

In the semiconductor device according to the first embodiment shown in FIG. 2E, a multilayer wiring and a contact hole are formed using an inexpensive and highly conductive Cu-embedded multilayer wiring, a capacitor and a resistor. And a transistor (not shown) formed on the semiconductor substrate is characterized in that the Cu buried shield layer 3 is formed by using a Cu buried wiring technique in the first wiring layer.

Further, since the electrode of the capacitor and the conductive film of the resistor are formed of TaN, leakage current of a transistor or the like due to diffusion of Cu having a large diffusion coefficient in an insulating film such as SiO ₂ can be reduced. Since the diffusion is suppressed by the diffusion prevention film, a highly reliable semiconductor device can be obtained.

In a conventional resistor made of conductive polysilicon on an STI region, the size of the polysilicon resistor is limited due to the area of the STI, the resistance value is varied due to a heat process, and the number of processes is small. All of these problems can be solved by using TaN, which forms one electrode of the capacitor, as the conductive film of the resistor.

For example, regarding the limitation on the size of the resistor, the area of the TaN conductive film of the resistor adjacent to the capacitor is made sufficiently large, and is patterned and trimmed, so that the resistance value can be adjusted with high precision. can do. Another significant advantage is that the temperature coefficient of the resistance value is smaller than that of the conventionally used conductive polysilicon.

The semiconductor device according to the first embodiment shown in FIG. 2E further includes one electrode 10a of the capacitor and a part of the TaN film forming the conductive film 10b of the resistor, the inductor and the semiconductor substrate. It is characterized in that it is used as a TaN shield layer 10c between the upper transistor.

The TaN films 10a, 10b,
10c is further covered with a nitride film 11 in order to prevent Cu diffusion from the Cu embedded wiring, and an inductor composed of the Cu embedded wiring 14 is formed on the interlayer insulating film 12 covering the nitride film 11.

The current flowing through the Cu buried wiring 14 forming the inductor is applied to the TaN shield layer 10c by magnetic induction.
In order to avoid this, the TaN shield layer 10c is patterned and divided, or a slit or the like is provided so as to prevent the image current. If the pattern shape of the TaN shield layer 10c is optimized in this way, a sufficient shield effect can be obtained without lowering the Q value of the inductor 14.

It is desirable that both the Cu embedded shield layer 3 and the TaN shield layer 10c have a small coupling capacitance with a passive element. Minimization must be considered at the same time.

As described above, one electrode 10 of the capacitor
a, a conductive film 10b of a resistor and a TaN shield layer 1
0c is required to have a high electrical conductivity, to prevent diffusion of Cu, and to have a small temperature coefficient. As well as TaN, TiAl, T
A film made of an intermetallic compound such as iN or WN can be used.

Incidentally, an inductor usually used in an analog circuit has a size of about 100 μm square, which has hindered a reduction in chip size in the analog circuit.
However, when forming an analog / digital hybrid semiconductor device including a logic circuit having more wiring layers than an analog circuit, if the TaN shield layer 10c is provided in a vacant wiring layer below the inductor. Since crosstalk is avoided and a large number of active elements such as transistors can be arranged on the semiconductor substrate immediately below the large inductor, the integration density of the semiconductor device can be greatly improved.

FIG. 3 is a cross-sectional view for easily explaining how the Cu embedded wiring technique (damascene wiring) is used in the semiconductor device of the first embodiment shown in FIG. It is. As shown in FIG. 3, a diffusion layer 1 having a high impurity concentration, for example, one of a source / drain region of a transistor is formed on a semiconductor substrate 1.
The case where a is formed and a Cu-embedded multilayer wiring is connected to the diffusion layer 1a will be described.

The first interlayer insulating film 2 is deposited on the upper surface of the semiconductor substrate 1, and for example, a concave portion of the Cu buried pad 6 is formed. Further, a contact hole 5 reaching the diffusion layer 1a is opened in the bottom of the concave portion of the Cu embedded pad 6. Next, for example, a TaN film is thinly sputtered so as to cover the concave portion of the Cu embedded pad 6 and the inner surface of the contact hole 5 and the surface of the first interlayer insulating film 2 so as to become a plating electrode in the Cu embedded plating process. .

Next, if the TaN film is used as a cathode and a Cu filling plating step is performed, the contact hole 5 and the concave portion 6 are filled with Cu, and Cu is deposited on the upper surface of the first interlayer insulating film 2 at the same time. By removing Cu on the surface of the first interlayer insulating film 2 by CMP polishing and flattening the surface, a Cu embedded pad 6 formed on the first Cu embedded wiring layer on the first interlayer insulating film 2 and a semiconductor substrate The upper diffusion layer 1a is connected via a Cu embedded contact hole.

Next, a wiring groove 14 (a vertical cross section of the wiring groove is shown) is opened in the second Cu buried wiring layer forming region on the second interlayer insulating film 4, and the Cu buried is formed at the bottom of one end. A contact hole connected to the pad 6 is opened. Subsequently, Cu is buried by electroplating in the same manner as described above, and the surface is planarized by CMP polishing.

Next, the third Cu on the third interlayer insulating film 12 is formed.
A wiring groove 15 (the cross section of the wiring groove is shown) is opened in the buried wiring layer formation region, and a contact hole 5 connected to the other end of the Cu buried wiring 14 is opened at the bottom of one end. Subsequently, Cu plating is performed in the same manner as described above by electroplating.
And polished by CMP to flatten the surface. By repeating the above operation, a Cu-embedded multilayer wiring connected to the active element on the semiconductor substrate can be formed.

In FIG. 3, the diffusion layer 1a on the semiconductor substrate
A case has been described in which a direct contact including a Cu buried pad 6 is formed thereon, but the same operation can be performed even if the Cu buried pad is replaced with a Cu buried wiring.

In the semiconductor device of the first embodiment shown in FIG. 2E, a Cu-embedded multilayer wiring as shown in FIG. 3 is used entirely. That is, a Cu-embedded shield layer is formed as a part of the first Cu-embedded wiring layer.
After the planarization of the interlayer insulating film, a step of laminating a TaN film and a Ta ₂ O ₅ film for forming a shield layer of the capacitor, the resistor and the inductor is included, and the Cu embedded inductor is formed as a part of the third Cu embedded wiring layer. Is formed.

Since the passive element and the shield layer of the semiconductor device are formed so as to be incorporated in the Cu-embedded multilayer wiring, for example, the shield layer of the inductor can be partially connected to the second Cu-buried wiring layer without increasing the number of steps. It is also possible to form as.

As described above, in a semiconductor device using a Cu-embedded multilayer wiring over the entire surface, extremely high reliability is required for the connection between the Cu-buried wiring layers by a large number of Cu-embedded contact holes.

As described above, since a residue called a crown is conventionally formed at a connection point between a Cu-buried wiring and a Cu-buried contact hole, it is necessary to manufacture a semiconductor device including a Cu-buried multilayer wiring at a high yield. Could not.

Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. In the second embodiment, a description will be given of a Cu buried interconnect technology which eliminates the problem of crown generation and provides the semiconductor device described in the first embodiment with a high yield. The Cu embedded wiring technology shown in FIG. 4 is characterized in that an SiON film having a function as an antireflection film is used instead of the coating type antireflection film described above with reference to FIG.

As shown in FIG. 4A, the silicon substrate 1
An interlayer insulating film 2 is formed thereon, and a SiON antireflection film 20 is deposited thereon. A resist film 21 is applied on the SiON antireflection film 20 to form an opening of a contact hole. Here, the silicon substrate 1 may be a lower wiring layer.

Next, as shown in FIG. 4B, the SiON antireflection film 20 and the interlayer insulating film 2 are anisotropically etched by RIE using the resist film 21 as a mask until the silicon nitride film 1 reaches the silicon substrate 1. The resist film 21 is removed.

In the conventional resist film 31 removing step described with reference to FIG. 5C, the antireflection film 30 is simultaneously removed in the resist film 31 removing step. In the step of removing the film 21, the anti-reflection film 20 is made of a SiON film and is not removed, as shown in FIG.
Remain as shown in FIG.

Next, as shown in FIG. 4D, a resist film 21 is applied again on the interlayer insulating film 2 and the SiON antireflection film 20 in which the contact holes are opened, and a region for forming a wiring groove is formed. Open. In this step, the resist film embedded in the contact hole is removed.

Next, by performing anisotropic etching by RIE under the etching conditions for the SiON anti-reflection film 20, the SiON anti-reflection film 20 covering the upper surface of the interlayer insulating film 2 is removed as shown in FIG. Is done. Continue with Si
If the anisotropic etching by RIE is performed while switching to the etching condition for O ₂ , a wiring groove can be formed in the interlayer insulating film 2.

In the process of forming the wiring groove, conventionally, FIG.
As shown in (f), the coating type anti-reflection film left on the inner wall of the contact hole causes the formation of the crown. However, in the wiring groove forming step in the second embodiment, the contact hole is formed. Since no anti-reflection film is present on the inner wall of the device, no crown is generated.

Next, as shown in FIG. 4G, by removing the resist film 20, a structure in which a contact hole is opened without forming a crown at the bottom of the wiring groove can be formed in the interlayer insulating film 2. it can. Subsequently, a plating electrode made of, for example, TaN is sputtered on the entire surface, Cu is buried by electroplating, and Cu deposited on the upper surface of the interlayer insulating film 2 is replaced with C.
If it is removed by MP, the required Cu embedded double groove wiring (Dua
l Damascene) wiring structure can be formed.

The Cu planarized by the CMP polishing as described above
By depositing an interlayer insulating film on the buried double groove wiring and repeating the same steps, the wiring layers can be easily multilayered.

The Cu-embedded multilayer wiring thus formed has no crown around the contact hole connecting each wiring layer, and is formed by electroplating in a state where the contact hole and the wiring groove are completely integrated. Since Cu is buried, the reliability of connection of the contact holes connecting the respective wiring layers is extremely high.

Since the wiring groove can be patterned into an arbitrary planar shape, the wiring groove is used to form the Cu buried shield layer 3 shown in FIG.
The embedded wiring 14 can be formed at the same time as the Cu embedded wiring of the corresponding wiring layer without any additional step.

The present invention is not limited to the above embodiment. For example, in the first embodiment,
A case has been described in which a Cu embedded shield layer is formed in the first wiring layer, a capacitor, a resistor, and a TaN shield layer are formed in the second wiring layer, and an inductor is formed in the third wiring layer. If it is formed in a lower layer of the element, it can be similarly carried out for other combinations of different wiring layers.

In the second embodiment, the SiON film is used as the anti-reflection film remaining on the upper surface of the interlayer insulating film even after the opening of the contact hole. In the step of removing the resist film used in the opening process, if the anti-reflection film remains on the upper surface of the interlayer insulating film without deterioration of the material,
It can be used similarly to the SiON film. In addition, various modifications can be made without departing from the spirit of the present invention.

[0077]

As described above in detail, according to the present invention, (1) a passive element such as a capacitor, a resistor, and an inductor is formed in an upper wiring layer constituting a Cu-embedded multilayer wiring; By forming a shield layer for blocking electrical and magnetic coupling in the lower wiring layer of the above, on the semiconductor substrate immediately below the passive element having a large occupation area,
Since active elements such as transistors can be arranged without crosstalk, the degree of integration of a semiconductor device including an analog circuit and an analog / digital mixed circuit can be greatly improved.

(2) Since the inductor and the shield layer are formed by using the Cu-embedded multilayer wiring technique, the inductor and the shield layer can be incorporated into the wiring layer of the Cu-embedded multilayer wiring without any additional steps. Can be.

(3) As a conductive material constituting the electrode of the capacitor, the resistive film of the resistor, and the shield layer, for example, TaN, TiAl, TiN, WN and the like have a barrier effect against Cu diffusion in the interlayer insulating film. Since a certain device is used, it is possible to reduce the number of steps, to avoid the occurrence of a leak current in the passive element and the active element of the semiconductor device due to Cu diffusion, and to greatly improve the reliability of the semiconductor device including the Cu embedded wiring. it can.

(4) By using these conductive materials as the film resistance of the resistor, the temperature coefficient of the resistance value is small, and the variation in the resistance value due to the heat process and the increase in the number of steps can be reduced. Also, compared with the conventional method of providing a resistor made of conductive polysilicon on the STI region,
Since the resistor can be formed in an arbitrary wiring layer between the interlayer insulating films, the resistance value can be accurately controlled by freely selecting the size and shape of the resistor.

(5) When these conductive materials are used as a shield layer of an inductor, if the shape of the shield layer is divided by slits or the like is optimized so as to reduce the loss due to the image current, it is possible to reduce the loss on the semiconductor substrate. In addition, the Q value of the inductor can be increased while avoiding crosstalk to the active element. Such optimization of the shape of the shield layer can be similarly performed when, for example, a Cu embedded shield layer is used as a shield layer of the inductor.

(6) In forming the Cu-embedded multilayer wiring used in the semiconductor device of the present invention, the SiON antireflection film used for forming the contact hole in the interlayer insulating film is used as it is for the formation of the wiring groove. In addition, the formation of a crown around the contact hole can be avoided, and a film such as TaN serving as a Cu embedded plating electrode can be uniformly sputtered on the inner surface of the opening of the contact hole and the wiring groove. At the same time that the Cu embedding in the wiring groove is integrated, the TaN film has a barrier effect of Cu diffusion, so that it is possible to provide a semiconductor device having a high yield, a small number of steps, and a high reliability. .

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure and a manufacturing process of a semiconductor device according to a first embodiment.

FIG. 2 is a sectional view showing the structure of the semiconductor device according to the first embodiment and a continuation of the manufacturing process;

FIG. 3 shows a multilayer Cu of the semiconductor device according to the first embodiment;
Sectional drawing of an embedded wiring.

FIG. 4 is a sectional view showing a method for forming a contact hole and a wiring groove according to a second embodiment;

FIG. 5 is a cross-sectional view showing a conventional method for forming a contact hole and a wiring groove.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2, 4, 12, 13 ... Interlayer insulating film 3 ... Cu buried shield layer 5 ... Cu buried contact hole 6 ... Cu buried pad 7, 14 ... Cu buried wiring 8 ... TaN electrode 9, 9a, 9b, 9c ... Ta ₂ O ₅ film 10,10a, 10b, 10c ... TaN film 11 ... nitride films 15 and 16 ... inductor Cu embedded lead wire 20 ... SiON antireflection film 21, 31 ... resist film 30 ... coating-type antireflection film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 P (72) Inventor Masahiro Inohara 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Toshiba Yokohama In-house F-term (reference) 5F033 HH11 HH32 JJ11 JJ32 KK11 KK32 MM01 NN01 NN37 NN38 NN39 PP15 PP27 QQ04 QQ13 QQ37 QQ48 RR06 RR08 SS21 TT01 VV03 VV08 VV09 VV10 XX23 AR05 AC10 AR05 AC05 AR05 AC05

Claims (13)

[Claims] A capacitor formed on a semiconductor substrate;
In a semiconductor device including a resistor and a passive element including an inductor, the semiconductor device includes a metal-embedded multilayer wiring, wherein the passive element is formed on an upper wiring layer of the metal-embedded multilayer wiring, and A semiconductor device, wherein a shield layer for avoiding crosstalk between the formed active element and the passive element is formed in a wiring layer below the upper wiring layer on which the passive element is formed. 2. A method according to claim 1, wherein at least any two of the electrode of the capacitor, the film resistance of the resistor, and the shield layer of the inductor are formed by dividing a continuous conductive layer made of the same conductive material. The semiconductor device according to claim 1, wherein: 3. The shield layer of the capacitor and the resistor,
2. The semiconductor device according to claim 1, wherein the inductor is formed by metal burying means similar to the metal buried multilayer wiring. 4. The semiconductor device according to claim 1, wherein the buried metal in the metal buried multilayer wiring is made of Cu. 5. The semiconductor device according to claim 1, wherein the shield layer of the inductor is divided and arranged immediately below the inductor. 6. The semiconductor device according to claim 1, wherein an active element of the semiconductor device is disposed immediately below the shield layer.
13. The semiconductor device according to claim 1. 7. The metal-embedded multilayer wiring, wherein an antireflection film for opening a contact hole and an antireflection film for opening a wiring groove formed on the contact hole are formed of the same antireflection film. 2. The semiconductor device according to claim 1, wherein 8. The semiconductor device according to claim 2, wherein the continuous conductive layer made of the same conductive material is made of any one of TaN, TiAl, TiN, and WN. 9. The semiconductor device according to claim 7, wherein said antireflection film is made of SiON. 10. A step of forming a first interlayer insulating film on a semiconductor substrate; a step of forming a first metal buried wiring in the first interlayer insulating film; A step of depositing a second interlayer insulating film, a step of forming a second metal buried interconnect in the second interlayer insulating film, and depositing a third interlayer insulating film on the second interlayer insulating film And a step of forming a third metal buried wiring in the third interlayer insulating film. The step of forming the first metal buried wiring comprises: Forming a metal buried shield layer forming a part of the buried wiring, wherein the step of forming the second metal buried wiring comprises at least one of an electrode of a capacitor, a film resistance of a resistor, and a shield layer of an inductor. Either two A step of forming a continuous conductive layer made of the same conductive material by dividing, and forming the third buried metal wiring, wherein the step of forming the third buried metal wiring comprises: A method for manufacturing a semiconductor device, comprising a step of forming. 11. The method of manufacturing a semiconductor device,
The step of forming the metal buried wiring layer includes: a step of depositing an interlayer insulating film on the semiconductor substrate; a step of depositing an antireflection film on the interlayer insulating film; A step of applying; a step of forming a contact hole pattern in the resist film; a step of etching the anti-reflection film using the first resist film as a mask; Etching the interlayer insulating film using the mask as a mask, removing the first resist film, applying a second resist film on the semiconductor substrate, and forming a wiring groove in the second resist film. Forming a pattern; etching the anti-reflection film using the second resist film as a mask; and forming the second resist film and the anti-reflection film. An etching step of forming a wiring groove shallower than the thickness of the interlayer insulating film in the interlayer insulating film as a mask; a step of removing the second resist film; and a metal material in the contact hole and the wiring groove. The method of manufacturing a semiconductor device according to claim 10, further comprising: embedding. 12. The semiconductor device according to claim 11, wherein a step of applying an antireflection film on said interlayer insulating film is included in place of the step of depositing an antireflection film on said interlayer insulating film. Manufacturing method. 13. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of removing the anti-reflection film after the step of removing the second resist film.