JP2001223325A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simply reliably connect in continuity between the insulating boards by visually confirming a connecting state of laminated semiconductor devices to easily inspect it, and reducing number of component of the device to simplify its constitution. SOLUTION: The semiconductor device comprises a plurality of insulating boards 10 for mounting electronic components 12 and sequentially laminated. The device further comprises first conductive wirings 11 projected from a peripheral edge of the respective boards 10 to be formed by bending in a predetermined shape, and second conductive wirings 11 projected from a peripheral edge of an uppermost or lowermost layer of the laminated boards 10 to be formed and extended to the board 10 of the lowermost or uppermost layer. In this case, the first and second boards 10 are connected in continuity at the peripheral edges.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of insulating substrates on which electronic components are mounted are sequentially laminated, and more particularly, to a conductive wiring which is bent at the periphery of each insulating substrate. Of these, it is preferable to apply the present invention to a semiconductor device which is electrically connected to the periphery of the insulating substrate by a conductive wiring extending from the uppermost layer to the lowermost layer or from the lowermost layer to the uppermost layer.

[0002]

2. Description of the Related Art In recent years, electronic equipment has been becoming lighter, thinner and smaller, and high-performance integration and high-speed signal processing have been advanced. Along with this, the shape of the semiconductor device is changed from a shape in which lead terminals, which are conductive wiring, are drawn out from the side surface of a package such as a QFP (Quad Flat Package) in a gull wing shape, for example, a BGA (Ball Grid Arra).
By forming electrodes using gold bumps or the like on the lower surface side of the package as shown in y), etc., the area occupied by the semiconductor device when mounting such a semiconductor device on a motherboard is significantly reduced. It is shifting to a shape that can be transformed.

[0003] As a semiconductor device further downsized than the BGA, for example, a semiconductor chip as an electronic component is mounted on a rigid substrate or the like as an insulating substrate made of ceramics by a method such as a flip chip mounting method. CSP (Chip Size Package) is attracting attention.

[0004]

However, according to the above-described conventional semiconductor device, it is difficult to reduce the area occupied by one such semiconductor device on the mother substrate by reducing the size of the package. Although it is possible, the number of mounting semiconductor devices mounted on the motherboard has been increasing along with the recent addition of new functions to electronic equipment. Was.

In such a semiconductor device, not only the mother substrate becomes large, but also the length of the lead terminals from the main semiconductor device to other semiconductor devices becomes extremely long. This results in distortion, an increase in power consumption, and the like, resulting in inconvenience that it is difficult to obtain predetermined electrical performance. Particularly, in the case of a media device having a high-speed and large-capacity circuit system, reducing the lead terminal length has been an important issue.

Further, even if the mother board is reduced in size, the number of semiconductor devices that can be mounted on a mounting area for one semiconductor device on the mother board is one. There is also a risk of limiting the number of semiconductor devices to be obtained.

As one method for solving such a problem,
Conventionally, for example, JP-A-10-223683, JP-A-63-6115
No. 0 and Japanese Patent Application Laid-Open No. 7-106509, etc., provide wiring, solder balls, inner leads, via holes, through holes, and the like on an insulating film or an insulating sheet on which a semiconductor chip is mounted. Insulating films and insulating sheets are sequentially laminated, and wiring, solder balls, inner leads,
There have been proposals for conductive connection via via holes and through holes.

However, in this case, it is difficult to visually confirm the connection state between the insulating films and the insulating sheets, and it is necessary to seal a part or the whole of the laminated insulating films and the insulating sheets with a resin. For this reason, it is difficult to repair even if some defects occur, and there is still an insufficient problem.

Further, as disclosed in Japanese Patent Application Laid-Open No. 7-14979, etc., a leadless chip carrier on which a semiconductor memory is mounted is sequentially stacked in a mounting case via an insulating sheet. There has also been proposed a carrier that is electrically connected to a carrier such that an end face through-hole electrode formed on a side surface thereof contacts a signal line in a mounting case.

However, even in this case, it is difficult to visually confirm the connection state between the stacked chip carriers, and a mounting case and signal lines inside the chip case are separately required to connect the chip carriers. Therefore, the number of parts increases, the configuration becomes complicated, and there is still an insufficient problem.

Accordingly, a first object of the present invention is to provide a semiconductor device in which the connection state between stacked semiconductor devices is visually checked and easily inspected, and the configuration is simplified by reducing the number of parts of the semiconductor device. Thus, the present invention is to easily and reliably conduct conductive connection between the laminated insulating substrates.

A second object is to prevent the conductive wiring from bending when one end of the conductive wiring is connected to the electrode of the electronic component.

A third problem is to stably stack a plurality of insulating substrates on which electronic components are mounted, and a fourth problem is to prevent the stacked insulating substrates from collapsing before conducting connection. It is to prevent.

A fifth problem is to prevent a plurality of conductive wirings from being separated, and a sixth problem is to stack a plurality of insulating substrates on which electronic components are mounted when stacking the plurality of insulating substrates. In order to simplify the positioning of the device.

A seventh object is to be able to withstand stress concentration generated between conductive wires at corners of each insulating substrate due to internal strain caused by heat at the time of conductive connection.

An eighth object is to form alignment marks for positioning without increasing the number of parts, and a ninth object is to easily form alignment marks for positioning.

[0017]

According to a first aspect of the present invention, there is provided a semiconductor device in which a plurality of insulating substrates on which electronic components are mounted are sequentially laminated to achieve the first object. One conductive wiring projecting from the peripheral portion of each insulating substrate, and being formed by bending into a predetermined shape, and projecting from the peripheral portion of the uppermost layer or the lowermost layer of the laminated insulating substrates, and forming the lowermost layer or the uppermost layer. And two conductive wirings extending to the insulating substrate, wherein the first and second insulating substrates are electrically connected at the peripheral edge.

According to a second aspect of the present invention, in order to achieve the second object, the electronic component is flip-chip mounted on one surface of each insulating substrate.

According to a third aspect of the present invention, in order to achieve the third object, a plurality of insulating substrates to be laminated are sequentially mounted on adjacent lower electronic components. I do.

According to a fourth aspect of the present invention, in order to achieve the fourth object, an adjacent insulating substrate and an electronic component are interposed with an adhesive.

According to a fifth aspect of the present invention, in order to achieve the above-mentioned fifth object, a plurality of 1 and 2 conductive wirings are arranged and arranged on a corresponding insulating substrate, respectively, and up to an uppermost layer or a lowermost layer. It is characterized in that a dispersion preventing member for bundling these two conductive wirings is provided at the end of the two conductive wirings extending.

According to a sixth aspect of the present invention, in order to achieve the sixth object described above, each of the insulating substrates has, at four corners thereof, positioning projections for laminating these insulating substrates. Features.

According to a seventh aspect of the present invention, in order to achieve the seventh object, one of the first and second conductive wires is wider than the other conductive wires at the corners. , Characterized by the following.

According to an eighth aspect of the present invention, in order to achieve the eighth object, an alignment mark for positioning is formed on a wide conductive wiring.

According to a ninth aspect of the present invention, in order to achieve the ninth object, the alignment mark is formed of a round hole.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 1 and 2 are an external perspective view and a vertical sectional view of a semiconductor device according to the present invention. In the illustrated semiconductor device, for example, an adhesive such that an insulating substrate 10 on which a semiconductor chip 12 such as an IC or an LSI, which is an electronic component, is mounted is superimposed on the lower semiconductor chip 12 in order. And laminated. Also,
On the other surface side of the lowermost insulating substrate 10 of the semiconductor device, electrodes 10A for electrically connecting the semiconductor device to a mother substrate or the like are arranged in a predetermined arrangement.

The insulating substrate 10 is made of glass epoxy, polyimide, or the like. A conductive wiring 11 is disposed on one surface of the insulating substrate 10 in a predetermined pattern. One end 11A of the conductive wiring 11 has an electrode 12A of the semiconductor chip 12. Are mounted by a flip chip mounting method or a TAB method to form modules MO1 to MO4, respectively.

The other end portion 11B of the conductive wiring 11 of each insulating substrate 10 of the semiconductor device having such a multilayer module structure protrudes at the peripheral edge of the insulating substrate 10 and, for example, Is formed so as to be bent downward toward the other surface side.

On the other hand, the other end 11 of the conductive wiring 11 of the uppermost insulating substrate 10 as shown in FIG. 3 or the lowermost insulating substrate 10 as shown in FIG.
B is formed so as to protrude at the peripheral edge of the insulating substrate 10 and extend to the other end 11B of the corresponding lowermost or uppermost conductive wiring 11.

In this semiconductor device, the other end 11B of the conductive wiring 11 of each of the insulating substrates 10 and the other end 11B of the conductive wiring 11 of the uppermost or lowermost insulating substrate 10 are connected to each other. The semiconductor device is electrically connected at a peripheral portion of the semiconductor device.

In the case of this embodiment, conductive wiring 1 extending from insulating substrate 10 in the uppermost or lowermost layer is used.
At the tip of the other end 11B of the first unit 1A, there is provided an anti-separation member 13 made of, for example, the same material as that of the insulating substrate 10 for bundling the conductive wirings 11. The wiring 11 has a structure in which each wiring 11 is fixed so as to have a constant pitch accuracy.

In order to form such a laminated structure, the module MO1 in which the semiconductor chip 12 is mounted on the insulating substrate 10,
MO2, MO3, MO4 are sequentially formed on the upper insulating substrate 10;
After laminating the semiconductor chip 12 one layer below via an adhesive, the conductive wires 11 of each layer are sequentially joined in the vertical direction to complete the electrical connection between the layers. At this time, in the semiconductor chips 12 of the modules MO1 to MO3, the electrodes of the semiconductor chips 12 and the conductive wires 11
Is sealed with a sealing resin FJ made of an insulating material or the like.

By stacking the modules MO1 to MO4, the leading ends of the conductive wirings 11 sequentially bent from the uppermost insulating substrate 10 are connected to the insulating substrate 10 in the next lower layer.
It comes into contact with the upper surface of the upper conductive wiring 11. Then, the contacting conductive wires are joined by soldering, a conductive paste material, welding, or the like.

As described above, in this semiconductor device, the respective semiconductor chips 12 are electrically connected to each other sequentially through the conductive wirings 11 of the respective insulating substrates 10, and are connected to the mother substrate via the lowermost electrodes 10 A. It is configured to be electrically connected to the electrode.

Incidentally, when the semiconductor chip 12 to be mounted is different, the wiring pattern of the conductive wiring 11 formed on the insulating substrate 10 of each layer is not always the same wiring pattern, and the electrodes of the non-common semiconductor chip are not necessarily the same. The wiring configuration is different for processing.

The insulating substrate 10 and the semiconductor chip 1
The thickness 2 is a thickness of several tens [μm] to several hundreds [μm]. The semiconductor chip 12 is formed by a mechanical polishing method such as gliding or polishing, or a chemical polishing method such as a method of dissolving the back surface on which no elements are formed in a wafer state or a chip state with an etching solution mainly composed of an HF solution, or the like. Is polished to a desired thickness by a CMP method or the like using the above method in combination.

Further, as shown in FIGS. 5 (a) and 5 (b), the bent portion of the other side 11B of the conductive wiring 11 in each of the insulating substrates 10 cuts the end of each of the insulating substrates 10. It can be formed by bending with a predetermined jig 20 in a chipped state.

Further, in this semiconductor device, as shown in FIG. 6, the conductive wiring 11 located at least at the end (closest to the corner) of the plurality of conductive wirings 11 arranged on the insulating substrate 10 is arranged. The width may be formed to be wider than the width of another conductive wiring 11 located inside the conductive wiring 11.

Accordingly, when stress concentration occurs in the conductive wiring 11 due to a difference in expansion between the semiconductor chip 12 and the insulating substrate 10, they can be prevented from being broken, and high reliability can be obtained. Can be obtained. Further, the width of the conductive wiring 11 varies depending on the dimensions of the insulating substrate 10 and environmental conditions, but it is desirable that the width of the wider one is 1.2 times or more larger than the width of the narrower one.

FIG. 6 shows a configuration in which protrusions 15 are provided at least at four corners of the insulating substrate 10. In this manner, the protrusion 15 is formed integrally with the insulating substrate 10 so as to protrude beyond its outer dimensions. By the way, in FIG. 6,
Although the description has been made using the insulating substrate 10 in a layer other than the uppermost or lowermost insulating substrate 10 in which the conductive wiring is formed long,
It is not limited to this.

With such a configuration, the position of the conductive wiring 11 is located inside the protrusion 15.
In addition, it is possible to prevent the conductive wiring 11 bent from the peripheral edge of the insulating substrate 10 from coming into contact with an external component or damaging the conductive wiring during operation. The protrusions 15 can not only protect the conductive wiring mechanically and electrically, but also can be used for alignment between the insulating substrates 10 when the insulating substrates 10 are laminated. If the tip of 15 is the outer shape for alignment,
Positioning can be facilitated.

In addition, if the outer dimensions of the projection 15 and the outer dimensions of the lowermost insulating substrate 10 having the electrodes 10A for connection to the electrodes of the mother board are made substantially the same, the protrusions 15 can be laminated. Not only is the positioning of the substrate easy, but also in the case where a protective resin is formed in the bent conductive wiring region, that is, in the side region of the insulating substrate, the protrusions of the lowermost insulating substrate 10 and the other insulating substrate 10 If the external dimensions of the 15 are substantially the same, not only can the protective resin be easily formed, but also the thickness of the protective resin can be made uniform.

Further, in this semiconductor device, the connection of the conductive wiring 11 between the laminated insulating substrates 10 is performed, for example, by disposing a solder material on the conductive wiring 11 and reflowing the solder material. Since the bent conductive wiring 11 is in contact with the conductive wiring 11 on the insulating substrate 10 located thereunder, the solder can be easily connected by melting the solder.

Further, for example, the solder may be melted in a solder bath provided with a heater, and the laminated modules MO1 to MO4 may be immersed and connected in the melted solder.

As described above, in the step of immersing the semiconductor device in the molten solder in the solder bath, when the semiconductor device is pulled up from the molten solder, at least one corner of the hexagonal semiconductor device is melted. When the angle θ formed with the solder surface is in the range of 30 ° to 60 °, a short circuit between adjacent conductive wirings 11 connecting the insulating substrates 10 can be prevented.

Further, on the other side of the lowermost insulating substrate 10, an external connection electrode 10A for connecting to the mother substrate is provided.
Are formed. In the examples of FIGS. 1, 2 and 4, a solder ball is formed as the electrode 10A, and a so-called C
SP (Chip Size Package), BGA (Ball Grid Arra)
y) shows the structure. The lowermost insulating substrate 10 and the conductive wiring 11 formed thereon are manufactured by the same method as the upper insulating substrate 10.

[0048]

As described above, according to the present invention,
In a semiconductor device in which a plurality of insulating substrates on which electronic components are mounted are sequentially stacked, conductive wiring between the insulating substrates is
By connecting at the periphery of these insulating substrates, the connection points can be visually confirmed from the outside, and the inspection of the connection points can be extremely easily performed, and the conductive connection between the insulating substrates can be reliably performed. it can.

Further, the conductive wiring between the insulating substrates is connected by the conductive wiring protruding from the peripheral edge of the uppermost or lowermost insulating substrate at the peripheral portion of the laminated insulating substrate. The connection can be performed without adding new connection parts, and the connection point of the semiconductor device can be visually confirmed from the outside. Therefore, the inspection of the connection point can be extremely easily performed, and thus the connection between the insulating substrates can be easily performed. Conductive connection can be easily and reliably performed.

Further, since the connection is made on the side surface of the laminated insulating substrate, even if a defect occurs in a part of the laminated insulating substrate, repair can be easily performed. In addition, since the conductive wiring for connection is formed to protrude from the side surface of the insulating substrate, the solder dip or
Since the connection can be realized collectively and reliably using a simple process such as solder reflow, a low-cost module can be realized.

According to the second aspect of the present invention, one end of the conductive wiring is connected to the electrode of the electronic component by flip-chip mounting the electronic component such that the conductive wiring is disposed on the insulating substrate. In this connection, the conductive wiring can be prevented from being bent and deformed by the insulating substrate.

According to the third aspect of the present invention, the lower one of the insulating substrates is laminated on the electronic component of the lower layer of each of the insulating substrates, so that a sense of stability when the plurality of insulating substrates are laminated is improved. be able to.

According to the fourth aspect of the present invention, since the adhesive is interposed between the insulating substrate and the electronic component adjacent in the laminating direction, the plurality of laminated insulating substrates can be connected before the conductive connection. Collapse can be prevented beforehand.

According to the fifth aspect of the present invention, a plurality of conductive wirings are arranged on the insulating substrate, and the end of the conductive wiring on the other end side of the uppermost or lowermost insulating substrate is provided with a scattering prevention member. Is provided, it is possible to prevent the conductive wirings from being separated and to fix the conductive wirings so as to have a constant pitch accuracy.

According to the sixth aspect of the present invention, since the projections are provided at the corners of the insulating substrate, the positioning at the time of laminating the upper and lower insulating substrates is further facilitated by using the projections. And high alignment accuracy can be obtained. In addition, it becomes a reference for the outer shape at the time of resin molding of the mounting body, so that accurate resin molding can be performed.

Further, since the projections are provided so as to protrude from the conductive wirings between the laminated insulating substrates, external force is applied to the conductive wirings, thereby preventing the conductive wirings from being deformed or damaged. can do.

According to the seventh aspect of the present invention, since the conductive wiring at the corner of the array of the plurality of conductive wirings on the insulating substrate is wider than the other conductive wirings, the electronic component and the insulating substrate Due to the difference between the expansion and the expansion, it is possible to prevent the conductive wiring from being broken when stress is applied thereto, and to improve reliability in connection.

According to the eighth aspect of the present invention, the alignment marks are provided on the conductive wirings at the corners of the conductive wirings. Positioning between them can be further simplified.

According to the ninth aspect of the present invention, since the alignment mark is formed by a round hole, the alignment mark can be easily formed collectively in another process.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of a semiconductor device according to the present invention.

FIG. 2 is a longitudinal sectional view of the semiconductor device.

FIG. 3 is a schematic perspective view showing the uppermost insulating substrate.

FIG. 4 is a schematic perspective view showing the lowermost insulating substrate.

5A and 5B are schematic cross-sectional views showing a procedure for bending a conductive wiring projecting from an insulating substrate by a jig, wherein FIG. 5A shows a state before bending and FIG. 5B shows a state after bending.

FIG. 6 is a plan view showing an insulating substrate in which projections are formed at four corners of the insulating substrate and corners of the conductive wiring are formed to be wide;

[Explanation of symbols]

 MO1 module MO2 module MO3 module MO4 module FJ sealing resin layer 10 insulating substrate 10A electrode 11 conductive wiring 11A one end 11B other end 11C alignment mark 12 semiconductor chip (electronic component) 13 anti-separation member 14 adhesive 15 protrusion 20 jig

Claims (9)

[Claims] 1. A semiconductor device in which a plurality of insulating substrates on which electronic components are mounted are sequentially laminated, wherein a first conductive wiring projecting from a peripheral portion of each of the insulating substrates and being bent into a predetermined shape is formed. A second conductive wiring protruding from a peripheral portion of an uppermost layer or a lowermost layer of the laminated insulating substrates and extending to the lowermost layer or the uppermost insulating substrate; A semiconductor device, wherein the insulated substrates are electrically connected at the periphery of each of the insulated substrates. 2. The semiconductor device according to claim 1, wherein said electronic components are flip-chip mounted on one surface of each of said insulating substrates. 3. The semiconductor device according to claim 1, wherein the plurality of insulating substrates to be stacked are sequentially mounted on adjacent lower electronic components. 4. The semiconductor device according to claim 3, wherein the adjacent insulating substrate and the electronic component have an adhesive therebetween. 5. A method according to claim 1, wherein a plurality of said conductive wirings are arranged on said insulating substrate and a plurality of said conductive wirings are provided at the tip of said conductive wiring extending to said uppermost layer or lowermost layer. 5. The semiconductor device according to claim 1, further comprising a dispersion preventing member for bundling the conductive wirings. 5. 6. The semiconductor device according to claim 1, further comprising positioning projections at the four corners of each of said insulating substrates for laminating said insulating substrates. 7. The semiconductor device according to claim 1, wherein one of the first and second conductive wirings has a wider end than the other conductive wiring. 8. The semiconductor device according to claim 7, wherein an alignment mark for positioning is formed on said wide conductive wiring. 9. The method according to claim 9, wherein the alignment mark is a circular hole.
The semiconductor device according to claim 8.