JP2001189449A - Lateral high breakdown voltage transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain a lateral parasitic bipolar transistor from being turned on, so as to provide a lateral high withstand voltage transistor which is set higher in breakdown strength. SOLUTION: An N--type drain region 2 and an N+-type source region 3 are formed in a P--type silicon substrate 1 separated from each other, a gate electrode 5 formed in a channel 4 insulated from the substrate 1, an N+-type drain contact region 6 formed in the drain region 2, a drain wiring 12 electrically connected to the drain region 2 via the drain contact region 6, a P+-type substrate contact region 7 formed in the source region 2 reaching the substrate 1, and a source wiring 13 electrically connected to the source region 3 and also to the substrate 1 through the intermediary of the substrate contact region 7. The substrate contact region 7 is extended, from the inside of a contact surface 15 of a source wiring 13 to the outside of the contact surface 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal high withstand voltage MO.
It relates to an S transistor.

[0002]

2. Description of the Related Art A lateral high voltage MOS transistor is a kind of power MOS transistor, and is used as a semiconductor element of a semiconductor product which switches a voltage of about several tens to several hundreds of volts, for example.

FIG. 7A is an enlarged plan view showing a part of a plane pattern of a conventional lateral high voltage MOS transistor, and FIG. 7B is a line 7B-7B in FIG. 7A. FIG. Note that a gate electrode is omitted in FIG.

As shown in FIGS. 7A and 7B, a low-concentration P ⁻ -type silicon substrate 101 is formed on a low-concentration N ⁻ -type drain region 102 and is spaced apart from the drain region 102. A high concentration N ⁺ type source region 103 is formed. On the substrate 101 between the drain region 102 and the source region 103, that is, on the channel 104, the substrate 1
The gate electrode 105 is formed insulated from the gate electrode 105.

In the drain region 102, an N ⁺ -type drain contact region 106 having a higher concentration than the drain region 102 is formed. Drain contact region 10
6 is sufficiently separated from the channel 104 by the field insulating film 108 formed in the surface region of the substrate 1. Field insulating film 108 is made of, for example, silicon dioxide, and is formed using a LOCOS technique, a trench isolation technique, or the like. In the source region 103, a high-concentration P ⁺ type substrate contact region 107 reaching the substrate 101 is formed.

On the field insulating film 108 and the substrate 101 on which the respective semiconductor regions are formed, an interlayer insulating film 109 made of, for example, silicon dioxide or the like is formed.
The interlayer insulating film 109 includes a contact hole 110 where the drain contact region 106 is exposed, and the source region 10.
3, and the substrate contact region 107 has a contact hole 111 that is exposed. On the interlayer insulating film 109, a drain wiring 112 contacting the drain contact region 106 via the contact hole 110, and a source wiring 113 contacting the source region 103 via the contact hole 111 and the substrate contact region 107 are formed. ing. The drain wiring 112 is electrically connected to the drain region 102 via the drain contact region 106. Reference numeral 116 in FIG. 7A indicates a contact surface between the drain wiring 112 and the drain contact region 106. The source wiring 113 is electrically connected to the source region 103 and is also electrically connected to the substrate 101 via the substrate contact region 107. The reference numeral 115 in FIG.
13, source region 103 and substrate contact region 10
7 shows the contact surface.

[0007]

However, the horizontal high withstand voltage M
In the OS transistor, as shown in FIG. 7A, since the drain region 102 is on the same plane as the source region 103, the drain region 102 is
There is a lateral parasitic bipolar transistor that uses 1 as a base and the source region 103 as an emitter. When the lateral parasitic bipolar transistor is turned on, the MO
This hinders the operation as an S transistor. The lateral parasitic bipolar transistor is turned on in the following situation, for example.

When the voltage of the drain is increased when the gate is turned on, avalanche breakdown starts at the curved portion 114 of the drain contact region 106, and the hole current is reduced.
It flows toward 01. This hole current passes under the source region 103, flows toward the substrate contact region 107, and usually escapes to the source wiring 113 via the substrate contact region 107.

However, when the drain voltage is further increased, the avalanche breakdown is further increased, and the hole current is increased. As the hole current increases, the source region 1
A large voltage is generated due to the resistance of the substrate 101 below the area 03. Therefore, the substrate 101 and the source region 1
03 is forward-biased, and the lateral parasitic bipolar transistor is turned on. When the lateral parasitic bipolar transistor is turned on, control by the gate becomes impossible, and the lateral high breakdown voltage MOS transistor is destroyed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a lateral high withstand voltage transistor which suppresses turn-on of a lateral parasitic bipolar transistor and has a higher breakdown strength.

[0011]

In order to achieve the above object, in a first aspect of the lateral high breakdown voltage transistor according to the present invention, a first conductivity type semiconductor substrate and a second conductivity type semiconductor substrate formed on the semiconductor substrate are provided. A conductive type drain region, a second conductive type source region formed on the semiconductor substrate at a distance from the drain region, and the semiconductor substrate between the drain region and the source region. A gate electrode formed insulated from the substrate, a drain contact region of a second conductivity type formed in the drain region and having a lower resistance than the drain region, and electrically connected to the drain region via the drain contact region. A drain wiring that is electrically connected, a first conductivity type substrate contact region formed in the source region and reaching the semiconductor substrate,
A source line electrically connected to the source region and electrically connected to the semiconductor substrate via the substrate contact region. The substrate contact region is formed so as to extend from the inside of the contact surface of the source wiring to the outside of the contact surface.

According to the lateral high withstand voltage transistor of the first aspect, the substrate contact region is formed to extend from the inside of the contact surface of the source wiring to the outside of the contact surface. Can be increased in comparison with the related art. As a result, the hole current that has flowed through the substrate easily flows to the source wiring, and the horizontal parasitic bipolar transistor is hard to turn on. Therefore, a lateral high withstand voltage transistor having a higher breakdown strength can be obtained.

In order to achieve the above object, in a second aspect of the lateral high breakdown voltage transistor according to the present invention, a semiconductor substrate of a first conductivity type and a drain region of a second conductivity type formed on the semiconductor substrate are provided. Forming a second conductive type source region formed apart from the drain region on the semiconductor substrate; and forming a second conductive type source region on the semiconductor substrate between the drain region and the source region, the semiconductor substrate being insulated from the semiconductor substrate. Gate electrode, a second conductivity type drain contact region formed in the drain region and having a lower resistance than the drain region, and a drain electrically connected to the drain region via the drain contact region. Wiring and
A first conductivity type substrate contact region formed in the source region and reaching the semiconductor substrate, electrically connected to the source region, and electrically connected to the semiconductor substrate via the substrate contact region; Source wiring to be provided. The semiconductor device further comprises a first conductivity type low resistance layer having a lower resistance than the semiconductor substrate, at an interface between the bottom surface of the source region and the semiconductor substrate.

In the lateral high breakdown voltage transistor according to the second aspect, the interface between the bottom surface of the source region and the semiconductor substrate is
Since the first conductivity type low resistance layer having a lower resistance than the semiconductor substrate is further provided, the resistance under the source region can be reduced as compared with the related art. As a result, the voltage generated when the hole current passes below the source region is reduced,
It becomes difficult for the lateral parasitic bipolar transistor to turn on. Therefore, a lateral high withstand voltage transistor having a higher breakdown strength can be obtained.

In order to achieve the above object, in a third aspect of the lateral high breakdown voltage transistor according to the present invention, a semiconductor substrate of a first conductivity type, a drain region of a second conductivity type formed on the semiconductor substrate, and Forming a second conductive type source region formed apart from the drain region on the semiconductor substrate; and forming a second conductive type source region on the semiconductor substrate between the drain region and the source region, the semiconductor substrate being insulated from the semiconductor substrate. Gate electrode, a second conductivity type drain contact region formed in the drain region and having a lower resistance than the drain region, and a drain electrically connected to the drain region via the drain contact region. Wiring and
A first conductivity type substrate contact region formed in the source region and reaching the semiconductor substrate, electrically connected to the source region, and electrically connected to the semiconductor substrate via the substrate contact region; Source wiring to be provided. The distance from the contact surface between the drain wiring and the drain contact region to the curved surface of the drain contact region is set so that the resistance value from the contact surface to the curved surface is about 10 ohms. It is characterized by.

In the lateral high breakdown voltage transistor according to the third aspect, the distance from the contact surface between the drain wiring and the drain contact region to the curved surface of the drain contact region is determined by the resistance value from the contact surface to the curved surface. Set to be around 10 ohms. That is, the distance from the contact surface between the drain wiring and the drain contact region to the curved surface of the drain contact region is made longer than before. For this reason, the electric field applied to the curved surface can be weakened as compared with the related art, and by increasing the distance to the curved surface, the avalanche breakdown conventionally concentrated on the curved surface can be reduced to the drain contact region. Can be dispersed at the bottom. As described above, the generation of a strong avalanche breakdown can be suppressed from the electric field concentration on the curved surface and the dispersion of the avalanche breakdown. As a result, the hole current flowing through the semiconductor substrate becomes small, and it becomes difficult for the lateral parasitic bipolar transistor to turn on. Therefore, a lateral high withstand voltage transistor having a higher breakdown strength can be obtained.

In order to achieve the above object, in a fourth aspect of the lateral high breakdown voltage transistor according to the present invention, a semiconductor substrate of a first conductivity type and a drain region of a second conductivity type formed on the semiconductor substrate are provided. Forming a second conductive type source region formed apart from the drain region on the semiconductor substrate; and forming a second conductive type source region on the semiconductor substrate between the drain region and the source region, the semiconductor substrate being insulated from the semiconductor substrate. Gate electrode, a second conductivity type drain contact region formed in the drain region and having a lower resistance than the drain region, and a drain electrically connected to the drain region via the drain contact region. Wiring and
A first conductivity type substrate contact region formed in the source region and reaching the semiconductor substrate, electrically connected to the source region, and electrically connected to the semiconductor substrate via the substrate contact region; Source wiring to be provided. The drain contact region is formed so as to reach the semiconductor substrate via a bottom of the drain region.

According to the lateral high withstand voltage transistor of the fourth aspect, since the drain contact region is formed so as to reach the semiconductor substrate via the bottom of the drain region, the contact surface between the drain wiring and the drain contact region is formed. Therefore, the distance to the curved surface of the drain contact region is longer than that of the related art. For this reason, the electric field applied to the curved surface can be made weaker than before, and the avalanche breakdown generated on the curved surface can be reduced. As a result, the hole current flowing through the semiconductor substrate decreases,
It becomes difficult for the lateral parasitic bipolar transistor to turn on. Therefore, a lateral high withstand voltage transistor having a higher breakdown strength can be obtained.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.

[First Embodiment] FIG. 1A is an enlarged plan view showing a part of a plane pattern of a lateral high voltage MOS transistor according to a first embodiment of the present invention.
1B is a cross-sectional view taken along line 1B-1B in FIG. 1A, and FIG. 1C is a cross-sectional view taken along line 1C-1C in FIG. Note that a gate electrode is omitted in FIG.

As shown in FIGS. 1A to 1C, a low-concentration P ⁻ -type silicon substrate 1 is formed with a low-concentration N ⁻ -type drain region 2 and formed at a distance from the drain region 2. A high concentration N ⁺ type source region 3 is formed. On the substrate 1 between the drain region 2 and the source region 3, that is, on the channel 4, a gate electrode 5 formed insulated from the substrate 1 is formed.

In the drain region 2, the drain region 2
An N ⁺ -type drain contact region 6 having a higher concentration than that is formed. Drain contact region 6 is sufficiently separated from channel 4 by field insulating film 8 formed in the surface region of substrate 1. The field insulating film 8
For example, it is made of silicon dioxide, and is formed by using a LOCOS technique, a trench isolation technique, or the like. In the source region 3, a high-concentration P ⁺ type substrate contact region 7 reaching the substrate 1 is formed.

On the substrate 1 on which the field insulating film 8 and each semiconductor region are formed, an interlayer insulating film 9 made of, for example, silicon dioxide or the like is formed. Interlayer insulating film 9
Has a contact hole 10 where the drain contact region 6 is exposed, and a contact hole 11 where the source region 3 and the substrate contact region 7 are respectively exposed. On the interlayer insulating film 9, a drain wiring 12 contacting the drain contact region 6 through the contact hole 10, a source region 3 contacting the source region 3 through the contact hole 11, and a source wiring 13 contacting the substrate contact region 7 are formed. ing. Drain wiring 12 is electrically connected to drain region 2 via drain contact region 6. FIG.
Reference numeral 16 in (A) indicates a contact surface between the drain wiring 12 and the drain contact region 6. Further, the source wiring 13 is electrically connected to the source region 3 and is also electrically connected to the substrate 1 via the substrate contact region 7. Reference numeral 15 in FIG.
3 shows a contact surface between the source wiring 13 and the source region 3 and the substrate contact region 7.

In the first embodiment, as shown in FIG. 1A, the substrate contact region 7 is formed from the inside to the outside of the contact surface 15 of the source wiring 13, preferably, the channel 4.
To form an extension. Thereby, the source wiring 1
3 and the contact ratio between the substrate contact region 7 is shown in FIG.
Of the conventional MOS transistor shown in FIG.
5 increases as compared with the MOS transistor formed only inside.

According to the first embodiment, since the contact ratio between the source wiring 13 and the substrate contact region 7 is increased as compared with the conventional case, the hole current is reduced via the substrate contact region 7 to the source wiring 13. It is easy to fall out.

As a result, the hole current is easily leaked to the source wiring 13, so that the drain region 2 is
, And the parasitic lateral bipolar transistor having the source region 3 as the emitter becomes difficult to turn on.

Therefore, for example, FIGS.
As compared with the conventional lateral high-voltage MOS transistor shown in (C), a lateral high-voltage MOS transistor having a higher breakdown strength can be obtained.

[Second Embodiment] The second embodiment is based on the first embodiment, and particularly improves the planar pattern of the substrate contact region 7.

FIG. 2A is an enlarged plan view showing a part of a plane pattern of a lateral high withstand voltage MOS transistor according to a second embodiment of the present invention, and FIG. 2B is a plan view of FIG. )
FIG. 2C is a sectional view taken along line 2B-2B in FIG.
It is sectional drawing which follows the 2C-2C line in (A). Note that a gate electrode is omitted in FIG.

As shown in FIGS. 2A to 2C, the difference between the second embodiment and the first embodiment is the plane pattern of the substrate contact region 7. FIG.

In the first embodiment, the plurality of substrate contact regions 7 are alternately formed so as to extend to reach the channels 4 on both sides. In the second embodiment, for example, all of the plurality of substrate contact regions 7 are extended to reach the channels 4 on both sides.

According to such a second embodiment, the first
The contact ratio between the source line 13 and the substrate contact region 7 is further increased as compared with the embodiment.

For this reason, the hole current is more easily released to the source wiring 13, and the parasitic lateral bipolar transistor having the drain region 2 as the collector, the substrate 1 as the base, and the source region 3 as the emitter is more difficult to turn on.

Therefore, compared with the lateral high withstand voltage MOS transistor according to the first embodiment, the improvement of the breakdown strength is achieved.
You can do more.

Third Embodiment In the first and second embodiments, the turn-on of the lateral parasitic bipolar transistor is suppressed by making it easy for the hole current flowing in the substrate 1 to escape to the source wiring 3.

In the third embodiment, when a hole current flows through the substrate 1, the voltage generated by the resistance of the substrate 1 below the source region 3 is reduced, thereby suppressing the turn-on of the lateral parasitic bipolar transistor. Things.

FIG. 3A is an enlarged plan view showing a part of a plane pattern of a lateral high voltage MOS transistor according to a third embodiment of the present invention, and FIG. 3B is a plan view showing FIG. )
It is sectional drawing which follows the 3B-3B line in the inside. Note that FIG.
In (A), the gate electrode is omitted.

As shown in FIGS. 3 (A) and 3 (B), the third embodiment is different from the MO shown in FIGS. 7 (A) to 7 (C).
The difference from the S transistor is that the impurity concentration at the interface between the bottom surface of the source region 3 and the substrate 1 is higher than that of the substrate 1,
That is, a P-type semiconductor region 17 having lower resistance than the substrate 1 is provided.

According to the third embodiment, the resistance under the source region 3 is reduced by providing the P-type semiconductor region 17 at the interface between the bottom surface of the source region 3 and the substrate 1 as shown in FIG.
7A to 7C, it can be made smaller than the conventional MOS transistor shown in FIG.

For this reason, the voltage generated when the hole current passes under the source region 3 becomes small, and the PN junction around the source region 3 is less likely to be forward-biased. As a result, the parasitic lateral bipolar transistor having the drain region 2 as the collector, the substrate 1 as the base, and the source region 3 as the emitter becomes difficult to turn on similarly to the first and second embodiments.

Therefore, for example, FIGS.
A MOS transistor having a higher breakdown strength can be obtained as compared with the conventional MOS transistor shown in FIG.

In the third embodiment, the plane pattern of the substrate contact region 7 is the same as that of the conventional transistor. However, the plane pattern of the substrate contact region 7 is the same as that of the transistors according to the first and second embodiments. It may be the same.

In this case, the hole current is
In addition, the parasitic lateral bipolar transistor is more difficult to turn on.

[Fourth Embodiment] In the fourth embodiment, the turn-on of the lateral parasitic bipolar transistor is suppressed by reducing the avalanche breakdown generated on the curved surface 14.

FIG. 4A is an enlarged plan view showing a part of a plane pattern of a lateral high withstand voltage MOS transistor according to a fourth embodiment of the present invention, and FIG. 4B is a plan view of FIG. )
It is sectional drawing in alignment with the 4B-4B line in the inside. FIG.
In (A), the gate electrode is omitted.

As shown in FIGS. 4A and 4B, the fourth embodiment uses the MO shown in FIGS. 7A to 7C.
The difference from the S transistor is that the contact surface 16 between the drain wiring 12 and the drain contact region 6
The plane distance D2 of the drain contact region 6 to the curved surface 14 is longer.

More specifically, the plane distance D2 is set to a value such that the resistance value R2 from the contact surface 16 to the curved surface 14 is about 10 ohms.

According to the fourth embodiment, by increasing the plane distance D2 from the contact surface 16 to the curved surface 14, the electric field applied to the curved surface 14 can be reduced as compared with the related art. . Further, by increasing the plane distance D2 to the curved surface 14, the avalanche breakdown conventionally concentrated on the curved surface 14 is also distributed to the bottom of the drain contact region 6.

As described above, the electric field applied to the curved surface 14 can be reduced, and the avalanche breakdown can be dispersed also at the bottom of the drain contact region 6, so that the occurrence of a strong avalanche breakdown can be suppressed. As a result, the hole current flowing through the substrate 1 can be reduced, and the horizontal parasitic bipolar transistor is less likely to be turned on.

Therefore, for example, FIGS.
As compared with the conventional lateral high-voltage MOS transistor shown in (C), a lateral high-voltage MOS transistor having a higher breakdown strength can be obtained.

In the fourth embodiment, the plane pattern of the substrate contact region 7 is the same as that of the conventional transistor. However, the plane pattern of the substrate contact region 7 is the same as that of the transistors according to the first and second embodiments. It may be the same.

Further, as in the third embodiment, a P-type semiconductor region 17 for reducing the resistance under the source region 3 may be further provided.

Further, in the above description, the plane distance D2 is such that the resistance value R2 from the contact surface 16 to the curved surface 14 is 10
Although the value is set to be around ohm, it can be simply defined as a distance. In this case, the thickness is preferably 5 μm or more and 25 μm or less. If the plane distance D2 is 5 μm or more, the avalanche breakdown is applied to the drain contact region 6.
The effect of being able to be dispersed also at the bottom can be obtained better.

The plane distance D2 is preferably 25 μm or less. If the thickness is 25 μm or more, the planar area of the MOSFET becomes large, and it is difficult to reduce the chip size.

A particularly preferred distance of the plane distance D2 is 15
It is about μm. At this time, it is more preferable that the resistance value R2 is around 10 ohms.

[Fifth Embodiment] The fifth embodiment is based on the fourth embodiment.

FIG. 5A is an enlarged plan view showing a part of a plane pattern of a lateral high voltage MOS transistor according to a fifth embodiment of the present invention, and FIG. )
It is sectional drawing which follows the 5B-5B line | wire inside. FIG.
In (A), the gate electrode is omitted.

As shown in FIGS. 5A and 5B, the third embodiment differs from the transistors shown in FIGS. 7A to 7C in that the third embodiment differs from the transistor shown in FIGS.
Below, an N ⁺ -type deep semiconductor region 6 ′ reaching the substrate 1 via the bottom surface of the drain region 2 is provided. The deep semiconductor region 6 ′ may be formed in addition to the drain contact region 6, or may be formed by deeply diffusing the drain contact region 6 itself into the substrate 1.
Thereby, the depth D2 'up to the curved surface 14 becomes longer, and the same effect as in the fourth embodiment can be obtained.

In the deep semiconductor region 6 ′, it is desirable that the total amount of N-type impurities such as arsenic and phosphorus is set to, for example, 3 × 10 ¹² cm ⁻² or more and the N-type impurities are sufficiently contained.

When the N-type impurity is sufficiently contained in the deep semiconductor region 6 'in this manner, when a surge is applied via the drain wiring 12, the deep semiconductor region 6' is not fully depleted but deep. The semiconductor region 6 'remains. When the deep semiconductor region 6 'remains, the effect of relaxing the electric field can be better obtained than when the entire deep semiconductor region 6' is depleted.

In the fifth embodiment, the plane pattern of the substrate contact region 7 is the same as that of the conventional transistor. However, the plane pattern of the substrate contact region 7 is the same as that of the transistors according to the first and second embodiments. It may be the same.

Further, as in the third embodiment, a P-type semiconductor region 17 for reducing the resistance under the source region 3 may be further provided.

It is also possible to combine with the fourth embodiment.

[Sixth Embodiment] FIG. 6A is a sectional view of a lateral high voltage MOS transistor according to a sixth embodiment of the present invention.

In the first to fifth embodiments, the horizontal wiring is formed by connecting the drain wiring 12 to the drain terminal D, connecting the source wiring 13 to the source terminal S, and connecting the gate electrode 5 to the gate terminal G. It can function as a high voltage MOS transistor.

However, as shown in FIG. 6A, by short-circuiting the source wiring 13 and the gate electrode 5, it is possible to function not as a lateral high-voltage MOS transistor but as a diode.

A preferred example of use when functioning as a diode is to use it as a protection diode. FIG. 6B shows one connection example of this protection diode. As shown in FIG. 6B, the protection diode has a cathode connected to the drain terminal D of the lateral high-voltage transistor and an anode connected to the source terminal S. Such a protection diode breaks down when a surge is applied to the drain terminal D of the lateral high breakdown voltage transistor, so that the surge is released to the source terminal S.

As described above, the lateral high withstand voltage MO according to the present invention is
The S transistor can also function as a diode by short-circuiting the source wiring 13 and the gate electrode 5.

Therefore, a plurality of lateral high-voltage MOS transistors according to the present invention are formed in a chip and function as MOS transistors as switching elements, and a part of them may function as a protection diode of the MOS transistor. it can.

In this case, since the MOS transistor itself has a high breakdown strength as described in the first to fifth embodiments and is connected to the protection diode, a higher breakdown strength can be obtained. .

Moreover, such a protection diode does not need to be particularly changed in each semiconductor region pattern formed in the chip, and can be obtained only by changing the wiring of each semiconductor region.

FIG. 6A shows an example in which the lateral high voltage MOS transistor according to the first embodiment functions as a diode, but the same applies to the second to fifth embodiments. Then, the source wiring 13 and the gate electrode 5 are short-circuited to function as a diode.

Although the present invention has been described with reference to the first to sixth embodiments, the present invention is not limited to these embodiments, and it is needless to say that various modifications can be made without departing from the gist of the present invention. .

[0074]

As described above, according to the present invention, it is possible to provide a lateral high withstand voltage transistor which suppresses the turn-on of the lateral parasitic bipolar transistor and has a higher breakdown strength.

[Brief description of the drawings]

FIG. 1A is an enlarged plan view showing a part of a plane pattern of a lateral high-voltage MOS transistor according to a first embodiment of the present invention, and FIG. 1B is a plan view of FIG. 1A is a cross-sectional view taken along line 1B-1B, and FIG. 1C is a cross-sectional view taken along line 1C-1C in FIG.

FIG. 2A is an enlarged plan view showing a part of a plane pattern of a lateral high-voltage MOS transistor according to a second embodiment of the present invention, and FIG. 2B is a plan view of FIG. 2A is a cross-sectional view along the line 2B-2B, and FIG. 2C is a cross-sectional view along the line 2C-2C in FIG. 2A.

FIG. 3A is an enlarged plan view showing a part of a plane pattern of a lateral high-voltage MOS transistor according to a third embodiment of the present invention, and FIG. 3B is a plan view of FIG. Sectional drawing which follows 3B-3B line in A).

FIG. 4A is an enlarged plan view showing a part of a plane pattern of a lateral high voltage MOS transistor according to a fourth embodiment of the present invention, and FIG. 4B is a plan view of FIG. Sectional drawing which follows the 4B-4B line in A).

FIG. 5A is an enlarged plan view showing a part of a plane pattern of a lateral high voltage MOS transistor according to a fifth embodiment of the present invention, and FIG. 5B is a plan view of FIG. Sectional drawing which follows the 5B-5B line in A).

FIG. 6A is a sectional view of a lateral high-voltage MOS transistor according to a sixth embodiment of the present invention, and FIG. 6B.
1 is an equivalent circuit diagram showing a lateral high-voltage MOS transistor with a protection diode.

FIG. 7A is an enlarged plan view showing a part of a plane pattern of a conventional lateral high voltage MOS transistor;
FIG. 7B is a cross-sectional view taken along line 7B-7B in FIG. 7A.

[Explanation of symbols]

1 ... low concentration P ^- -type silicon substrate, 2 ... low concentration N ^- type drain region, 3 ... high concentration N ⁺ -type source region, 4 ... channel, 5 ... gate electrode, 6 ... high concentration N ⁺ -type drain contact region, 6 ': deep high-concentration N ⁺ type semiconductor region, 7: high-concentration P ⁺ -type substrate contact region, 8: field insulating film, 9: interlayer insulating film, 10: contact hole, 11: contact hole, 12: drain wiring, 13: Source wiring, 14: Curved surface, 15: Contact surface of source wiring, 16: Contact surface of drain wiring, 17: P-type semiconductor region

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Takao Ito 1 Tokoba, Komukai Toshiba-cho, Kawasaki-shi, Kanagawa F-term in the Toshiba Microelectronics Center (reference) 5F040 DA00 DA23 DA24 DA27 DB04 DB06 DC01 EC19 EF01 EF13 EF18 EH05 EK01 EM01

Claims (4)

[Claims] A first conductivity type semiconductor substrate; a second conductivity type drain region formed on the semiconductor substrate; and a second conductivity type drain region formed on the semiconductor substrate so as to be separated from the drain region. A source region, a gate electrode formed on the semiconductor substrate between the drain region and the source region and insulated from the semiconductor substrate, and a resistance formed on the drain region, the resistance being higher than that of the drain region. A drain contact region having a low second conductivity type; a drain wiring electrically connected to the drain region via the drain contact region; and a first conductivity type formed in the source region and reaching the semiconductor substrate. A substrate contact region, electrically connected to the source region, and electrically connected to the semiconductor substrate via the substrate contact region; ; And a source wiring, said substrate contact region, the inner contact surfaces of the source wire, the lateral high-voltage transistor, characterized in that the extended form to the outside of the contact surface. 2. A semiconductor substrate of a first conductivity type; a drain region of a second conductivity type formed on the semiconductor substrate; and a second conductivity type formed on the semiconductor substrate at a distance from the drain region. A source region, a gate electrode formed on the semiconductor substrate between the drain region and the source region and insulated from the semiconductor substrate, and a resistance formed on the drain region, the resistance being higher than that of the drain region. A drain contact region having a low second conductivity type; a drain wiring electrically connected to the drain region via the drain contact region; and a first conductivity type formed in the source region and reaching the semiconductor substrate. A substrate contact region, electrically connected to the source region, and electrically connected to the semiconductor substrate via the substrate contact region; A lateral high-breakdown-voltage transistor, comprising: a source wiring; and a first-conductivity-type low-resistance layer having a lower resistance than the semiconductor substrate at an interface between a bottom surface of the source region and the semiconductor substrate. . 3. A semiconductor substrate of a first conductivity type; a drain region of a second conductivity type formed on the semiconductor substrate; and a second conductivity type formed on the semiconductor substrate at a distance from the drain region. A source region, a gate electrode formed on the semiconductor substrate between the drain region and the source region and insulated from the semiconductor substrate, and a resistance formed on the drain region, the resistance being higher than that of the drain region. A drain contact region having a low second conductivity type; a drain wiring electrically connected to the drain region via the drain contact region; and a first conductivity type formed in the source region and reaching the semiconductor substrate. A substrate contact region, electrically connected to the source region, and electrically connected to the semiconductor substrate via the substrate contact region; And a distance from a contact surface between the drain wiring and the drain contact region to a curved surface of the drain contact region, wherein a resistance value from the contact surface to the curved surface is about 10 ohms. A lateral high withstand voltage transistor characterized in that: 4. A semiconductor substrate of a first conductivity type; a drain region of a second conductivity type formed on the semiconductor substrate; and a second conductivity type formed on the semiconductor substrate at a distance from the drain region. A source region, a gate electrode formed on the semiconductor substrate between the drain region and the source region and insulated from the semiconductor substrate, and a resistance formed on the drain region, the resistance being higher than that of the drain region. A drain contact region having a low second conductivity type; a drain wiring electrically connected to the drain region via the drain contact region; and a first conductivity type formed in the source region and reaching the semiconductor substrate. A substrate contact region, electrically connected to the source region, and electrically connected to the semiconductor substrate via the substrate contact region; ; And a source wiring, the drain contact region, lateral high-voltage transistor, characterized in that through the bottom of the drain region is formed so as to reach the semiconductor substrate.