JP2001156289A - Manufacturing method of insulated gate semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a manufacturing method for making a source / drain region shallower in an insulated gate semiconductor device such as a MOS transistor without lowering productivity. SOLUTION: The manufacturing method according to the present invention provides a method of manufacturing a semiconductor device, comprising the steps of:
Forming an insulating layer 14 on the semiconductor substrate, implanting an impurity 15 into a predetermined region of the semiconductor substrate via the insulating layer 14, etching the insulating layer 14 Forming a side wall spacer 17 on the side wall of the gate electrode 13 and a step of forming the source and drain regions 20 by diffusing the implanted impurities by heat treatment. The implantation through the insulating layer 14 makes it possible to reduce the range of impurity implantation into the silicon substrate regardless of ion implantation with high implantation energy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an insulated gate semiconductor device, and more particularly to a PMOSFET (P type).
Metal Oxide Semiconductor Field Effect Transistor)
The present invention relates to a method of manufacturing a semiconductor device suitable for forming source / drain regions.

[0002]

2. Description of the Related Art The miniaturization and high performance of electronic devices require higher integration and higher performance of semiconductor devices mounted thereon. Many technologies have been developed and put into practical use to meet this demand. As a technique for meeting such a demand in a MOS transistor, a technique for forming a source / drain region to be shallower is extremely important, along with a technique for reducing a gate channel width and a technique for thinning a gate oxide film.

[0003] Techniques for forming shallower source / drain regions are more important in the manufacture of PMOS transistors. The reason is that boron (B11), which is widely used as an impurity for forming source / drain regions in a PMOS transistor, is smaller than arsenic (As) and phosphorus (P) used in an NMOS transistor. This is because it is relatively difficult to make the source / drain regions shallow because of the large diffusion coefficient.

[0004] In the fabrication of PMOS transistors, a common method for making the source / drain regions shallow is:
The purpose is to reduce the implantation energy during B + ion implantation. By performing ion implantation with an implantation energy of 10 KeV or less (less than half of the general implantation energy), the reach of the ions to the silicon substrate, that is, the implantation range is reduced, and the diffusion by the subsequent heat treatment is extended. Area becomes shallower. However, this method has a problem in terms of transistor productivity. That is, when the implantation energy applied to the B + ions is reduced, the beam current at the time of implantation decreases, and the time required for the source / drain regions to reach the target ion concentration becomes longer, and the time required for the process increases. I do. FIG. 4 shows the relationship between the implantation energy in B + ion implantation and the implantation time when implanting a dose of 2 × 10 ¹⁵ / cm ² . As is clear from the figure, the implantation time becomes longer as the implantation energy becomes lower. This is due to the fact that as the implantation energy decreases, the beam efficiency of the implanter decreases and less boron is ionized.

As a conventional method for keeping the production efficiency low while making the source / drain regions shallow, there is a method using boron fluoride (BF2) ions as implanted ions instead of B + ions. Since the mass number of BF ₂ + ions is larger than that of B + ions, the range of implantation into the silicon substrate is reduced. That is, when trying to achieve ion distribution in the depth direction equivalent to that of B + ion implantation by BF ₂ + ion implantation, the implantation energy can be made higher, and as a result, the time required for ion implantation is reduced. Can be shorter. However, BF ₂ +
When ions are used, there is a problem that fluorine (F) contained therein accelerates the “penetration” of the gate oxide film by boron (B). That is, a phenomenon occurs in which boron in the P + polysilicon penetrates the gate oxide film by the heat treatment in a later step and diffuses into the silicon substrate. This phenomenon significantly changes the threshold voltage of the MOS transistor.

As another method for making the source / drain regions shallow, there is a method in which the implantation region is made amorphous to reduce the ion implantation range prior to B + ion implantation. The implantation region is made amorphous by silicon (S
This is achieved by implanting i) or germanium (Ge) into the region. However, according to this method, silicon (Si) or germanium (Ge) is implanted before B + ion implantation.
Is added. The addition of the manufacturing process eventually leads to a decrease in the productivity of the MOS transistor. Also, the implantation of additional atoms into the source / drain regions significantly reduces their crystallinity and increases the potential for inducing crystal defects.

[0007]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for making the source / drain regions shallower in an insulated gate type semiconductor device such as a MOS transistor without reducing the productivity. It is in.

The method of manufacturing an insulated gate semiconductor device according to the present invention does not require the use of BF + ions as implanted ions and does not require the implanted region to be made amorphous. Can be avoided.

[0009]

SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing an insulated gate semiconductor device such as a MOS transistor. In the present invention, a step of forming a gate electrode on an active region of a semiconductor substrate via a gate insulating film; a step of forming an insulating layer on the semiconductor substrate; Implanting impurities into the region, forming the sidewall spacers on the sidewalls of the gate electrode by etching the insulating layer, and forming source and drain regions by diffusing the implanted impurities by heat treatment. Having. The implantation through the insulating layer makes it possible to reduce the range of impurity implantation into the silicon substrate irrespective of ion implantation with high implantation energy.

In this case, the thickness of the insulating layer formed on the semiconductor substrate is preferably in the range of 800 to 1800 angstroms.

It is preferable that a silicon oxide film (SiO ₂ ) or a silicon nitride film (Si ₃ N ₄ ) be used as a material of the insulating layer.

In a preferred embodiment, the implantation energy for implanting the impurity is 25 keV or more, and the impurity concentration of the region where the impurity is implanted is 1 × 10 ¹⁸ / cm 3.
³ to 1 × 10 ²⁰ / cm ³ , which is determined by the relationship between the thickness of the insulating layer and the desired depth of the source / drain region.

The present invention may further comprise a step of implanting an impurity into a predetermined region of the semiconductor substrate to form low-concentration source and drain regions after the step of forming the gate electrode. can do.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 1A to 1E show a process for manufacturing a PMOS transistor according to the present invention. In the manufacturing process shown in FIG. 1A, a gate insulating film 12 is formed on the n-type silicon substrate 10 after the field oxide film 11 has been formed, and then, for example, 2000
A gate electrode 13 made of polysilicon of about 5000 Å is formed in a predetermined pattern.

In the step shown in FIG.
An insulating film 14 for forming 7 (FIG. 2D) is deposited on the silicon substrate 10. The insulating film 14 is preferably 800
Silicon oxide film (SiO ₂ ) with thickness of ~ 1800 angstroms
Alternatively, it is a silicon nitride film (Si ₃ N ₄ ). The thickness of the insulating film 14 is important in determining the ion distribution in the depth direction to the silicon substrate in the subsequent ion implantation (hereinafter, this may be referred to as the junction depth). Here, it should be noted that the junction depth is generally governed by the thickness of the insulating film 14 and the implantation energy of the ion implantation.

In the method for manufacturing a PMOS transistor according to the present invention, an impurity 15 is implanted in the step shown in FIG. A p + region 16 is formed in the substrate 10. That is, the implanted impurities 15 reach the silicon substrate 10 through the insulating film 14. Here, boron (B) is used as the impurity 15. The implantation of the impurity 15 needs to be performed with an implantation energy at which the ions pass through the insulating film 14 and reach the silicon substrate 10.
With an implantation energy of 25 to 75 keV, 1 × 10 ¹⁵ / cm ² to 1 × 10 ¹⁶ /
Preferably, the dose is applied between cm ² . The ion implantation energy should be determined in relation to the thickness of the insulating film 14, but when the thickness of the insulating film 14 is 800 Å, the ion implantation energy is 25
At ~ 50 keV and 1300 Å, the ion implantation energy is 38-60 keV, and when the thickness is 1800 Å, the ion implantation energy is 55-75 keV
It is preferable to be within the range.

After the ion implantation for forming the source / drain regions is completed, the insulating film 14 is etched to form the side wall spacers 17 in the step shown in FIG. Generally, the insulating film 14 is uniformly etched over the entire surface by anisotropic dry etching, and the sidewall spacer 17 remains.

In the step shown in FIG. 1E, the heat treatment activates and diffuses the region 16, thereby forming the source / drain region 20. Typically, a heat treatment at a temperature in the range of 800 to 1100 ° C. for 60 minutes or less promotes activation and diffusion of implanted ions. By the heat treatment, the source / drain region 20 having the desired junction depth is obtained. 1E, an interlayer insulating film such as silicate glass (PSG) is formed on the substrate 10 and a connection hole to a source / drain region is formed. Then, a metal layer such as aluminum (Al) serving as a wiring is formed here by PVD (Physical Vapor Depo).
sition) method to complete a series of processes.

FIG. 2 is a simulation result showing the relationship between the junction depth of the source / drain regions and the ion implantation energy according to the manufacturing process of the present invention. The graph shows simulation results according to the present invention using three types of insulating layers (800, 1300, and 1800 angstroms) having different thicknesses for forming the sidewall spacer. In addition, for comparison, a simulation result by a conventional manufacturing method in which ion implantation is performed after forming a side wall spacer is shown. From this graph, according to the manufacturing method of the present invention, in order to obtain source / drain regions having the same junction depth,
It will be apparent that the ion implantation can be performed with a higher implantation energy than the conventional method. Ion implantation with high implantation energy is completed in a shorter time, and the productivity of the semiconductor device is improved. Further, the junction depth can be made shallower in a practically necessary time required for ion implantation.

The production method of the present invention uses an LDD (Lightly Dop
The present invention can also be applied to a manufacturing process of a semiconductor device having an ed drain structure, that is, a low concentration drain structure. FIG.
(F) shows a step of manufacturing the PMOS transistor having the LDD structure according to the present invention. For the details of steps common to the manufacturing steps shown in FIG. 1 in this manufacturing step, refer to the above description.

In the manufacturing process shown in FIG. 3A, the n-type silicon substrate 30 after forming the field oxide film 31 is formed.
A gate electrode 33 is formed thereon via a gate insulating film 32. In FIG. 3B, an impurity 41 is implanted to form low-concentration source and drain regions.
A p- region 42 is formed in the mold silicon substrate 30. The impurity 41 to be implanted is typically boron (B). The above ion implantation is performed at an implantation energy of 5 to 30 keV,
It is preferable to apply at a dose of from × 10 ¹² / cm ² to 1 × 10 ¹⁵ / cm ² .

In the step shown in FIG.
An insulating film 34 for forming 7 is formed on the silicon substrate 30.
Is deposited. As in the previous embodiment, the side wall spacer 37
Prior to the formation of, the steps shown in FIG.
A pure substance 35 is implanted, and a p + region is formed in the n-type silicon substrate 30.
An area 36 is formed. That is, the implanted impurity 35
Reaches the silicon substrate 30 through the insulating film 34.
You. The impurity 35 is the same as the impurity 41 previously implanted.
Is used. At this time, as a side wall spacer 37 later
Immediately below the remaining region of the insulating film 34, the region of the insulating film is
And the impurities 35 do not reach. Follow
Thus, in the silicon substrate 30, p + and p- regions,
Two regions 36 and 42 having different impurity concentrations are formed.
The Rukoto. The implantation of the impurity 35 is 25 to 75 keV.
At injection energy, 1 × 10 ^Fifteen/cm^Two~ 1 × 10¹⁶/cm^TwoThe dose of
It is preferably applied in an amount.

After the ion implantation for forming the source / drain regions is completed, the insulating film 34 is etched to form the side wall spacers 37 in the step shown in FIG. Generally, the insulating film 34 is uniformly etched over the entire surface by anisotropic dry etching, and the sidewall spacers 37 remain. In the step shown in FIG. 3F, the heat treatment activates and diffuses the regions 36 and 42, thereby forming the source / drain regions 40 and 43. By the heat treatment, the source / drain region 40 having the desired junction depth is obtained. A typical process following the conventional process shown in FIG. 3 (F) is a silicate glass (PSG).
An interlayer insulating film such as is formed on the substrate 30 and a connection hole to the source / drain region is processed. Then, a metal layer such as aluminum (Al) serving as a wiring is deposited here by a PVD method, and a series of processes is completed.

The embodiment of the present invention has been described with reference to the drawings. Obviously, the scope of application of the present invention is not limited to the items shown in the above embodiment. The manufacturing method according to the present invention may be used together with another method for reducing the junction depth of the source / drain regions.

[0025]

As described above, according to the present invention, the source / drain regions in an insulated gate semiconductor device such as a MOS transistor can be made shallower without lowering the productivity.

The method of manufacturing an insulated gate semiconductor device according to the present invention does not require the use of BF + ions as implanted ions and does not require the implanted region to be made amorphous. Can be avoided.

[Brief description of the drawings]

FIG. 1 is a process chart showing a manufacturing process of a PMOS transistor according to the present invention.

FIG. 2 is a simulation result showing a relationship between a junction depth of a source / drain region and ion implantation energy according to a manufacturing process of the present invention.

FIG. 3 is a process chart showing a manufacturing process of a PMOS transistor having an LDD structure according to the present invention.

FIG. 4 is a graph showing a relationship between implantation energy and implantation time in B + ion implantation.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 11 field oxide film 12 gate insulating film 13 gate electrode 14 insulating film 15 impurity 16 region 17 side wall spacer 19 gate insulating film 20 source / drain region

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Tsutomu Kubota 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan F-term (reference) in Texas Instruments Co., Ltd. 5F040 DA13 DC01 EC07 EF02 EK01 FA05 FA07 FA16 FA18 FB02 FB04 FC16 FC21

Claims (8)

[Claims] A step of forming a gate electrode on an active region of the semiconductor substrate via a gate insulating film; a step of forming an insulating layer on the semiconductor substrate; Implanting impurities into the region, forming the sidewall spacers on the sidewalls of the gate electrode by etching the insulating layer, and forming source and drain regions by diffusing the implanted impurities by heat treatment. A method for manufacturing an insulated gate semiconductor device having: 2. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein said insulating layer has a thickness in a range of 800 to 1800 angstroms. 3. The method of manufacturing an insulated gate semiconductor device according to claim 2, wherein said insulating layer is a silicon oxide film. 4. The method for manufacturing an insulated gate semiconductor device according to claim 2, wherein said insulating layer is a silicon nitride film. 5. The method for manufacturing an insulated gate semiconductor device according to claim 2, wherein the implantation energy for implanting the impurity is 25 keV or more. 6. The insulated gate semiconductor device according to claim 2, wherein the impurity concentration of the region into which the impurity is implanted is 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²⁰ / cm ³ . Production method. 7. The method of manufacturing an insulated gate semiconductor device according to claim 6, wherein said impurity is boron. 8. After the step of forming the gate electrode,
8. The insulated gate semiconductor according to claim 1, further comprising a step of implanting impurities into predetermined regions of the semiconductor substrate to form low concentration source and drain regions. Device manufacturing method.