JP2001153924A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the area of a chip by reducing the number of pads for monitoring and measuring the output voltage of a reference voltage-generating circuit and the output voltage of a step-down circuit in a semiconductor storage device having on the chip at least the step-down circuit, the reference voltage- generating circuit, a test circuit and a plurality of the pads for connecting the chip to the outside. SOLUTION: The outputs of the reference voltage-generating circuit 12 and the step-down circuit 13 are connected to the same pad 2 via pMOS transistors P1 and P2, respectively. Complementary output signals C1 and C2 from the test circuit 14 are inputted to gate electrodes of the pMOS transistors P1 and P2, thereby complementarily turning the transistors on and off. Accordingly, one pad is shared in place of conventionally required two pads. Since the MOS transistor as a circuit element is small, an area increase by the test circuit 14 and the pMOS transistors P1 and P2 is negligible in comparison with an area decrease by one pad.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a technique effective for reducing the number of pads on a chip.

[0002]

2. Description of the Related Art In recent years, the capacity of a semiconductor memory device has been remarkably increased, and accordingly, MOS transistors forming various circuits and memory cells in a chip have a planar dimension such as a gate width and a gate length, and a gate oxide. Three-dimensional dimensions such as film thickness have also been reduced. In addition, even in a capacitor which is a component of a memory cell, the dielectric film thickness is reduced in order to secure a capacity despite a reduction in area.

In a large-capacity storage device in which a circuit is constituted by miniaturized and thinned elements as described above, for example, breakdown or deterioration of a gate insulating film of a MOS transistor or a dielectric film of a capacitor or a short channel MOS In order to prevent the deterioration of transistor characteristics due to the application of a high electric field between the source and drain of the transistor, and to reduce the electric field applied to the element in order to reduce the electric field applied to the element in order to ensure the reliability of the storage device, A power supply voltage (internal power supply voltage) for operating the circuit is made lower than a power supply voltage (external power supply voltage) supplied from outside the storage device. For this purpose, the external power supply voltage is reduced to a predetermined internal power supply voltage. It has a step-down circuit. Further, a reference voltage generating circuit for generating a constant voltage (reference voltage) independent of an external power supply voltage is provided in order to obtain a voltage used as a reference when the voltage is lowered.

FIG. 6 shows an example of a relationship among an external power supply voltage V _CC , an internal (step-down) power supply voltage V _INT, and a reference voltage V _REF in a semiconductor memory device. In FIG. 6, the horizontal axis represents the external power supply voltage V _CC , and the vertical axis represents each of the voltages V _CC , V _INT , V _CC
Indicates _REF . As shown in FIG. 6, the reference voltage V _REF is during external power supply voltage V _CC is low in proportion to the external power supply voltage V _CC, constant regardless of the external power supply voltage at a certain value V _CC1 or more external power supply voltage Become. On the other hand, the internal power supply voltage V _INT
Is the same value as the external power supply voltage V _{CC in the} region where the external power supply voltage is lower than V _CC1 and the external power supply voltage is V _CC1 to V _CC1.
In the range of _CC2, a constant value determined by the reference voltage _VREF is maintained. Further, in a region where the external power supply voltage is equal to or higher than V _CC2 , a straight line proportional to the external power supply voltage is obtained. In a semiconductor memory device, it is general that the operation is guaranteed to the customer when the external power supply voltage is in the range of V _{CC1 to} V _CC2 , and the area where the external power supply voltage is V _CC2 or more is stored during the manufacturing process. It is used in a so-called BT (bias-temperature) test in which an initial failure is screened by simultaneously applying a temperature and a voltage higher than the operation guarantee range to the device.

By the way, the value of the output voltage V _REF of the reference voltage generating circuit and the value of the output voltage V _INT of the step-down circuit as the internal power supply voltage _depend on the operation margin of the storage device and, consequently, the normal operation of the storage device. It is important to know exactly what these values are because they are important factors that govern whether or not to do so. Therefore, in order to enable the voltage to be directly measured from outside the storage device, the output points of the reference voltage generation circuit and the step-down circuit are connected to pads on the chip (electrodes for connection with the outside of the chip provided on the chip). ). In that case, conventionally, the output point of the reference voltage generation circuit is connected to the dedicated pad, while the output point of the step-down circuit is also connected to the dedicated pad, so that the respective output voltages V _REF and V _INT are connected. It is common to output to separate pads. It should be noted that the reference voltage V _REF and the step-down power supply voltage V _INT are sufficient as long as their voltage values can be measured from outside the storage device, and it is not always necessary to measure both at the same time.

FIG. 7 schematically shows an example of a layout of a chip in a conventional semiconductor memory device as described above. Referring to FIG. 7, a chip 1C shown in FIG. 7 includes a test circuit block 11B, a reference voltage generation circuit 12,
Three circuit blocks of the step-down circuit 13 are formed,
Two pads 20 and 21 are provided on the edge of the chip. Of course, these three circuits and 2
In addition to the one pad, for example, various circuit blocks required for storage operation such as a memory cell array, an address decoder and a driver of a row and a column, a sense amplifier and an input / output circuit, and wiring for connecting the circuit blocks are provided. Are formed, and furthermore, a number of pads are formed for exchanging input / output signals between each circuit block and the outside of the chip or for receiving and supplying an external power supply voltage V _CC , Not shown for simplicity.

In the chip 1C shown in FIG. 7, the output point of the reference voltage generating circuit 12 is directly connected to the pad 20 and the output point of the step-down circuit 13 is directly connected to the pad 21. V _REF can be measured from the outside via the pad 20, and the output voltage V _INT of the step-down circuit can be measured from the outside via the pad 21.

The test circuit block 11B includes several test circuits, and includes a chip select signal CS, a row address strobe signal RAS,
Column address strobe signal CAS and a write enable signal WE is the entry of the storage device to the test mode when a certain condition, which test in the test circuit block 11B according to the result obtained by decoding the address signal A _n at that time A desired function test can be performed depending on whether the circuit is activated. This test circuit block 1
1B is a circuit normally provided in the semiconductor memory device for testing the function of the memory device before the memory device is shipped as a product.

[0009]

As described above, the capacity of a semiconductor memory device in recent years has increased remarkably. For this reason, elements such as MOS transistors and capacitors and wiring between circuit blocks have been extremely miniaturized. The area of so-called internal circuits, such as circuit blocks and memory cell arrays, required for storage operations has been decreasing. However, the pad provided on the chip is further connected to an external connection terminal such as a lead terminal provided on the package by, for example, wire bonding. Due to the connection structure or the construction method, it is difficult to reduce the area from the current state. As a result, the area of the chip has been greatly influenced by the number of pads.

However, the conventional semiconductor memory device has two dedicated pads for the reference voltage V _REF and the internal power supply voltage V _INT which need not always be measured simultaneously. Therefore, if these two pads can be shared by one pad, the chip area can be reduced accordingly.

Therefore, the present invention provides a step-down circuit on a chip,
In a semiconductor memory device including at least a reference voltage generation circuit, a test circuit block, and a plurality of pads for connection to the outside of the chip, monitor and measure the output voltage of the reference voltage generation circuit and the output voltage of the step-down circuit. The purpose of the present invention is to reduce the number of pads for performing the operation.

[0012]

According to the present invention, there is provided a semiconductor memory device comprising: a step-down circuit for stepping down a power supply voltage externally supplied; a reference voltage generating circuit for generating a voltage independent of the power supply voltage; A test circuit block for switching the semiconductor memory device to a test mode in accordance with an external signal to test the function of the semiconductor memory device, and at least a plurality of pads for electrical connection to the outside of the chip; An analog switch connected between the output point of the reference voltage generation circuit and one pad and between the output point of the step-down circuit and the one pad, and the semiconductor memory device has entered the test mode. Means for switching the opening and closing of the analog switch depending on whether or not
Switching means for switching the opening and closing of one analog switch and the opening and closing of the other analog switch so as to be complementary to each other is provided.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram schematically showing an example of a layout of a chip in the semiconductor memory device according to the first embodiment of the present invention. Comparing FIG. 1 with FIG. 7, chip 1A according to the present embodiment is different from chip 1C of the conventional semiconductor memory device in that the number of voltage measurement pads is reduced to one (pad 2). The output voltage of the reference voltage generation circuit 12 is also
Is also output through the same one pad 2, and p is output between the output point of the reference voltage generating circuit 12 and the pad 2.
The channel type MOS transistor (pMOS transistor) P1 and the pMOS transistor P2 inserted between the output point of the step-down circuit 13 and the pad 2 so as to form a current path, and the test circuit block 11A A test circuit 14 for controlling on / off of the pMOS transistors P1 and P2 is additionally provided.

The signal C1 from the test circuit 14 is input to the gate electrode of the pMOS transistor P1.
The signal C2 from the test circuit 14 is also input to the gate electrode of the MOS transistor P2. 2
The two signals C1 and C2 are complementary to each other. Test circuit 14, when the chip select signal CS, a row address strobe signal RAS, a storage device in response to a column address strobe signal CAS and a write enable signal WE has entry to the test mode, and decodes the address signal A _n The output signal C1 and the output signal C2 are both activated when the test circuit 14 is in the inactive state and when the test circuit 14 is in the active state. Interchange.

FIG. 2 shows an operation waveform of each signal in the present embodiment. Referring to FIG. 2, at time T10, chip select signal C externally input to chip 1A.
S, row address strobe signal RAS, column
When the address strobe signal CAS and the write enable signal WE change from the high level to the low level, the storage device enters the test mode at the rising edge of the clock signal CLK immediately after (time T11), and the test circuit 14
Is activated. Before time T11, the storage device is in a normal storage operation mode, and the test circuit is in an inactive state.

When the storage device is in a normal storage operation mode before time T11, the test circuit 14 is inactive and outputs a high-level signal C1 and a low-level signal C2. Therefore, the pMOS transistor P1 is in the off state, the pMOS transistor P2 is in the on state, and the internal power supply voltage V _INT output from the step-down circuit 13 is output to the pad 2.

When the storage device enters the test mode at time T11, at the same time, the output signal C1 of the test circuit 14 changes from the high level to the low level, and the signal C2 changes from the low level to the high level.
As a result, the pMOS transistor P1 switches from the off state to the on state, the pMOS transistor P2 switches from the on state to the off state, and the reference voltage V _REF output from the reference voltage generation circuit 12 is output to the pad 2. You.

According to the present embodiment, by entering the test mode and activating the test circuit 14, the output voltage of the reference voltage generation circuit and the output voltage of the step-down circuit are switched by one pad, and the direct measurement is performed. can do. In this case, the chip select signal CS, the row address strobe signal RAS, the column address strobe signal CAS, and the write enable signal WE are also the address signals A.
_{Since n is} also a signal necessary for normal storage operation, a new control signal is not required for switching the output voltage to the pad 2 and the number of pads does not increase due to its input. . That is, the number of pads is reduced by one in the entire storage device.

In the case of this embodiment, two pMOS transistors (P1, P2), a test circuit 14,
The number of wirings from the test circuit 14 to the gate electrodes of the pMOS transistors P1 and P2 increases. Address signal A
_It is necessary to add a configuration for selecting and activating and deactivating the test circuit 14 to the _n decoders. However, the area required for them is overwhelmingly smaller than the area per pad, so the overall chip
The area can be reduced by one pad. For example, in a typical large-capacity DRAM of 128 megabits or the like, each pad generally has a square shape of about 100 μm × 100 μm. On the other hand, in a large-capacity storage device of, for example, about 128 Mbits, MOS transistors forming an internal circuit in a chip typically include:
A channel having a channel length of about 1.0 μm and a channel length of about 0.7 μm is used. As described later, the test circuit 14, at most can configure about eight MOS transistors, also, Deco address signal A _n - so also the transistors required to configure additional Da estimated at several approximately,
The area which increases due to the above-mentioned test circuit 14 or the above-mentioned reason is only a few percent of one pad. In addition, in the case of pads, since they must be regularly arranged at the edge of the chip, etc., an increase in the number of pads immediately affects the chip area, whereas MOS transistors P1 and T1 as transistors and switches in the test circuit are used. P2
Alternatively, the wiring and the like can be laid out in a dead space or the like on the chip. Therefore, it can be said that there is no influence on the chip area in extreme cases.

In this embodiment, between the output point of the reference voltage generating circuit 12 and the pad 2 and between the step-down circuit 1
Although a p-channel type MOS transistor is used as the MOS transistor inserted between the output point No. 3 and the pad 2, these transistors may be constituted by n-channel type MOS transistors. In this case, however, the pad 2 and the output point of the reference potential generating circuit 12 and the pad 2 and the step-down circuit 1
3 between the output points, the so-called “threshold drop” in the nMOS transistor (in the nMOS transistor,
When the drain voltage and the gate voltage are given, a potential difference occurs due to a phenomenon that the source voltage does not become more than a voltage obtained by subtracting the threshold voltage of the transistor from the gate voltage), so that the reference voltage V _REF and the step-down power supply voltage V _INT To measure accurately, the voltage value of the measured pad 2 must be
It is necessary to make correction based on the threshold voltage of the transistor.

Next, a second embodiment of the present invention will be described. FIG. 3 is a diagram schematically showing an example of a layout of a chip in a semiconductor memory device according to a second embodiment of the present invention. Comparing FIG. 3 with FIG. 1, chip 1B according to the present embodiment is different from chip 1A according to the first embodiment in that nMOS transistors N1 and N2 are used instead of pMOS transistors. point, the gate electrode thereof nMOS transistors N1, N2, a boosted output voltage V _B from the booster circuit 15, and a point is input through the pMOS transistor P3, P4 respectively, the pMOS transistor P3, P4, test The point is that they are turned on and off complementarily by the signals C1 and C2 from the circuit 14.

The booster circuit 15 boosts the external power supply voltage V _cc to a higher voltage V _cc + α (= V _B ). For example, in a large-capacity DRAM, a booster circuit 15 starts with a memory cell of one transistor and one capacitor. In order to prevent a signal voltage read to the data line or written to the memory cell from the data line from being lowered by a threshold drop in the nMOS transistor as a switch,
It is for applying a high voltage to a word line, and is conventionally an indispensable circuit for a large-capacity semiconductor memory device. In the present embodiment, since the booster circuit mounted on such a conventional semiconductor memory device is used as it is, it is not necessary to newly provide the booster circuit 15 and the chip area does not increase.

FIG. 4 shows an operation waveform of each signal in the present embodiment. Referring to FIG. 4, in the present embodiment, as in the first embodiment, at time T20, row address strobe signal RAS, column address strobe signal CAS, and write enable signal WE become high. The rising edge of the clock signal CLK immediately after falling from the low level to the low level (time T21)
The test mode is entered from the normal storage operation mode.

When the storage device is in a normal storage operation mode before time T21, the test circuit 14 is in an inactive state and outputs a high-level signal C1 and a low-level signal C2. Therefore, the transistor P3 of the two pMOS transistors connected to the output point of the test circuit 14 is off. On the other hand, pMO
The S transistor P4 is in the ON state and the pad 2
The gate electrode of the nMOS transistor N2 is connected to, and transmits the output voltage V _B of the booster circuit 15. As a result, the transistor N1 of the two nMOS transistors connected to the pad 2 is turned off,
The S transistor N2 is in the ON state and the pad 2
Outputs the internal power supply voltage V _INT output from the step-down circuit 13. At this time, the output voltage V of the booster circuit 15 applied to the gate electrode of the nMOS transistor N2
_{Since B} has been boosted to a voltage of V _CC + α higher than the power supply voltage V _CC, there is no threshold drop in the nMOS transistor N2. Therefore, the internal power supply voltage V
_INT is output as it is, and there is no need to correct the measured value of the internal power supply voltage _VINT .

Next, when the storage device enters the test mode at time T21, at the same time, the output signal C1 of the test circuit 14 changes from the previous high level to the low level, and the signal C2 changes from the low level to the high level. . As a result, the transistor P3 of the two pMOS transistors connected to the test circuit 14 switches from the off state to the on state, and the pMOS transistor P3
4 changes to the off state. As a result, of the two nMOS transistors connected to the pad 2, the transistor N
1 is changed from the OFF state to the ON state given the output voltage V _B of the booster circuit 15 to the gate electrode, whereas, nMOS
The transistor N2 changes from the on state to the off state,
The reference voltage V _REF output from the reference voltage generation circuit 12 is output to the pad 2. At this time, the gate electrode of the nMOS transistor N1 has V _CC + higher than the power supply voltage V _CC.
Since the output voltage V _B of the booster circuit 15 which is the voltage α is applied, there is no threshold voltage drop of the nMOS transistor N1. Accordingly, the reference voltage V _REF is output to the pad 2 as it is, and there is no need to correct the measured value.

FIG. 5 shows a circuit diagram of an example of the test circuit 14 in the present embodiment. Test circuit 1 shown in FIG.
4, the decode output of the address signal A _n is activated at the high level, when the decode output is at a low level in an inactive state. Now, when the decode output is low level and the test circuit 14 is in the inactive state, that is, before the time T21 in the timing chart shown in FIG. 4, the nMOS transistor N5 is on, the N7 is off, and the pMOS transistor P4 is It turns on.
Further, the nMOS transistor N6 is off, the N8 is on, and the pMOS transistor P3 is off.
Therefore, in FIG. 3, the nMOS transistor N2 is
Since the boosted voltage V _B = V _CC + α is applied to the gate electrode via the pMOS transistor P 4, the gate electrode is turned on, and the output voltage V _INT of the step-down circuit is output to the pad 2. On the other hand, nMOS
Transistor N1 cuts off between the output point of reference voltage generating circuit 12 and pad 2.

On the other hand, when the decode output is low level and test circuit 14 is inactive, ie, after time T21 in the timing chart shown in FIG.
When the S transistor N5 is off and N7 is on, p
MOS transistor P4 is turned off. Also, nMO
When the S transistor N6 is on and N8 is off, p
MOS transistor P3 is turned on. Thus, in FIG. 3, nMOS transistor N1 becomes conductive because given the boosted voltage V _B to the gate electrode through the pMOS transistor P3, the output voltage V of the reference voltage generating circuit
_REF is output to pad 2. On the other hand, the nMOS transistor N2 cuts off between the output point of the step-down circuit 13 and the pad 2.

As an example, the test circuit 14 shown in FIG.
Naturally, the present invention can be applied to the storage device according to the first embodiment. However, in the second embodiment, unlike those of the first embodiment, on a step-up voltage V _B, so off, nMOS transistor N5 in the test circuit 14,
Considering that a high electric field is applied to N6, the first gate having a gate width of about 3.0 μm and a gate length of about 1.0 μm is used.
It is preferable to use a transistor having a larger size than that of the embodiment. Further, compared with the first embodiment, two additional pMOS transistors P3 and P4 are required. Therefore, the area is larger than that of the first embodiment, but the increase is negligible compared to the area of one pad.

[0029]

According to the present invention, two pads which are conventionally required for monitoring and measuring the output voltage of the reference voltage generating circuit and the output voltage of the step-down circuit can be shared by the same one pad. The chip area can be reduced by the reduced number.

A pMOS transistor or an nMOS transistor can be used for the analog switch. When an nMOS transistor is used as an analog switch, it is necessary to correct a measured value based on a phenomenon in which the threshold voltage of the nMOS transistor drops. In this case, the output voltage of a booster circuit usually mounted in a conventional storage device is required. If input is made to the gate electrode of the nMOS transistor as an analog switch, correction of the measured value is not required.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an example of a layout of a chip in a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms of respective signals in the first embodiment.

FIG. 3 is a diagram schematically illustrating an example of a layout of a chip in a semiconductor memory device according to a second embodiment of the present invention;

FIG. 4 is a diagram illustrating operation waveforms of respective signals according to the second embodiment.

FIG. 5 is a diagram illustrating a circuit diagram of an example of a test circuit.

FIG. 6 is a diagram showing an example of a relationship among an external power supply voltage, an internal power supply voltage, and a reference voltage in a semiconductor memory device.

FIG. 7 is a diagram schematically illustrating an example of a layout of a chip in a semiconductor memory device according to a conventional technique.

[Explanation of symbols]

 1A, 1B, 1C chip 2 pad 11A, 11B test circuit block 12 reference voltage generation circuit 13 step-down circuit 14 test circuit 15 step-up circuit 20, 21 pad

Claims (8)

[Claims] 1. A step-down circuit for stepping down a power supply voltage applied from outside, a reference voltage generating circuit generating a voltage independent of the power supply voltage on a chip, and testing a semiconductor memory device in response to an external signal A test circuit block for switching to a mode to test the function of the semiconductor memory device, and at least a plurality of pads for electrical connection to the outside of the chip; and one pad with an output point of the reference voltage generation circuit And an analog switch respectively connected between the output point of the step-down circuit and the one pad; and opening and closing the analog switch depending on whether or not the semiconductor memory device enters a test mode. Switching means for switching the opening and closing of one analog switch and the opening and closing of the other analog switch so as to be complementary to each other; The semiconductor memory device characterized in that it comprises. 2. The semiconductor memory device according to claim 1, wherein a MOS field effect transistor is used for said analog switch. 3. The semiconductor memory device according to claim 2, wherein said MOS field effect transistor is of a p-channel type. 4. The semiconductor memory device according to claim 2, wherein said MOS field effect transistor is of an n-channel type. 5. A booster circuit on a chip for boosting an externally applied power supply voltage and supplying the boosted voltage to a gate electrode of each of the n-channel MOS field effect transistors, wherein a supply destination of an output voltage of the booster circuit is provided. 5. The semiconductor memory device according to claim 4, wherein the switching means switches the conduction and non-conduction of the two n-channel MOS field-effect transistors in a complementary manner. 6. A step-down circuit for stepping down a power supply voltage applied from the outside on a chip, a reference voltage generating circuit for generating a voltage independent of the power supply voltage, and whether or not the semiconductor memory device enters a test mode A test circuit for outputting two signals complementary to each other, a plurality of pads for electrical connection with the outside, an output point of the step-down circuit, and one of the plurality of pads. A first p-channel MOS field-effect transistor connected to form a current path between the first and second pads, and a current path connected between an output point of the reference voltage generation circuit and the one pad. And a second p-channel MOS field-effect transistor, comprising: two complementary output signals of the test circuit; A semiconductor memory device, wherein one of the gates is assigned to each of the gates and input. 7. A step-down circuit for stepping down a power supply voltage applied from the outside on a chip, a reference voltage generating circuit for generating a voltage independent of the power supply voltage, and whether or not the semiconductor memory device enters a test mode A test circuit for outputting two signals complementary to each other, a plurality of pads for electrical connection with the outside, an output point of the step-down circuit, and one of the plurality of pads. A first n-channel MOS field-effect transistor connected to form a current path between the first and second pads, and a current path connected between an output point of the reference voltage generation circuit and the one pad. And a second n-channel MOS field-effect transistor, wherein the two complementary output signals of the test circuit are supplied to the first and second n-channel MOS field-effect transistors. A semiconductor memory device, wherein one of the gates is assigned to each of the gates and input. 8. A step-down circuit for stepping down an externally applied power supply voltage on a chip, a reference voltage generation circuit for generating a voltage independent of the power supply voltage, and whether or not the semiconductor memory device enters a test mode A test circuit that outputs two signals complementary to each other, a circuit that boosts the power supply voltage, a plurality of pads for electrical connection with the outside, an output point of the step-down circuit, and the plurality of pads. A first n-channel MOS field-effect transistor connected so as to form a current path with one of the pads, and between the output point of the reference voltage generation circuit and the one pad A second n-channel MOS field-effect transistor connected to form a current path, an output point of the booster circuit, and the first n-channel MOS
An analog switch connected to form a current path between the gate electrode of the field effect transistor and an analog switch whose opening and closing are controlled by one output signal of the test circuit; and an output point of the booster circuit. The second n-channel MOS
A semiconductor switch comprising: an analog switch connected to form a current path with a gate electrode of a field-effect transistor, wherein the analog switch is controlled to be opened and closed by the other output signal of the test circuit. Storage device.