JP2001148427A - Improved method for simulation of soi element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simulate an SOI element by setting a floating body voltage to an optional desired value at the optional point of time during simulation by an electronic design model encoded by design software for the FET logic design of an SOI base. SOLUTION: An ideal voltage source having a desired floating body voltage value is added to a model serially to an ideal current source having the value of the constant multiple of a voltage applied to itself. In the case a constant is zero, a current does not flow and an additional element does not affect a circuit. If the constant is not zero, the ideal current source is considered the same as a resistor, the current flows into a floating body node or flows out from there and the voltage is set. Other than the time of desiring the change of the floating body voltage, the constant is maintained at zero at all times. An improved process judges whether or not an element is classified into one of some categories by the topology analysis of a circuit element and decides which element of the circuit is in AC balance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to silicon-on-insulator (SOI) integrated circuits, and more particularly, to delay calculations used in creating circuit designs.
The present invention relates to a method for considering an OI FET floating body voltage.

[0002]

BACKGROUND OF THE INVENTION In the context of the methods described herein, simulations have been used in the formation of silicon devices, which include a process known as silicon-on-insulator (SOI) that forms SOI devices. The thin film element to be formed is included. SOI device performance depends on the current voltage on the floating body of the device (including the circuit). This floating body voltage further depends on the switching history of the element (or circuit). The simulations used to create silicon devices (including circuits) include a conventional delay measurement process, but until the development of the technology described in the related application, a known method has a way to account for the effects of current floating body voltages. Simulation technology did not exist. Conventional methods that take into account the hysteresis effect of the current floating body voltage required either simulating the exact history in question or limiting the problem. Neither method is applicable to delay rules, and neither method allows for modification of simulation ordering within one run. In theory, consideration of the effect of the current floating body voltage is possible by simulating the entire switching history, but this is not practical and therefore the conventional delay estimation process uses a method to account for this effect. Did not have any. In addition, the use of simulation history was not acceptable because the usual procedure was to measure delays for several different loads within one simulation run. This dependence on the history of the simulation provides different and unpredictable results depending on the order of the simulation runs.

[0003] The present inventors have concluded that there is a need for a method of simulating the above-described action, which can be used in a system used to simulate electrical delays, but such a method has not been described to date. However, it has not been achieved yet. Common examples of electrical simulation and design systems include the systems described in U.S. Patent Application No. 5,396,615 by Mitsubishi Electric Corporation and U.S. Patent Application No. 5,384,720 by Hitachi Microsystems.

[0004] There are numerous publications and patents that show how SOI devices have been treated in the past and what simulation techniques have been used. Among them are the documents referred to in the present application and prior applications. For example, Messrs. Dubois, (E), Shahidi, (G.
G. ) And Sun, (JYC) unpublished report from IBM on January 1993, "Analysis of the Speed."
Performance of ThinFilm CMOS / SOI Ring Oscillator
In s ", they analyzed the performance advantages of thin-film SOI / CMOS ring oscillators over bulk silicon counterparts using compact analytical modeling for circuit simulations, and found that SOI speed improvements over bulk at the time were significant. Sections state that they can be explained in terms of threshold voltage reduction, floating body doping factor, and junction capacitance.Based on DC current measurements of individual devices, their tabulated models provide high accuracy. Unresolved differences between the simulated and measured propagation delays were found in both approaches.The resultant current and the stored power in the ring oscillator The researchers found that this difference was due to an underestimation of the charge and discharge currents, and these researchers found that the dependence of the propagation delay on the supply voltage was By analysis, the transient increase in current is determined not to be the cause of this difference. SO for basic principle
The sensitivity of the DC current characteristic of the I element was discussed,
Circuit simulations have systematically accounted for poor prediction of delay per stage.
Although this report is internal to IBM, it does not show how to simulate the effects of current floating body voltages on SOI device designs, and expresses the disappointment of research in this area on inadequate prediction of delay by circuit simulation. ing.

The present inventors have concluded that there is a need in SOI circuit element design for a way to simulate the effects of current floating body voltages, but to date this has not been achieved by others. According to the work at IBM described in the prior application, the partially depleted SOI device is:
The accumulated electric charge is retained in the floating body of the element. This creates a "body voltage". The floating body voltage affects the threshold voltage (VT) of the device and thus the performance of the circuit.

Heretofore, this effect has not been significant in bulk silicon devices. First Related US Patent Application No. 938
No. 676 describes a method in which the floating body voltage is set randomly or set to track process changes. The actual measured floating body voltage is not completely random. The methods set forth in other related disclosures show how to attempt to more accurately describe the effects of floating body voltages.

[0007]

It would be desirable to improve upon these conventional solutions, and the present inventors describe a more specialized method of obtaining an estimate of the floating body voltage.
Although the method is less common than the parent application, more accurate results are obtained when the method is used.

[0008]

As described below, the inventor has developed a method for setting the floating body voltage to any desired value at any time during a simulation. The circuit analysis method set forth in the prior application selected the voltage on the SOI transistor floating body to limit all possible voltages.
The methods of the other referenced applications somewhat limit the possibilities. Here, we analyze which part of the circuit is in AC equilibrium and apply special processing to that part. We also consider the case where different parts of the circuit being analyzed have different histories, and recognize that the assumption that all transistors have a "slow" or "fast" history is not sufficient.

[0009] Again, the improvement gained by using the method is that designers can easily establish delay rules that work with their current design method by analyzing which parts of the circuit are in AC equilibrium. Enable. The designer can have multiple delay simulations within one run and get the same answer regardless of ordering. As a result of this method, performance limitations are identified and the designer does not have to keep trying different combinations of input and history to find the best or worst value. These and other improvements are set forth in the detailed description below. For a better understanding of the advantages and features of the present invention, please refer to the accompanying drawings and the following detailed description.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, the inventor of FIG.
The method used in the simulation model of the SOI device was developed in connection with. The method involves adding an ideal voltage source having a desired floating body voltage value to the model in series with an ideal current source having a value that is a constant (referred to as GJ) times the voltage applied to the model during simulation. Setting the floating body voltage to any desired value. FIG. 1 shows what the inventor calls a floating body, and the current floating body voltage is the current floating body voltage at a point B corresponding to the floating body. This figure is NFE
Applicable to either T or PFET. In this FIG. 1, the illustrated elements are described by labels at the bottom of FIG. In FIG. 1, reference numeral 1 represents an ideal voltage source, and reference numeral 2 represents an ideal current source.

If the constant GJ is zero, no current will flow and no additional elements will affect the circuit. If the constant GJ is non-zero, the ideal current source is considered the same as the resistor. Thus, current flows into or out of the floating node,
Set that voltage.

The constant GJ is always kept at zero except when it is desired to change the floating body voltage.

To select the value of the ideal voltage source that sets the desired floating body voltage, two steps are performed.
First, the static floating body voltage is calculated simply by considering the terminal voltage and the temperature of the device. This voltage is a voltage at which the floating body naturally settles after a long time without switching operation.

[0014] From its basic static voltage, the limits of this voltage change are found on the basis of the different types of switching operations possible. For example, increasing the gate voltage while keeping the drain and source voltages of the device constant provides a given effect on the floating body voltage.

Taking into account all possible switching types gives a range of possible voltage changes around the static floating body voltage. Depending on the type of simulation desired, one of these voltages is randomly selected to vary the static voltage to represent a device with an unknown switching history or to select a value corresponding to a known switching history Or choose the value that gives the best or worst delay.

Since the floating body voltage can be reset to any desired point in time, resetting the voltage before each delay measurement begins can solve the problem of continuous delay within one simulation run.

To solve the problem of estimating delay in the delay estimator (eg, delay rule generation), an offset from the floating body voltage can be included as part of the best / worst case decision. For example, to find the fastest delay of the circuit, in addition to selecting the fastest process and environmental variables, select the floating body voltage that gives the fastest delay. This can be done automatically, for example, by a distribution in IBM's AS / X (described below).

This method has been implemented in IBM's AS / X system for SOI simulation models and other circuit simulators such as SPICE.
It can be used by any designer using I-based FET logic. These methods are encoded in standard electronic design software, and they are generally described in their documentation.

It should be understood that in practice the voltages are not random. The improvement of the invention compared to FIG. 1 will be described in connection with the circuit of FIG. This is part of the standard latch circuit widely used in our circuit.

From FIG. 2 it can be easily seen that the path of interest leads from either of the two inputs to the circuit on the right. If a slow history is assumed for all transistors, the delay of the path is slow, and for a similarly fast history the delay is fast. However, in this circuit, delay is not the only item of interest. We are also interested in the relative times of arrival of signals from the "clock" and "data" inputs. This is used, for example, in latch setup time calculations.

In most systems, the clock runs repeatedly for long periods of time. Therefore, for example, the transistor T0
It can be readily seen that and T3 must be in AC steady state floating body voltage conditions.

However, data input is unpredictable. Its value depends on the exact calculations performed in this circuit. Therefore, if the data pattern is T2 and T5
It is necessary to assume that such transistors have a slow history. Alternatively, a fast history for these transistors or any other possible history between these values may be assumed.

Thus, by a simple topology analysis,
All transistors can be classified into categories based on their terminal signals. Here, T0 and T3
Are classified as "clock" transistors. Because their gates are connected to the clock signal and their drains and sources are connected to the power supply.

Similarly, T2 and T5 are classified as "data" transistors. This is because their gates are connected to data signals and their drains and sources are connected to a power supply. Here, the transistors T1 and T
4 is left behind. These are called "mixed" transistors. This is because their gates depend on the clock, and the source and drain have data-like characteristics. Less commonly, different types of "mixed" transistors have a data signal on the gate and a clock signal on the drain.

Accordingly, the present inventor has modified the previously disclosed transistor model to allow explicit specification of the type of history. The inventor realizes this in a range from a slow value to a fast value. The above topology analysis tells the category to which the transistor belongs. For example, a "clock" transistor is assigned to the case with only a balanced value. The reason for this is that the gate voltage is constantly switching. In contrast, the "data" transistor has to be assumed for the entire range of floating body voltage values since nothing is known about the history.

A simplification that can be achieved is to combine a "clock" transistor and a "mixed" transistor set. According to the simulation of the present invention, almost no inaccuracy occurs, and the topology analysis can be simplified. This step is optional, and all four types of transistors can be retained for detailed analysis.

The method can be implemented as a set of AS / X models for delay rule generation for standard library applications.

While the preferred embodiment of the present invention has been described above, those skilled in the art will be able to achieve various improvements and improvements, both now and in the future, within the scope of the present invention.

In summary, the following is disclosed regarding the configuration of the present invention.

(1) A method used in a simulation model of an SOI device including an SOI circuit, wherein which portion of the circuit is in AC equilibrium, and an ideal voltage source having a desired floating body voltage value is analyzed. At any point during the simulation to set the floating body voltage to any desired value by adding the model in series with an ideal current source having a value that is a constant multiple of the voltage applied to itself. Including methods. (2) The method according to (1), wherein when the constant is zero, no current flows and no additional element affects the circuit. (3) The method of (2) above, wherein if the constant is non-zero, the ideal current source is considered the same as a resistor and current flows into or out of the floating node and sets its voltage. (4) The method according to (3), wherein the constant is always kept at zero except when it is desired to change the floating body voltage. (5) To select the value of the ideal voltage source that sets the desired floating body voltage, first includes calculating the static floating body voltage simply by taking into account the terminal voltage and temperature of the device. The method according to (4), wherein the static floating body voltage is a voltage at which the floating body naturally settles after a long time without switching operation. (6) The method according to (5), wherein from the basic static voltage a limit of this voltage change is found based on different types of switching operations possible. (7) The limit of variation of the static floating body voltage is found by increasing the gate voltage to provide a given effect on the floating body voltage while keeping the drain and source voltages of the device constant. And the method according to (6). (8) different switching types are taken into account, and after taking into account all switching types, a range of possible voltage changes around the static floating body voltage is provided.
The described method. (9) The method of (5), including providing an offset from the floating body voltage as part of a best / worst case determination. (10) The method according to (5), further comprising the step of resetting the floating body voltage to any desired time during the simulation by resetting the floating body voltage before each delay measurement starts. (11) The method according to (1), wherein the method is encoded in design software for SOI-based FET logic design. (12) By analyzing which parts of the circuit are in AC equilibrium, at any point during the simulation, while examining the terminal signals of the circuit elements while setting the floating body voltage to any desired value. The method according to (1), wherein the element topology analysis is performed by determining a category to which the analyzed circuit element belongs. (13) The method according to (12), wherein the topology analysis is performed on a gate element, and in the analysis, it is determined whether the gate element is connected to a periodic signal. (14) The method of (13), wherein during the topology analysis, if it is determined that the gate element is switching repeatedly, the gate is determined to be in AC equilibrium. (15) The topology analysis targets the drain element,
The method according to (12), wherein the analysis determines whether the drain element is connected to a periodic signal. (16) The method according to (15), wherein during the topology analysis, if it is determined that the drain element is switching repeatedly, the drain element is determined to be in AC equilibrium. (17) The topology analysis includes a test of a plurality of circuit elements. In the analysis, it is determined whether or not the elements are connected to a periodic signal. If it is determined that none of the elements is connected to a periodic signal, the analysis is performed. The method according to (12), wherein no assumption is made regarding the category to which the circuit element belongs. (18) The topology analysis includes a test of the analyzed circuit including a plurality of circuit elements, and in the analysis, it is determined whether the elements are connected to a periodic signal, and one of the elements is determined.
The method of (12) above, wherein if one is connected to the periodic signal and the other is not connected to the periodic signal, it is determined that the analyzed circuit belongs to the category of mixed category circuit elements.

[Brief description of the drawings]

FIG. 1 shows what is called a floating body by the present inventor, and the current floating body voltage is a point B corresponding to the floating body.
It is a figure which shows the current floating body voltage in (internal floating body node).

FIG. 2 illustrates the improvements made to the disclosure of FIG.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor George E. Smith Third, U.S.A. 12590, Wappingers Falls, NY, Mina Drive 24 (72) Inventor Faribolz Asadaradij U.S.A. Stacy Lane 24 (72) Inventor Paul Di Muench 12603 United States, Cherry Hill Drive, Poughkeepsie, NY 1301 (72) Inventor Lawrence F. Wagner Jr. Fishkill, NY 12524-1403 USA Concord Road 22 (72) Inventor Timothy El Walters Linker, Poughkeepsie, NY 12601 United States of America Drive 19

Claims (18)

[Claims] 1. A method for use in a simulation model of an SOI device including an SOI circuit, comprising: analyzing which part of the circuit is in AC equilibrium; and determining an ideal voltage source having a desired floating body voltage value. Setting the floating body voltage to any desired value at any point during the simulation by adding to the model in series with an ideal current source having a value that is a constant multiple of the voltage applied to itself. Method. 2. The method of claim 1, wherein when the constant is zero, no current flows and no additional elements affect the circuit. 3. The method of claim 2, wherein if the constant is non-zero, the ideal current source is considered the same as a resistor, and current flows into or out of the floating node and sets its voltage. . 4. Except when a change in floating body voltage is desired.
4. The method according to claim 3, wherein said constant is always maintained at zero. 5. The step of calculating a static floating body voltage by simply considering the terminal voltage and temperature of the device to select the value of the ideal voltage source that sets the desired floating body voltage. 5. The method of claim 4, wherein the static floating body voltage is a voltage at which the floating body settles naturally after a long period of time without switching action. 6. The method as claimed in claim 5, wherein from said basic static voltage, the limits of this voltage change are found based on possible different types of switching operations. 7. The limit of said static floating body voltage change is to increase the gate voltage to provide a given effect on the floating body voltage while keeping the drain and source voltages of the device constant. 7. The method of claim 6, wherein the method is found. 8. The method of claim 6, wherein different switching types are considered, and after all switching types are considered, a range of possible voltage changes around the static floating body voltage is provided. 9. Providing an offset from the floating body voltage as part of a best / worst case decision.
The method of claim 5. 10. The method of claim 5, including the step of resetting the floating body voltage to any desired time during the simulation by resetting the floating body voltage before each delay measurement begins. 11. The method of claim 1, wherein said method is encoded in design software for SOI-based FET logic design. 12. By analyzing which part of the circuit is in AC equilibrium, at any point during the simulation, while setting the floating body voltage to any desired value, the terminal signals of the circuit elements are The method of claim 1, further comprising performing a topology analysis of the device by determining a category to which the analyzed circuit element belongs based on the survey. 13. The method of claim 12, wherein said topology analysis is directed to a gate element, and determining in said analysis whether said gate element is connected to a periodic signal. 14. The method of claim 13, wherein during the topology analysis, if it is determined that the gate element is switching repeatedly, the gate is determined to be in AC equilibrium. 15. The method of claim 12, wherein the topology analysis is directed to a drain element, and wherein the analysis determines whether the drain element is connected to a periodic signal. 16. The method of claim 15, wherein during the topology analysis, if it is determined that the drain element is switching repeatedly, the drain element is determined to be in AC equilibrium. 17. The method as claimed in claim 17, wherein the topology analysis includes a test of a plurality of circuit elements, and if the analysis determines whether the elements are connected to a periodic signal, and determines that none of the elements are connected to a periodic signal, 13. The method of claim 12, wherein no assumption is made about the category to which the analyzed circuit element belongs. 18. The method according to claim 18, wherein the topology analysis includes a test of the analyzed circuit including a plurality of circuit elements, wherein in the analysis it is determined whether the elements are connected to a periodic signal and one of the elements is connected to the periodic signal. 13. The method of claim 12, wherein if the other is not connected to the periodic signal, the analyzed circuit is determined to belong to a category of mixed category circuit elements.