CN1171168C - Improved method for simulating silicon-on-insulator devices - Google Patents

Abstract

To simulate an SOI element by setting a floating body voltage to an optional desired value at the optional point of time during simulation by an electronic design model encoded by design software for the FET logic design of an SOI base. An ideal voltage source having a desired floating body voltage value is added to a model serially to an ideal current source having the value of the constant multiple of a voltage applied to itself. In the case a constant is zero, a current does not flow and an additional element does not affect a circuit. If the constant is not zero, the ideal current source is considered the same as a resistor, the current flows into a floating body node or flows out from there and the voltage is set.

Description

Improved method for simulating silicon-on-insulator devices

technical field

The present invention relates to silicon-on-insulator integrated circuits, and more particularly to methods for solving SOI FET floating body voltages in delay calculations for creating circuit designs.

Background technique

This application, USSN 08/938,676 filed September 26, 1997, is an improvement and continuation-in-part of US Patent No. 6,023,577, published February 8, 2000, and claims priority from this application. The title of the invention is a method for simulating SOI devices, and the inventor is George E. Smith, III, et al.

Other related pending applications of inventors here, George E. Smith, III, and others include U.S.S.N. 09/294,045, Improving Methods for Statically Timing SOI Devices and Circuits, filed April 19, 1999; U.S.S.N.09/294,163, filed April 19, for improved methods of statically timed SOI devices and circuits; and U.S.S.N.09,294,178, filed April 19, 1999, for improved methods of statically timed SOI devices and circuits.

These pending applications have the same assignee as this application, International Business Machines Corporation, Armonk, New York.

The specifications of these copending applications are hereby incorporated by reference into this application.

Trademarks: S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, New York, USA. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.

As background to the methods that will be described, analog techniques have been used to produce silicon devices, including thin film devices, by the so-called silicon-on-insulator (also known as SOI) process to produce SOI devices. The performance of an SOI device is dependent on the current voltage on the floating body of the device (including circuitry). Whereas the bulk voltage depends on the switching history of the device (or circuit). Simulations for the production of silicon devices, including circuits, include conventional time-delay measurement processes, but prior to the development of the technology referred to in the related application, there was no simulation technique that addressed the effects of current body voltage. Existing approaches to address the effects of current body voltage history either require the simulation-accurate laws in question, or attempt to skip the issue. Neither method works with delay rules. Neither method allows correcting the order of simulations within a run. Theoretically, the effect of the current body voltage can be resolved by simulating the entire switching history, but this is not practical, so conventional delay estimation processes simply do not have the means to account for this effect. Furthermore, since it is common practice to measure delays for several different loads in one simulation run, the use of simulation history is not acceptable. Dependencies on the simulation history will give unpredictable results depending on the order in which the simulations are run.

We believe there is a need for a method of simulating the effects that can be used in systems that simulate electrical time delays, such as those illustrated in US Patent 5,396,615 to Mitsubishi Denki K.K. and US Patent 5,384,720 to Hitachi Micro Systems Inc. These two are only general examples of electrical modeling and design systems, the invention can also be used in other systems which have not been realized heretofore.

It should be noted that there are now numerous publications and patents on how others have utilized SOI devices and what analog techniques they have used. These include publications and prior applications cited in this patent publication, including an unpublished report in International Business Machines Corporation, Messrs. Dubois, (E.) January 1993; Shahidi, (G.G.) and Sun (J.Y.C. ), "Speed Performance Analysis of Thin-Film CMOS/SOI Diagnostic Oscillators," which, after analyzing the performance advantages of thin-film SOI/CMOS ring oscillators over their bulk silicon counterparts using small analytical models for circuit simulations, states that at time The speed improvement on SOI compared to bulk silicon can be explained in terms of threshold voltage, bulk doping coefficient and junction capacitance reduction. It is also possible to utilize their tabular model based on DC current measurements of individual devices for even greater accuracy. A residual bias between simulated and measured propagation delays was found in both methods. Comparing the overall current and the stored charge in a ring oscillator recognizes the source of this difference when underestimating the charge/discharge current. By analyzing the applied voltage and the propagation delay, the researchers determined that a momentary boost in current was not responsible for the difference. They discuss and find that the DC current characteristics of SOI devices are sensitive to grounding rules, systematically explaining the inaccurate prediction of the time delay for each stage with the help of current simulations. The report was internal to IBM, but it showed that there was no way to simulate the effect of current body voltage in the design of SOI devices, and stated that inaccurate predictions of delays made by circuit simulations in this field gave researchers caused frustration.

We conclude that a method of simulating the effect of current body voltage is needed in the design of SOI circuit devices, but no one else has achieved this method so far. In efforts described in past IBM applications, partially depleted SOI devices maintained stored charge in the bulk of the device. This charge results in a "bulk voltage". The bulk voltage in turn affects the threshold voltage (VT) of the device and thus affects the performance of the circuit.

In the past, for bulk silicon devices, this effect was not important. The first related application cited was USSN 08/938,676, filed September 26, 1997, now US Patent No. 6,023,577, published February 8, 2000, which describes a method for randomly setting the bulk voltage, Or a method of setting the body voltage through process changes. The actual measured body voltage is not completely random. This approach, shown in other related publications, shows an attempt to more accurately represent the effect of bulk voltage.

Needing to improve on the progress made in the past, we will introduce a more specialized method for estimating bulk voltage. Although the method is not as general as that in the parent application, it is more precise in its field of application.

Contents of the invention

As described below, we developed a method for setting the floating body voltage to any desired value at any point during the simulation. The method of analyzing the circuit given in the prior application selects a voltage for the body of the SOI transistor which limits all possible voltages. The approaches in the other mentioned applications somewhat narrow the possibilities. Here, we analyze which parts of the circuit are likely to be AC balanced and treat that part specifically. We also consider the case where different parts of the circuit being analyzed have different histories, and realize now that it is not sufficient to assume that all transistors have a "fast" or "slow" history.

Furthermore, by analyzing which parts of the circuit are likely to be in AC balance, the improvements achieved by using this method allow designers to easily establish delay rules that work with their current design methods. In a single run, designers can run multiple simulations and get the same results, regardless of the order. Due to our approach, there are now known performance limitations, but the designer does not have to keep trying different combinations of inputs and histories to discover best and worst case values. These and other improvements are set forth in the detailed description that follows. For a better understanding of the advantages and features of the present invention, refer to the following drawings and detailed description:

Description of drawings

Figure 1 shows what we call a floating body and the current body voltage at point B (internal floating body node), where B is the body.

FIG. 2 shows a modification of the disclosure of FIG. 1 .

Detailed ways

According to the present invention, with reference to Fig. 1, we have developed a kind of method for simulating the model of SOI device, generally comprise the following steps: by adding an ideal voltage source and its ideal current source in series in the model, during simulation Set the floating body voltage to any desired value at any time, where the value of the voltage source is the desired body voltage and the value of the current source is a constant (called GJ) times the voltage across it. As we said, Figure 1 shows what we call a floating body and the current body voltage is the current body voltage at point B (internal floating body node), where point B is the body. The diagram applies to both NFETs and PFETs. In FIG. 1 , the elements shown are described by reference numerals below FIG. 1 . In Figure 1, numeral 1 represents an ideal voltage source, and numeral 2 represents an ideal current source.

When the constant GJ is zero, no current flows and additional components have no effect on the circuit. When the constant GJ is non-zero, an ideal current source looks like a resistor. Accordingly, current can flow into or out of the bulk node to set the voltage of the bulk node.

The constant GJ is kept at zero except when the bulk voltage needs to be changed.

Selecting the value of the ideal voltage source to set the desired floating body voltage requires two steps. First, the static bulk voltage can be uniquely calculated by considering the terminal voltage and temperature of the device. This voltage is the voltage that the main body naturally determines after a long time without switching.

From this reference static voltage, according to the different types of possible switching actions, the limits of the voltage change can be found. For example, increasing the gate voltage of a device while keeping the source and drain voltages constant has a specific effect on the bulk voltage.

Considering all possible switching types will give the possible range of voltage changes around the static bulk voltage. Depending on the type of simulation desired, we can pick one of these voltages arbitrarily, change the quiescent voltage to represent the unknown switching history of the device, or choose a value based on the known switching history, or choose a given best or worst The value of the condition delay.

Since the bulk voltage can be reset at any time we want, we can solve the problem of continuous time delays in a simulation by resetting the voltage before starting each time delay measurement.

To address the problem of predicting delays in a delay predictor (eg, a delay rule generator), the offset from bulk voltage can be included as part of the best/worst case determination. For example, to find the fastest time delay for a circuit, in addition to choosing the fastest process and environmental variables, one can also choose the bulk voltage that gives the fastest time delay. For example, this can be done automatically by AS/X sold by IBM (described below).

This approach has been implemented by IBM's AS/X system or other circuit simulators such as SPICE using models that simulate SOI, and can be used by any SOI designer using FET-based logic. These methods can be coded into standard electronic design software and are usually described in their documentation.

Now, we must understand that voltages are not random in fact. Referring to Fig. 2, in the improvement we describe below, we will illustrate the circuit shown in Fig. 2 in comparison with Fig. 1 and subsequently. This is part of a standard latch circuit that is widely used in our circuits.

It is easy to see from Figure 2 that the path we care about is from one of the two inputs to the right side of the circuit. If it is assumed that all transistors have a slow history, it is clear that the delay of the path will also be slow, and similarly for the fast history, the delay will also be fast. However, delay is not the only concern in this circuit. We are also concerned with the relative time of arrival of the signals input by "clock" and "data". For example, this can be used to calculate the setup time of a latch.

In most systems, clocks run in a repetitive fashion for long periods of time. Thus, it will quickly become apparent that, for example, transistors T0 and T3 must be at the bulk voltage state of the AC steady state.

However, data input is unpredictable. Its value will be based on precise calculations performed in the circuit. Therefore, it needs to be assumed that the data pattern in transistors such as T2 and T5 has a slow history, for example. Also, there may be a fast history for these transistors, or any other possible history between these values.

Therefore, we can classify all transistors by simple topological analysis according to their terminal signals. Here, we can refer to T0 and T3 as "clock" transistors. This is due to the fact that their gates are connected to the clock signal, while their source and drain are connected to the power supply.

Similarly, T2 and T5 can be classified as "data" transistors. This is due to the fact that their gates are connected to the data signal, while their source and drain are connected to the power supply. This leaves transistors T1 and T4. We call them "hybrid" transistors because their gate depends on the clock signal and the source and drain have data-like characteristics. Although not commonly seen, another type of "hybrid" transistor has a data signal on the gate and a clock signal on the drain.

Therefore, we modified models of transistors published in the past to allow unambiguous assignment of historical types. This is achieved by ranging from slow to fast values. The topological analysis above tells us which class a transistor belongs to. For example, "clock" transistors need only be specified as balanced values. Since the gate voltage is switching all the time, we can do this. On the other hand, since the history is not known, it must be allowed to assume the full range of bulk voltage values for the "data" transistors.

Simplification can be done by merging "clock" and "mixed" groups of transistors. According to our simulations, this produces a small amount of error and allows for simplified topology analysis. This step is optional and all four types of transistors can be kept for detailed analysis.

Our approach can be implemented as a set of AS/X models for delayed rule generators for standard library usage.

While the preferred embodiment of the invention has been described, it should be understood that various modifications and enhancements will occur, now and in the future, to those skilled in the art within the scope of the following claims. These claims are intended to explain the proper scope of the invention first described.

Claims (18)

1. A method for use in a model for simulating an SOI device comprising an SOI circuit, comprising the steps of: By analyzing which parts of the circuit are likely to be in AC balance and adding an ideal voltage source in series with an ideal current source to the model, the floating body voltage can be set to any desired value at any time during the simulation, where the value of the voltage source is For the desired body voltage, the value of the current source is a constant multiplied by the voltage across it. 2. A method for use in a model according to claim 1, wherein when the constant is zero, no current flows and any additional element has no effect on the circuit. 3. The method for use in a model according to claim 2, wherein when the constant is non-zero, the ideal current source appears like a resistor whereby current can flow into or out of the body node, setting the voltage of the body node. 4. The method for use in a model according to claim 3, wherein said constant is kept at zero except when a change in bulk voltage is required. 5. A method for use in a model according to claim 4, wherein by choosing the value of the ideal voltage source will set the required floating body voltage, wherein first, only the static body voltage is calculated by considering the terminal voltage and temperature of the device, in this step The static body voltage mentioned in is the voltage naturally determined by the body after no switching action for a long time. 6. Method for use in models according to claim 5, wherein from said reference static voltage the limits of the voltage change are found according to the different types of possible switching actions. 7. The method used in the model according to claim 6, wherein by increasing the gate voltage of the device, while keeping the source and drain voltages constant will have a specific effect on the body voltage, it is found that the static body voltage changes limit. 8. Method for use in a model according to claim 6, wherein different switching types are considered and after all switching types are considered, the possible range of voltage changes around the static bulk voltage is given. 9. A method for use in a model according to claim 5, comprising providing an offset in body voltage as part of the best case/worst case determination. 10. A method for use in a model according to claim 5, including the step of resetting said bulk voltage at any time required in the simulation by resetting the voltage before each delay measurement is started. 11. The method for use in a model according to claim 1, wherein said method is coded into design software using SOI based on FET logic design. 12. A method for use in a model according to claim 1, wherein when setting the floating body voltage to any desired value at any moment during the simulation by analyzing which parts of the circuit are likely to be in AC balance, based on detecting the terminal signal of the circuit element The topology analysis of the device is carried out by determining the type of the analyzed circuit element. 13. The method for use in a model according to claim 12, wherein said topology analysis is for analyzing a gate element and determining in the analysis whether said gate element is connected to a periodic signal. 14. The method for use in a model according to claim 13, wherein the gate element is determined to be AC balanced if it is determined during the topology analysis that the gate element is repeatedly switched. 15. The method for use in a model according to claim 12, wherein said topology analysis is for analyzing a drain element and determining in the analysis whether said drain element is connected to a periodic signal. 16. The method for use in a model according to claim 15, wherein the drain element is determined to be AC balanced if it is determined that the drain element is periodically switched during the topology analysis. 17. The method for use in a model according to claim 12, wherein said topology analysis comprises testing a plurality of circuit elements, and determining in the analysis whether said elements are connected to a periodic signal, if both are not connected to a periodic signal, then No assumptions are made about the type of circuit element being analyzed. 18. The method for use in a model according to claim 12 , wherein said topology analysis comprises testing the analyzed circuit comprising a plurality of circuit elements, and determining in the analysis whether said elements are connected to periodic signals, if said elements If one of them is connected to a periodic signal and the other is not connected to a periodic signal, it is determined that the analyzed circuit is a mixed type of circuit element.

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