JP2001077127A - Compound semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a reactive product at a Schottky junction interface between an electrode and a semiconductor layer, and to prevent component elements of the electrode from diffusing into a semiconductor layer, and a component element of the semiconductor layer from diffusing into the electrode, in a method for manufacturing a compound semiconductor device. SOLUTION: A process where an impurity is introduced into a compound semiconductor layer 1 to form a first impurity introduction layer 3, a process where a nitride absorbing layer 4 and a nitride-containing high melting-point metal layer 5 are formed sequentially on the first impurity introduction layer 3, a process where the nitride-containing high melting-point metal layer 5 is patterned to form a first electrode G, a process where the nitride absorption layer 4 is patterned which becomes a part of the first electrode G, and a process where the compound semiconductor layer 1 is heated to activate the impurity while the nitrogen in the nitrogen-containing high melting-point metal layer 5 is absorbed into the nitrogen absorbing layer 4, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a compound semiconductor device and a method for manufacturing the same, and more particularly, to a compound semiconductor device having a Schottky electrode structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art A compound semiconductor device, in particular, a field effect transistor (FET) using gallium arsenide (GaAs),
Excellent in high speed and high frequency operation performance, such FE
Semiconductor devices with integrated T are used in digital application devices. In particular, a self-aligned MES (metal-semiconductor) formed by implanting n-type impurities at a high concentration into a GaAs layer using a high heat resistant gate electrode as a mask.
(emiconductor) FET is often used. Since the gate electrode is made of a high heat-resistant metal such as tungsten silicide, the impurity ion implanted region is 8
Activation at a temperature of 00 ° C. has the advantage that the Schottky junction of the gate electrode does not deteriorate and the manufacturing process can be simplified.

In order to improve the high-speed operation performance of the FET, the gate length has been shortened, and an LDD structure capable of suppressing the influence of the short channel effect caused by the shortened gate length has been adopted for the FET. Next, ME
The step of forming the SFET will be briefly described. First, Fig. 1 (a)
As shown in FIG. 7, an n-type active layer 102 is formed on a semi-insulating GaAs substrate 101 by introducing impurities by ion implantation. Subsequently, a gate electrode 103 made of a high heat-resistant metal such as tungsten silicide (WSi) is formed on the n-type active layer 1.
02.

[0004] Next, as shown in FIG.
A photoresist 104 is applied on the substrate 01, and is exposed and developed to form a window 104a in the FET formation region.
Thereafter, using the photoresist 104 and the gate electrode 103 as a mask, an n-type impurity is ion-implanted into the GaAs substrate 101 to form an n′-type active layer 105. Subsequently, after removing the photoresist 104, a Si layer is formed on the GaAs substrate 101.
An O ₂ film 106 is formed. Furthermore, as shown in FIG. 1 (c), after forming a photoresist 107 having a window 107a in the FET region on the SiO ₂ film 106, by etching the SiO ₂ film 106 by reactive ion etching Photos The SiO ₂ film 106 is left only under the resist 107 and on the side surfaces of the gate electrode 103. Si on the side of the gate electrode 103
The O ₂ film 106 is called a sidewall (S). Then, using the sidewall S, the gate electrode 103 and the photoresist 107 as a mask, an n-type impurity is ion-implanted into the GaAs substrate 101 and n ⁺
A mold active layer 108 is formed. The n ⁺ -type active layer 108 and the n'-type active layer 105 form an LDD structure.

After removing the photoresist 107 and the SiO ₂ film 106, as shown in FIG. 1D, the GaAs substrate 101
By heating 1, n-type impurities in n-type active layer 102, n′-type active layer 105 and n ⁺ -type active layer 108 are activated. After removing the annealing protective film 109,
When a source electrode 110s and a drain 110d are formed on the two n ⁺ -type active layers 109, respectively, as shown in FIG. 1E, the basic structure of the MESFET is completed. The source electrode 110s and the drain 110d are made of a material that makes ohmic contact with the GaAs substrate 101.

Incidentally, in order to suppress the short channel effect, not only adopting the LDD structure as described above but also making the n-type active layer 102 shallower has been studied. However, when the n-type active layer 102 is made thin, there is a problem that the resistance between the source and the drain becomes large. In order to reduce the resistance of the n-type active layer 102, it is necessary to increase the substrate heating temperature for activating the n-type impurity to increase the impurity activation rate. When the substrate heating temperature is increased, it is important that the gate electrode 103 is not deteriorated. As a constituent material of the gate electrode 103, tungsten nitride silicide (WSiN) having higher heat resistance than tungsten silicide, The application of a refractory metal containing nitrogen, such as titanium tungsten nitride (TiWN), is being studied.

When the substrate heating temperature increases, arsenic (As) in the GaAs substrate 101 diffuses into the WSi film through the crystal grain boundaries of the WSi film serving as the gate electrode.
Voids are generated in the portion of the crystal 1 from which arsenic has escaped. Silicon is generally used as the n-type impurity,
When silicon moves in the GaAs substrate 101 and enters the As vacancy during the heat treatment for activating the impurities, the silicon acts as an acceptor, the electron concentration decreases at the Schottky contact surface, and the n-type active layer 102 Has a high resistance value.

On the other hand, when the gate electrode 103 is formed using WSiN as a constituent material, arsenic in the GaAs substrate 101 is unlikely to diffuse into the gate electrode 103 because the WSiN film has an amorphous and dense film quality. It has been known. In order to obtain a sufficiently dense WSiN film, a certain nitrogen content is required. However, if the nitrogen content is too high and exceeds a certain value, a reaction product is likely to be generated between the WSiN film and the GaAs layer. Regarding the generation of the reaction product, for example,
J. Vac. Sci. Techno. B 14 (6). Pp3543-3549, 1996.

When the reaction product is formed, the Schottky characteristics deteriorate, the Schottky barrier height decreases, and the reverse breakdown voltage deteriorates. Further, when such a reaction product is generated in the MESFET, there is a problem that the formation of the reaction product proceeds in the channel, and eventually the channel is cut off, thereby hindering the FET operation. In order to solve such a problem, a structure using a WSiN film having a nitrogen content of less than 20 atoms% as a gate electrode has been disclosed in Japanese Patent Laid-Open Publication No. H10-163,873.
It is described in 8-64619.

A gate electrode is formed from a two-layer structure of a WSi film and a WSiN film on a GaAs layer to form a Schottky barrier between the GaAs layer and the WSi film.
% of the first WSiN film and the second WS having a large nitrogen content
The gate electrode is formed from the two-layer structure of the iN film, and the GaAs layer and the first are formed.
A structure in which a Schottky barrier is formed between the WSiN films described in JP-A-8-64618 is described.

[0011]

However, even in a FET using a WSiN film having a nitrogen content of less than 20 atom% as a gate electrode, when the FET is continuously energized or when the temperature is higher than room temperature. When the FET is operated for a long time, the reaction product due to nitrogen gradually grows at the Schottky junction, and the Schottky characteristic and the FET characteristic may gradually change. In addition, since the nitrogen content is limited to less than 20 atoms%, the denseness of the atomic arrangement is not sufficient to suppress arsenic diffusion, and the temperature for activating the impurities may be significantly increased. Can not.

Such a problem also occurs in an FET using a WSiN film having different upper and lower nitrogen contents as a gate electrode. In the FET having a gate electrode based on the two-layer structure of the WSi film and the WSiN film, the WSi film needs to have a certain thickness in order to prevent nitrogen in the WSiN film from penetrating the WSi film and reaching the GaAs layer. become. In this case, the problem that arsenic in the Schottky junction diffuses into the WSi film through the WSi grain boundary and the resistance of the channel increases, that is,
The same problem occurs when the gate electrode is composed of a single layer of WSi. However, in that FET, the diffusion of arsenic into the gate electrode stops at the interface between the WSi film and the WSiN film, so that the amount of arsenic loss in the channel region is smaller than when the gate electrode is composed of a single WSi layer. As a result, the resistance of the channel does not decrease significantly. However, when the gate length is reduced and the channel thickness is further reduced to suppress the short channel effect, arsenic loss cannot be ignored.

An object of the present invention is to prevent the formation of reaction products at the Schottky junction interface between an electrode and a semiconductor layer, to prevent the constituent elements of the electrode from diffusing into the semiconductor layer, and to further prevent the constituent elements of the semiconductor layer from being diffused. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can prevent the diffusion of the semiconductor device into the electrodes.

[0014]

Means for Solving the Problems (1) The above-mentioned problems are:
As shown in FIGS. 3 (d), 5 (c), 7 (c), and 10 (c), a nitrogen-containing layer is formed on the compound semiconductor layer and forms a Schottky junction with the compound semiconductor layer. The problem is solved by a compound semiconductor device having a high melting point metal layer and a stoichiometric metal nitride layer formed between the high melting point metal layer and the compound semiconductor layer.

In the compound semiconductor device, the compound semiconductor may be gallium arsenide. In the compound semiconductor device, it is preferable that the metal nitride layer has a barrier property against element diffusion. In the compound semiconductor device, the metal nitride layer may be titanium nitride or titanium tungsten nitride. (2) As shown in FIGS. 2 and 3,
Forming a first impurity-doped layer by introducing impurities into the compound semiconductor layer, forming a nitrogen-absorbing layer and a nitrogen-containing high-melting-point metal layer on the first impurity-doped layer in order, Patterning the refractory metal layer to form a first electrode; patterning the nitrogen absorbing layer to become a part of the first electrode; and heating the compound semiconductor layer to form the first electrode. And simultaneously absorbing nitrogen in the nitrogen-containing high-melting metal layer into the nitrogen-absorbing layer.

In the method for manufacturing a compound semiconductor device, the nitrogen absorbing layer may be continuously patterned as the first electrode under the same conditions as the nitrogen-containing high melting point metal layer. In the method for manufacturing a compound semiconductor device, as shown in FIGS. 2 and 3, after patterning the nitrogen-containing high melting point metal layer and before heating the compound semiconductor layer, the first electrode is Forming a second impurity-doped layer having a higher impurity concentration than the first impurity-doped layer on both sides of the electrode by introducing an impurity into the compound semiconductor layer by using the mask as a mask, further comprising: And forming a second and third electrode in ohmic contact on each of the second impurity introduction layers on both sides of the first electrode after heating the compound semiconductor layer.

In the method of manufacturing a compound semiconductor device, as shown in FIGS. 6 and 7, after the nitrogen-containing high melting point metal layer is patterned and before the compound semiconductor layer is heated, the first Using the electrode as a mask, introducing an impurity into the compound semiconductor layer through the nitrogen absorption layer, and forming a second impurity introduction layer having a higher impurity concentration than the first impurity introduction layer on both sides of the first electrode. Forming, forming sidewalls on both sides of the first electrode, introducing impurities into the compound semiconductor layer through the nitrogen absorption layer using the first electrode and the sidewalls as a mask. Forming a third impurity-doped layer having a higher impurity concentration than the second impurity-doped layer on both sides of the electrode; removing the sidewall; Patterning the nitrogen-absorbing layer using a pole as a mask, and further comprising, after heating the compound semiconductor layer, a top surface of each of the third impurity-doped layers on both sides of the first electrode. A step of forming second and third electrodes that make ohmic contact with the second electrode.

In the method of manufacturing a compound semiconductor device, as shown in FIGS. 8 to 10, after the patterning of the nitrogen-containing high melting point metal layer and before the heating of the compound semiconductor layer, the first Forming side walls on both sides of the first electrode, and using the first electrode and the side walls as a mask to introduce an impurity into the compound semiconductor layer through the nitrogen absorption layer; Forming a second impurity introduction layer having a high impurity concentration on both sides of the electrode, removing the sidewall, and patterning the nitrogen absorption layer using the first electrode as a mask. And the first
By introducing an impurity into the compound semiconductor layer using the electrode as a mask, the third impurity-doped layer having an impurity concentration higher than the first impurity-doped layer and lower than the second impurity-doped layer is formed as the third impurity-doped layer. Forming in a region between the first electrode and the second impurity-introduced layer, further comprising, after heating the compound semiconductor layer, forming the second impurity-introduced layer on both sides of the first electrode. A step of forming second and third electrodes in ohmic contact with each other may be provided.

In the above-described method for manufacturing a compound semiconductor device, the removal of the sidewall and the patterning of the nitrogen absorption layer may be performed using the same etchant. In the method for manufacturing a compound semiconductor device described above, the nitrogen absorption layer may be used as an etching stop layer when the nitrogen-containing high melting point metal layer is patterned to form the first electrode.

In the above-described method for manufacturing a compound semiconductor device, the sidewall is formed by forming an insulating film on the compound semiconductor layer and the first electrode, and thinning the insulating film by dry etching. It may be formed by being left only on the side wall of the first electrode, and at the time of dry etching, the nitrogen absorption layer may be used as an etching stopper.

In the above-described method for manufacturing a compound semiconductor device, a step of forming a low-resistance metal layer on the uppermost portion of the gate electrode to form a T-shape may be further provided. The nitrogen absorption layer may be selected from a titanium layer and a titanium tungsten layer, and a gallium arsenide layer may be used as the compound semiconductor layer. Next, the operation of the present invention will be described.

According to the present invention, a nitrogen absorbing layer such as titanium or titanium tungsten is interposed between a compound semiconductor layer for Schottky junction and a nitrogen-containing high melting point metal layer, and thereafter, impurities in the compound semiconductor layer are activated. In the heat treatment for conversion to nitrogen, nitrogen diffused from the nitrogen-containing high melting point metal is absorbed. Thereby, since nitrogen bonds with the constituent elements of the nitrogen absorption layer, the formation of a reaction product due to nitrogen at the Schottky junction interface can be prevented. Further, since the compound bonded to nitrogen by heat in the nitrogen absorption layer is stable and has a barrier property to prevent diffusion of the element, mutual diffusion of the element between the high melting point metal and the semiconductor layer is suppressed.

The nitrogen compound formed by such heat is more stoichiometric than the nitrogen compound formed from the beginning by sputtering or the like, and is in a state where nitrogen is hard to diffuse.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 2 and 3 are cross-sectional views showing steps of manufacturing a semiconductor device according to a first embodiment of the present invention.

First, as shown in FIG.
A photoresist 2 is applied on the GaAs substrate 1, and is exposed and developed to open a window 2a in the transistor formation region. Subsequently, an n-type active layer 3 having a depth of about 10 to 15 nm is formed in the transistor formation region of the GaAs substrate 1 by implanting silicon ions (Si ⁺ ) into the GaAs substrate 1 through the window 2a. In this case, the silicon ions are 2 ×
It is implanted at a dose of 10 ¹¹ to 1 × 10 ¹³ / cm ² .

After the photoresist 2 is removed, titanium (T) is deposited on the GaAs substrate 1 as shown in FIG.
i) The nitrogen absorbing layer 4 made of 18 to 22 is sputtered.
nm thick, and then a tungsten nitride silicide (WSi) having a nitrogen content of 30 atoms% is formed on the nitrogen absorbing layer 4.
N) Layer 5 was coated with a reactive sputtering method to form 360 to 44
It is formed to a thickness of 0 nm. When the WSiN layer 5 was formed by the reactive sputtering method, a gas obtained by mixing argon and nitrogen at a ratio of 10: 2 was used, and tungsten silicide (WSi) was used as a target.

Further, a photoresist 6 is formed on the WSiN layer 5.
Is applied and exposed and developed to a width of 0.2 to 0.4 μm.
Gate electrode shape. The width is generally called a gate length, and is a length in a direction from the source to the drain. next,
As shown in FIG. 2C, the WSiN layer 5 is etched using the photoresist 6 as a mask to form a gate electrode. The etching of the WSiN layer 5 is performed by mixing SF ₆ , CHF ₃ and N ₂ in a ratio of 1: 4.
ECR plasma dry etching using a gas mixed at a ratio of 3: 3. At the time of this etching, the high frequency power was set to 10 W. Under such etching conditions, the etching rate of the titanium layer constituting the nitrogen absorption layer 4 is small, so that the nitrogen absorption layer 4 functions as an etching stopper when the WSiN layer 5 is etched.

After removing the photoresist 6,
As shown in FIG. 2D, a portion of the nitrogen absorption layer 4 exposed from the WSiN layer 5 is removed with a high concentration hydrofluoric acid (C-HF) solution. In this case, since the nitrogen absorption layer 4 is as thin as about 20 nm, side etching does not occur even by wet processing. The nitrogen absorption layer 4 and the WSiN layer 5 patterned on the GaAs substrate 1 as described above are used as the gate electrode G.

Next, as shown in FIG.
A photoresist 7 is applied on the substrate, and the photoresist 7 is exposed and developed to open a window 7a in the element formation region. Thereafter, silicon ions (Si ⁺ ) are implanted into the GaAs substrate 1 by using the photoresist 7 and the gate electrode G as a mask.
An n′-type active layer 8 is formed in the GaAs substrate 1 on both sides of the gate electrode G.
s, 8d are formed. In this case, silicon ions are implanted under the conditions of a dose of 5 × 10 ¹³ / cm ² and an acceleration energy of 40 keV.

Further, after removing the photoresist 7, a 300 nm thick silicon dioxide (SiO ₂ ) layer 9 is formed as an insulating film on the surface of the GaAs substrate 1 and the gate electrode G. Next, a photoresist 10 is applied on the SiO ₂ layer 9, and is exposed and developed to form a window 10a in the element formation region.
Open. Subsequently, the SiO ₂ layer 9 exposed from the window 10a is vertically etched by a reactive ion etching method, an inductively coupled (ICP) plasma etching method or the like, and as shown in FIG. Only the side wall 9a is left on the side surface of the gate electrode G.

Further, silicon ions are implanted into the GaAs substrate 1 using the side wall 9a, the gate electrode G, and the photoresist 10 as a mask, thereby forming two regions of the GaAs substrate sandwiching the gate electrode G and the side wall 9a. The n ⁺ -type active layers 11 s and 11 d are formed in 1. In this case, silicon ions are implanted under the conditions of a dose of 5 × 10 ¹³ / cm ² and an acceleration energy of 70 to 90 keV.

The n ⁺ -type active layers 11 s and 11 d and n ′
The LDD structure is constituted by the active layers 8s and 8d.
Thereafter, the photoresist 10 is removed, and the SiO ₂ layer 9 is further removed using a buffered hydrofluoric acid solution. Next, as shown in FIG. 3C, an annealing protective layer 12 made of silicon nitride, aluminum nitride, silicon oxide, or the like is formed on the gate electrode G and on the surface of the GaAs substrate 1. And the GaAs substrate 1
In order to activate the impurities introduced into the
Heat at a temperature of 0 to 870 ° C, for example, 860 ° C for, for example, 10 seconds.

At this time, the WSiN layer 5 constituting the gate electrode G
Since the nitrogen in the reacts with the titanium constituting the nitrogen absorbing layer 4 therebelow, a Ti-N bond is formed in the nitrogen absorbing layer 4,
At the same time, in the nitrogen absorption layer 4 on the interface side between the nitrogen absorption layer 4 and the GaAs substrate 1, titanium and arsenic react and extremely thermally stable Ti
-As bonds are formed. The TiN conversion of such a titanium layer
When the excess titanium is eliminated in the nitrogen absorption layer 4 due to the TiAs formation, the reaction stops, so that nitrogen does not reach the GaAs substrate 1.

Therefore, the interface between the gate electrode G and the GaAs substrate 1
The material of the nitrogen absorption layer 4 by heat treatment is titanium
To a titanium compound, and the gate electrode G
The formation of nitrogen reaction products between the GaAs substrates 1
Absent. After removing the annealing protection layer 12, FIG.
As shown in (d), one of n ⁺On the active layer 11s
To form a source electrode 13s in contact with the
⁺Electrode that makes ohmic contact with the active layer 11d
13d is formed.

Thus, the basic structure of the MESFET is completed. As described above, according to the present embodiment, since the nitrogen in the WSiN layer 5 is prevented from reacting with the GaAs substrate 1 by the nitrogen absorption layer 4, the nitrogen content of the WSiN layer 5 is made sufficiently large. No problem. In addition, the diffusion of arsenic from the GaAs substrate 1 into the gate electrode G at the Schottky junction interface is suppressed by the nitrogen absorption layer 4.

Therefore, even if the activation temperature is increased, the resistance of the channel region does not increase due to arsenic escape in the n-type active layer 3 immediately below the Schottky junction.
FET characteristics such as mutual conductance g _m is improved. Further, in the present embodiment, since a reaction product due to nitrogen is not generated between the gate electrode G and the GaAs substrate 1, the temperature is higher than that of a conventional WSiN single-layer gate electrode. However, the gate electrode G can maintain good Schottky characteristics, and does not cause fluctuations in FET characteristics due to reaction products.

Further, since TiN is a high heat-resistant barrier metal, it is stable during heat treatment and suppresses element mutual diffusion between the gate electrode G and the GaAs substrate 1 even for elements other than nitrogen and arsenic. Therefore, an extremely stable Schottky junction interface can be obtained. Since the titanium layer constituting the initial nitrogen absorption layer 4 is thin, the nitrogen absorption layer 4 is made of TiAs
The height φ _B of the barrier between the gate electrode G and the GaAs substrate 1 is determined by the Fermi level of WSiN and GaAs, even if it changes to TiN or TiN. Can be.

Further, in this embodiment, since the initial nitrogen absorption layer 4 is used as an etching stopper when etching the WSiN layer 5,
There is no adverse effect such as the removal of the surface of the GaAs substrate 1. Therefore, the cross-sectional areas of the n'-type active layers 8s and 8d are reduced by the thinning, so that the resistance between the source and the drain is increased and the mutual conductance is not reduced.

By the way, in this embodiment, titanium is used as the nitrogen absorption layer 4 and titanium nitride is formed therein by a subsequent heat treatment. However, a titanium nitride layer is formed between the GaAs substrate 1 and the WSiN layer 5 from the beginning. There are the following advantages as compared with the case of forming. That is, when the nitrogen concentration of the titanium nitride layer is low, since nitrogen is present in a solid solution state in titanium and does not form a Ti-N bond, the reaction product is generated by nitrogen that escapes from the titanium nitride layer. Are easily formed. When the nitrogen concentration of the titanium nitride layer is high,
Since excess nitrogen exists in a solid solution state in the titanium nitride layer formed by the -N bond, a reaction product due to nitrogen is also formed. Stoichiometric (stoichiometric)
Although titanium nitride has an extremely good barrier property, it is difficult to form stoichiometric titanium nitride by sputtering or the like.

Therefore, when a titanium nitride layer is formed on a GaAs substrate from the beginning, a reaction product layer due to nitrogen is likely to be formed between the gate electrode and the GaAs substrate.
On the other hand, in the present embodiment, nitrogen is diffused relatively slowly in the titanium layer (4) to achieve a constant concentration, and the stoichiometric titanium nitride layer is formed by the WSiN layer 5 and the GaAs substrate 1
Therefore, the possibility that surplus nitrogen remains in the titanium nitride layer is very small.

Since the thickness of the titanium layer constituting the nitrogen absorption layer 4 is smaller than the thickness of the WSiN layer, nitrogen in the WSiN layer 5 diffuses into the titanium layer and the nitrogen concentration changes. Also,
The amount of change is negligibly small. (Second Embodiment) In this embodiment, a process for forming a MESFET using tungsten nitride instead of a titanium layer as the nitrogen absorption layer shown in the first embodiment will be described.

FIGS. 4 and 5 are cross-sectional views showing steps of forming a semiconductor device according to the second embodiment of the present invention. In these figures, the same reference numerals as those in FIGS. 2 and 3 indicate the same elements. First, as shown in FIG.
In the GaAs substrate 1, n is formed in the same manner as in the first embodiment.
After forming the mold active layer 3, a nitrogen absorption layer 14 of tungsten nitride (TiW) having a thickness of 27 to 33 nm is formed on the GaAs substrate 1 by sputtering. Subsequently, a WSiN layer 5 having a thickness of 360 to 440 nm is formed on the nitrogen absorption layer 14.
To form Further, a photoresist 6 having a gate electrode shape is formed on the WSiN layer 5.

Note that a TiWN layer may be used instead of the WSiN layer 5. Next, as shown in FIG. 4 (b), the WSiN layer 5 and the nitrogen absorption layer 14 are successively etched using the photoresist 6 as a mask, and the resulting pattern is used as a gate electrode G. The etching is SF ₆
Using a gas that mixes CHF ₃ and N ₂ at a ratio of 1: 4: 3,
ECR plasma dry etching with high frequency power of 12 W is used. According to such conditions, since both the WSiN layer 5 and the nitrogen absorption layer 14 can be etched, the pattern formation of the gate electrode G is shortened as compared with the first embodiment.

Subsequently, after the photoresist 6 is removed, as shown in FIG. 4C, a photoresist 7 having a window 7a in an element formation region is formed on the GaAs substrate 1, and then the first embodiment is performed. Similarly to the above, silicon ions are implanted into the GaAs substrate 1 using the photoresist 7 and the gate electrode G as a mask to form n'-type active layers 8s and 8d in the GaAs substrate 1 on both sides of the gate electrode G. .

Further, the photoresist 7 is removed and GaAs
After the SiO ₂ film 9 is formed on the surface of the substrate 1 and the gate electrode G, a photoresist 10 having a window 10a in an element formation region is formed on the SiO ₂ film 9 as shown in FIG. Then, similarly to the first embodiment, the Si exposed from the window 10a is
By etching the O ₂ film 9 by the reactive ion etching method, the SiO ₂ film 9 is left only on the side surface of the gate electrode G in the element formation region, and this is
And

Next, as shown in FIG. 5A, silicon ions are implanted into the GaAs substrate 1 by using the photoresist 10, the gate electrode G and the side wall 9a as a mask to form the gate electrode G and the side wall. N ⁺ -type active layers 11s and 11d are formed in the GaAs substrate 1 in two regions sandwiching 9a. Further, after removing the resist 10 and the SiO ₂ film 9,
As shown in FIG. 5B, the annealing protective film 12
Cover the As substrate 1. Then, the GaAs substrate 1 is heated to, for example, 860 ° C.
At a temperature of 10 seconds for an impurity activation heat treatment.

At this time, the nitrogen in the WSiN layer 5 is
4 is absorbed in the TiW layer constituting
A WN layer is formed. Since the TiW layer is a pseudo alloy in which titanium (Ti) is dissolved in tungsten (W) crystal,
During the heat treatment, nitrogen in the WSiN layer 5 diffuses into the TiW layer and reacts with titanium to form a Ti-N bond. Further, since a WN bond is formed in a part of the TiW layer, the TiW layer eventually changes to a stoichiometric TiWN layer. Although the TiWN layer itself forms a good Schottky junction with the GaAs substrate 1, it is difficult to grow a stoichiometric TiWN layer by reactive sputtering or the like, like the TiN of the first embodiment. That is, if a TiWN layer is formed from the beginning of film formation by sputtering or the like, a reaction product will be formed due to excess nitrogen contained in the TiWN layer.

After performing such a heat treatment, the annealing protective film 12 is removed, and as shown in FIG. 5C, a source electrode 13s is formed on one n ⁺ -type active layer 11s, and the other is formed. A drain electrode 13d is formed on the n ⁺ -type active layer 11d.
To form Thus, the MESFET is completed. As described above, according to the present embodiment, the gate electrode G
A good Schottky junction can be formed by forming a stoichiometric TiWN layer at the interface between the substrate and the GaAs substrate 1. In addition, the nitrogen absorption layer 14 is made of a TiW layer or Ti
Since the WSiN layer is composed of the WN layer, the WSiN layer 5 and the nitrogen absorption layer 14 constituting the gate electrode G can be continuously etched by the same etchant, and the patterning process of the gate electrode G can be simplified compared to the first embodiment. Can be
Cost reduction can be achieved. (Third Embodiment) In the first embodiment, when silicon ions are implanted to form the n'-type active layers 8s and 8d,
The surface of the GaAs substrate 1 is exposed from the element formation region excluding the gate electrode G. In the present embodiment, a description will be given of a semiconductor device manufacturing process including a process of covering the surface of the GaAs substrate 1 with a nitrogen absorption layer during such silicon ion implantation.

FIGS. 6 and 7 show an MES according to the third embodiment.
FIG. 4 is a cross-sectional view illustrating a step of forming the FET, and the same reference numerals as in FIGS. First, an n-type active layer 3 is formed on a GaAs substrate 1 according to the steps described in the first embodiment, and a nitrogen absorption layer 4 made of titanium and a WSiN layer 5 are sequentially formed on the GaAs substrate 1. Subsequently, as shown in FIG. 6A, the WSiN layer 5 is patterned by photolithography so as to have a gate electrode shape.

Next, as shown in FIG. 6B, a photoresist 15 is applied on the nitrogen absorbing layer 4 without etching the nitrogen absorbing layer 4, and the photoresist 15 is exposed and developed to form an element forming region. A window 15a is formed on the substrate. Then, with photoresist 15
Using the WSiN layer 5 as a mask, the GaAs
By implanting silicon ions into the substrate 1, n′-type active layers 8 s and 8 d are formed on both sides of the WSiN layer 5 having a gate electrode shape.
To form In this case, the GaAs
It is necessary to implant silicon ions into the substrate 1, and the acceleration energy for ion implantation is set higher than that of the first embodiment.
5 keV. The dose of silicon ions is 5 ×
It is set to 10 ¹³ / cm ² .

Next, after removing the photoresist 15, an SiO ₂ film is formed on the nitrogen absorption layer 4 and the WSiN layer 5, and the SiO ₂ film is vertically etched by a reactive ion etching method to obtain a structure shown in FIG. As shown in (c), only the side wall 16 is left on the side wall of the WSiN layer 5 having a gate electrode shape. At this time, since the GaAs substrate 1 is covered with the nitrogen absorption layer 4, the surface of the GaAs substrate 1 is prevented from being etched.

The SiO ₂ film has a thickness of 300 nm by the CVD method.
Formed to a thickness of The etching of the SiO ₂ film is performed using IC
Using a P etching method, the etching gas is CH
A gas in which F ₃ and O ₂ are mixed at a ratio of 14: 1 is used. Under such etching conditions, the titanium layer constituting the nitrogen absorption layer 4 is hardly removed when the SiO ₂ film is etched.
Selective etching of the O ₂ film becomes possible.

Next, as shown in FIG. 6D, a photoresist 17 is applied on the nitrogen absorption layer 4, the WSiN layer 5 and the side walls 16, and the photoresist 17 is exposed and developed to form a window in the element formation region. 17a is formed. Then, the photoresist 17,
Using WSiN layer 5 and sidewall 16 as a mask,
Ga in two regions sandwiching WSiN layer 5 and sidewall 16
By implanting silicon ions into the As substrate 1, n
^{The +} type active layers 11s and 11d are formed. In this case, silicon ions need to be implanted into the GaAs substrate 1 through the nitrogen absorption layer 4, and the acceleration energy for ion implantation is set higher than in the first embodiment. For example, silicon ions have a dose of 5 × 10 ¹³ / cm ² and an acceleration energy of 75 to 9
It is implanted under the condition of 0 keV.

After removing the photoresist 17, FIG.
As shown in (a), the sidewall 1 made of SiO ₂ is C-
When removed by the HF solution, the nitrogen absorption layer 4 in a region not covered by the WSiN layer 5 is also etched. When removing the nitrogen absorption layer 4, the surface of the GaAs substrate 1 is not roughened. Thus, the gate electrode G is constituted by the WSiN layer 5 and the nitrogen absorption layer 4 remaining thereunder.

Thereafter, as shown in FIG.
The plate 1 and the gate electrode G are covered with an annealing protective film 12, and
Then, activation annealing is performed at 860 ° C. for 10 seconds. This place
In the case of the first embodiment, the nitrogen
The top of the tan film is stoichiometric TiN,
Changes to TiAs at the bottom. Next, the annealing protective film 12 is
After removal, as shown in FIG. ⁺Type activity
A source electrode 13s is formed on the active layer 11s, and the other n
⁺Forming a drain electrode 13d on the active layer 11d
You.

Thus, the MESFET is completed. In the present embodiment, the nitrogen absorption layer 4 is kept until the silicon ion implantation for forming the n ⁺ -type active layers 11s and 11d is completed.
Since the GaAs substrate 1 is formed on the GaAs substrate 1, the GaAs substrate 1 is not exposed to a resist stripping solution or plasma during dry etching.

Thus, the depths of the n'-type active layers 8s and 8d can be optimized. (Fourth Embodiment) In the above embodiment, impurity ions are implanted in the order of the type active layer, the n ′ type active layer, and the n ⁺ type active layer. Will be described below.

FIGS. 8 to 10 are sectional views showing the steps of manufacturing the semiconductor device according to the fourth embodiment of the present invention. First, the first
As in the embodiment, an n-type active layer 3 is formed in a GaAs substrate 1, and a nitrogen absorption layer 4 made of titanium and a WS are formed on the GaAs substrate 1.
After forming the iN layer 5, the WSiN layer 5 is patterned into a gate electrode shape.

Next, as shown in FIG. 8A, an insulating film 18 such as SiO ₂ is formed on the nitrogen absorbing layer 4 and the WSiN layer 5 having a gate electrode shape. Etching by the side wall 1 only on the side wall of the WSiN layer 5
Leave as 8a. Subsequently, as shown in FIG. 8B, a photoresist 19 is applied on the nitrogen absorption layer 4, the WSiN layer 5, and the side wall 18a, and is exposed and developed to form a window 19a in the element formation region. I do.

Further, using the photoresist 19, the WSiN layer 5, and the side wall 18a as a mask, the window 19a is formed.
Silicon ions are implanted into the GaAs substrate 1 through the WSiN layer 5 and the sidewall 1 in the shape of a gate electrode.
N ⁺ -type active layer 1 in GaAs substrate 1 in two regions sandwiching
1s and 11d are formed. Next, as shown in FIG. 8C, after removing the photoresist 19, the sidewall 18a and the nitrogen absorption layer 4 are removed by a C-HF solution.
The nitrogen absorption layer 4 remains only under the gate electrode-shaped WSiN layer 5. Thereby, the WSiN layer 5 and the nitrogen absorbing layer 4 thereunder are used as the gate electrode G.

Thereafter, as shown in FIG. 9A, another photoresist 20 is applied on the GaAs substrate 1, and is exposed and developed to form a window 20a in the element formation region. Then, using the photoresist 20 and the gate electrode G as a mask, silicon ions are implanted into the GaAs substrate 1 to form an n'-type active layer 8s in a region between the gate electrode G and the n ⁺ -type active layers 11s and 11d. 8d is formed.

Subsequently, after the photoresist 20 is removed, as shown in FIG.
The substrate 1 is heated at 750 to 870 ° C. for several seconds to several tens of seconds.
In this case, as in the first embodiment, GaAs is used as the annealing protective film.
The substrate 1 may be covered. At the time of this heat treatment, as in the first embodiment, the upper part of the titanium layer constituting the nitrogen absorbing layer 4 absorbs nitrogen in the WSiN layer 5 to become a TiN layer, and the lower part becomes TiN layer.
As layer.

Next, as shown in FIG.
An organic film 21 having an excellent flatness, for example, a photoresist is formed on the gate electrode G to a thickness such that the gate electrode G is hidden. Subsequently, as shown in FIG. 10A, the organic film 21 is thinned using a plasma-containing oxygen-containing gas to expose the upper surface of the gate electrode G. Subsequently, a low resistance layer 22 of gold (Au) or the like is formed on the gate electrode G by using an electroless plating method. After that, the photoresist 21 is removed using a solvent.
The formation of the low resistance layer 22 is not limited to the electroless plating method, but may be a lift-off method or a selective CVD method. The low resistance layer 22 forms the upper part of the gate electrode G.

Next, as shown in FIG.
^A source electrode 13s is formed on the ⁺ active layer 11s, and a drain electrode 13s is formed on the other n ⁺ active layer 11d. Thereby, the basic structure of the MESFET is completed. As described above, in the present embodiment, the n ⁺ -type active layer 1
After forming 1s and 11d, the nitrogen absorption layer 4 is removed from the GaAs substrate 1 except for the gate electrode formation region, and thereafter, the n'-type active layers 8s and 8d are formed.

The reason why the nitrogen absorption layer 4 is removed at the time of implanting silicon ions for forming the n'-type active layers 8s and 8d is as follows. In order to suppress the short channel effect, it is necessary to accurately control the thicknesses of the n'-type active layers 8d and 8s. However, when ions are implanted into the GaAs substrate 1 through the titanium layer constituting the nitrogen absorption layer 4, the thicknesses of the n 'type active layers 8s and 8d fluctuate due to variations in the thickness of the nitrogen absorption layer 4. Further, when ions are implanted through the nitrogen absorbing layer 4, the implanted ions are scattered and the ion energy distribution width is increased as compared with the case where the nitrogen absorbing layer 4 is not provided, and the film thickness of the n′-type active layers 8s and 8d is reduced. Becomes uneven.

On the other hand, in the present embodiment, the nitrogen absorption layer 4 is left during the etching for forming the sidewalls 18a, and the nitrogen absorption layer 4 protects the GaAs substrate 1 from the etching. . In addition, before forming the n'-type active layers 8s and 8d, the nitrogen absorbing layer 4 thereunder is also removed at the same time as the sidewalls 18a.
Ion implantation for forming the active layers 8s and 8d can be performed with good controllability.

Since a high melting point metal containing nitrogen generally has a high resistivity, if the gate length of the gate electrode G made of a high melting point metal containing nitrogen is shortened in order to improve FET characteristics, the gate electrode resistance becomes extremely high. Get higher. However, in the present embodiment, as in the first embodiment, the GaAs substrate 1
The gate electrode G can be formed stably with a Schottky junction, and the gate resistance can be effectively reduced by forming the gate electrode G into a multi-layered T-type having a low resistance layer 22 thereon.

It is to be noted that such a T-type gate electrode is provided in the first
The present invention may be applied to any of the third to third embodiments. (Other Embodiments) In the above four embodiments, F
Although the formation of the nitrogen absorption layer between the gate electrode and the GaAs substrate when forming the ET has been described, also in the step of forming the Schottky diode on the GaAs substrate, the above-described process is performed between the metal and the GaAs substrate. It is possible to prevent a nitrided product from being formed at the Schottky junction with the nitrogen absorption layer interposed, and prevent arsenic from diffusing into the metal layer. Therefore, in a semiconductor integrated circuit device or the like in which a MESFET and a diode are formed on the same substrate, the number of diode stages can be reduced, and the degree of integration can be further increased.

In the above-described embodiment, the GaAs substrate is described as an example of the compound semiconductor substrate.
When a P substrate or the like is used, the above-described effects are obtained. Furthermore, the nitrogen-containing high melting point metal formed on the nitrogen absorbing metal is not limited to WSiN and TiWN,
WN and other nitrogen-containing materials may be employed.

[0070]

As described above, according to the present invention, a nitrogen absorbing layer such as titanium or titanium tungsten is interposed between a compound semiconductor layer for Schottky junction and a nitrogen-containing high melting point metal layer. Since the nitrogen diffused from the nitrogen-containing high-melting point metal is absorbed by the nitrogen absorption layer by heating for activating the impurities in the semiconductor layer,
Formation of a reaction product due to nitrogen at the Schottky junction interface can be prevented.

The compound bonded to nitrogen by heat in the nitrogen absorption layer is stable and has a barrier property to prevent the diffusion of the element, so that the mutual diffusion of the element between the refractory metal and the semiconductor layer is suppressed. .

[Brief description of the drawings]

1 (a) to 1 (e) are cross-sectional views showing steps of manufacturing a conventional semiconductor device.

FIGS. 2A to 2D are cross-sectional views (part 1) illustrating a process for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIGS. 3A to 3D are cross-sectional views (part 2) illustrating a process for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIGS. 4A to 4D are cross-sectional views (No. 1) illustrating the steps of manufacturing the semiconductor device according to the second embodiment of the present invention.

5 (a) to 5 (c) are cross-sectional views (part 2) illustrating a process for manufacturing a semiconductor device according to a second embodiment of the present invention.

6 (a) to 6 (d) are cross-sectional views (part 1) illustrating a process for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIGS. 7A to 7C are cross-sectional views (part 2) illustrating a process for manufacturing a semiconductor device according to a third embodiment of the present invention.

8 (a) to 8 (c) are cross-sectional views (part 1) illustrating a process for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 9A to 9C are cross-sectional views (part 2) illustrating a process for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 10A to 10C are cross-sectional views (part 3) illustrating a process for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... GaAs substrate (compound semiconductor layer), 2 ... photoresist, 3 ... n-type active layer (impurity introduction layer), 4 ... nitrogen absorption layer, 5 ... WSiN layer (nitrogen containing high melting point metal layer), 6, 7 ... Photoresist, 8s, 8d ... n 'type active layer (impurity introduction layer), 9 ... SiO2 layer, 9a ... side wall, 10 ... photoresist, 11s, 11d ... n ⁺ type active layer (impurity introduction layer), 12 ... Annealing protection film, 13s ... source electrode,
13d: drain electrode, 14: nitrogen absorption layer, 15: photoresist, 16, 17: sidewall, 18: SiO2
Layers, 18a: sidewalls, 19, 20: photoresist, 21: organic film, 22: low resistance layer, G: gate electrode.

Claims (15)

[Claims] 1. A nitrogen-containing high melting point metal layer formed on a compound semiconductor layer and making a Schottky junction with the compound semiconductor layer, and a stoichiometric layer formed between the high melting point metal layer and the compound semiconductor layer. A compound semiconductor device comprising: a metal nitride layer having a metric metal nitride. 2. The compound semiconductor device according to claim 1, wherein said compound semiconductor layer is a gallium arsenide layer. 3. The compound semiconductor device according to claim 1, wherein said metal nitride layer has a barrier property against element diffusion. 4. The method according to claim 1, wherein said metal nitride layer is a titanium nitride layer or a titanium tungsten nitride layer.
3. The compound semiconductor device according to item 1. 5. A step of forming a first impurity-doped layer by introducing impurities into a compound semiconductor layer, and a step of sequentially forming a nitrogen-absorbing layer and a nitrogen-containing high-melting-point metal layer on the first impurity-doped layer. Patterning the nitrogen-containing high melting point metal layer to form a first electrode; patterning the nitrogen absorption layer to form a part of the first electrode; and heating the compound semiconductor layer Thereby activating the impurity and simultaneously absorbing nitrogen in the nitrogen-containing high-melting point metal layer into the nitrogen-absorbing layer. 6. The compound semiconductor device according to claim 5, wherein said nitrogen absorption layer is continuously patterned as said first electrode under the same conditions as said nitrogen-containing high melting point metal layer. Production method. 7. An impurity is introduced into the compound semiconductor layer using the first electrode as a mask after the patterning of the nitrogen-containing high melting point metal layer and before heating the compound semiconductor layer. Forming a second impurity-doped layer having a higher impurity concentration than the first impurity-doped layer on both sides of the electrode, after heating the compound semiconductor layer, forming the second impurity-doped layer on both sides of the first electrode. 6. The method according to claim 5, further comprising the step of forming second and third electrodes in ohmic contact on each of the second impurity-doped layers. 8. After the patterning of the nitrogen-containing high melting point metal layer and before the heating of the compound semiconductor layer, the compound semiconductor layer is passed through the nitrogen absorption layer using the first electrode as a mask. A step of introducing an impurity and forming a second impurity introduction layer having a higher impurity concentration than the first impurity introduction layer on both sides of the first electrode; and forming sidewalls on both sides of the first electrode. Using the first electrode and the sidewall as a mask, introducing an impurity into the compound semiconductor layer through the nitrogen absorbing layer, and forming a third impurity-doped layer having a higher impurity concentration than the second impurity-doped layer. Forming on both sides of the electrode, removing the sidewall, and patterning the nitrogen absorption layer using the first electrode as a mask. Forming a second and third electrode in ohmic contact on each of the third impurity introduction layers on both sides of the first electrode after heating the compound semiconductor layer. A method for manufacturing a compound semiconductor device according to claim 5. 9. A step of forming sidewalls on both sides of the first electrode after patterning the nitrogen-containing high melting point metal layer and before heating the compound semiconductor layer; And using the sidewalls as a mask to introduce impurities into the compound semiconductor layer through the nitrogen absorption layer, forming second impurity introduction layers having a higher impurity concentration than the first impurity introduction layer on both sides of the electrode. Removing the sidewalls; patterning the nitrogen absorption layer using the first electrode as a mask; and forming the compound semiconductor layer using the first electrode as a mask. By introducing an impurity, a third impurity introducing layer having an impurity concentration higher than the first impurity introducing layer and lower than the second impurity introducing layer is provided in front of the first electrode. Forming in a region between the second impurity-introduced layers, wherein after the compound semiconductor layer is heated, ohmic contacts are formed on each of the second impurity-introduced layers on both sides of the first electrode. 6. The method for manufacturing a compound semiconductor device according to claim 5, further comprising a step of forming a third electrode. 10. The method of manufacturing a compound semiconductor device according to claim 8, wherein the removal of the sidewall and the patterning of the nitrogen absorbing layer are performed using the same etchant. 11. The nitrogen absorbing layer is used as an etching stop layer when patterning the nitrogen-containing high melting point metal layer to form the first electrode. A method for manufacturing a compound semiconductor device according to claim 9. 12. The sidewall is formed only on the side wall of the first electrode by forming an insulating film on the compound semiconductor layer and the first electrode, and thinning the insulating film by dry etching. 10. The method according to claim 8, wherein the nitrogen absorbing layer is used as an etching stopper during the dry etching. 13. The method according to claim 5, further comprising the step of forming a low-resistance metal layer on the top of said gate electrode to form a T-shape. 14. The method according to claim 5, wherein said nitrogen absorbing layer is one of a titanium layer and a titanium tungsten layer. 15. The method according to claim 5, wherein said compound semiconductor layer is a gallium arsenide layer.