JP2001057556A - Buffer controller and its control processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a buffer control system where a network load can be relieved. SOLUTION: When a buffer is fully occupied (YES in S4), a cell is aborted (S7), and a cell abort flag is set to '1' and stored (S2). When an input cell is an EOP cell (YES in S3), the cell abort flag is referred (S8). When the cell abort flag is set to '1', whether or not a head cell is stored in a cell buffer is discriminated (S12), and when the head cell is stored in the cell buffer(YES in S12), EPD processing is conducted (S17). When the head cell is outputted (NO in S12), EPD processing is conducted (S13).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer control apparatus and a control processing method therefor, and more particularly to a buffer control apparatus and a control processing method for an ATM (asynchronous transfer mode) communication apparatus. More specifically, the ATM communication device has a common cell buffer memory,
The present invention relates to an improvement in a buffer control device that performs EPD (early packet discard) / PPD (partial packet discard) processing.

[0002]

2. Description of the Related Art An ATM communication apparatus is composed of several virtual channels (VCs) connecting one input port to one output port. Conventionally, this kind of buffer control device is used for performing EPD control and PPD control in a switch or a demultiplexer using a common cell buffer memory as disclosed in, for example, Japanese Patent Application Laid-Open No. 10-75252. ing.

FIG. 11 is a block diagram showing an example of a conventional buffer control device described in Japanese Patent Application Laid-Open No. 10-75252. In FIG. 11, a routing tag extraction unit 3 extracts a routing tag, which is output route information, from the header of the input cell a. The write controller 8 reads a free address of the common cell buffer 1 from a free address FIFO (first-in first-out) memory 10 and writes data to the common cell buffer 1. At the same time, the address is written as a used address in the used address FIFO memories 11 to 14 corresponding to the output ports aa to ad.

[0004] The read control unit 9 is provided with a busy address FIF.
An address is read from the O memory 11, and the common cell buffer 1 is accessed at that address to output output data b. The branch (CDI) 2 is, for example, 2.4 Gb / s
Are output to the output ports aa to ad as signals of, for example, 600 Mb / s. The common buffer queue length counter 6 is incremented by one each time cell data is written to the common cell buffer 1, and is decremented by one each time cell data is read. Therefore, in the common buffer queue length counter 6, the amount of cell data stored in the common cell buffer 1 is counted and stored in the form of a queue length.

The queue length threshold value excess detecting section 7 monitors the count value of the counter 6, and when the count value exceeds a predetermined threshold value, the information (YES as to whether the threshold value has been exceeded).
/ NO information) j is sent to the packet discard control unit 4. In the packet state management table 5, three states (transferring, paused, and discarded) are written for each VC. The packet discard controller 4 controls the write controller 8 with reference to these three states and the threshold excess information j to perform EPD control. A buffer full flag k indicating whether or not the storage state of the common cell buffer 1 is full (full) is provided, and the state information of the buffer full flag k is input to the packet discard control unit 4.

[0006] The packet discarding control unit 4 stores the status information of the buffer full flag k and the packet status management table 5.
Based on this information, the write control unit 8 is controlled to implement the PPD function. Here, the EPD control is control for discarding a new packet a without entering the buffer 1 in a state where the number of staying cells in the buffer 1 for writing a cell exceeds a predetermined threshold. In other words, a control is performed in which a threshold value is set for the buffer length, and when the threshold value is exceeded, a newly input packet of the layer is discarded. Also,
In the PPD control, when the buffer 1 for writing the input cell a becomes full and the cell a is discarded without being able to write, a cell belonging to the same packet as the discarded cell is input. In this case, even if there is an empty space in the buffer 1, the input cell is discarded without writing.

In the EPD control and the PPD control, the AAL (ATM adaptation layer) 5 uses the PT (payload type) of the header of the cell as the EOP (end of packet) display. Performs processing by recognizing the packet.

[0008]

However, in the conventional buffer control device described in Japanese Patent Application Laid-Open No. H10-75252 shown in FIG. 11, when cell loss occurs during packet reception, a newly input cell is Will be discarded,
There is a problem that cells already written in the cell buffer are not discarded. In other words, packets that need to be retransmitted due to cell discarding flow over the network in an overlapping manner, which places an extra load on the network.

Also, in the PPD control, after a cell is discarded, the cell of the same packet is continuously discarded, and only the EOP cell is written in order to delimit the packet. , E
There is a problem that the writing of the OP cell cannot be performed. In other words, there is no delimiter from the next input packet, and even if the next packet is normally written in the cell buffer, it becomes a combined packet with dropped cells, and a normally input packet may be discarded. .

[0010] It is an object of the present invention to provide a buffer control device and a control processing method thereof that reduce the load on the network. That is, when a cell is discarded during reception of a packet, the load of the network is reduced by discarding the cell of the packet currently staying in the buffer.

Another object of the present invention is to prevent a normal packet from being discarded due to generation of a combined packet in PPD processing.

[0012]

SUMMARY OF THE INVENTION A buffer control device according to the present invention is a buffer control device in an asynchronous transfer mode for transmitting cells constituting a packet while sequentially and temporarily storing them in a buffer memory provided for each virtual channel. A buffer full detecting means for detecting that the buffer memory is in a buffer full state, and a buffer full cell discarding means for discarding the cell subsequently input when the buffer memory is in a buffer full state A cell discard flag generating means for setting a cell discard flag when the cell is discarded, and referring to the cell discard flag when the last cell of the packet is inputted, and setting the same if the cell discard flag is set. Packet discarding means for discarding all cells belonging to the packet.

A packet head cell detecting means for detecting a position of a head cell of the packet; and, when a head cell of the packet has been already output from the buffer memory when a last cell of the packet has been inputted. Tagging means for tagging a leading portion of the buffer memory in which cells are discarded and emptied.

Further, the buffer full detecting means determines that the buffer memory is full when the storage amount of the cells in the buffer memory exceeds a threshold value. Furthermore, the buffer full cell discarding means, when discarding of the cell once occurs, regardless of the storage state of the buffer memory, all subsequent cells belonging to the same packet until immediately before the last cell. It is characterized by being discarded.

The control processing method according to the present invention is a control processing method for an asynchronous transfer mode buffer control device for transmitting cells constituting a packet while temporarily storing them in a buffer memory provided for each virtual channel. Detecting that the buffer memory is in a buffer full state, discarding the cell that is subsequently input when the buffer memory is in a buffer full state, and detecting a cell if the cell is discarded. Setting a discard flag, and referencing the cell discard flag when the last cell of the packet is input, and discarding all cells belonging to the same packet when the cell discard flag is set. It is characterized by the following.

Further, the step of detecting a position of a head cell of the packet is performed, and when the head cell of the packet is already output from the buffer memory when the last cell of the packet is input, the cell is discarded. Tagging the empty portion of the buffer memory.

The operation of the present invention is as follows. EPD /
In the PPD process, a packet start address is managed by a counter in addition to a write address and a read address. This realizes the discard of the packet staying in the buffer during the EPD / PPD processing. Therefore, a packet having a discarded cell does not flow through the network, and the load on the network is reduced. In addition, normal packet discarding due to the generation of a combined packet during PPD processing is eliminated.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a buffer control device according to the present invention.
Portions equivalent to 11 are denoted by the same reference numerals. In FIG. 1, the buffer control device according to the present invention
It has a cell buffer memory (cell buffer) 1 for storing TM (asynchronous transfer mode) cells a for each connection (virtual channel; VC; communication route).
In addition, the cell buffer 1 stores the FI divided for each connection.
An FO (first-in first-out) memory (for example, a FIFO memory element).

Also, from the header portion of the input cell a,
A cell identification unit 3 for extracting a cell type and a connection number, and a write control unit 8 for determining a write address to the cell buffer 1 from the connection number of the input cell a.
Having. Further, it has a read control unit 9 for determining a read address from the cell buffer 1 and a cell discard management unit 21 for holding a flag “1” when a packet being received has a cell discard.

Furthermore, a buffer full detector 22 is provided for detecting a buffer full by comparing the buffer size with the number of staying cells (write address h-read address g). Further, it is determined whether or not the head cell of the packet being received is not output from the cell buffer 1.
Packet head cell output detection unit 2 that detects by comparing packet head address f with read address g
3.

The operation of the embodiment of the present invention will be described with reference to the flowchart of FIG. First, the cell identification unit 3 determines that the input cell a
Of the user cell (ordinary cell used for communication), EOP (end of packet; last cell of the packet, indicating the delimiter of the packet) cell, connection (route) as routing information
The number c is extracted. Based on this information c, when the input cell a is a user cell (step S1 is YES), the buffer full detection unit 22 compares the buffer size of the connection with the number of staying cells (read address d-write address e). Then, a determination is made as to whether the buffer is full, and the cell discard management unit 21 is notified.

If the input cell a is not a user cell (eg, a control cell not used for communication) (NO in step S1), the input cell a is discarded (step 2).
1). The packet head cell output detector 23 detects whether the head cell of the packet being received is not output from the cell buffer 1 by comparing the packet head address f with the read address g, and performs cell discard management. Notify the unit 21. The cell discard management unit 21 manages a cell discard flag i for each connection.

If the input cell a is a user cell (step S1 is YES) and is not an EOP cell (step S3 is NO), then the state of the buffer 1 is referred to (step S4). If the buffer is not full (step S4
Is NO), an instruction to write the input cell a into the cell buffer 1 is notified to the write control unit 8 (step S5), and the cell discard flag i holds the previous state (step S6). If the buffer is full (YES in step S4), an instruction to perform cell discard is sent to the write control unit 8 (step S4).
7) The cell discard flag is set to "1" and held (step S2).

If the input cell a is a user cell (YES in step S1) and is an EOP cell (YES in step S3), the cell discard flag i is referred to (step S8). If the flag i is "1", it is determined whether or not the head cell of the packet is in the cell buffer 1 (step S12), and if the head cell is in the cell buffer (step S12 is YES). , EPD
Processing is performed (step S17).

If the head cell has been output from the cell buffer 1 (NO in step S12), the instruction to perform the PPD process is notified to the write control unit 8 (step S13). If the cell discard flag i is "0", the state of the buffer 1 is referred to next (step S9). If the buffer is not full (step S9 is NO), the input cell a is written into the buffer 1 (step S10). Then, the cell discard information i is cleared (step S11). If the buffer is full (YES in step S9), the process proceeds to step S12.

The write control unit 8 manages write addresses (counters) d and h to the cell buffer 1 and a packet start address (counter) f. Further, when receiving the instruction i to write the input cell a to the cell buffer 1 from the cell discarding management unit 21, it outputs the write address d to the cell buffer 1 and increments the write address d of the connection by +1. Further, when an instruction to discard the input cell a is received, writing to the cell buffer 1 is stopped.

When the EPD processing is received (step S
17), the write address d is changed to the packet start address f
To perform a process of discarding all cells of the packet (steps S18, S19, S2).
0). If the PPD process has been received (step S1
3) The write address d and the packet start address f are rewritten to the read address e + 1, and the input cell a is tagged (tagged) and written to the read address e of the cell buffer 1 (step S14). As a result, the discard processing of the cells staying in the cell buffer 1 and the writing of only the tagged EOP cells are performed (step S1).
5, 16).

When a cell write instruction is received when an EOP cell is input, the packet start address f is rewritten to a write address d + 1. The read control unit 9 manages counters for the read addresses e and g. The read control from the cell buffer 1 is performed, and the counter of the connection from which the data was read is incremented by +1.

Operation of EPD / PPD processing FIG.
This will be described in detail with reference to FIG. In these figures, the storage status of the constituent cells of the packet in the cell buffer 1 is shown, and EOP cells are indicated by black circles, and cells other than the EOP cells are indicated by white circles. Numerals ("1" to "m") are sequentially entered and shown in the constituent cells of the packet. Further, the cell buffer 1 is constituted by a FIFO (first-in first-out) memory element, and it becomes possible to write (store) a new cell by the read amount.

The EPD processing in the present invention means that, when an EOP cell is input, if the packet is discarded and the head of the packet is in the cell buffer 1, the packet staying in the cell buffer 1 is deleted. This is the process of discarding all cells. Even if no cell is discarded when an EOP cell is input, the same processing is performed when the EOP cell itself is discarded due to buffer full and the head of the packet is in the cell buffer 1.

Similarly, the PPD process means that when a packet is discarded at the time of input of an EOP cell and the head of the packet is output from the cell buffer 1, the packet staying in the cell buffer 1 is output. Is a process of discarding all cells of the EOP, tagging the input EOP cells, and writing the cells into the cell buffer. Also,
Even when no cell is discarded when an EOP cell is input, the same processing is performed when the EOP cell itself is discarded because the buffer is full and the head of the packet is output from the cell buffer 1. Here, the reason why the EOP cell is tagged and written into the cell buffer 1 is to provide a delimiter from the next input packet.

FIG. 6 shows an example of the EPD process. FIG.
As shown in FIG. 6A, the input cell numbers "1" to "7" are stored in the cell buffer 1, but as shown in FIG. Are discarded because the buffer is full, and the cell discard flag becomes “1”. Thereafter, as shown in FIG. 6C, the cell is read from the cell buffer 1, and the cell buffer 1 becomes empty, and the input cell number "1" is set.
0 "is stored.

Next, as shown in FIG. 6D, when an EOP cell with an input cell number "11" is input, the cell discard flag is "1", and the first cell "1" of the packet is the cell buffer 1 , As shown in FIG.
The PD processing is performed, and all cells of the packet staying in the cell buffer 1 are discarded.

FIG. 7 shows another example of the EPD processing. As shown in FIGS. 7A to 7C, for example, the reading of the cell buffer 1 is sequentially performed, and the input cell numbers “1” to “10” are read.
Is stored normally. However, as shown in FIG.
When the EOP cell of the input cell number “11” is input, the cell discard flag is “0” since the packet is not discarded, but the cell buffer 1 is assumed to be in the buffer full state. In this case, the EOP cell with the input cell number “11” cannot be stored. Therefore, as shown in FIG. 7 (e), since the head cell of the packet is in the cell buffer 1,
All cells of the packet that have been subjected to PD processing and stay in the cell buffer 1 are discarded.

FIG. 8 shows an example of the PPD process. FIG.
As shown in (a) and (b), input cell numbers “1” to “1”
It is assumed that “3” has been normally stored (partially read), and as shown in FIG. 8C, after the first cell “1” of the packet being received is output from the cell buffer 1, the input cell number “1” is output.
The cell of "4" is discarded because the buffer is full, and the cell discard flag becomes "1". Thereafter, as shown in FIG. 8D, when the EOP cell of the input cell number "15" is input, the cell discard flag is set to "1". 1 ", and the first cell" 1 "of the packet is output from the cell buffer 1. Therefore, FIG.
As shown in (e), after performing the PPD process and discarding all cells of the packet staying in the cell buffer 1,
The input EOP cell is tagged and written at the head of the cell buffer.

FIG. 9 shows another example of the PPD process. As shown in FIG. 9A, the input cell numbers "1" to "7" are normally stored in the cell buffer 1, but as shown in FIG. Number "8",
It is assumed that the cell “9” is discarded because the buffer is full, and the cell discard flag becomes “1”. Further, as shown in FIG. 9C, the head cell “1” of the packet is read from the cell buffer 1 and the input cell numbers “10” to “14” are read.
Is stored normally.

Thereafter, as shown in FIG. 9D, when the EOP cell of the input cell number "15" is input, the cell discard flag is "1", and the first cell "1" of the packet is transmitted from the cell buffer 1. Since it has been output, PPD processing is performed. As a result, as shown in FIG. 9E, after all the cells of the packet staying in the cell buffer 1 are discarded, the input EOP cell is tagged and written to the head of the cell buffer 1.

FIG. 10 shows still another example of the PPD process. As shown in FIGS. 10A to 10C, it is assumed that the input cell numbers “1” to “14” have been normally stored (partly read). Thereafter, as shown in FIG. 10D, when the EOP cell of the input cell number "15" is input, the cell discard flag is "0" because the packet is not discarded, but the cell buffer 1 is in the buffer full state. Since the first cell “1” of the packet has been output from the cell buffer 1, the PPD process is performed. As a result, as shown in FIG. 10E, after all cells of the packet staying in the cell buffer 1 are discarded, the input EOP cell is tagged and written to the head of the cell buffer 1.

FIG. 2 is a block diagram showing another embodiment of the present invention. The other embodiment of the present invention shown in FIG. 2 is obtained by adding a threshold excess detection unit 24 to the embodiment of the present invention shown in FIG. It adds a function of discarding the next packet when the threshold value is exceeded (EPD control), which is performed in the conventional buffer control device shown in FIG. 11, and sets threshold information of each connection in the threshold excess detection unit 24. When cell a is input, the threshold value of the connection is compared with the number of staying cells (write address h-read address g) to detect an excess of the threshold value.

Cell Discard / Packet Head Cell Management Unit 25
When the leading cell of the packet is input, if the threshold value is exceeded with reference to the threshold value exceeding signal, an instruction to discard the input cell is notified to the write control unit 8, and the cell discarding flag is set to "1". . While the cell discard flag is "1", all cells input to the connection are discarded, and the cell discard flag is set to "0" when an EOP cell is input. In addition, a packet head cell flag is provided to detect the head cell of the packet, and is set to "1" when an EOP cell is input and to "0" when a user cell other than the EOP cell is input.

Thus, when the packet head cell flag is "1" and a user cell is input, the input cell is set as the head cell of the packet, and the above processing is performed. Therefore, in addition to the basic EPD / PPD control according to the present invention, a write prohibition process of a new packet when the threshold value is exceeded is realized.

FIG. 3 is a block diagram showing still another embodiment of the present invention. Another embodiment of the present invention shown in FIG.
The cell discard management section 21 of the embodiment of the present invention shown in FIG. 1 is changed to a cell discard / tagging management section 26. FIG.
In the embodiment of the present invention, the packet is discarded by the EPD / PPD process when the EOP cell is input. However, in this method, the packet is not discarded after the cell is discarded until the EOP cell is input. . If the buffer 1 has a space, the input cell a is written even after the cell discard.

On the other hand, in the embodiment shown in FIG. 3, when a cell is discarded, the packet is discarded, and all the cells a inputted thereafter are discarded. This prevents waste cells from staying after disposal.

Next, the operation of still another embodiment of the present invention shown in FIG. 3 will be described. Only the additional operation of the embodiment shown in FIG. 1 will be described. In FIG. 3, a cell discard / tagging management unit 26 manages a cell discard flag and a tagging instruction flag. If the input cell is a user cell and the buffer full detection unit 22 detects buffer full, the cell discard / tagging management unit 22 notifies the write control unit 8 of a discard instruction of the input cell a and sets the cell discard flag. Set to “1”.

At this time, if the packet has not been discarded before (the previous state of the cell discard flag is "0") and is the first cell discarded in the packet, the EPD / PPD
The processing is notified to the writing control unit 8 at the same time. EPD / P
For switching the PD, the packet head cell output detection unit 23 selects the PPD process when the head cell of the packet has been output from the cell buffer 1, and selects the EPD process when the head cell of the packet is in the cell buffer 1.

At the time of PPD processing, the tagging instruction flag is set to "1". The cell a input thereafter is
Discarding is performed while the cell discard flag is "1", and the cell discard flag is set to "0" when an EOP cell is input. When an EOP cell is input, the tagging instruction flag is referred to at the same time. When the flag is "1", the input cell (EOP cell) a is tagged without being discarded and written into the cell buffer 1. Thereby, EP
In addition to the D / PPD control, a packet discarding process at the time of cell discarding is realized.

FIG. 4 is a block diagram showing another embodiment of the present invention. The embodiment shown in FIG. 4 is obtained by adding a counter flag management unit 27 to the embodiment of the present invention shown in FIG. In the embodiment shown in FIG. 1, the buffer full detector 22 and the packet head cell output detector 23
The write address h, the packet start cell address f, and the read address g are compared. However, since the addresses f, g, and h are always added except when the packet is discarded, it is necessary to make the number of bits (capacity) of the address counter large enough to realize this.

For example, to count cell a input at 150 Mb / s for 10 years, about 130 giga (4 of 2)
7) bits, and a 47-bit counter is required.

In the embodiment shown in FIG. 4, the number of bits of each address counter is reduced by managing the carry flag of the write address counter and the packet start cell address counter by the counter flag management unit 27. Next, the operation of the embodiment shown in FIG. 4 will be described. Only the additional operation of the embodiment shown in FIG. 1 will be described.

In FIG. 4, the write control unit 8 manages a write address counter and a packet head cell address counter. Further, the read address control unit 9 manages a read address counter. The number of bits of each address counter is, for example, the number of buffer sizes of each connection of the cell buffer 1. For example, when the buffer size is 512 (2 9) cells, the number of bits of each address counter is 9 bits. Hereinafter, the description will be made on the assumption that the number of bits of the address counter is 9 bits.

When the input cell a is a user cell and is written in the cell buffer 1, the write address counter is incremented by +1. When 512 cells are written, the write address counter returns to 0. The carry flag of the write address counter generated at this time is notified to the counter flag management unit 27. Also, EOP
Even when a cell is input and the packet start address enters the next counter cycle, the carry flag of the packet start address counter is notified to the counter flag management unit 27.

When receiving each carry flag from the write control unit 8, the counter flag management unit 27 sets each carry flag of the connection to "1". Each carry flag has a read address counter of 512.
It becomes "0" when reading the cell and entering the next counter cycle. Also, the flag information is transmitted to the buffer full detection unit 2.
2. By notifying to the packet head cell detecting unit 23 and adding (adding) to the upper bits of the address in each block and performing comparison, the magnitude relation of the addresses is guaranteed. Thus, EPD / PPD control can be realized with a smaller circuit.

[0053]

As described above, according to the present invention, when a cell is discarded during reception of a packet, the effect of reducing the load on the network is to discard the cell of the packet that is currently staying in the buffer. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of another embodiment of the present invention.

FIG. 3 is a block diagram of still another embodiment of the present invention.

FIG. 4 is a block diagram of still another embodiment of the present invention.

FIG. 5 is a flowchart of an embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of an EPD processing operation.

FIG. 7 is an explanatory diagram of another example of the EPD processing operation;

FIG. 8 is an explanatory diagram of an example of a PPD processing operation.

FIG. 9 is a diagram illustrating another example of the PPD processing operation.

FIG. 10 is an explanatory diagram of still another example of the PPD processing operation.

FIG. 11 is a block diagram of an example of a conventional buffer control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Cell buffer 3 Cell identification part 8 Write control part 9 Read control part 21 Cell discard management part 22 Buffer full detection part 23 Packet head cell output detection part

Claims (7)

[Claims] 1. An asynchronous transfer mode buffer control device for transmitting cells forming a packet while sequentially storing data in a buffer memory provided for each virtual channel, wherein the buffer memory is in a buffer full state. Buffer full detecting means for detecting that there is a buffer full cell discarding means for discarding the cell which is subsequently input when the buffer memory is in a buffer full state, and a cell discard flag when the cell is discarded. Means for generating a cell discard flag, and discarding all cells belonging to the same packet when the last cell of the packet is input and referring to the cell discard flag when the cell discard flag is set. Buffer control device comprising: 2. A packet head cell detecting means for detecting a position of a head cell of the packet, wherein a head cell of the packet is already output from the buffer memory when a last cell of the packet is input. 2. The buffer control device according to claim 1, further comprising: tagging means for tagging a leading portion of said buffer memory, said cell being discarded and emptied. 3. The buffer full detecting means determines that the buffer memory is full when the storage amount of the cells in the buffer memory exceeds a threshold value. 3. The buffer control device according to 2. 4. The buffer full cell discarding means, if the cell is discarded once, regardless of the storage status of the buffer memory, all cells belonging to the same packet until immediately before the last cell. 4. The buffer control device according to claim 1, wherein the buffer control device is discarded. 5. The buffer control device according to claim 1, wherein said buffer memory is a first-in first-out memory. 6. A control processing method for a buffer control device in an asynchronous transfer mode for transmitting cells constituting a packet while temporarily storing the data in a buffer memory provided for each virtual channel, wherein the buffer memory is in a buffer full state. Detecting, and discarding the cell that is subsequently input when the buffer memory is in the buffer full state, and setting a cell discard flag when the cell is discarded, Referencing the cell discard flag when the last cell of the packet is input, and discarding all cells belonging to the same packet if the cell discard flag is set. . 7. The method according to claim 1, further comprising: detecting a position of a head cell of the packet; and, when the head cell of the packet has already been output from the buffer memory when the last cell of the packet is input, 7. The method according to claim 6, further comprising the step of: tagging a leading portion of the buffer memory that has been discarded and emptied.