JP2947687B2 - Buffer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer device,
For example, it can be applied to ATM communication and the like.

[0002]

2. Description of the Related Art In recent years, ATMs (Asynchronous) have been used.
s Transfer Mode, asynchronous transfer mode)
The construction of a broadband ISDN based on the Internet is underway. And, for example, in this broadband ISDN,
Provides communication services such as video, telephone, and high-speed data. SDH (Synchronous Digital Hierarchy: Broadband ISDN)
(rarchy) interface speed is 155.
52 Mbps (this is called STM-level 1), 1
55.52 Mbps × 4 = 622.08 Mbps (this is referred to as STM-level 4) and the like.
The data of these interfaces is data multiplexed by the synchronous multiplexing method. This synchronous multiplexing is called synchronous digital hierarchy (SDH).

[0003] SDH in such ATM communication is a network interface (NNI: Network Node).
Interface) and a subscriber network interface (user-network interface).

[0004] SDH data (for example, STM-
An interface circuit for extracting an ATM cell stream from (4 data) is also being developed. For the technology of such an interface circuit, see, for example, Reference: 1
Published by the Institute of Electronics, Information and Communication Engineers, March 15, 992, 1992
IEICE Spring Conference Lecture Book Volume 3, page 3-8, "622.08 Mbps SDH-ATM Interface Circuit", etc.

[0005] The specifications of the STM-4 frame are described in CCITT Recommendation G. 707, G.R. 708, G.R. 7
09 and the like.

Here, an example of a conventional SDH interface device will be described. FIG. 2 is a functional block diagram of this example.

In FIG. 2, SDH from the transmission path network
When the data is supplied to the transmission path terminating circuit 11, the data is subjected to frame synchronization and the like, so that every line (1080 bytes)
The data is converted into 8-bit parallel data (byte data) and supplied to the ATM cell extraction circuit 2. Then, the ATM cell extraction circuit 2 outputs the STM-4 frame (one frame is 9 rows ×
An ATM cell is extracted from (1080 bytes) and supplied to the ATM cell write control circuit 31.

Here, the STM-4 frame is shown in the frame format of FIG. In FIG. 3, the STM-4 frame is an SOH (Section).
Over Head) area, POH (Path Ov)
er Head) area (1 byte), pointer area (2
4 bytes), a negative stuff byte area (12 bytes), a positive stuff byte area (12 bytes), a fixed stuff byte area (3 bytes), and the like.

[0009] The ATM cell is mapped to an area excluding the SOH area, POH area, pointer area, and fixed stuff byte area of the STM-4 frame. And the negative stuff byte area and the positive stuff byte area are
There are cases where the ATM cell is mapped and cases where the ATM cell is not mapped.

The cell format of the ATM cell comprises a header (5 bytes) and an information field (48 bytes) as shown in FIG.

Further, in FIG. 2, the ATM cells output from the ATM cell extracting circuit 2 are not always continuously extracted and output. This corresponds to the SOH area (36
Bytes), POH area (1 byte), pointer area (2
Since the ATM cells may not be mapped to the 4 bytes), the negative stuff byte area (12 bytes), the positive stuff byte area (12 bytes), etc., the output of the ATM cells from the ATM cell extraction circuit 2 is often interrupted. . In the negative stuff byte area (12 bytes) or the positive stuff byte area (12 bytes), ATM cells may be mapped depending on SDH data in order to perform phase adjustment or the like.

Next, the ATM cell write control circuit 31
The ATM cells supplied from the TM cell extraction circuit 2 while being interrupted frequently are sequentially written into the buffer memory 4. Further, when reading is performed, the reading is controlled by the ATM cell reading circuit 51. Note that this buffer memory 4
For example, a dual-port memory that can perform reading and writing in parallel is used.

However, the buffer memory 4 stores the AT
When reading out M cells, it is required to continuously output cells in the apparatus, and it is necessary to prevent discontinuous reading and output.

FIG. 5 shows an example of a cell format in the device when reading out ATM cells. This figure 5
In the case where the ATM cell written in the buffer memory 4 is read, a tag (1 byte) is added by an ATM cell reading circuit 51 to read the ATM cell (5 bytes of header and 48 bytes of information field) of the main body. Let me out
Output as a cell (54 bytes) in one device. This tag is used, for example, for routing in an ATM exchange.

However, if there is no readable ATM cell in the buffer memory 4, the ATM cell reading circuit 51 generates and outputs an idle cell in the device instead. The format of the device idle cell is the same cell format as device cell Le in FIG. 5 above.
The difference is that information for idle display is set in a tag, a header, and an information field. The idle cell in the device has no function of carrying information.

As described above, one cell of A is stored in the buffer memory 4.
If there is a TM cell, the ATM cell is output as an internal cell. If no ATM cell is written, an idle cell is generated and output instead of the ATM cell. We will not be interrupted.

As described above, the supply destination of the cell in the apparatus (for example,
The reason why the supply of the ATM cells to the switching equipment is not interrupted is to prevent the stop of the clock supply based on the supply of the ATM cells, to match the speed in the physical layer, and the like.

When the ATM cell output from the ATM cell extracting circuit 2 is interrupted as shown in FIG. 3, there is a case where the ATM cell is interrupted continuously for up to 52 bytes. That is, 24 bytes (pointer area) +12 bytes (negative stuff byte area) +12 bytes (positive stuff byte area) +1 byte (POH area) +3 bytes (fixed stuff byte area)
= 52 bytes.

[0019]

Therefore, if no ATM cell has been written to the buffer memory 4 by more than 52 bytes, if the writing of the input ATM cell is interrupted after the reading of the ATM cell is started, the ATM being read is not read. The cells may be interrupted.

The memory capacity of the buffer memory 4 is, for example, 2 bytes of 53 bytes of memory capacity of one ATM cell.
Since 53 × 2 = 106 bytes are used, there is a problem that the ATM cell cannot be written as described below.

Here, a description will be given with reference to FIGS. FIG. 6 is an explanatory diagram for explaining a conventional problem. FIG. 7 is a timing chart of the write / read operation in the case of FIG.

That is, the first AT is stored in the buffer memory 4.
While there is no valid ATM cell to read while the first to 50th bytes of the M cell (cell A in FIG. 7) are being written, the ATM cell reading circuit 5 uses the first idle cell in the device in FIG. (Idle cell α) is generated and output. Then, 5 of the first ATM cell (cell A in FIG. 7)
When the output of the first device idle cell (54 bytes, idle cell α in FIG. 7) is completed at the time when the 0th byte is written, the ATM cell readout circuit 51 then reads an ATM cell that can be read. It is confirmed in the buffer memory 4 whether or not there is (time c in FIGS. 6 and 7). As a result, since the 51st byte of the first ATM cell (cell A in FIG. 7) is still written, the first ATM cell (cell A in FIG. 7) cannot be read out. The device generates and outputs an idle cell in the device (idle cell γ in FIG. 7) (time a in FIGS. 6 and 7).

After the writing of up to 53 bytes of the first ATM cell (cell A in FIG. 7) is completed, the writing of the second ATM cell is continuously performed. At the time when the generation output of the idle cell (54 bytes, idle cell γ in FIG. 7) ends at time b in FIGS. 6 and 7, the 51st byte write of the second ATM cell (cell B in FIG. 7) Has been completed. That is, the buffer memory 4 stores the 51st of the second ATM cell (cell B in FIG. 7).
53 bytes of the byte and the first ATM cell (cell A in FIG. 7)
A total of 104 bytes have been written for the bytes.
Therefore, the free memory area has 2 bytes.

The ATM cell readout circuit 51 adds a tag (1 byte) to the output of the third device cell (valid cell A in FIG. 7) and outputs it to the buffer memory 4.
The first ATM cell (53 bytes, cell A in FIG. 7) is read out and output as a valid cell A in the apparatus in FIG.

When the output of the third device cell (54 bytes, valid cell A in FIG. 7) is completed (time d), the second ATM cell (53 bytes, cell B in FIG. 7) is output. ) Has been completed, and the writing of the 52nd byte of the third ATM cell (cell C in FIG. 7) has been completed.

Therefore, the empty memory area of the buffer memory 4 has 2 bytes at the time b when the generation and output of the second in-device idle cell is completed, but the empty memory area in the third device at the time d is When the output of the cell (valid cell A in FIG. 7) is completed, the free memory area has been reduced to 1 byte.

Then, the byte B0 of the tag of the cell B in the device
Is generated and output, the byte C53 of the cell C is written, and the free memory area of the buffer memory 4 becomes 0 at this point. Therefore, next, byte D1 of ATM cell D
Cannot be written unless the byte B1 of the ATM cell B has been read.
Since the byte D1 cannot be written in this manner, the ATM cell D
Must be discarded. Then, after discarding the ATM cell D and reading the ATM cell B, the ATM cell E can be written.

As described above, when writing and reading of the ATM cell are continued, the empty memory area of the buffer memory 4 is reduced every time one cell in the device is output, and byte data which cannot be written is generated. This ATM cell must be discarded.

The cause of such a problem is that when writing an ATM cell, writing is performed in 53 bytes. In the case of reading, similarly, reading is performed in 53 bytes. However, A
When reading a TM cell, the ATM cell reading circuit 51
Therefore, it is necessary to generate and add a tag of 1 byte and then output it as a read 54-byte device cell. Therefore, the buffer memory 4 can write the byte data of the ATM cell in one clock time in which one byte of the tag is generated and added, but the buffer memory 4
The reading from is controlled to be stopped.

Therefore, while the tag is generated and added (one clock time), reading of the ATM cell from the buffer memory 4 is stopped, and during this period, writing of the subsequently supplied input ATM cell is performed. Therefore, the free memory area of the buffer memory 4 decreases each time cells in one device are output, and eventually the writing becomes impossible.

In this way, if it becomes impossible to write the ATM cell, the ATM cell must be discarded. Discarding ATM cells is a loss of communication data, and thus has a serious problem of deteriorating ATM communication quality.

As one method for solving such a problem, the problem is solved by setting the memory capacity of the buffer memory 4 to the memory capacity for three ATM cells, ie, 3 × 53 = 159 bytes. Can be considered.

However, in this case, the amount of hardware such as the buffer memory 4 becomes large, and it is not suitable for an LSI, etc., so that it cannot be adopted as an optimal method.

The present invention has been made in view of the above problems, and has as its object to extract a packet (for example, an ATM cell) arranged in a frame and write it into a storage means. An object of the present invention is to provide a buffer device capable of performing writing and reading efficiently with a simple configuration without discarding packets when reading data as necessary.

[0035]

In order to achieve the above object,
Therefore, the present invention uses a predetermined number of bits (for example, bytes) as a unit.
(For example, fixed length packets)
Information (eg, ATM cells)
Data, ATM cells, etc.) meet certain rules (eg,
Frames arranged according to STM-4)
(For example, STM-4 frame)
Extracting means for extracting the output and output packets
Stored in units of bits, and stored in units of the specified number of bits (for example,
(For example, 1 byte).
Each packet read from the storage means has the predetermined number of bits.
A tag to which a tag (for example, a tag in the device) is added and transmitted.
In the buffer device, the extraction means sequentially extracts and outputs
Within the frame in which each packet to be
Position information of each information (for example, byte position information in a frame)
Information), the information written to the storage means is detected.
The position where the future interruption state of this packet is detected in advance.
Information detection means, and a predetermined video stored in the storage means.
Storage number information that outputs the number of data units as the storage number information
Judgment from detection means, the position information and the stored number information
To control the reading of packets from the storage means
As a result, the corresponding one packet is
Even if it is interrupted at the time of delivery, at least at the time of reading
And control means for preventing interruption.
I do.

[0036]

[0037]

According to the present invention, once stored in the storage means,
When the stored packet is read from the storage unit, the storage
The read side of the stage adds a tag to the packet.
It is. And with the addition of the tag, the free space of the storage means
The amount gradually decreases.

On the other hand, the packet is interrupted due to the position information.
If they are going to be stored consecutively instead of
Because it can be detected in advance, the maximum
Without preparing for a break, for example, one predetermined bit number unit
It is necessary to perform control so that the data is read out immediately after it is stored.
Can be.

Therefore, the effect of the gradual decrease of the free space is solved.
It can be erased, and the reading side breaks less than a packet unit.
Packets that are newly stored while preventing
It is possible to prevent the situation that the
You.

At this time, the minimum storage means required
The amount is determined by a predetermined rule regarding the arrangement of each information in the frame.
Changes depending on the frequency at which packets determined by rules are interrupted
But often very small, on the order of a few packets.
This is a large value.

[0041]

[0042]

[0043]

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment in which the buffer device of the present invention is applied to an SDH interface device will be described with reference to the drawings.

FIG. 1 is a functional block diagram of the SDH interface device of this embodiment. 1. In FIG. 1, components having the same functions as those of the conventional components shown in FIG. FIG. 3 shows an outline of a format of, for example, an STM-4 frame as SDH data. Further, the format of the ATM cell is the format of FIG. 4, and the format of the cell in the apparatus is also the format of FIG.

In FIG. 1, the SDH interface device according to this embodiment is different from the conventional configuration in that
Characteristic components include a frame byte position detection circuit 6 and a read condition detection circuit 7.

However, even in the conventional configuration, the transmission line termination circuit 1 is further improved. That is, conventionally, S
Detecting the head of the STM-4 frame from the DH data,
The data was converted into 8-bit parallel byte data and supplied to the ATM cell extraction circuit 2. In this embodiment, the transmission line termination circuit 1 further includes a frame byte position detection circuit 6.
Also supplies the terminated STM-4 frame information .

Then, the ATM cell extracting circuit 2 extracts an ATM cell from the supplied byte data and supplies it to the ATM cell writing control circuit 3 as in the conventional case. And
The ATM cell write control circuit 3 not only writes the supplied ATM cells to the buffer memory 4 but also in this embodiment, in an improved manner, generates byte number information of the ATM cells written to the buffer memory 4. Then, the written byte number information is supplied to the newly provided read condition detecting circuit 7.

The buffer memory 4 has a memory capacity of two ATM cells as in the conventional case. That is, 2 × 53 = 106 bytes. And
The byte data supplied from the ATM cell write control circuit 3 is written, and the byte data written by the request from the ATM cell read circuit 5 is read.
It is supplied to the ATM cell reading circuit 5.

On the other hand, the frame byte position detecting circuit 6
From the STM-4 frame information, frame byte position information indicating which byte and which byte of the current STM-4 frame is the byte data supplied to the ATM cell extraction circuit 2 is detected. The position information is supplied to the read condition detection circuit 7.

Then, the read condition detecting circuit 7 judges the supplied frame byte position information and the number of bytes written in the buffer memory 4 to generate a read control signal at an optimum timing and sends the read control signal to the ATM cell read circuit 5. Supply.

That is, since the reading condition detecting circuit 7 recognizes the current byte from the frame byte position information,
After several bytes, SOH area (36 bytes), pointer area (24 bytes), negative stuff byte area (12 bytes)
It is possible to predict whether or not the writing of the ATM cell is interrupted in the normal stuff byte area (12 bytes), the fixed stuff byte area (3 bytes), the POH area (1 byte), and the like.

Therefore, depending on the result of the prediction, the read control signal causes the ATM cell read circuit 5 to transmit the AT signal.
It is also possible to read out M cells or, conversely, generate and output idle cells in the device.

For example, if the read condition detecting circuit 7 determines from the frame byte position information that the extraction of ATM cells is not interrupted for a while in the future, the buffer memory 4
When the first byte is written into the ATM cell readout circuit 5, it is determined that the readout is possible, and a readable readout control signal is supplied to the ATM cell readout circuit 5.

The ATM cell read circuit 5 supplied with the readable read control signal generates and outputs one byte of the tag, causes the first byte written in the buffer memory 4 to be read, and thereafter reads the second byte. When reading up to the 53rd byte, it is possible to form and output cells in the device (similar to FIG. 5) in 54 bytes as in the conventional case.

Therefore, even if byte data is continuously supplied to the buffer memory 4 without interruption as in the prior art,
Every time 53 bytes of ATM cells are read (that is, every 54 bytes of cells in the device are output), the free memory area of the buffer memory 4 decreases, and it becomes impossible to write byte data. I can't get it.

Further, a read control signal is generated based on the byte number information and the frame byte position information of the byte data written in the buffer memory 4 to cause the ATM cell reading circuit 5 to read the ATM cell. ,
Alternatively, an idle cell in the device can be generated and output.

For example, the read condition detecting circuit 7
When the number of bytes after which writing of the ATM cell is interrupted is predicted based on the frame byte position information, the number of bytes at which the ATM cell is interrupted (for example, (1 byte POH area) is smaller than the number of bytes of the byte data written in the buffer memory 4, the ATM cell is interrupted, and even if there is a time when writing is not performed, the already written byte Since the number of data is larger, the output of cells in the device due to reading of already written byte data is not interrupted.

Accordingly, in this case, the read condition detection circuit 7 causes the ATM cell read circuit 5 to read the byte data of the ATM cell which has already been written, and to output the read byte data as the internal cell.

Conversely, the read condition detecting circuit 7
If the number of bytes at which the M cell is interrupted (for example, a pointer area of 24 bytes) is larger than the number of bytes of the byte data written in the buffer memory 4, the reading of the ATM cell already written is expected to be interrupted. The read condition detection circuit 7 does not allow the ATM cell read circuit 5 to read ATM cells from the buffer memory 4.

Until the number of bytes of the byte data in the buffer memory 4 becomes larger than the number of interrupted bytes of the ATM cell, the reading is stopped, and the writing of the extracted ATM cell is performed. Therefore, while reading from the buffer memory 4 is stopped, the internal idle cells are generated and output as needed.

According to the above-described embodiment, the buffer memory 4 stores 52 bytes of ATM cells in the conventional manner (there is no ATM cell, for example, a 36-byte SOH area, a 24-byte pointer area, and a 1-byte POH area). (Area: 3 bytes, fixed stuff byte area, 12 bytes of positive stuff byte area, 52 bytes of 12 bytes of negative stuff byte area) Even if no data has been written, it is determined that the input ATM cell is extracted without interruption. Thus, the ATM cells already written in the buffer memory 4 can be converted into cells in the device and output without interruption.

The memory capacity of two ATM cells (2 × 53 bytes) is always sufficient even if the memory capacity of the buffer memory 4 is not set to the memory capacity of three ATM cells (3 × 53 bytes). While securing free memory area,
The output of the cell in the apparatus can be performed.

Therefore, even if ATM cells are continuously extracted as in the prior art, there is no problem that the ATM cells are discarded. Therefore, the quality of ATM communication can be improved as compared with the related art.

In the above embodiment, the STM-
Although an example of extracting ATM cells from the frame No. 4 has been described, the present invention is not limited to this. When the present invention is applied to an apparatus that extracts ATM cells from frames such as STM-0, 1, 16 and the like, the present invention is applied by changing the memory capacity of the buffer memory 4 and slightly changing other circuits. be able to.

Further, as shown in FIG.
It is composed of a tag of bytes, a header of 5 bytes, and an information field of 48 bytes, but is not limited to this number of bytes. Other numbers of bytes may be used. Also,
Similarly, the format of the ATM cell in FIG. 4 is not limited to this.

Further, in the above embodiment, the buffer memory 4 may be a RAM, or may be a storage means including a plurality of flip-flops or a register.

Furthermore, in the above embodiment, when writing byte data to the buffer memory 4, the data is written without performing an error check of the header (5 bytes) or correcting an error in the case of a header error. . However, for example, after the header error check is performed by the ATM cell extraction circuit 2 or the ATM cell write control circuit 3 or the like, if it is normal, the data is directly written into the buffer memory 4. If abnormal, the header is corrected and written into the buffer memory 4. In the case of an abnormality, the cell may be discarded.

Further, in the above embodiment, an example in which an ATM cell is included in a frame has been described. However, in the example in which a packet (data in units other than the ATM cell) is arranged in the frame. Even if there is, the same can be applied by slightly changing the circuit and the like.

Further, in the above embodiment, the SDH
The SDH was applied as an interface device.
However, the present invention is not limited to this.

[0071]

According to the present invention, as described above,
You don't always have to be prepared for the biggest break
That packets are going to be stored continuously
When it is determined from the position information, for example, one predetermined bit
Control to read out as soon as several units are stored
Of gradual decrease of free space in storage means with tag addition
On the other hand, when the interruption is large,
Read until a sufficient number of constant bit units are stored
Is not performed, any one packet can be read at the time of reading.
Can be reliably prevented from being interrupted. But
Storage of packets even with the smallest storage means
That storage cannot be done
high. Also, the capacity of the minimum storage means required in the present invention.
The amount is determined by a predetermined rule regarding the arrangement of each information in the frame.
Changes depending on the frequency at which packets determined by rules are interrupted
But often very small, on the order of a few packets.
This is a large value.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of an embodiment when the present invention is applied to an SDH interface device.

FIG. 2 is a functional block diagram of a conventional SDH interface device.

3 is a S TM-4 frame format.

FIG. 4 is a format of an ATM cell.

FIG. 5 shows a format of a cell in the device.

FIG. 6 is an explanatory diagram for explaining a problem of a conventional example.

FIG. 7 is a timing chart of a conventional write / read operation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transmission line termination circuit, 2 ... ATM cell extraction circuit, 3 ... A
TM cell write control circuit, 4 ... buffer memory, 5 ... A
TM cell reading circuit, 6 ... frame byte position detecting circuit, 7 ... read condition detecting circuit.

Continuation of front page (72) Inventor Noriaki Takahashi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-4-79540 (JP, A) JP-A-4- 98943 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 12/28 H04J 3/00

Claims (1)

(57) [Claims] 1. A packet configured in units of a predetermined number of bits.
Each information including the packet is arranged according to the prescribed rules.
Extractor that extracts the relevant packet from the existing frame
And a packet extracted and output in units of the predetermined number of bits.
Storage means for storing and reading out in a unit of the predetermined number of bits.
And each packet read from the storage means has
A buffer device that adds a tag of a fixed number of bits and transmits it
In each packet are sequentially extracted output from said extracting means distribution
The position information of each of the above information is detected in the placed frame.
The corresponding packet written in the storage means.
Location detection to detect future breaks in the future
Means, and a predetermined number of bits unit stored in the storage means.
A storage number information detecting means for outputting as storage number information, and determining the storage number based on the position information and the storage number information;
By controlling the reading of packets from the means
One packet to be interrupted when stored in the storage means
Even if it does, it will not be interrupted at least at the time of reading
Buffer device, characterized in that it comprises a Unisuru control means.