JP2001053075A - Wiring structure and method of forming wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize wiring which is excellent in both electric properties and environmental resistance and to enable a semiconductor device or a wiring board where the above wiring is provided inside to be improved in reliability. SOLUTION: A via hole is provided on insulating layers 11 and 13, a metal thin film 14 is formed covering the insulating layer 13 and a lower conductor layer 12 so as to be electrically connected to the lower conductor layer 12 through the intermediary of the via hole, a wiring layer 17 is formed on the metal thin film 14, and the surface of the metal thin film 14 is covered with a coating layer 18 formed of material excellent in environmental resistance. It is preferable that nickel/gold, nickel/palladium or nickel/palladium/gold is used as the above material which is excellent in environmental resistance and used for forming the coating layer 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure and a wiring forming method, and more particularly, to a wiring structure made of a material having relatively low environmental resistance, such as copper (Cu) or silver (Ag). The present invention relates to a technique useful for solving inconvenience.

[0002]

2. Description of the Related Art In recent years, multi-layered wiring and finer wiring have been developed due to higher integration and higher speed of LSI. In particular, in logic devices, in order to realize high performance transistor characteristics, it is necessary to reduce the minimum pitch of wiring in accordance with the gate length, and furthermore, a wiring structure that can withstand use conditions at high current density is required. Is done. When the wiring pitch is reduced, the signal delay caused by the inter-wiring capacitance and wiring resistance, which has not been considered so much, cannot be ignored. In order to avoid this, it is necessary to use a wiring material having a low resistivity and an interlayer insulating film having a low dielectric constant.

As a wiring material, aluminum (Al) has been conventionally used, but recently, Cu capable of realizing a low wiring resistance with the same wiring cross-sectional area as Al has been used. Cu can have the same wiring pitch and the same wiring resistance as Al and can reduce the thickness of the wiring, and as a result, the capacitance between wirings can be reduced. In particular, in a semiconductor device having a chip size package (CSP) structure which has been developed to meet the needs for miniaturization and high density of the semiconductor device required in recent years, each semiconductor element formed on a wafer It is necessary to perform rewiring for connecting the electrode pads (parts finally separated as individual semiconductor chips) to the outside of the package via an insulating layer such as a polyimide layer between the electrode pads and the wafer. As a wiring material used for the rewiring, Cu is mainly used from the viewpoint of excellent electrical characteristics.

Further, in addition to the advantage of excellent electrical characteristics, the use of Ag as a wiring material has been studied from the viewpoint that the conductivity can be further enhanced by the skin effect when the frequency is increased. ing.

[0005]

As described above, in a conventional semiconductor device having a CSP structure, a wiring material having excellent electrical characteristics is used for rewiring, but generally, Cu or Ag is used.
Such a material having excellent electrical characteristics as described above may cause contamination and migration due to diffusion in a high-temperature and high-humidity environment.

For example, a metal atom penetrates into an adjacent insulating layer to deteriorate its insulating property, or a metal atom moves with an electron momentum due to a high current density in the wiring layer, and the metal layer moves to the wiring layer. Inconveniences such as disconnection and short circuit due to deformation are assumed. In other words, it is not appropriate to use a material having excellent electrical characteristics as it is, such as Cu or Ag, as the wiring material in terms of the environment surrounding the wiring.

[0007] Such a problem is not peculiar to the semiconductor device having the CSP structure, but is generally a structure in which wiring made of Cu, Ag, or the like having relatively low environmental resistance is provided. For example, a wiring board such as a build-up wiring board can similarly occur. In addition, if such contamination or migration occurs, the reliability of a wiring board such as a semiconductor device having a CSP structure or a build-up wiring board in which the wiring is provided is not preferable.

The present invention has been made in view of the problems in the prior art, and realizes wiring excellent in not only electrical characteristics but also environmental resistance. It is an object of the present invention to provide a wiring structure and a wiring forming method that can contribute to the improvement of the reliability of the wiring.

[0009]

According to one aspect of the present invention, there is provided a semiconductor device, comprising: a conductive layer that is electrically connected to a lower conductive layer through a via hole formed in an insulating layer; Thus, there is provided a wiring structure characterized in that the surface of the wiring layer formed on the insulating layer is covered with a coating layer made of a material having excellent environmental resistance.

According to another aspect of the present invention, a via
Form a resist layer on the insulating layer where the holes were formed,
A step of patterning the resist layer to follow a pattern shape that is made thicker by adding a predetermined margin to a required wiring pattern, and forming an opening in a portion of the resist layer including a region corresponding to the via hole; Forming a conductor layer so as to fill the opening, and removing the surface layer portions on the upper surface side and side surface side of the conductor layer by etching until the pattern shape of the conductor layer becomes the required wiring pattern shape. And forming a coating layer made of a material having high environmental resistance on the surface of the wiring layer.

According to still another aspect of the present invention, a first resist layer is formed on an insulating layer in which a via hole is formed, and the first resist layer is formed into a predetermined wiring pattern. Forming a first opening in a portion of the first resist layer including a region corresponding to the via hole by patterning the pattern so as to conform to a pattern shape which is thickened in consideration of a margin of the pattern; Forming a second resist layer so as to cover the first resist layer and the first opening, and patterning the second resist layer so as to conform to the shape of the required wiring pattern; Forming a second opening in the second resist layer at the position of the opening, forming a wiring layer in the second opening, and removing the patterned second resist layer And the wiring Wiring forming method characterized in that the surface of a step of forming a coating layer made of a material excellent in environmental resistance is provided.

According to the wiring structure and the wiring forming method of the present invention, a wiring (wiring layer) formed of a material having excellent electrical characteristics but relatively low environmental resistance, such as Cu or Ag, is used. Since the surface is covered with a material (coating layer) having excellent environmental resistance, a structure in which environmental resistance is added to required electrical characteristics of the entire wiring can be realized. As a result, inconveniences (contamination due to diffusion, migration, etc.) seen in the conventional wiring can be eliminated, and the reliability of a semiconductor device, a wiring board, or the like having the wiring therein can be improved. Become.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a wiring forming method for realizing a wiring structure according to the present invention will be described with reference to the accompanying drawings. 1 to 4 show an application example of a wiring forming method according to a first embodiment of the present invention.
4A to 4C sequentially show manufacturing steps of a semiconductor device having a CSP structure.

First, in the first step (see FIG. 1A),
A wafer 10 in which a plurality of semiconductor chips (not shown) are formed is manufactured. As an example, silicon nitride (SiN) or phosphorus glass (PSG)
After forming a passivation film 11 as a protection film made of a material such as aluminum, a conductor layer (electrode pad) of aluminum (Al) formed in a required pattern on each semiconductor chip.
The passivation film 11 corresponding to the region 12 is removed. As a result, as shown in the figure, the wafer 10 in which the electrode pads 12 are exposed and the surface of which is covered with the passivation film 11 except for the region corresponding to the electrode pads 12 is manufactured. In this case, the passivation film 11 is formed on the wafer 10.
, The insulating layer formed in the next step may also serve as a passivation film.

In the next step (see FIG. 1B), photosensitive polyimide is applied to the surface of the wafer 10 by photolithography to a thickness of about 6 μm as a photosensitive resist for forming an insulating layer. After performing a soft bake (pre-bake) process on the resist layer, exposure and development (patterning of the resist layer) are performed using a mask (not shown), and a hard bake (post-bake) process is further performed. The patterning of the resist layer is performed so as to follow the shape of the electrode pad 12. Therefore, when exposure and development are performed, the resist layer (polyimide layer) corresponding to the electrode pad 12 is removed as shown in the figure, and the insulating layer 13 having an opening (via hole) reaching the electrode pad 12 is formed. It is formed.

In this embodiment, photosensitive polyimide is used as the material of the insulating layer 13, but a resin such as non-photosensitive polyimide may be used instead. However, in this case, since photolithography cannot be used, openings (via holes) are formed by, for example, laser processing.
Will be formed. In the next step (see FIG. 1C), a metal thin film 14 is formed on the entire surface by sputtering in a vacuum atmosphere. The metal thin film 14 has a two-layer structure of a chromium (Cr) layer provided for improving the adhesion to the lower insulating layer 13 and a copper (Cu) layer laminated thereon. The metal thin film 14 is formed by depositing Cr on the entire surface by sputtering to form a lower Cr layer, and further depositing Cu thereon to form an upper Cu layer. Here, the upper Cu layer is formed to a thickness of about several Å.

The thus formed metal thin film 14
Functions as a power supply layer for electrolytic plating necessary for forming a wiring layer, forming a coating layer, and forming a film on the surface of a bonding wire in a later step, that is, functions as a plating base film. In the next step (see FIG. 1D), for example, a dry film is formed as a photosensitive resist 15 on the metal thin film 14, and further, exposure and development (patterning of the resist layer) are performed using a mask (not shown). )I do. This patterning is performed so as to follow the shape of a wiring pattern formed in a later step. Thus, an opening P1 is formed in a portion of the resist layer 15 corresponding to the wiring region.

The “wiring pattern” here is
It refers to a pattern which is made thicker by adding a predetermined margin to a required wiring pattern corresponding to the final wiring layer. This predetermined margin defines the thickness of the coating layer formed in a later step. In the next step (see FIG. 2A), a Cu plating layer 16 is formed so as to fill the opening P1 (see FIG. 1D) by electrolytic plating with power supply from the metal thin film (power supply layer) 14. I do. The Cu plating layer 16 follows the shape of the wiring pattern.

In the next step (see FIG. 2B), in order to secure a space for forming a coating layer in a later step, Cu
The plating layer 16 (see FIG. 2A) is isotropically etched to change the shape of the wiring pattern to a required wiring pattern corresponding to the final wiring layer 17 as shown in the figure. Narrow the width. By this etching process, the surface layer portion (upper surface side and side surface side) of the Cu plating layer 16 is removed, and the removed portions have equal spaces S.
P is secured. On the other hand, the remaining portion of the Cu plating layer 16 is defined as the final wiring layer 17. This wiring layer 17 is also called “rewiring layer”. In the present embodiment, the thickness of the wiring layer 17 is selected to be about several tens of μm.

In addition, the portion of the Cu layer below the Cu plating layer 16 (the upper layer portion of the power supply layer 14) is actually removed by this etching treatment. Are slightly different, but are not shown for simplicity of illustration. In the next step (see FIG. 2C), similarly, nickel (Ni) plating and gold (Au) plating are applied to the surface of the Cu wiring layer 17 by electrolytic plating by power supply from the metal thin film (power supply layer) 14. To form a Ni / Au plating layer with a thickness of about 1 μm.
This Ni / Au plating layer is provided as a coating layer 18. In forming the covering layer 18, Ni plating and Au
Instead of plating, Ni plating and palladium (Pd) plating may be applied to form a Ni / Pd plating layer. Alternatively, instead of Ni plating and Au plating, Ni plating and P
d plating and Au plating may be performed to form a Ni / Pd / Au plating layer.

The coating layer 18 formed over the surface of the wiring layer 17 protects the wiring layer 17 (prevention of contamination, migration, etc.) as intended by the present invention, and also facilitates the workability of wire bonding described later. Help. In the next step (see FIG. 2D), the resist layer 15 (see FIG. 2C) is peeled off using a resist peeling solution such as a NaOH solution and removed.

In the next step (see FIG. 3A), for example, a dry film is formed as a photosensitive resist 19 on the metal thin film 14 and the coating layer 18 and further exposed using a mask (not shown). And development (patterning of the resist layer). This patterning is performed so as to conform to the shape of a terminal forming portion of the wiring layer 17 (covering layer 18), that is, a portion (bonding pad) to which a wire is to be bonded by wire bonding performed in a later step.
Thus, an opening P2 is formed in a portion of the resist layer 19 corresponding to the region of the bonding pad.

Further, an Au wire 20 as an external connection terminal is bonded to the bonding pad exposed at the opening P2 by wire bonding. The wire 20 has a diameter of about 25 μm and is formed in an S-shape. In the next step (see FIG. 3B), in order to give the wire 20 an elastic force, a nickel alloy plating is applied by electrolytic plating by feeding from the metal thin film (feeding layer) 14, and the surface of the wire 20 is formed. The Ni alloy film 21 is formed. As a result, the total diameter of the wire (represented by the reference numeral 22) having the Ni alloy film 21 formed on the surface is reduced to about 50 μm.
And

At this time, as can be seen from the structure shown, the Ni alloy film 21 is also formed on the surface of the bonding pad (the exposed portion of the coating layer 18 where the terminal is formed). N
As a material for forming the i-alloy film 21, for example, nickel-cobalt (Ni-Co), nickel-chromium-molybdenum (Ni-Cr-Mo), or the like can be used.

In the next step (see FIG. 3C), NaO
The resist layer 19 (see FIG. 3B) is stripped using a resist stripper such as H solution and removed. In the next step (see FIG. 4A), the exposed power supply layer 14 is removed by etching. That is, the Cu layer in the upper layer of the power supply layer 14 is removed with an etchant that dissolves Cu, and then the Cr layer in the lower layer is removed with an etchant that dissolves Cr. Thereby, the insulating layer (polyimide layer) 13 is exposed as shown.

In the next step (see FIG. 4B), in order to facilitate the soldering when the semiconductor chip is mounted on a printed circuit board or the like in a later step, the surface is formed by electroless plating. An Au film 23 is formed on the surface of the wire 22 having the Ni alloy film formed thereon to a thickness of about 0.1 μm. At this time, the entire wafer is immersed in a plating solution containing a metal salt and a reducing agent as main components to perform electroless plating.
Actually, as shown in the figure, the Au film 23 is formed not only on the surface of the wire 22 but also on the surface of other metal parts (the coating layer 18 and the power supply layer 14). In addition, for convenience of illustration, Au
The wire on which the coating 23 is formed is represented by reference numeral 24.

In the last step (see FIG. 4C), the wafer 10 is cut by a dicer or the like to separate individual semiconductor chips CP, and each semiconductor chip is mounted on a mounting board 25 such as a printed board. This is as shown in wire 2
This is performed by applying the tip of the substrate 4 to a corresponding electrode pad (not shown) on the mounting substrate 25 and bonding it with solder 26.

As described above, according to the first embodiment, as shown in FIG. 2, the wiring layer 17 made of Cu having excellent electrical characteristics but relatively poor environmental resistance is used.
Is coated with a coating layer 18 made of a material having excellent environmental resistance.
(Ni / Au plating layer or Ni / Pd plating layer), it is possible to realize a structure in which required electrical characteristics and environmental resistance are added to the entire wiring.

As a result, it is possible to eliminate inconveniences such as contamination due to diffusion and migration, which are observed in the conventional wiring. This contributes to improving the reliability of the semiconductor device having the CSP structure in which the wiring is provided. In addition, since the spaces SP at equal intervals can be formed around the wiring layer 17 by isotropic etching, the coating layer 1 to be formed so as to cover the surface of the wiring layer 17 is formed.
8 can be made uniform in thickness. This is the coating layer 1
From the viewpoint of protection of the wiring layer 17 by 8, it further contributes to prevention of contamination, migration and the like.

As described in connection with the step of FIG. 3B, the S-shaped wires 20 (22, 24) as the external connection terminals of the semiconductor chip have elasticity, The semiconductor chip CP is mounted on the mounting substrate 2 in the process of FIG.
5 can reduce the stress generated when mounted on
As a result, the connection reliability between the two can be improved. Further, since the impedance can be optimized by the length and shape of the wire, it is possible to contribute to the improvement of the electrical characteristics of the semiconductor device. Furthermore, since the wire shape has a relatively large surface area as compared with an electrode structure such as a solder bump, it is advantageous in terms of a heat radiation effect.

In the first embodiment described above, an etch-back process is used to secure a space for forming a coating layer, which is a feature of the present invention (see FIG. 2B), but the coating layer is formed. Needless to say, the method for securing the space is not limited to this. One example is shown in FIG. FIG. 5 shows partial steps for explaining a wiring forming method according to the second embodiment of the present invention.

A semiconductor device having a CSP structure to which the wiring forming method according to the present embodiment is applied is subjected to the same steps as those of FIGS. 1A to 1C in the first embodiment, and further to FIG. After the steps shown in FIG. 5A to FIG. 5D, it is manufactured through the same steps as the steps after FIG. 2C in the first embodiment. In the present embodiment, as a technique for securing a space for forming a coating layer, two types of resists are used, and each patterning is devised.

First, in the step shown in FIG. 5A, a first resist layer 31 is applied on the metal thin film 14, and the resist layer is patterned so as to conform to the shape of the wiring pattern. An opening Q1 is formed in a corresponding portion of the resist layer 31. Here, the “wiring pattern” refers to a pattern that is made thicker by adding a predetermined margin to a required wiring pattern as described above.

Next, in the step shown in FIG.
A second resist layer 32 is applied so as to cover the first and first resist layers 31, and the resist layer is patterned so as to follow a required wiring pattern shape. The opening Q2 formed thereby defines a required wiring pattern width. Next, in the step shown in FIG. 5C, the openings Q are formed by electrolytic plating with power supply from the metal thin film (power supply layer) 14.
Then, a Cu plating layer 33 is formed on the substrate 2. This Cu plating layer 33 constitutes a final wiring layer, and its thickness is selected to be about several tens of μm as in the first embodiment.

Further, in the step shown in FIG. 5D, the second resist layer 32 (see FIG. 5C) is removed. As a result, a uniform space for forming the covering layer is secured around the wiring layer 33 as shown in the figure. Thereafter, a coating layer is formed so as to fill this space (see FIG. 2 (c)).
The resist layer 31 is removed (see FIG. 2D). When removing each of the resist layers 31 and 32, treatment is performed using a chemical solution capable of dissolving only the other resist layer without affecting one resist layer.

In each of the above-described embodiments, Cu is used as a wiring material constituting a final wiring layer.
Of course, other wiring materials such as Ag may be used instead of the above. Further, in each of the above-described embodiments, the semiconductor device having the CSP structure using the S-shaped wire as the external connection terminal has been described. However, the form of the external connection terminal is not limited to this. May be used.

One example of a semiconductor device using such solder balls as external connection terminals is shown in FIG. 6, and can be manufactured, for example, as follows. First, after going through the same steps as the steps of FIGS. 1A to 2D in the first embodiment, the metal thin film 14 and the coating layer 18 are formed.
A photosensitive resist such as a dry film is patterned on the substrate so as to follow the shape of the via / post, and then electrolytic plating is performed by power supply from a metal thin film (power supply layer) 14.
Using the patterned resist layer as a mask, a Cu via post 41 is formed, and if necessary, a barrier metal layer is formed on the top of the via post. Then, the resist layer is removed, and the exposed power supply layer is removed. 14 is removed by etching, and the wafer 10 is further sealed with a sealing resin (sealing resin layer 4).
After sealing by 2), a solder ball 43 as an external connection terminal is bonded to the exposed top of the via post 41 by reflow. Thereafter, the wafer 10 is cut together with the sealing resin layer 42 by a dicer or the like, separated into individual semiconductor chips, and each semiconductor chip is mounted on a mounting substrate.

Further, the semiconductor device illustrated in FIG. 6 has a structure in which a via post is provided on the wiring layer 17 covered with the covering layer 18, but the structure of the semiconductor device without such a via post is as follows. Of course, it is good. An example of such a semiconductor device having no via post is shown in FIG. 7, and can be manufactured, for example, as follows.

First, FIG. 1A in the first embodiment
2D, the exposed power supply layer 14 is removed by etching, and then the sealing resin layer 44 is formed so as to cover the exposed insulating layer 13 and the coating layer 18.
Is formed by, for example, potting, a via hole is formed by laser or the like in a region of the sealing resin layer 44 corresponding to the terminal forming portion of the coating layer 18 (wiring layer 17), and then an external connection is formed in the via hole A solder ball 45 as a terminal is arranged, and the solder ball 45 is bonded to the coating layer 18 (wiring layer 17) by performing reflow. Thereafter, as in the case of FIG. 6, the semiconductor chips are separated into individual semiconductor chips and mounted on a mounting board.

Incidentally, a solder resist layer may be formed instead of the sealing resin layer 44. In this case, the solder resist layer is applied by applying a solder resist so that a solder ball joint is opened by screen printing, or by applying a photosensitive solder resist and patterning the resist layer by exposure and development. Can be formed by

In each of the embodiments described above, the case where the present invention is applied to the formation of a redistribution layer in a semiconductor device having a CSP structure has been described. However, as apparent from the gist of the present invention, the applied form is Of course, it is not limited to. For example, in order to mount a semiconductor device having a CSP structure or a semiconductor device having a package structure such as a ball grid array (BGA), the semiconductor device has been put into practical use in order to meet the needs for finer wiring and higher density required in recent years. The present invention can also be applied to a wiring board such as a build-up wiring board, for which progress has been made.

Many kinds of build-up wiring boards can be manufactured by combining the material of the interlayer insulating layer and the process of forming via holes. The manufacturing process is generally as follows.
The formation of the insulating layer, the formation of the via hole in the insulating layer, and the formation of the conductor pattern (that is, the wiring layer) including the inside of the via hole are sequentially repeated to build up each layer. In such a process, when forming a conductor pattern (wiring layer), the wiring forming method according to each embodiment described above can be applied.

FIG. 8 shows an example. In the figure, 50 is a core substrate (insulating material) of a build-up wiring board,
51 is a second insulating layer of the build-up wiring board, 52 is a solder resist layer for protecting the build-up wiring board,
53 and 56 are metal thin films corresponding to the metal thin film 14 (see FIG. 4A), 54 and 57 are wiring layers corresponding to the wiring layer 17 (see FIG. 4), and 55 and 58 are coating layers 18 (see FIG. 4A). The coating layer 59 corresponding to ()) is a coating layer 58 (wiring layer 57) exposed from an opening formed in the solder resist layer 52.
Shows the land part. The land 59 is connected to an electrode terminal of a semiconductor element mounted on the build-up wiring board.

[0044]

As described above, according to the present invention, it is possible to realize a wiring excellent not only in electrical characteristics but also in environmental resistance. Can be improved in reliability.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device having a CSP structure to which a wiring forming method according to a first embodiment of the present invention is applied.

FIG. 2 is a cross-sectional view showing a manufacturing process following the manufacturing process of FIG. 1;

FIG. 3 is a cross-sectional view showing a manufacturing process following the manufacturing process of FIG. 2;

FIG. 4 is a cross-sectional view showing a manufacturing process following the manufacturing process of FIG. 3;

FIG. 5 is a cross-sectional view showing a partial step for explaining a wiring forming method according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing another application example (part 1) of the wiring forming method according to each embodiment of the present invention.

FIG. 7 is a cross-sectional view showing another application example (part 2) of the wiring forming method according to each embodiment of the present invention.

FIG. 8 is a sectional view showing another application example (part 3) of the wiring forming method according to each embodiment of the present invention.

[Explanation of symbols]

CP semiconductor chip 10 wafer 11 protective film (passivation film) 12 conductor layer (Al electrode pad) 13 insulating layer (polyimide layer) 14, 53, 56 metal thin film (power supply layer, plating base film) 15, 19,31,32 ... resist layer 16 ... conductor layer (Cu plating layer) 17,33,54,57 ... wiring layer (Cu plating layer) 18,55,58 ... coating layer (Ni / Au plating layer or N
i / Pd plating layer) 20, 22, 24 ... wire (external connection terminal) 21 ... Ni alloy film 23 ... Au film 25 ... mounting board 26 ... solder 41 ... via post 42, 44 ... sealing resin layer 43, 45 ... solder balls (external connection terminals) 50 ... core substrate (insulating material) 51 ... insulating layer 52 ... solder resist layer 59 ... land portion

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshihiro Ihara Nagano Prefecture Nagano City Oita Kurita-jisha Toshida 711 Inside Shinko Electric Industries Co., Ltd. F-term (reference) in Denki Kogyo Co., Ltd. AA26 AA40 BB15 BB30 CC01 CC07 CC09 CC16 DD04 DD24 GG04 5F046 AA20

Claims (9)

[Claims] The surface of a wiring layer formed on an insulating layer is electrically connected to a lower conductive layer through a via hole formed in the insulating layer by using a material having excellent environmental resistance. A wiring structure characterized by being covered with a covering layer made of: 2. The wiring structure according to claim 1, wherein nickel / gold, nickel / palladium, or nickel / palladium / gold is used as the material having excellent environmental resistance. 3. A resist layer is formed on the insulating layer in which the via hole is formed, and the resist layer is patterned so as to follow a pattern shape obtained by adding a predetermined margin to a required wiring pattern. Forming an opening in a portion of the resist layer including a region corresponding to the via hole; forming a conductor layer so as to fill the opening; and a surface layer portion on an upper surface side and a side surface side of the conductor layer Forming a wiring layer by removing the conductive layer by etching until the pattern shape of the conductive layer becomes the shape of the required wiring pattern, and forming a coating layer made of a material having excellent environmental resistance on the surface of the wiring layer. Forming a wiring. 4. Prior to the step of forming the opening, a metal thin film is formed by sputtering so as to cover the insulating layer in which the via hole is formed and a lower conductive layer exposed from the via hole. 4. The method according to claim 3, further comprising the step of: forming a conductor layer so as to fill the opening by electrolytic plating using the metal thin film as a power supply layer. 5. A first resist layer is formed on an insulating layer in which a via hole is formed, and the first resist layer follows a pattern shape obtained by adding a predetermined wiring pattern to a predetermined margin and adding a predetermined margin. The vias
Forming a first opening in a portion of the first resist layer including a region corresponding to the hole; and forming the patterned first resist layer and the first
Forming a second resist layer so as to cover the opening of the second resist layer, and patterning the second resist layer so as to conform to the shape of the required wiring pattern; and forming a second resist layer at the position of the first opening. Forming a second opening in the layer; forming a wiring layer in the second opening; removing the patterned second resist layer; and resisting a surface of the wiring layer. Forming a coating layer made of a material having excellent environmental properties. 6. A metal thin film is sputtered so as to cover the insulating layer in which the via hole is formed and a lower conductive layer exposed from the via hole before the step of forming the first opening. 6. The method according to claim 5, further comprising the step of: forming a wiring layer in the second opening by electrolytic plating using the metal thin film as a power supply layer. 7. The wiring forming method according to claim 5, wherein the removal of the patterned second resist layer is performed using a chemical solution that does not affect the first resist layer. 8. The wiring forming method according to claim 3, wherein the predetermined margin defines a thickness of the covering layer to be formed on a surface of the wiring layer. 9. The method according to claim 3, wherein nickel / gold, nickel / palladium, or nickel / palladium / gold is used as the material having excellent environmental resistance. Wiring formation method.