[go: up one dir, main page]

JP2001044327A - Wiring board and its mounting structure - Google Patents

Wiring board and its mounting structure

Info

Publication number
JP2001044327A
JP2001044327A JP11217012A JP21701299A JP2001044327A JP 2001044327 A JP2001044327 A JP 2001044327A JP 11217012 A JP11217012 A JP 11217012A JP 21701299 A JP21701299 A JP 21701299A JP 2001044327 A JP2001044327 A JP 2001044327A
Authority
JP
Japan
Prior art keywords
resin
wiring board
connection
connection electrode
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11217012A
Other languages
Japanese (ja)
Inventor
Shinya Kawai
信也 川井
Masahiko Azuma
昌彦 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP11217012A priority Critical patent/JP2001044327A/en
Publication of JP2001044327A publication Critical patent/JP2001044327A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

(57)【要約】 【課題】絶縁基板の裏面に複数の接続用電極層と接続端
子が配設された配線基板を外部回路基板に実装した場合
において、発生する応力を緩和し、強固に且つ長期にわ
たり安定した接続状態を維持する。 【解決手段】絶縁基板1と、該絶縁基板1の表面および
/または内部に配設された配線回路層2と、前記絶縁基
板1の裏面に配設された複数の接続用電極層3と、該接
続用電極層3に導電性接着剤8によって取着された複数
の接続端子7を具備する配線基板Aにおいて、接続端子
7のうち少なくとも4隅z位置する接続端子7aを導電
性樹脂を含有するか、あるいは絶縁性樹脂と金属粉末と
の混合物からなり、ヤング率が30GPa以下、接続用
電極層3のヤング率よりも低い樹脂含有導体材料によっ
て形成し、これをプリント基板などの外部回路基板Bに
実装する。
(57) [Summary] [Problem] To reduce the stress generated when a wiring board having a plurality of connection electrode layers and connection terminals arranged on the back surface of an insulating substrate is mounted on an external circuit board, and to reduce the stress generated. Maintain a stable connection for a long time. An insulating substrate, a wiring circuit layer disposed on the surface and / or inside the insulating substrate, a plurality of connection electrode layers disposed on a back surface of the insulating substrate, and In the wiring board A having the plurality of connection terminals 7 attached to the connection electrode layer 3 with the conductive adhesive 8, at least four corners z of the connection terminals 7 are made of conductive resin. Or made of a resin-containing conductor material having a Young's modulus of 30 GPa or less and lower than the Young's modulus of the connection electrode layer 3, made of a mixture of an insulating resin and a metal powder, and formed of an external circuit board such as a printed board. Mount on B.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えばセラミック
やガラスセラミックあるいは合成(有機)樹脂等により
構成される絶縁基板と配線回路層および接続端子を具備
する半導体素子収納用パッケージなどの配線基板と、そ
れをマザーボードなどの外部回路基板に実装した実装構
造の改良に関するものである。
The present invention relates to an insulating substrate made of, for example, ceramic, glass ceramic or synthetic (organic) resin, and a wiring substrate such as a semiconductor device housing package having a wiring circuit layer and connection terminals. The present invention relates to the improvement of a mounting structure in which the mounting structure is mounted on an external circuit board such as a motherboard.

【0002】[0002]

【従来技術】従来より、配線基板は、絶縁基板の表面お
よび/または内部に配線回路層が配設された構造からな
り、代表例として、半導体素子、特にLSI等の半導体
素子を収容するための半導体素子収納用パッケージが挙
げられる。
2. Description of the Related Art Conventionally, a wiring board has a structure in which a wiring circuit layer is disposed on the surface and / or inside of an insulating substrate, and as a typical example, a semiconductor element, particularly a semiconductor element such as an LSI is accommodated. A package for housing a semiconductor element is exemplified.

【0003】半導体素子収納用パッケージは、絶縁層と
してアルミナに代表されるセラミック、あるいはガラス
セラミック、さらには有機樹脂等が用いられている。特
にアルミナを用いた半導体素子収納用パッケージでは、
その表面および内部にWやMo等の配線回路層が設けら
れ、さらに底面には、外部回路基板との接続用電極層が
配設される。さらに、その絶縁基板の上面中央部には、
半導体素子との接続用電極層が形成され、その上に半導
体素子を載置し、ワイヤボンディング等により配線回路
層と電気的に接続された後、樹脂等を用いて封止され
る。あるいは、その絶縁基板の上面中央部には、半導体
素子を載置し収容するためのキャビティが形成され、こ
のキャビティは半導体素子を載置した後、蓋体をロウ付
けすることにより気密封止される。
[0003] In the package for housing a semiconductor element, a ceramic typified by alumina, a glass ceramic, an organic resin or the like is used as an insulating layer. Especially for semiconductor element storage packages using alumina,
A wiring circuit layer of W, Mo or the like is provided on the surface and inside, and an electrode layer for connection to an external circuit board is provided on the bottom surface. Furthermore, in the center of the upper surface of the insulating substrate,
An electrode layer for connection with the semiconductor element is formed, the semiconductor element is mounted thereon, and is electrically connected to the wiring circuit layer by wire bonding or the like, and then sealed with a resin or the like. Alternatively, a cavity for mounting and housing the semiconductor element is formed at the center of the upper surface of the insulating substrate, and after mounting the semiconductor element, the cavity is hermetically sealed by brazing a lid. You.

【0004】一般に半導体素子の集積度が高まるほど、
それに形成される電極数も増大するが、これに伴い、こ
れを収納する半導体収納用パッケージにおける外部回路
基板との接続端子電極数も増大する。ところが、電極数
を増大させるとパッケージの大型化を招くため、パッケ
ージの小型化への要求と相まって、パッケージの接続端
子電極の形成密度を高くする必要がある。
In general, as the degree of integration of semiconductor devices increases,
Although the number of electrodes formed thereon also increases, the number of connection terminal electrodes for connecting to an external circuit board in a semiconductor storage package for storing the same also increases. However, an increase in the number of electrodes leads to an increase in the size of the package. Therefore, it is necessary to increase the formation density of the connection terminal electrodes of the package, in conjunction with the demand for downsizing the package.

【0005】かかる市場要求において、パッケージの下
面にコバールなどの金属ピンを接続したピングリッドア
レイ(PGA)が製品化されているが、最近、パッケー
ジの4つの側面に導出された配線回路層にガルウイング
状(L字状)の金属ピンが接続されたタイプのクワッド
フラットパッケージ(QFP)、パッケージの4つの側
面に電極パッドを備え、リードピンがないリードレスチ
ップキャリア(LCC)、Siチップをフリップチップ
実装したチップサイズパッケージ(CSP)、さらに絶
縁基板の下面に半田からなる球状端子を多数配置したボ
ールグリッドアレイ(BGA)等がありこれらの中でも
BGAが最も高密度化が可能である。
[0005] In response to such market demands, a pin grid array (PGA) in which metal pins such as Kovar are connected to the lower surface of the package has been commercialized, but recently, gull wings are provided on wiring circuit layers led out on four sides of the package. -Type (L-shaped) quad flat package (QFP) with metal pins connected, electrode pads on four sides of the package, leadless chip carrier (LCC) without lead pins, flip chip mounting of Si chip And a ball grid array (BGA) in which a large number of spherical terminals made of solder are arranged on the lower surface of the insulating substrate. Of these, the BGA can achieve the highest density.

【0006】このボールグリッドアレイ(BGA)によ
れば、接続用電極層に半田などのロウ材からなる球状体
の接続端子をロウ付けし、この球状の接続端子を外部回
路基板の接続用電極層上に載置当接させ、しかる後、上
記端子自体を約250〜400℃で加熱溶融するか、ま
たは接続端子を低融点のロウ材によって接続端子を接続
用電極層と接続することによって配線基板を外部回路基
板上に実装される。
According to the ball grid array (BGA), a spherical connection terminal made of a brazing material such as solder is brazed to the connection electrode layer, and the spherical connection terminal is connected to the connection electrode layer of the external circuit board. Then, the terminal is heated and melted at about 250 to 400 ° C., or the connection terminal is connected to the connection electrode layer with a low melting point brazing material. Is mounted on an external circuit board.

【0007】[0007]

【発明が解決しようとする課題】配線基板や半導体素子
収納用パッケージにおける絶縁基板として、セラミック
あるいはガラスセラミック系配線基板は、有用性の高い
強度や気密封止性あるいは配線回路層などの多層化技術
など、有機樹脂を用いる場合に比べ高い信頼性が得られ
ている。
As an insulating substrate in a wiring board or a package for accommodating a semiconductor element, a ceramic or glass-ceramic wiring board has a high usefulness, a hermetic sealing property, or a multilayer technology such as a wiring circuit layer. For example, higher reliability is obtained as compared with the case where an organic resin is used.

【0008】また、半導体素子収納用パッケージなどの
配線基板上に半導体素子を収容した配線基板をプリント
基板などの外部回路基板表面に実装した場合、半導体素
子の作動時に発する熱が絶縁基板とプリント基板の両方
に繰り返し印加されるが、セラミックあるいはガラスセ
ラミック絶縁基板の熱膨張係数は一般に約4〜7ppm
/℃程度であるのに対して、パッケージを実装する外部
回路基板として多用されているプリント基板(ガラス−
エポキシ絶縁層にCu配線層が形成されたもの)の熱膨
張係数は11〜18ppm/℃と非常に大きいため、双
方間の大きな熱膨張係数差によって、大きな熱応力が発
生し、配線基板やパッケージをプリント基板に長期にわ
たり安定に電気的に接続させることができないという問
題があった。
Further, when a wiring board containing a semiconductor element is mounted on a wiring board such as a package for housing a semiconductor element on the surface of an external circuit board such as a printed board, heat generated during operation of the semiconductor element is generated between the insulating board and the printed board. The thermal expansion coefficient of the ceramic or glass ceramic insulating substrate is generally about 4 to 7 ppm.
/ ° C, whereas printed circuit boards (glass-
(Cu wiring layer formed on epoxy insulating layer) has a very large thermal expansion coefficient of 11 to 18 ppm / ° C., so that a large thermal expansion coefficient causes a large thermal stress to be generated, resulting in a wiring board or package. Cannot be stably electrically connected to a printed circuit board for a long period of time.

【0009】特に、端子数が300を超えるパッケージ
や大型のパッケージでは、その熱応力の影響が大きくな
り、そのため、半導体素子の作動および停止の繰り返し
により、配線基板下面の接続用電極層の外周部および配
線基板側の接続用電極層と接続端子との接合界面に特に
大きな熱応力が作用し、その結果、接続用電極層が絶縁
基板から剥離したり、接続端子が配線基板側の接続用電
極層から剥離するなど、配線基板をプリント基板に長期
にわたり安定に電気的に接続させることができないとい
う問題があった。
Particularly, in the case of a package having more than 300 terminals or a large package, the influence of the thermal stress increases. Therefore, the operation of the semiconductor element is repeatedly started and stopped, so that the outer periphery of the connection electrode layer on the lower surface of the wiring board is reduced. In particular, a large thermal stress acts on the bonding interface between the connection electrode layer on the wiring board side and the connection terminal, and as a result, the connection electrode layer is peeled off from the insulating substrate, or the connection terminal is disconnected from the connection electrode on the wiring board side. There has been a problem that the wiring board cannot be stably electrically connected to the printed board for a long period of time, such as peeling from the layer.

【0010】さらには、配線基板あるいは半導体収納用
パッケージを実装した外部回路基板を各種電子機器本体
にネジ、ピン等を用いて実装する際に発生する機械的応
力や外部回路基板のたわみ、変形等による機械的応力、
電子機器本体の落下時等に加わる衝撃による応力など、
様々な応力が配線基板下面の接続用電極層の外周部およ
び配線基板側の接続用電極層と接続端子との接合界面に
作用し、その結果、接続用電極層が絶縁基板から剥離し
たり、接続端子が接続用電極層から剥離し、配線基板を
プリント基板に長期にわたり安定に電気的接続させるこ
とができないという問題があった。
Further, mechanical stress, bending, deformation, etc., generated when mounting an external circuit board on which a wiring board or a semiconductor package is mounted to various electronic device bodies using screws, pins, etc. Mechanical stress,
Such as the stress caused by the impact applied when the electronic device falls, etc.
Various stresses act on the outer peripheral portion of the connection electrode layer on the lower surface of the wiring board and the bonding interface between the connection electrode layer on the wiring board and the connection terminal, and as a result, the connection electrode layer peels off from the insulating substrate, There has been a problem that the connection terminal is separated from the connection electrode layer, and the wiring board cannot be stably and electrically connected to the printed board for a long time.

【0011】したがって、本発明は、絶縁基板の裏面に
複数の接続用電極層と接続端子が配設された配線基板を
外部回路基板に実装した場合において、発生する応力を
緩和し、強固に且つ長期にわたり安定した接続状態を維
持できる高い信頼性の配線基板およびその実装構造を提
供することを目的とする。
Therefore, the present invention reduces the stress generated when a wiring board having a plurality of connection electrode layers and connection terminals arranged on the back surface of an insulating substrate is mounted on an external circuit board, and provides a strong and robust structure. It is an object of the present invention to provide a highly reliable wiring board capable of maintaining a stable connection state for a long time and a mounting structure thereof.

【0012】[0012]

【課題を解決するための手段】本発明者らは、半導体素
子収納用パッケージ等の配線基板の外部回路基板に対す
る実装時、あるいは使用時において生じる熱応力を緩和
するために、種々検討を重ねた結果、少なくとも4隅に
位置する接続端子を樹脂含有導体材料によって形成する
ことによって、樹脂含有導体材料が応力を吸収し、長期
にわたり安定した接続状態を維持でき、高い信頼性を得
ることができることを見い出した。
Means for Solving the Problems The present inventors have conducted various studies in order to reduce the thermal stress generated when a wiring board such as a package for housing a semiconductor element is mounted on an external circuit board or used. As a result, by forming the connection terminals located at least at the four corners with the resin-containing conductor material, the resin-containing conductor material can absorb stress, maintain a stable connection state for a long time, and obtain high reliability. I found it.

【0013】即ち、本発明の配線基板は、絶縁基板と、
該絶縁基板の表面および/または内部に配設された配線
回路層と、前記絶縁基板の裏面に配設された複数の接続
用電極層と、該接続用電極層に導電性接着剤によって取
着された複数の接続端子を具備する配線基板において、
前記接続端子のうち少なくとも4隅に位置する接続端子
を樹脂含有導体材料によって形成したことことを特徴と
するものである。
That is, the wiring board of the present invention comprises: an insulating substrate;
A wiring circuit layer provided on the surface and / or inside of the insulating substrate, a plurality of connecting electrode layers provided on the back surface of the insulating substrate, and attached to the connecting electrode layer by a conductive adhesive; In a wiring board having a plurality of connection terminals,
At least four connection terminals among the connection terminals are formed of a resin-containing conductor material.

【0014】また、本発明の配線基板の実装構造は、絶
縁基板と、該絶縁基板の表面および/または内部に配設
された配線回路層と、前記絶縁基板の裏面に配設された
複数の第1の接続用電極層と、該第1の接続用電極層に
取着された複数の接続端子を具備する配線基板と、絶縁
体と、該絶縁体表面に配設された複数個の第2の接続用
電極層とを具備する外部回路基板と、を具備し、前記外
部回路基板の表面に前記配線基板を載置し、前記第1の
接続用電極層と、前記第2の接続用電極層とを前記接続
端子を介してそれぞれ電気的に接続してなる配線基板の
実装構造において、前記接続端子のうち少なくとも4隅
に位置する接続端子を樹脂含有導体材料によって形成し
たことを特徴とするものである。
Further, the mounting structure of the wiring board according to the present invention comprises an insulating substrate, a wiring circuit layer disposed on the surface and / or inside the insulating substrate, and a plurality of wiring circuits disposed on the back surface of the insulating substrate. A first connection electrode layer, a wiring board including a plurality of connection terminals attached to the first connection electrode layer, an insulator, and a plurality of first electrodes disposed on the insulator surface. An external circuit board comprising: a first connection electrode layer; and a second connection electrode layer, wherein the first connection electrode layer and the second connection electrode layer are mounted on the surface of the external circuit board. In a mounting structure of a wiring board in which electrode layers are electrically connected to each other via the connection terminals, connection terminals located at at least four corners of the connection terminals are formed of a resin-containing conductor material. Is what you do.

【0015】なお、かかる構成において、前記樹脂含有
導体材料が、導電性樹脂を含有すること、あるいは絶縁
性樹脂と金属粉末との混合物からなること、ヤング率が
30GPa以下であり、且つ接続用電極層のヤング率よ
りも低いこと、さらには、樹脂含有導体材料中の樹脂の
熱分解温度が、上記導電性接着剤の融点よりも高いこと
が望ましい。
In this configuration, the resin-containing conductor material contains a conductive resin, or is made of a mixture of an insulating resin and metal powder, has a Young's modulus of 30 GPa or less, and has a connection electrode. It is desirable that the Young's modulus of the layer is lower than that of the conductive adhesive, and that the thermal decomposition temperature of the resin in the resin-containing conductor material is higher than the melting point of the conductive adhesive.

【0016】また、前記接続端子としては球状体または
柱状体からなるボールグリッドアレイ(BGA)型パッ
ケージであることが望ましい。
It is preferable that the connection terminal is a ball grid array (BGA) type package made of a spherical body or a columnar body.

【0017】[0017]

【発明の実施の形態】図1は、本発明の配線基板の一例
として、BGA型半導体素子収納用パッケージAの
(a)概略断面図と(b)その要部断面図、図2はパッ
ケージAの裏面の平面図、図3は図1のパッケージAを
外部回路基板としてプリント基板Bへの実装構造を説明
するための概略断面図である。
FIG. 1 is a schematic cross-sectional view of a package A for storing a BGA type semiconductor device as an example of a wiring board according to the present invention, and FIG. FIG. 3 is a schematic cross-sectional view for explaining a mounting structure on a printed circuit board B using the package A of FIG. 1 as an external circuit board.

【0018】図1(a)によれば、半導体素子収納用パ
ッケージAは、絶縁基板1の表面および内部に配線回路
層2が形成され、絶縁基板1の裏面には、図2に示すよ
うに、複数の接続端子7が配列されて被着形成されてい
る。絶縁基板1の上面中央部には半導体素子4がガラ
ス、樹脂等の接着剤を介して絶縁基板1に接着固定さ
れ、半導体素子4は配線回路層2とワイヤボンディング
5により電気的に接続され、さらにその上から封止樹脂
6により覆うことにより封止されている。そして、半導
体素子4と、絶縁基板1の下面に形成された複数の接続
用電極層3とは、配線回路層2を経由して電気的に接続
するように配設されている。
Referring to FIG. 1A, a package A for storing semiconductor elements has a wiring circuit layer 2 formed on the surface and the inside of an insulating substrate 1, and on the back surface of the insulating substrate 1, as shown in FIG. A plurality of connection terminals 7 are arranged and adhered. At the center of the upper surface of the insulating substrate 1, a semiconductor element 4 is adhered and fixed to the insulating substrate 1 via an adhesive such as glass or resin, and the semiconductor element 4 is electrically connected to the wiring circuit layer 2 by wire bonding 5, Furthermore, it is sealed by covering it with a sealing resin 6 from above. The semiconductor element 4 and the plurality of connection electrode layers 3 formed on the lower surface of the insulating substrate 1 are provided so as to be electrically connected via the wiring circuit layer 2.

【0019】なお、半導体素子の実装方法および封止方
法としては、配線基板上面中央部に半田バンプ等を用い
て直接載置するフリップチップ実装や、配線基板上面に
キャビティを形成し、キャビティ内に載置しその上から
蓋体をロウ付けすることにより気密封止する方法などが
ある。
As a method for mounting and sealing a semiconductor element, flip-chip mounting in which a semiconductor chip is directly mounted at the center of the upper surface of a wiring substrate using a solder bump or the like, or forming a cavity in the upper surface of the wiring substrate and forming a cavity in the cavity There is a method of airtight sealing by mounting and brazing a lid from above.

【0020】また、半導体素子収納用パッケージAによ
れば、接続用電極層3の表面には、球状体または柱状体
からなる接続端子7が半田などの導電性接着剤8によっ
て取着されている。
Further, according to the semiconductor element housing package A, the connection terminals 7 made of a spherical body or a columnar body are attached to the surface of the connection electrode layer 3 by the conductive adhesive 8 such as solder. .

【0021】本発明によれば、上記のBGA型半導体素
子収納用パッケージAにおいて、絶縁基板1の裏面に複
数形成された接続端子7の少なくとも図2に示すパッケ
ージAの裏面の平面図に示す配列のうち、少なくとも4
隅に位置する接続端子7を樹脂含有導体材料によって形
成したことが大きな特徴である。
According to the present invention, in the BGA type semiconductor element housing package A, the arrangement of the plurality of connection terminals 7 formed on the back surface of the insulating substrate 1 is shown in at least the plan view of the back surface of the package A shown in FIG. At least 4
A major feature is that the connection terminals 7 located at the corners are formed of a resin-containing conductor material.

【0022】この樹脂含有導体材料からなる接続端子7
は、図1(b)のように配列された複数の接続端子7の
うち、図2の4隅に位置する接続端子7aを意味する。
これは、パッケージAを外部回路基板Bに実装した場合
において、応力が最も大きくなる部分が4隅に位置する
接続端子7aであるためで、さらには、4隅に位置する
接続端子7aとともに、接続端子7aに近接する接続端
子7bを樹脂含有導体材料によって形成することが望ま
しく、さらには、絶縁基板1の裏面に形成されたすべて
の接続端子7を樹脂含有導体材料によって形成すること
が最も望ましい。
Connection terminal 7 made of this resin-containing conductor material
Means connection terminals 7a located at four corners in FIG. 2 among a plurality of connection terminals 7 arranged as shown in FIG. 1B.
This is because, when the package A is mounted on the external circuit board B, the portions where the stress is greatest are the connection terminals 7a located at the four corners. It is desirable that the connection terminals 7b adjacent to the terminals 7a be formed of a resin-containing conductor material, and it is most desirable that all of the connection terminals 7 formed on the back surface of the insulating substrate 1 be formed of a resin-containing conductor material.

【0023】この樹脂含有導体材料は、少なくとも樹脂
成分を含有するものであればよく、体積固有抵抗が10
0μΩ・cm以下であることが望ましい。具体的には、
1)導電性成分として導電性樹脂を含む場合、2)金属
粉末と上記導電性樹脂または絶縁性樹脂との混合物から
なるものである。
The resin-containing conductor material only needs to contain at least a resin component, and has a volume resistivity of 10%.
Desirably, it is 0 μΩ · cm or less. In particular,
1) When a conductive resin is contained as a conductive component, 2) It is composed of a mixture of a metal powder and the above-mentioned conductive resin or insulating resin.

【0024】導電性を有する樹脂としては、周知の樹脂
が用いられ、例えば、ポリアセチレン系樹脂、ポリフェ
ニレン系樹脂、イオン性樹脂等が挙げられる。
As the resin having conductivity, a well-known resin is used, and examples thereof include a polyacetylene resin, a polyphenylene resin, and an ionic resin.

【0025】また、金属粉末としては、Au、Ag、C
u、Al、Ni、Fe、Pd、Pt、W、Mo、Mn、
Pb、Sn、Bi、SbおよびInから選ばれる少なく
とも1種以上、好適には、Au、Ag、Cu、Al、N
i、PtおよびPdから選ばれる少なくとも1種以上、
最適にはAu、AgおよびCuから選ばれる少なくとも
1種以上の金属粉末あるいは2種以上の合金粉末が好適
に用いられる。
As the metal powder, Au, Ag, C
u, Al, Ni, Fe, Pd, Pt, W, Mo, Mn,
At least one or more selected from Pb, Sn, Bi, Sb and In, preferably Au, Ag, Cu, Al, N
i, at least one or more selected from Pt and Pd;
Most preferably, at least one or more metal powders or two or more alloy powders selected from Au, Ag and Cu are suitably used.

【0026】導電性成分として上記の導電性樹脂を含有
する場合、又は金属粉末を含有する場合、樹脂分として
は、保形性および使用環境下での安定性の点で少なくと
も熱硬化性樹脂あるいは紫外線硬化型樹脂が望ましく、
このような樹脂成分としては、エポキシ系樹脂、ウレタ
ン系樹脂、アクリル系樹脂、ポリイミド系樹脂、ポリエ
ステル系樹脂、ポリフェノール系樹脂の群から選ばれる
少なくとも1種が挙げられる。
When the above-mentioned conductive resin is contained as a conductive component or when a metal powder is contained, the resin component is at least a thermosetting resin or a thermosetting resin in terms of shape retention and stability in a use environment. UV curing resin is desirable,
Examples of such a resin component include at least one selected from the group consisting of an epoxy resin, a urethane resin, an acrylic resin, a polyimide resin, a polyester resin, and a polyphenol resin.

【0027】また、樹脂含有導体材料が上記金属粉末と
上記樹脂成分とからなる場合、金属粉末の含有量は80
重量%以上であることが望ましい。
When the resin-containing conductor material comprises the metal powder and the resin component, the content of the metal powder is 80%.
It is desirable that the content be not less than% by weight.

【0028】本発明によれば、このような樹脂分を含有
する接続端子7を形成させることにより、樹脂が有する
低ヤング率特性によって、後述する外部回路基板Bの実
装時において種々の要因によって発生する応力をこの樹
脂含有導体材料によって緩和することができる。
According to the present invention, by forming the connection terminal 7 containing such a resin component, the connection terminal 7 has a low Young's modulus characteristic due to the resin, and is generated by various factors when the external circuit board B described later is mounted. Stress can be reduced by the resin-containing conductor material.

【0029】従って、前記樹脂含有導体材料のヤング率
が、前記接続用電極層3よりもヤング率が低いことが効
果的であり、特にヤング率が30GPa以下、20GP
a以下、最適には15GPa以下であることが望まし
く、所望のヤング率を得るためには、用いる樹脂成分の
性質によって金属粉末の選択およびその配合比や硬化条
件を適宜変えることにより行う。
Therefore, it is effective that the resin-containing conductor material has a Young's modulus lower than that of the connection electrode layer 3, especially a Young's modulus of 30 GPa or less and 20 GPa or less.
a, preferably 15 GPa or less, and the desired Young's modulus is obtained by appropriately selecting the metal powder and appropriately changing the mixing ratio and the curing conditions depending on the properties of the resin component used.

【0030】さらに、樹脂含有導体材料中の樹脂の熱分
解温度は、接続端子7を取着するために用いられる導電
性接着剤の融点よりも高いことが望ましい。これは、導
電性接着剤の融点よりも熱分解温度が低いと、接続端子
7を接続用電極層3に取着する際に、樹脂分が分解して
揮散してしまうためである。
Further, the thermal decomposition temperature of the resin in the resin-containing conductor material is desirably higher than the melting point of the conductive adhesive used for attaching the connection terminal 7. This is because if the thermal decomposition temperature is lower than the melting point of the conductive adhesive, the resin component is decomposed and volatilized when the connection terminal 7 is attached to the connection electrode layer 3.

【0031】なお、接続端子7は、接続用電極層3に導
電性接着剤8を形成し、導電性接着剤8の上に接続端子
7を位置合わせして載置し、導電性接着剤8が溶融し樹
脂含有導体材料中の樹脂が熱分解しない温度にてリフロ
ー炉や赤外線炉あるいはVPSなどにより加熱して導電
性接着剤8を溶融させることにより、接続用電極層3上
にあるいは樹脂含有導体材料の接続端子7を取着するこ
とができる。
The connection terminal 7 is formed by forming a conductive adhesive 8 on the connection electrode layer 3, positioning the connection terminal 7 on the conductive adhesive 8, and placing the conductive adhesive 8. Is melted and heated in a reflow oven, infrared oven, VPS, or the like at a temperature at which the resin in the resin-containing conductor material does not thermally decompose, thereby melting the conductive adhesive 8 on the connection electrode layer 3 or containing the resin. The connection terminal 7 made of a conductive material can be attached.

【0032】次に、上記の構造からなるパッケージAを
外部回路基板Bに実装した場合の構造について説明す
る。図3のパッケージAの外部回路基板B(以下、プリ
ント基板Bと称する。)への実装構造によれば、プリン
ト基板Bは、絶縁体10表面に、パッケージAにおける
絶縁基板1の裏面に取着形成された複数の接続端子7と
対応するように、複数の接続用電極層9が被着形成され
ており、パッケージAの絶縁基板1の裏面に形成された
接続用電極層3上の接続端子7とプリント基板B表面の
接続用電極層9とが半田などの導電性接着剤11によっ
て接続されている。
Next, the structure when the package A having the above structure is mounted on the external circuit board B will be described. According to the mounting structure of the package A of FIG. 3 on an external circuit board B (hereinafter, referred to as a printed board B), the printed board B is attached to the surface of the insulator 10 and to the back surface of the insulating substrate 1 in the package A. A plurality of connection electrode layers 9 are formed so as to correspond to the plurality of connection terminals 7 formed, and the connection terminals on the connection electrode layer 3 formed on the back surface of the insulating substrate 1 of the package A. 7 and the connection electrode layer 9 on the surface of the printed circuit board B are connected by a conductive adhesive 11 such as solder.

【0033】かかる実装構造において、本発明では、パ
ッケージAの接続用電極層3とプリント基板Bの接続用
電極層9との接続端子7を介し、少なくとも4隅に位置
する接続端子7を樹脂含有導体材料によって形成する。
In such a mounting structure, according to the present invention, the connection terminals 7 located at at least four corners are made of a resin containing via the connection terminals 7 between the connection electrode layer 3 of the package A and the connection electrode layer 9 of the printed board B. It is formed of a conductive material.

【0034】また、少なくとも4隅に位置する接続部と
は、図2で説明したように、4隅に位置する接続端子7
aを意味する。これは、パッケージAを外部回路基板B
に実装した場合において、応力が最も大きくなる部分が
4隅に位置する接続端子7aであるためで、さらには、
4隅に位置する接続端子7aとともに、複数の接続端子
7aに近接する接続端子7bを樹脂含有導体材料によっ
て形成することが望ましく、さらには、絶縁基板1の裏
面に形成されたすべての接続端子7を樹脂含有導体材料
によって形成することが最も望ましい。
The connection portions located at least at the four corners are, as described with reference to FIG. 2, the connection terminals 7 located at the four corners.
means a. This is because package A is connected to external circuit board B
This is because, when mounted on the connection terminal, the portion where the stress becomes the largest is the connection terminal 7a located at the four corners.
It is preferable that the connection terminals 7a located at the four corners and the connection terminals 7b adjacent to the plurality of connection terminals 7a be formed of a resin-containing conductor material. Further, all the connection terminals 7a formed on the back surface of the insulating substrate 1 are formed. Is most desirably formed of a resin-containing conductor material.

【0035】そして、半導体素子収納用パッケージAを
プリント基板Bに実装するには、パッケージAの接続端
子7がプリント基板Bの接続用電極層9表面の導電性接
着剤11に当接するように位置合わせして載置し、両者
をリフロー炉や赤外線炉あるいはVPSなどにより加熱
して導電性接着剤11を加熱溶融させて、樹脂含有導体
材料からなる接続端子7、導電性接着剤11を介して接
続用電極層9上に固着することによりパッケージAをプ
リント基板Bに実装する。
In order to mount the package A for housing semiconductor elements on the printed circuit board B, the connection terminals 7 of the package A are positioned so as to contact the conductive adhesive 11 on the surface of the connection electrode layer 9 of the printed circuit board B. The conductive adhesive 11 is heated and melted by a reflow oven, an infrared oven, a VPS, or the like, and is heated and melted. The package A is mounted on the printed circuit board B by being fixed on the connection electrode layer 9.

【0036】なお、接続端子7と接続用電極層9を接続
するための導電性接着剤は、上述したようなPb−Sn
系などの半田の他に、4隅の接続端子7を形成している
樹脂含有導体材料と同様の導体材料によって形成しても
よい。
The conductive adhesive for connecting the connection terminal 7 and the connection electrode layer 9 is made of Pb-Sn as described above.
In addition to a solder such as a system, it may be formed of the same conductive material as the resin-containing conductive material forming the connection terminals 7 at the four corners.

【0037】かくして上記構成の実装構造によれば、半
導体素子の電源ON、OFF時等に発生する温度の上
昇、下降に伴って、パッケージAの絶縁基板1とプリン
ト基板Bとの間の熱膨張差により発生する熱応力が生じ
た場合、その応力が集中しクラックが発生しやすい箇所
にヤング率の低い樹脂含有導体材料の接続端子7が存在
するため、発生した応力がこの樹脂含有導体材料からな
る接続端子7により緩和されるため、クラックの発生が
抑制され、破壊にいたるのを防止でき、接続部の寿命を
著しく延ばすことができる結果、実装構造の長期信頼性
を高めることができる。
Thus, according to the mounting structure having the above-described structure, the thermal expansion between the insulating substrate 1 of the package A and the printed board B is caused by the rise and fall of the temperature generated when the power of the semiconductor element is turned on and off. When a thermal stress occurs due to the difference, the stress is concentrated, and the connection terminal 7 of the resin-containing conductor material having a low Young's modulus exists in a portion where cracks are easily generated. Since the connection terminals 7 alleviate the cracks, generation of cracks can be suppressed, breakage can be prevented, and the life of the connection portion can be significantly extended. As a result, long-term reliability of the mounting structure can be improved.

【0038】[0038]

【実施例】次に本発明の実施例を以下の通り詳述する。
アルミナを主成分とするセラミックグリーンシートに対
して、穴加工を行い、タングステンを主成分とするペー
ストを充填した後、その下面にビアホールに接続する接
続用電極層3、ビアホールを含む配線回路層2をスクリ
ーン印刷により形成し、さらに焼成後の基板厚みが2m
mとなるようにグリーンシートを加圧積層し、積層体を
得た。この積層体を配線回路層2、接続用電極層3とと
もに同時焼成して35mm□の配線基板(半導体素子収
納用パッケージA)を作製し、さらに接続用電極層3の
表面にNi−Auめっきを施した。
Next, embodiments of the present invention will be described in detail as follows.
A hole is formed in a ceramic green sheet containing alumina as a main component, a paste containing tungsten as a main component is filled, and a connection electrode layer 3 connected to a via hole and a wiring circuit layer 2 containing a via hole are formed on the lower surface thereof. Is formed by screen printing, and the thickness of the fired substrate is 2 m.
The green sheets were pressure-laminated so as to obtain m, and a laminate was obtained. This laminate is simultaneously fired together with the wiring circuit layer 2 and the connection electrode layer 3 to produce a 35 mm square wiring board (semiconductor element storage package A), and the surface of the connection electrode layer 3 is plated with Ni-Au. gave.

【0039】なお、接続用電極層3は、729個とし、
そのピッチは1.27mmとし、これを配線基板Aの裏
面にマトリックス状に配置した。
The number of connection electrode layers 3 is 729,
The pitch was 1.27 mm, which was arranged in a matrix on the back surface of the wiring board A.

【0040】その後、接続用電極層3上にPb37重量
%−Sn63重量%の半田ペーストを印刷し、この配線
基板の接続端子7のうち、4隅、周辺部、全面の電極層
3表面上に表1に示すように、樹脂成分に熱硬化性エポ
キシ樹脂、金属粉末としてAgを含み、且つヤング率を
適宜変えた樹脂含有導電材料によりあらかじめ直径0.
8mmの球状に成形した接続端子を載置し、リフロー炉
により230℃に加熱して半田を溶融して上記球状の接
続端子を固着した。
After that, a solder paste of 37% by weight of Pb-63% by weight of Sn is printed on the connection electrode layer 3, and the connection terminals 7 of this wiring board are coated on the surface of the electrode layer 3 at four corners, peripheral portions, and the entire surface. As shown in Table 1, the resin component contained a thermosetting epoxy resin, Ag as a metal powder, and a resin-containing conductive material whose Young's modulus was appropriately changed.
An 8 mm spherical connection terminal was placed, and heated to 230 ° C. in a reflow furnace to melt the solder and fix the spherical connection terminal.

【0041】また、プリント基板B上の接続用電極層9
上にも同様にして、Pb37重量%−Sn63重量%の
半田ペーストを印刷した。その後、配線基板Aをプリン
ト基板B上に位置あわせして載置した後、リフロー炉に
て230℃で処理して接続端子7を接着させて実装し
た。
The connection electrode layer 9 on the printed circuit board B
Similarly, a solder paste of 37% by weight of Pb and 63% by weight of Sn was printed. Thereafter, the wiring substrate A was positioned and mounted on the printed circuit board B, and then processed at 230 ° C. in a reflow furnace, and the connection terminals 7 were bonded and mounted.

【0042】なお、本実施例で用いたアルミナ製配線基
板の熱膨張係数は7ppm/℃、プリント基板の熱膨張
係数は14ppm/℃である。
The thermal expansion coefficient of the wiring board made of alumina used in this embodiment is 7 ppm / ° C., and the thermal expansion coefficient of the printed circuit board is 14 ppm / ° C.

【0043】次にこれら実装構造をそれぞれ大気雰囲気
にて−40℃と125℃の各温度に制御した恒温槽に交
互に配置し、双方ともに15分間づつ保持した場合を1
サイクルとした温度サイクル試験を最高1000サイク
ルまで行った。そして、50サイクル毎にプリント基板
Bの接続用電極層9と配線基板Aの接続用電極層3間の
電気抵抗を測定し、電気抵抗の変化が現れるまでのサイ
クル数を表1に示した。
Next, these mounting structures were alternately arranged in a constant temperature bath controlled at -40 ° C. and 125 ° C. in the air atmosphere, and both were held for 15 minutes.
A temperature cycle test was performed up to 1000 cycles. Then, the electrical resistance between the connection electrode layer 9 of the printed board B and the connection electrode layer 3 of the wiring board A was measured every 50 cycles, and the number of cycles until a change in the electrical resistance appeared is shown in Table 1.

【0044】なお、比較例として、全ての接続端子7を
Pb37%−Sn63%の共晶半田あるいはPb90%
−Sn10%の高温半田にて形成して球状の端子を用い
て上記と同様にして配線基板をプリント基板表面に実装
し、同様の評価を行った。
As a comparative example, all the connection terminals 7 were made of eutectic solder of Pb 37% -Sn 63% or Pb 90%.
A printed circuit board was mounted on the surface of the printed circuit board in the same manner as described above using a spherical terminal formed with high-temperature solder of -Sn10% and subjected to the same evaluation.

【0045】[0045]

【表1】 [Table 1]

【0046】表1から明らかなとおり、接続端子に樹脂
含有導体材料を全く用いない試料No.1、2では250
サイクル以下で抵抗変化が生じたのに対して、本発明に
従い、樹脂含有導体材料からなる接続端子を少なくとも
4隅に形成することにより、耐久性の向上が見られた。
特に、樹脂含有導体材料からなる接続端子を4隅に形成
し、樹脂含有導体材料をヤング率30GPa以下とする
ことにより、温度サイクル試験を500サイクルまで行
っても抵抗変化が見られず、特に、4隅とそれに近接す
る周囲の10個を樹脂含有導体材料からなる接続端子に
よって、さらには、全ての接続端子を樹脂含有導体材料
によって形成することによってさらに耐久性を向上させ
ることができた。
As is clear from Table 1, in Sample Nos. 1 and 2 in which no resin-containing conductor material is used for the connection terminals, 250
While the resistance change occurred in the cycle or less, the durability was improved by forming the connection terminals made of the resin-containing conductor material in at least four corners according to the present invention.
In particular, by forming connection terminals made of a resin-containing conductor material at four corners and setting the resin-containing conductor material to a Young's modulus of 30 GPa or less, no resistance change is observed even when a temperature cycle test is performed up to 500 cycles. The durability can be further improved by forming the connection terminals made of the resin-containing conductor material at the four corners and the surrounding ten terminals, and further, by forming all the connection terminals with the resin-containing conductor material.

【0047】かかる結果から、本発明の構成によって、
配線基板の外部回路基板に長期間にわたり正確かつ強固
に電気的接続させることが可能となり、配線基板の半導
体回路素子の大型化による多端子化に十分対応できる信
頼性の高い配線基板の実装構造を実現できた。
From these results, according to the configuration of the present invention,
A highly reliable wiring board mounting structure that can be accurately and firmly electrically connected to the external circuit board of the wiring board for a long period of time and that can sufficiently cope with the increase in the number of terminals due to the enlargement of semiconductor circuit elements on the wiring board. I realized it.

【0048】[0048]

【発明の効果】以上詳述したように、本発明の配線基板
およびその実装構造によれば、少なくとも4隅位置する
接続端子を樹脂含有導体材料によって形成したことによ
り、半導体素子が収納された半導体素子収納用パッケー
ジなどの配線基板を、ガラス−エポキシ樹脂等を絶縁体
とする外部回路基板に対して、強固に且つ長期にわたり
安定した接続状態を維持できる。
As described above in detail, according to the wiring board and the mounting structure of the present invention, the connection terminal located at least at the four corners is formed of the resin-containing conductor material, so that the semiconductor element containing the semiconductor element is accommodated. It is possible to maintain a stable and stable connection state for a long period of time between a wiring board such as an element storage package and an external circuit board using glass-epoxy resin or the like as an insulator.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の配線基板の一例としてBGA型半導体
素子収納用パッケージAの(a)概略断面図、(b)要
部断面図である。
FIG. 1A is a schematic sectional view of a package A for housing a BGA type semiconductor element as an example of a wiring board of the present invention, and FIG.

【図2】図1のパッケージAの裏面の平面図である。FIG. 2 is a plan view of the back surface of the package A of FIG.

【図3】図1のパッケージAを外部回路基板としてプリ
ント基板Bへの実装構造を説明するための概略断面図で
ある。
FIG. 3 is a schematic cross-sectional view for explaining a mounting structure on a printed circuit board B using the package A of FIG. 1 as an external circuit board.

【符号の説明】[Explanation of symbols]

A・・・配線基板(半導体素子収納用パッケージ) B・・・外部回路基板(プリント基板) 1・・・絶縁基板 2・・・配線回路層 3、9・・・接続用電極層 4・・・半導体素子 7・・・接続端子 8、11・・・導電性接着剤 A: Wiring board (package for storing semiconductor elements) B: External circuit board (printed board) 1: Insulating board 2: Wiring circuit layer 3, 9, ... Electrode layer for connection 4 ...・ Semiconductor element 7 ・ ・ ・ Connection terminal 8, 11 ・ ・ ・ Conductive adhesive

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E319 AA03 AC11 AC16 BB11 CC22 CD26 GG11 5E336 AA04 BB16 BB18 CC32 CC36 CC58 EE03 EE08 GG01 5E344 AA01 BB06 BB08 BB10 CC23 DD03 DD06 EE01  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E319 AA03 AC11 AC16 BB11 CC22 CD26 GG11 5E336 AA04 BB16 BB18 CC32 CC36 CC58 EE03 EE08 GG01 5E344 AA01 BB06 BB08 BB10 CC23 DD03 DD06 EE01

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】絶縁基板と、該絶縁基板の表面および/ま
たは内部に配設された配線回路層と、前記絶縁基板の裏
面に配設された複数の接続用電極層と、該接続用電極層
に導電性接着剤によって取着された複数の接続端子を具
備する配線基板において、前記接続端子のうち少なくと
も4隅に位置する接続端子を樹脂含有導体材料によって
形成したことを特徴とする配線基板。
1. An insulating substrate, a wiring circuit layer disposed on the surface and / or inside the insulating substrate, a plurality of connection electrode layers disposed on a back surface of the insulating substrate, and the connection electrode In a wiring board having a plurality of connection terminals attached to a layer by a conductive adhesive, at least four connection terminals among the connection terminals are formed of a resin-containing conductor material. .
【請求項2】前記樹脂含有導体材料が、導電性樹脂を含
有すること、あるいは絶縁性樹脂と金属粉末との混合物
からなることを特徴とする請求項1記載の配線基板。
2. The wiring board according to claim 1, wherein the resin-containing conductor material contains a conductive resin or is made of a mixture of an insulating resin and a metal powder.
【請求項3】前記樹脂含有導体材料のヤング率が30G
Pa以下であり、且つ前記接続用電極層のヤング率より
も低いことを特徴とする請求項1記載の配線基板。
3. The resin-containing conductor material has a Young's modulus of 30 G.
2. The wiring board according to claim 1, wherein the wiring board is equal to or less than Pa and lower than the Young's modulus of the connection electrode layer.
【請求項4】前記樹脂含有導体材料中の樹脂の熱分解温
度が、上記導電性接着剤の融点よりも高いことを特徴と
する請求項1記載の配線基板。
4. The wiring board according to claim 1, wherein a thermal decomposition temperature of the resin in the resin-containing conductor material is higher than a melting point of the conductive adhesive.
【請求項5】前記接続端子が、球状体または柱状体から
なることを特徴とする請求項1記載の配線基板。
5. The wiring board according to claim 1, wherein said connection terminal is formed of a spherical body or a columnar body.
【請求項6】絶縁基板と、該絶縁基板の表面および/ま
たは内部に配設された配線回路層と、前記絶縁基板の裏
面に配設された複数の第1の接続用電極層と、該第1の
接続用電極層に取着された複数の接続端子を具備する配
線基板と、絶縁体と、該絶縁体表面に配設された複数個
の第2の接続用電極層とを具備する外部回路基板と、を
具備し、前記外部回路基板の表面に前記配線基板を載置
し、前記第1の接続用電極層と、前記第2の接続用電極
層とを前記接続端子を介してそれぞれ電気的に接続して
なる配線基板の実装構造において、 前記接続端子のうち少なくとも4隅に位置する接続端子
を樹脂含有導体材料によって形成したことを特徴とする
配線基板の実装構造。
6. An insulating substrate, a wiring circuit layer disposed on a surface and / or inside the insulating substrate, a plurality of first connection electrode layers disposed on a back surface of the insulating substrate, A wiring board having a plurality of connection terminals attached to the first connection electrode layer, an insulator, and a plurality of second connection electrode layers provided on the insulator surface. An external circuit board, and the wiring board is placed on the surface of the external circuit board, and the first connection electrode layer and the second connection electrode layer are connected via the connection terminal. In a mounting structure of a wiring board electrically connected to each other, at least four connection terminals among the connection terminals are formed of a resin-containing conductor material.
【請求項7】前記樹脂含有導体材料が、導電性樹脂を含
有すること、あるいは絶縁性樹脂と金属粉末との混合物
からなることを特徴とする請求項6記載の配線基板の実
装構造。
7. The mounting structure for a wiring board according to claim 6, wherein the resin-containing conductor material contains a conductive resin or is made of a mixture of an insulating resin and a metal powder.
【請求項8】 前記樹脂含有導体材料のヤング率が30
GPa以下であり、且つ前記接続用電極層のヤング率よ
りも低いことを特徴とする請求項6記載の配線基板の実
装構造。
8. The resin-containing conductor material has a Young's modulus of 30.
7. The mounting structure of a wiring board according to claim 6, wherein GPa is equal to or less than GPa and lower than the Young's modulus of the connection electrode layer.
【請求項9】前記樹脂含有導体材料中の樹脂の熱分解温
度が、上記導電性接着剤の融点よりも高いことを特徴と
する請求項6記載の配線基板の実装構造。
9. The mounting structure according to claim 6, wherein a thermal decomposition temperature of the resin in the resin-containing conductor material is higher than a melting point of the conductive adhesive.
【請求項10】前記接続端子が、球状体または柱状体か
らなることを特徴とする請求項6記載の配線基板の実装
構造。
10. The mounting structure for a wiring board according to claim 6, wherein said connection terminal is formed of a spherical body or a columnar body.
JP11217012A 1999-07-30 1999-07-30 Wiring board and its mounting structure Pending JP2001044327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11217012A JP2001044327A (en) 1999-07-30 1999-07-30 Wiring board and its mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11217012A JP2001044327A (en) 1999-07-30 1999-07-30 Wiring board and its mounting structure

Publications (1)

Publication Number Publication Date
JP2001044327A true JP2001044327A (en) 2001-02-16

Family

ID=16697453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11217012A Pending JP2001044327A (en) 1999-07-30 1999-07-30 Wiring board and its mounting structure

Country Status (1)

Country Link
JP (1) JP2001044327A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007029505A1 (en) * 2005-09-02 2007-03-15 Matsushita Electric Industrial Co., Ltd. Module
JP2008193036A (en) * 2007-01-31 2008-08-21 Tamura Kaken Co Ltd Semiconductor package substrate for mounting conductive balls and the like, method of manufacturing the same, and conductive jointing material for the semiconductor package substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007029505A1 (en) * 2005-09-02 2007-03-15 Matsushita Electric Industrial Co., Ltd. Module
JP2008193036A (en) * 2007-01-31 2008-08-21 Tamura Kaken Co Ltd Semiconductor package substrate for mounting conductive balls and the like, method of manufacturing the same, and conductive jointing material for the semiconductor package substrate

Similar Documents

Publication Publication Date Title
EP0117111B1 (en) Semiconductor device assembly
US6351389B1 (en) Device and method for packaging an electronic device
JP3631638B2 (en) Mounting structure of semiconductor device package
KR100744930B1 (en) Manufacturing Method of LTC Module
JP2001338999A (en) Package for storing semiconductor elements
JPH10189815A (en) Mounting structure of semiconductor element mounting board
JP4013339B2 (en) Manufacturing method of electronic component having bump
JP3872236B2 (en) Wiring board and its mounting structure
JP2001044327A (en) Wiring board and its mounting structure
JP2002076193A (en) Package for mounting semiconductor element and package mounting board
JP3218281B2 (en) Connection structure between boards
JP2000340705A (en) Wiring board and its mounting structure
JP3297567B2 (en) Package for housing semiconductor element and its mounting structure
JP3347583B2 (en) Wiring board mounting structure
JP3692215B2 (en) Wiring board mounting structure
JPH08172144A (en) Semiconductor device and manufacturing method thereof
JP2001044319A (en) Wiring board and its mounting structure
JP2001244390A (en) Package for semiconductor device and its mounting structure
JP2001102492A (en) Wiring board and its mounting structure
JP4398223B2 (en) Semiconductor device
JP2001077527A (en) Wiring board mounting structure
JP2000195996A (en) Electronic circuit module
JP3610239B2 (en) Wiring board for mounting semiconductor device and mounting structure thereof
JPH11340347A (en) Package for storing semiconductor elements
JP2002324876A (en) Wiring board and its mounting structure

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050120

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050125

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050325

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050809

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051011

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20051115