JP2001036690A - Image sensor and driving method - Google Patents

Abstract

(57) [Problem] There is a demand for a high-performance, low-cost image sensor that uses a general-purpose MOS-IC and is a simultaneous reading and sequential reading method. In an image sensor including an array of pixels, a readout circuit, and a scanning circuit, each pixel 1 has a photoelectric conversion element 2, a buffer amplifier 7 with a control switch connected to individual electrodes of the photoelectric conversion element 2, and a buffer amplifier. 7, a transfer switch 8 that is conductive during the activation period of the buffer amplifier 7, a storage capacitor 9 connected to the other end of the transfer switch 8, and a clamp switch connected to the other electrode of the storage capacitor 9. It consists of a switch 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image sensor such as a CCD and a method for driving the image sensor.

[0002]

2. Description of the Related Art An image sensor is a device comprising an array of photoelectric conversion elements and a scanning circuit, and converts the distribution of brightness of a space or a document surface into a time-series electric signal. IC,
With the development of LSI technology, technology related to image sensors has also been developed, and CCD image sensors and MOS image sensors have been developed and put into practical use. In a CCD image sensor, signal charges generated by a photodiode, which is a pixel, are simultaneously transferred to a charge transfer device (CCD) in synchronization with a transfer pulse, and then sequentially input to an output amplifier by the charge transfer function of the CCD and amplified. A time-series image signal is obtained from an output terminal. The image signals are simultaneously captured by the photodiodes, and the read signals are sequentially output in synchronization with the transfer clock of the CCD. In other words, the image signals are simultaneously read and sequentially read out, which is easy to use. Although a CCD image sensor is capable of high-sensitivity and high-speed reading, it has a complicated manufacturing process and expensive elements as compared with ordinary ICs and LSIs.

As an image sensor other than the CCD, there is a MOS image sensor disclosed in Japanese Patent Publication No. 2603449. The image sensor includes a photoelectric conversion element, a reset MOS transistor provided for each photoelectric conversion element, a pair of storage capacitors for a bright signal and a dark signal provided for each photoelectric conversion element, A transfer MOS transistor for transferring an image signal to a capacitor; an output control MOS transistor for sequentially outputting the stored image signal from the pair of storage capacitors to a pair of output lines common to pixels; It is composed of a shift register that generates pulses. A bright signal voltage and a dark signal voltage are simultaneously stored in respective storage capacitors from each photoelectric conversion element by a pair of transfer MOS transistors. The signal voltages stored in these storage capacitors are output to a pair of output lines via a pair of output control MOS transistors controlled by a scanning signal from a scanning circuit. This image sensor is also easy to use because image signals are simultaneously read and sequentially read. However, this type of image sensor requires two storage capacitors per pixel. When the capacity of each storage capacitor is smaller than the capacity of the output line, the signal voltage appearing on the output line is greatly attenuated. In order to suppress the signal attenuation, it is necessary to increase the capacity of the storage capacitor for each pixel. However, the increase in the area occupied by the capacitor due to the increase in the capacity becomes an obstacle to high resolution and also increases the area of the image sensor chip. This increases the cost of the image sensor chip. Furthermore, when a phototransistor is used for the photoelectric conversion element,
A Bi-CMOS process is required and the manufacturing process becomes complicated. Further, since this image sensor has a differential output, an external differential amplifier is required, and peripheral circuits are complicated.

On the other hand, in recent years, standard MOS-IC
The development of a MOS image sensor that can be manufactured by a process and is advantageous in terms of cost has been activated. A conventional example of such a MOS image sensor is disclosed in JP-A-3-11096.
2, and those described in JP-A-8-125807. Photodiode, MOS as photoelectric conversion element
It includes a reset switch composed of a transistor, a buffer amplifier, an access switch composed of a MOS transistor, a scan shift register, and the like. The photodiodes are reset at a certain accumulation time, and a bright signal voltage appears on the individual electrodes of each photodiode immediately before the reset, a dark signal voltage appears immediately after the reset, and the scan pulse from the shift register passes through the buffer amplifier. A time-series image signal is output to a common image signal output line via an access switch controlled by the switch. Sequential capture of these,
The sequential readout image sensor accesses the pixels by the scanning pulse and performs the reset operation by the reset pulse in each access period at the same time, so a complicated scanning timing pulse and a capacitor for holding the image signal are unnecessary, and the circuit becomes simple. At the same time, the chip area is reduced, which is economical.

[0005]

However, in an image sensor of sequential capture and sequential read, the capture timing of the image signal differs for each pixel. For example, LEDs (red,
(Green, blue) In the case of a color image sensor unit provided with a light source, the three color LED lines are turned on at the same time.
The amount of exposure differs greatly between the pixel at the head of the scan and the pixel at the end of the scan, so that a faithful image cannot be read. There is no problem with an image sensor in which the light source is always lit and the image sensor is sequentially fetched and sequentially read out.
Even with a monochrome image sensor in which the light source blinks at the same time, the same problem as that of the color image sensor described above occurs.

On the other hand, a conventional general-purpose MOS image sensor of a simultaneous image signal simultaneous reading and sequential reading system holds a bright signal voltage and a dark signal voltage in a pair of storage capacitors, and supplies a common image signal via an access transistor. The signals are sequentially output to a signal output line. When the capacity of the output line is larger than that of the storage capacitor, the signal voltage is greatly attenuated due to voltage division by the capacity. In order to reduce this attenuation rate, it is necessary to attach a large-capacity storage capacitor for each pixel, so that a high-resolution image sensor cannot be made due to an increase in pixel area, and the cost of the image sensor chip increases due to an increase in chip area. Is a problem.

As described above, an image sensor of a general-purpose MOS-IC that simultaneously captures image signals and sequentially reads images has not been put to practical use. General purpose MO
Remaining issues remain, such as a rational image signal capturing method using an S-IC, a signal holding method requiring only a small-capacity storage capacitor, and a method of reading out stored image signals with a reduced attenuation factor.

The present invention, taking into account such problems of the conventional image sensor, enables simultaneous capture of image signals, has high sensitivity, and can be constituted by one small-capacity storage capacitor for each pixel. It is an object of the present invention to provide a MOS image sensor using a general-purpose MOS-IC.

[0009]

The image sensor of the present invention comprises at least an array of pixels, a readout circuit, a shift register, and a timing pulse generation circuit, and is formed on a Si chip. Further, by incorporating a self-biased gate grounded amplifier including a MOS transistor and a gate bias capacitor as an output amplifier, the S / N is improved and the peripheral circuit of the image sensor can be simplified.

Each pixel has a photoelectric conversion element and a reset MOS.
A transistor, a buffer amplifier with a control switch connected to the individual electrode of each photoelectric conversion element, a storage capacitor connected to the output terminal of the buffer amplifier, a clamp switch connected between the other terminal of the storage capacitor and a reference voltage source, etc. Consists of The photoelectric conversion elements are reset at regular time intervals, and a bright signal voltage appears immediately before reset and a dark signal voltage appears immediately after reset on the individual electrodes of each photoelectric conversion element. Before and after the reset timing, the control switches are turned on all the pixels at the same time, and after the clamp switches are turned on all the pixels during the conduction period of the control switches before the start of the reset operation, the control switch is turned on after the reset operation. By turning off the clamp switch simultaneously for all the pixels, the signal voltage terminal of each pixel, that is, the other terminal of each storage capacitor, can generate and hold the signal voltage of each pixel based on the reference voltage.

The readout circuit is connected to a signal voltage terminal of each pixel,
The MOS transistor for impedance conversion to which a gate electrode is connected, the MOS transistor for access, and one electrode of a refresh switch and one electrode of an access MOS transistor connected between the signal voltage terminal and the reference voltage source are connected in common. It consists of image signal output lines, and time-series bright and dark signals are alternately output to a common image signal output line via an access MOS-FET by a scanning pulse and a refresh pulse from a shift register.

According to the present invention, the read mode is a simultaneous capture, and the sequential read image sensor is replaced with a normal MOS.
-It can be manufactured by an IC process, and the readout circuit has a high impedance, so the storage capacitor has a small capacity and requires only one. Therefore, the pixel area can be reduced and a high-resolution image sensor can be realized. The area can be reduced, and the cost of the image sensor chip can be reduced.

By incorporating a self-biased gate-grounded amplifier in the above-mentioned image sensor chip, the signal delay due to the parasitic capacitance of the image signal line is minimized by utilizing the low input impedance characteristic, and the S / N characteristic is improved. be able to.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) An image sensor is composed of at least an array of pixels, a readout circuit, a shift register, and a timing pulse generation circuit, and is formed on a Si chip. First, a pixel of the image sensor according to the first embodiment of the present invention will be described with reference to an equivalent circuit diagram shown in FIG. The pixel 1 includes an inverting amplifier 7 as a buffer amplifier including at least a photoelectric conversion element 2, a reset MOS transistor 3, and MOS transistors 5 and 6 with a control switch MOS transistor 4, a transfer MOS transistor 8, a storage capacitor 9, And a MOS transistor 10 as a clamp switch.

Here, a photodiode is used as the photoelectric conversion element 2. In a MOS-IC, a photodiode can be formed by diffusing impurities of different conductivity types into a Si substrate in an array with a desired light receiving window size, and has a simpler structure than a phototransistor. The storage capacitor is made of metal manufactured by the MOS-IC process.
Oxide film capacity or p / n junction capacity. 11 is a positive power supply line, 12 is an amplifier control pulse line, 13 is a transfer pulse line, 14 is a reset pulse line, 15 is a reset voltage line, 16 is a reference voltage line, and 17 is a clamp pulse line. Reference numeral 18 denotes a signal voltage terminal of the pixel. Reference numeral 19 denotes a parasitic capacitance associated with the signal voltage terminal, and is not a capacitor that is intentionally provided.

The individual electrode of each photoelectric conversion element 2 is connected to the gate of the driver transistor 5 of the inverting amplifier 7, and the output terminal of the inverting amplifier 7 is connected to one of the storage capacitors 9 via the transfer MOS transistor 8 operating as a transfer switch. Terminal. The other end of the storage capacitor 9 is connected to a reference power supply line 16 via a clamp MOS transistor 10 as a clamp switch.

Next, the operation of the image sensor according to the first embodiment of the present invention will be described. FIG. 2 is an operation timing chart of the image sensor according to the present invention.
Is a reset pulse φrs, 21 is a signal voltage Vp appearing on an individual electrode of the photoelectric conversion element 2, 22 is an output voltage Vao of the inverting amplifier 7, 23 is a pulse φsw for controlling the control switch 4 of the inverting amplifier 7, and 24 is a transfer pulse. φT, 25 is a clamp pulse, and 26 is the waveform of the stored signal voltage Vso appearing at the other end of the storage capacitor, that is, at the signal voltage terminal 18.

In the waveform of the output voltage Vao at 22, the solid line indicates the time during which the inverting amplifier is in the active state, and the dotted line indicates the period during which the inverting amplifier is inactive, ie, in the floating state. FIG. In the waveform of the output voltage Vao, the signal voltage in the active state is maintained except for the feedthrough noise due to crosstalk when the inverting amplifier changes from the active state to the inactive state. The amplitude of the output voltage Vso is
Is represented by the following equation, where C is the capacitance value of C, and Csp is the capacitance value of the parasitic capacitance 19.

[0019]

Vso = C × Vao / (C + Csp) It can be seen from the above equation that as the parasitic capacitance Csp / C with respect to the capacitance C of the storage capacitor 9 increases, the signal voltage attenuates. In the present embodiment, the parasitic capacitance associated with the signal voltage terminal 18 is mainly the gate capacitance of one MOS transistor and the drain capacitance of two MOS transistors, and is extremely small, so that the attenuation of the signal voltage is kept small.
Further, the storage capacitor 9 having a small capacity can be used while keeping the attenuation rate at a constant value. Therefore, a high-resolution image sensor with a small pixel area is also possible with the configuration of the present invention.

The photoelectric conversion element 2 operates in a charge storage mode, and its individual electrodes are reset at a predetermined storage time by a reset MO.
The reset voltage is reset to a reset voltage by applying a reset pulse φrs to the gate electrode of the S transistor 3. Immediately after each reset operation, the voltage Vp of the individual electrode of the photoelectric conversion element 2 becomes a constant reset voltage Vrs, which is a state where no photoelectric current is accumulated by the photoelectric conversion element, and becomes a dark signal voltage of each pixel. As shown by the waveform Vp, the voltage of the individual electrode of the photoelectric conversion element 2 rises linearly with the accumulation of the photocurrent, and becomes a bright signal voltage proportional to the exposure amount immediately before the reset operation. That is, the level difference of Vp immediately before and immediately after the reset is a substantial image signal.

By applying a control pulse, which becomes active before and after the reset timing, to the gates of the control switches 4 of all the pixels, the control switches 4 are simultaneously turned on for all the pixels, and the output of the inverting amplifier 7 is inverted and amplified. Signal voltage can be obtained. The signal voltage appearing at the output terminal is transferred to the storage capacitor 9 by applying a transfer pulse φt to the gate of the transfer switch.

During the conduction period of the transfer switch 8 before the start of the reset operation, the clamp switch 10 is made conductive by applying a clamp pulse φc1 to the gate of the clamp switch 10 at the same time for all pixels, and then the control switch 4 after the reset operation is performed. By turning off the clamp switch 10 at the same time for all the pixels during the conduction period, the accumulated signal voltage Vso of each pixel based on the reference voltage is generated and held at the other terminal of each accumulation capacitor 9, that is, the signal voltage terminal 18. be able to. It is desirable that the clamp pulse φc1 for turning on the clamp switch MOS transistor 10 be high during the high period of the control pulse φsw.

The inverting amplifier 7 is provided for each pixel and amplifies a signal in the vicinity of the photoelectric conversion element 2 to perform S / N.
At the same time as improving the characteristics, the dark signal is transferred to the storage capacitor 9 at the timing when the inverting amplifier 7 is in the active state, and then the bright signal is transferred. The power consumption of the inverting amplifier 7 can be reduced by the operation of the switch 4. In addition, since a bright signal voltage based on a signal voltage in a dark state is held, only one capacitor is required, so that a chip area can be reduced and cost can be reduced.

In the image sensor, a large number of pixels are arranged on a Si chip. The reset operation, the inverting amplifier activation operation, the transfer operation, and the clamp operation are performed at the timings shown in FIG. It takes place all at once. Therefore, the image sensor performs a simultaneous capturing operation. (Second Embodiment) A readout circuit of an image sensor according to a second embodiment of the present invention will be described with reference to an equivalent circuit diagram shown in FIG. The readout circuit is provided for each pixel 1a, 1
b, 1c signal voltage terminals 18a, 18b, 1
8c MO for impedance conversion with gate electrode connected to 8c
S transistors 30a, 30b, 30c and access M
It comprises an OS transistor 31a, 31b, 31c, and an image signal output line 33 which commonly connects the other electrodes of the refresh MOS transistors 32a, 32b, 322c and the access MOS transistor.

Each refresh MOS transistor is connected between the reference power supply line 16 and the signal voltage terminal 18 of each pixel. Numeral 34 denotes a shift register which generates a scanning pulse in response to an external clock pulse and start pulse, and numeral 35 denotes a timing pulse generator which generates various timing pulses applied to pixels.

The reference numerals 36 and 37a, 37b, and 37c receive the refresh pulse and the clock pulse, respectively.
A circuit that generates a refresh pulse for controlling the S transistors 32a, 32b, and 32c, and that generates a pulse that turns on the refresh MOS transistor 32 in the latter half of each access pulse, the circuit type is not necessarily an inverter and an AND circuit. However, the present invention is not limited to this. Vrs and Vbb denote a reset power supply and a reference power supply, respectively, which are commonly applied to all pixels, and are connected to a reset power supply line 15 and a reference voltage line 16 of each pixel.

Next, a signal reading operation according to the second embodiment of the present invention will be described with reference to FIG. 40, 4
Reference numerals 1 and 42 denote accumulated signal voltages Vso1, Vso2, and Vson appearing at the signal voltage terminals 18 of the pixels 1, 2, and n, respectively. 43, 44 and 45 are shift registers 34, respectively.
From the scanning pulses Y1, Y2, Yn. 46, 47, 4
8 is a refresh pulse. Storage signal voltage 40 (V
so1), 41 (Vso2) and 42 (Vson) are applied to the gates of the access MOS transistors 21a, 21b and 21c, respectively, and refresh pulses 46 (R1) and 47 are applied.
(R2) and 48 (Rn) are applied to the gates of the refreshing MOS transistors 32a, 32b and 32c, respectively, so that the time-series bright signal Isig and the reference signal Id are alternately applied to the common image signal output line 33, Output in order.

Therefore, in the reading order, the holding time of the storage signal voltage is short in the first pixel and the holding time of the storage signal voltage is short in the rear pixel, but the leakage current of the storage capacitor and the MOS transistor is sufficiently small. It doesn't matter. That is, according to the present invention, the image sensor sequentially accesses the accumulated signal voltage Vso appearing at the signal voltage terminal 18 and simultaneously turns on the refresh MOS transistor in the latter half of each access timing, so that the signal current Isig based on the reference signal Id. And the reference signal Id
Are alternately output to the image signal output line 33 in pairs. As a result, signal processing for reducing fixed pattern noise in the subsequent signal processing circuit is facilitated. (Third Embodiment) FIG. 5 shows an image sensor with an amplifier according to a third embodiment of the present invention. Except for the amplifier section, it comprises the array of pixels according to the first embodiment and the readout circuit according to the second embodiment.
The amplifier unit 50 includes a driving MOS transistor 51,
Load MOS transistor 52 and amplifier set MO
S transistor 53 and gate voltage holding capacitor 5
4, a source resistor 55, and a buffer circuit 56. The source MOS transistor 51 has a source resistor 55 at its source, the gate of the transistor 51 has a gate voltage holding capacitor 54, and an amplifier setting MOS transistor 51.
One electrode of the transistor 53 is connected to the drain of the drive MOS transistor 51, the source of the load MOS transistor 52 and the other electrode of the amplifier set MOS transistor 53, and to the input terminal of the buffer circuit 56. The output terminal of the buffer circuit 56 is the output terminal of the image sensor with the amplifier.

The amplifier section 50 operates by receiving the alternating signal current Isig · Id from the image signal output line 33 at the source of the driving MOS transistor 51. When the amplifier setting MOS transistor 53 is turned on at the reference signal output timing, the drive MOS transistor 5
One gate is self-biased to the drain voltage of the reference signal and is held by the gate voltage holding capacitor 54. In a MOS transistor, since the leakage current of the gate electrode is extremely small, the gate bias voltage can be held with high accuracy. At the output timing of the bright signal, the amplifier setting MOS transistor 54 is turned off, and an output voltage based on the gate voltage held by the gate voltage holding capacitor 54 appears at the drain of the drive MOS transistor 51. The drain voltage is output via the buffer circuit 56. Even if the amplifier setting transistor 53 is turned on at the timing of the bright signal output and turned off at the timing of the reference signal output, normal operation can be performed although the signal output polarity is different. The self-biased gate grounded amplifier 50 keeps the input impedance low, minimizes the signal delay due to the parasitic capacitance of the image signal line, improves the S / N due to the built-in amplifier, and automatically drives the MOS drive. Since the gate voltage of the transistor 51 can be set to an appropriate voltage, the transistor 51 can be manufactured with a high yield against fluctuations in the IC process.

[0030]

According to the present invention, it is possible to manufacture a high-sensitivity image sensor of simultaneous reading and sequential reading in the reading mode by a general-purpose MOS-IC process.

The pixel is composed of simple devices and circuits, and functions to take in, amplify, and accumulate signals. Since the readout circuit has a high input impedance, the storage capacitor in the pixel section requires only a small capacitance. The area occupied can be reduced, and a high-resolution image sensor becomes possible.
Image sensor chips become cheaper.

Since the image signal current Isig and the reference signal Id are alternately paired and output to the image signal output line 33, signal processing for reducing fixed pattern noise in a subsequent signal processing circuit is facilitated.

By incorporating a self-biased gate-grounded amplifier in the image sensor chip, it is possible to improve the S / N and to simplify the peripheral circuits.

Therefore, it is considered that the present invention exerts a great effect on an image or video input device in various information processing devices.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a pixel of an image sensor according to a first embodiment of the present invention.

FIG. 2 is a timing chart for capturing an image signal of a pixel according to the first embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of a signal reading unit of an image sensor according to a second embodiment of the present invention.

FIG. 4 is a timing chart for signal reading according to a second embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of an image sensor with an amplifier according to a third embodiment of the present invention.

[Explanation of symbols]

1, 1a, 1b, 1c: Pixel 2: Photoelectric conversion element 3: Reset MOS transistor 7: Inverting amplifier with control switch 8: Transfer MOS transistor 9: Storage capacitor 10 ... Clamping MOS transistor 18 ... Signal voltage terminal 20 ... Reset pulse φrs 21 ... Signal voltage Vp 22 ... Output voltage Vao 23 ... Controlling pulse φsw 24 ... Transfer pulse φT 25: clamp pulse 26: stored signal voltage Vso 30a, 30b, 30c: impedance conversion M
OS transistor 31a, 31b, 31c access MOS transistor 32a, 32b, 32c refresh MOS transistor 33 image signal output line 34 shift register 35 timing pulse generator 40 41, 42... Accumulated signal voltages Vso1, Vso2, Vso
n 43, 44, 45: scanning pulse Y1, Y2, Yn 46, 47, 48: refresh pulse 51: driving MOS transistor 52: load MOS transistor 53: amplifier setting MOS Transistor 54: MOS transistor for holding gate voltage 55: Source resistance

Claims (8)

[Claims] A photoelectric conversion element operating in a charge accumulation mode;
An array of pixels including a buffer amplifier, a storage capacitor, and a control switch; an impedance conversion transistor, an access transistor, and an image signal output commonly connected to the other end electrode of the access transistor attached to each pixel. In an image sensor including a readout circuit including a line and a scanning circuit for sequential reading, each pixel in the array of pixels includes a control switch connected to the photoelectric conversion element and an individual electrode of the photoelectric conversion element. A buffer switch, a transfer switch connected to the output terminal of the buffer amplifier, and conducting during the activation period of the buffer amplifier; a storage capacitor connected to the other end of the transfer switch; A clamp switch connected between the end electrode and the reference voltage line The image sensor characterized in that it comprises. 2. The image sensor according to claim 1, wherein said photoelectric conversion element is a photodiode. 3. The image sensor according to claim 1, wherein said control switch, said transfer switch and said clamp switch are MOS transistors. 4. The image sensor according to claim 1, wherein said buffer amplifier is an inverting amplifier using a MOS transistor. 5. The driving method for driving an image sensor according to claim 1, wherein a buffer amplifier with a control switch connected to an individual electrode of a photoelectric conversion element included in the pixels arranged in the array is reset timing. Before and after, the control switches are turned on all the pixels at the same time, and the clamp switches are turned on all the pixels at the same time during the conduction period of the control switches before the start of the reset operation. A driving method for an image sensor, wherein a signal voltage of each pixel based on a reference voltage is generated and held at the other end of each of the storage capacitors by simultaneously turning off a clamp switch for all pixels. 6. A photoelectric conversion element operating in a charge storage mode,
An array of pixels including a buffer amplifier, a storage capacitor, and a control switch; an impedance conversion transistor, an access transistor attached to each pixel, and an image signal output commonly connected to the other end of the access transistor An image sensor comprising: a readout circuit including a line; and a scanning circuit for sequential reading, wherein the readout circuit is used for impedance conversion in which a gate electrode is connected to the other end of the storage capacitor, which is an output terminal of each pixel. A MOS transistor and an access MO having a drain electrode connected to a source electrode of the transistor;
An S transistor, a refresh switch connected between an output line terminal of each pixel and a reference voltage line,
An image signal output line formed by commonly connecting source electrodes of the transistors for access. 7. A driving method for driving an image sensor according to claim 6, wherein an image signal appearing at the other end of said storage capacitor as an output terminal of each pixel is received by a gate electrode of a MOS transistor for impedance conversion. In synchronization with the access pulse of each pixel, the refresh switch is turned off in the first half of the access pulse to output a signal current, and the refresh switch is turned on in the second half of the access pulse to output the reference current. A method for driving an image sensor, comprising: 8. The image sensor according to claim 1 or 6, a driver MOS transistor; and a load MOS transistor.
An image sensor comprising: a transistor; a MOS transistor switch for generating a self-bias; a capacitor for holding a gate bias voltage; and a self-biased gate-grounded amplifier including a source resistor.