JP2001036052A - Semiconductor integrated circuit device and design method thereof - Google Patents

Abstract

(57) Abstract: A semiconductor having a highly integrated and highly reliable connection structure, in which the degree of freedom of wiring of connection portions in integrated circuits depending on separate design data (CAD data) is improved. An integrated circuit device and a method for designing the same are provided. A connection portion between wiring patterns on a gate array integrated circuit side and a macro cell side on an LSI chip is automatically arranged and wired by different wiring layers. The connection end 13 is provided with a multi-layer connection-dedicated pattern STCON at one of the wiring ends on the gate array integrated circuit 11 side or the macro cell 12 side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal wiring structure in a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which integrated circuits composed of different design data are integrated on the same semiconductor chip, and a design thereof. About the method.

[0002]

2. Description of the Related Art With the increase in the number of functions and the large-scale integration of semiconductor integrated circuit devices, the entire circuit has not been developed for one LSI chip product, and some of the functions have been obtained from externally obtained macrocells and other functions. It may be commercialized using cells and the like.

For example, a DRAM (Dy) that provides a memory function is provided on an integrated circuit chip composed of a gate array or the like.
namic Random Access Memory (macro cell) mixed or modularized RISC (Reduced Instructio)
n Set Computer) type processor / macrocell. As a result, ASIC (Application Specif
It is possible to design and manufacture multi-functional, large-scale LSI chip products such as IC integrated circuits (ICs for specific applications) in a short time.

[0004] Such a macro cell obtained from the outside is incorporated into a gate array integrated circuit such as a SOG (Sea of Gate) or the like together with design data. In that case, the design data of the gate array integrated circuit and the design data of the macro cell are different CAs.
In many cases, it is designed using D (Computer Aided Design) data.

[0005] Wiring configurations of integrated circuits relying on separate design data (CAD data) such as the gate array integrated circuit and the macro cell as described above are connected by a specific wiring layer (the same wiring layer). That is common. In addition, while the wiring configuration is required, integrated circuits depending on different design data can be mixedly mounted on one integrated circuit chip. The designer must keep this in mind when designing a hybrid package.

[0006]

As described above, in the technical configuration in which integrated circuits which depend on different design data (CAD data) are mixedly mounted on one integrated circuit, two integrated circuits having the same specific wiring layer are used. The connection between the integrated circuits is made, and the layout of the connection is restricted.

[0007] With the recent multifunctional, large-scale, high-integration of LSI chip products, the above-mentioned restrictions cause congestion in the wiring layer. Such a configuration rather hinders the reliability and miniaturization of the product. In addition, in order to maintain high reliability in connection structures between integrated circuits that require higher integration, it has been necessary to spend calculation time in the design stage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to improve the degree of freedom of wiring of a connection portion between integrated circuits which depend on different design data (CAD data). An object of the present invention is to provide a semiconductor integrated circuit device having an integrated and highly reliable connection structure and a design method thereof.

[0009]

According to the present invention, there is provided a semiconductor integrated circuit device comprising: a first semiconductor integrated circuit; a second semiconductor integrated circuit disposed adjacent to the first semiconductor integrated circuit;
A first interconnection belonging to the first semiconductor integrated circuit and an interconnection of a second interconnection belonging to a second semiconductor integrated circuit, wherein the interconnection is formed in at least a different interconnection layer; And a multilayer structure in which the second wiring and the second wiring can be connected to each other.

The present invention is a method of designing a semiconductor integrated circuit device in which a second semiconductor integrated circuit is arranged adjacent to a first semiconductor integrated circuit and a desired connection relationship between the two is established. When the wiring layer related to the connection end of each of the second semiconductor integrated circuits is different, the connection end of either the first or the second semiconductor integrated circuit can be connected to each of the multi-layered wiring layers. Configure the wiring extension end,
A wiring belonging to the first semiconductor integrated circuit and a wiring belonging to the second semiconductor integrated circuit are arranged and connected.

According to the present invention, the degree of freedom of connection to different wiring layers is provided by the region constituted by the wiring extending ends of the multilayer structure.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing a main part of a semiconductor integrated circuit device according to a basic embodiment of the present invention. For example, on the LSI chip 1, there is shown a connection portion 13 between wiring patterns on the side of the gate array integrated circuit 11 having the SOG configuration and on the side of the integrated circuit 12 (referred to as macro cell 12) composed of macro cells. Element M such as MOS
The wiring layers on M1 and M2 consist of three layers and are indicated by AL1, 2, and 3.

In the case of automatically arranging and wiring components configured depending on mutually different design data, a mutual connection 1
3 may need to be connected using different wiring layers. The reason is mainly to ease layout and reduce congestion in the wiring layer.

In view of the above, the connection portion 1 between the above wiring patterns
Reference numeral 3 designates a multi-layer connection-dedicated pattern STCON at one of the wiring ends of the gate array integrated circuit 11 side and the macro cell 12 side.

Accordingly, for example, in the macro cell 12, even if the wiring layer of the design data as it is (the wiring layer having the connecting wiring end portion) is different from the wiring layer to which the gate array integrated circuit 11 is connected. , Easily connectable.

In this example, the connection-specific pattern STCON
Is configured as follows. The wiring patterns 131 and 13 are stacked in a stacked manner above the element isolation insulating film 20 at the joint between the gate array integrated circuit 11 and the integrated circuit of the macro cell 12.
2,133 are provided. Then, if necessary, via V
An IA (here, VIA2) is formed, and the connection wirings 111 and 121 formed in different wiring layers are electrically connected. VIAs 1, 3, and 4 indicated by broken lines represent vias that can be formed in other patterns out of the one connection-specific pattern STCON, and are not actually formed because they are not used in this example.

According to the above configuration, separate design data (C
The degree of freedom of the wiring of the connection part in the integrated circuits depending on (AD data) is significantly improved as compared with the related art. In addition, congestion of the connection wiring can be positively alleviated.
As a result, high integration and high reliability can be obtained at the connection portions between the integrated circuits.

FIG. 2 is a schematic projection view of a connection-only pattern (STCON) for describing a method of designing a semiconductor integrated circuit device according to an embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals. When the macro cell 12 is arranged adjacent to the gate array integrated circuit 11 as described above and a desired connection relationship between them is established, in the arrangement and wiring design stage, the wiring layers to be connected are different due to the difference in design data between the two. Shall be

Therefore, stacked wiring patterns 131a, 132a and 133a are formed (arrangement design) at the extending end of each connection wiring 111 belonging to the gate array integrated circuit 11 or each connection wiring 121 belonging to the macro cell 12.
Keep it.

Via contacts VCON3a-1 to VCON-3
Are prepared for connection between the wiring patterns 133a and 132a. Via contacts VCON2a-1 to VCON2-4 are prepared for connection between wiring patterns 132a and 131a.
In this way, a plurality of via contacts are prepared (as data) in each of the pattern layers 132a and 133a. Thereby, a specific via is selected and formed in an actual process.

In this manner, the wirings belonging to the gate array integrated circuit 11 and the wirings belonging to the macro cell 12 existing in different wiring layers are automatically arranged and connected. This mode is useful when there is no room to extend the connection wirings 111 and 121 in the longitudinal direction or when it is difficult to match the data of the wiring grids on the gate array integrated circuit 11 side and the macro cell 12 side.

FIG. 3 is a schematic projection view of a connection-only pattern (STCON) for explaining a method of designing another semiconductor integrated circuit device according to an embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals. In FIG. 2, the via-formable portion is provided so as to intersect with the direction in which the connection wiring (111, 121) of the gate array integrated circuit 11 or the macro cell 12 extends, but in this example, the via-formable portion is provided. The configuration was changed.

In FIG. 3, the stackable wiring patterns 131 b, 132 b, and 132 are provided in such a manner that the via formation is possible in the same direction as the extending direction of the connection wiring (111, 121) of the gate array integrated circuit 11 or the macro cell 12. 1
33b is configured (arranged and designed).

That is, the via contact VCON3b-
1 to -3 are wiring patterns 133 as necessary.
The via contacts VCON2b-1 to -3 have data that can function for connection between the wiring patterns 132b and 131b, respectively, as needed.

However, the former and the latter cannot exert their respective functions in the same place, and it is necessary to make one of them function with priority and exclude the other. As a result, vias at predetermined locations are selected and formed in the actual process. Therefore, the actual formation position of the via also becomes the same as the direction in which the connection wiring 111 or 121 extends.

In this way, the wirings belonging to the gate array integrated circuit 11 and the wirings belonging to the macro cell 12 existing in different wiring layers are automatically arranged and connected. This embodiment is useful when the connection points of the adjacent connection wirings 111 and 121 are close to each other or when the wiring pitch is narrow.

According to each of the above embodiments and the method thereof, even if the two integrated circuits to be connected have different wiring layers to be connected to each other, the multi-layer connection dedicated pattern STCO
By arranging and designing N, the degree of freedom of wiring of the connection part is remarkably improved. Therefore, a highly reliable connection structure with high integration can be easily realized.

It should be noted that the connection-specific pattern STCON having the above-mentioned multilayer structure is not limited to the shape shown in FIGS. 2 and 3, and a different pattern may be formed in each layer. Also,
The number of layers and the number of vias that can be formed are not particularly limited. Some patterns may be prepared in library data relating to automatic placement and routing so as not to hinder adjacent wiring.

As a result, especially when it is necessary to mount design data of a complicated macro cell of a wiring including a multilayer wiring, wiring connection can be performed so that both wiring ends to be connected are stably connected. A highly reliable connection structure can be realized without spending much time newly calculating on CAD.

[0030]

As described above, according to the present invention,
By providing a multi-layer connection-dedicated pattern, the degree of freedom of the wiring of the connection part is improved, so that it is possible to easily cope with connection wiring layers of different layers depending on different design data (CAD data). Can be connected. As a result, it is possible to provide a semiconductor integrated circuit device capable of realizing a highly integrated and highly reliable connection structure in a short time and a design method thereof.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a main configuration of a semiconductor integrated circuit device according to a basic embodiment of the present invention.

FIG. 2 is a schematic projection view of a connection-only pattern for explaining a method of designing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is a schematic projection view of a connection-only pattern for explaining a method of designing another semiconductor integrated circuit device according to an embodiment of the present invention.

[Explanation of symbols]

11: gate array integrated circuit, 12: macro cell, 13
... Wiring pattern mutual connection part, STCON... Connection-dedicated pattern, 111, 121... Connection wiring, VIA1.
Vias, 131, 132, 133 ... wiring patterns.

Claims (7)

[Claims] A first semiconductor integrated circuit; a second semiconductor integrated circuit disposed adjacent to the first semiconductor integrated circuit; a first wiring belonging to the first semiconductor integrated circuit; Interconnects belonging to the semiconductor integrated circuit of the above, wherein the interconnects include a multi-layer structure capable of connecting the first interconnect and the second interconnect formed at least in different interconnect layers. And a semiconductor integrated circuit device. 2. The interconnection part of the multilayer structure, wherein vias between respective layers are arranged in a direction intersecting with a direction in which an end of the first wiring or the second wiring extends when viewed from above. Item 2. The semiconductor integrated circuit device according to item 1. 3. The interconnection part of the multilayer structure, wherein vias between respective layers are arranged in the same direction as the direction in which the end of the first wiring or the second wiring extends when viewed from above. 2. The semiconductor integrated circuit device according to 1. 4. A method for designing a semiconductor integrated circuit device, comprising: arranging a second semiconductor integrated circuit adjacent to a first semiconductor integrated circuit and establishing a desired connection relationship between the first and second semiconductor integrated circuits; When the wiring layer relating to the connection end of each semiconductor integrated circuit is different, the wiring extension of the multilayer structure connectable to each of the multilayer wiring layers to the connection end of either the first or second semiconductor integrated circuit. A method of designing a semiconductor integrated circuit device, comprising: forming an end portion; and arranging and connecting a wiring belonging to the first semiconductor integrated circuit and a wiring belonging to a second semiconductor integrated circuit. 5. The wiring extending ends of the multilayer structure are arranged in a direction in which vias between respective layers intersect with a direction in which a connection end of one of the first and second semiconductor integrated circuits extends when viewed from above. The semiconductor integrated circuit device according to claim 4, wherein: 6. A wiring extending end of the multilayer structure, wherein vias between respective layers are arranged in the same direction as a direction in which a connection end of one of the first and second semiconductor integrated circuits extends when viewed from above. 5. The semiconductor integrated circuit device according to claim 4, wherein: 7. The semiconductor according to claim 4, wherein a plurality of vias are prepared between the respective layers and a predetermined via is selected at the wiring extending end of the multilayer structure. A method for designing an integrated circuit device.